Front-End Emulator with GOL chip
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Initial idea
The purpose of the FE-emul board is to study the link in terms of
latency and BER (comparing the transmitted data, that would be impossible
with the actual Front-End).
Old Design files (~ Dec 02, not correct): schematic,
assembly drawing,
CAD file,
BOM [do not mount crystal],
part_properties by
Terry Shaw.
New Design files:
PCB,
BOM
by
Terry Shaw.
FPGA design:
version 0 (17 Feb 03);
version marker_n_counters;
version "Running 1s" pattern and IDLEs (to resync).
The FE-emulator can receive a clock from the UMD Multipurpose clock board, provided you cut the VCC connection.
GOL startup problem
STATUS:
10 Bare PCBs received at UMD - 7 Jan 03
2 boards stuffed - 23 Apr 03
Bypassed power regulator, stuffed R68, R69 =>First Data transmission to HTR - 12 Sept 03
Fall 2003: 2 more boards stuffed, one working, delivered to Cern.
March 2004: remaining 6 boards stuffed.
Tullio Grassi - March 2005
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