2003 Testbeam HTR Information

 

  • Tullio Grassi’s Web Page is a good place to start for general HTR information.
  • On that page you will see a link to HTR pre-production board [2002-2003] – this has info for the current HTR board that you are using now.
  • Our current clocking scheme uses a 2·fLHC oscillator for the deserializer reference clock, and the TTCrx “40MHz” LHC clock for the system clock.  This is all implemented on a 3-mezzanine card assembly which hangs off the Princeton Fanout card. 

·        You will see lots of information about this setup here.

·        Here you will find a schematic for the clocking scheme.

  • There is a program written to “talk” to the HTRs in the VME crate:

·        To run it, you do the following

      1. log onto cmsmoe1.cern.ch as daq (password…ask Laza or ….)
      2. cd HtrSpy
      3. the executable is called “htr”, you invoke it by typing the word without the quotes.
      4. when you run it, you will get a menu which looks like the following.  The first thing you will have to do is to set the VME slot number (item 1).  Once that is set, you are then free to go into any of the other sub-menus.

  Note: VMEIL addressing is A24

 Enter:

   0 = Debug Level                                             Currently 0

   1 = set VME slot number                              Slot is 0

   2 = scan for HTR in slot 0

   3 = scan for HTRs

   4 = read VME version

   5 = read XILINX version

   6 = toggle TOP/BOTTOM Xilinx                 currently TOP

   7 = execute VME sysreset

   8 = execute internal HTR VME reset

   9 = execute XILINX FPGA reset

   A = go to SPY FIFO menu

   B = go to FLASH menu

   C = talk to Xilinx FPGA

   D = talk to TTCvi

   E = Histogram menu

   F = talk to VME FPGA

  -1 = exit

       Your choice?

      1. you can also run it with arguments such that it pretty much just runs and exits.  Here are the arguments:
        • htr –h       will give you help on what it can do
        •   -d <num>     debug (debug level 0 is the default, higher gives more output
        •   -t/-b        set default TOP or BOTTOM xilinx  (mostly for experts)
        •   -c <num>     set fiber number (1-8 inclusive)   (mostly for experts)
        •   -f         LOOP over HTRs in crate, printout versions of all FPGAs in HTR card
          • the program should return 0xC  for all HTRs – current version as of 5/25/03 is version 12 (hex C)
        •   -X       LOOP over HTRs in crate, TOP/BOT, configure from flash
          • causes all HTRs to reload both TOP and BOT xilinx code from onboard FLASH
        •   -1           LOOP over HTRs in crate, TOP/BOT, issue START
          • sometimes this is useful, but during a run the DAQ will take care of it – this is mostly for debugging
        •   -0           LOOP over HTRs in crate, TOP/BOT, issue STOP
          • ditto…
        •   -p           LOOP over HTRs in crate, TOP/BOT, calculate mean/sigma for all fibers
          • this can be a useful way to see if all 6 input fibers (we are only lighting up 6 of 8) are delivering data.  The output will look something like the following.  For each set of 8 fibers (TOP and BOT) it will read the data from the spy fifo’s and calculate means, RMS, and printout with the number of points read.  The fifo’s are 512 deep, but these are 16-bit words so these fifo’s will contain 255 full 32-bit GOL words as delivered by the front-ends.  Below, you see “QIE 0  #Data  255” and that is how it should be.  Any fibers that do not give something like this (especially all 3 QIEs should have 255 ± 1) probably means that the synch has been lost.

===> Found HTR in slot 5

Enter 1 to scan, 0 to bail

1

=================================================

Scaning all fibers for TOP Xilinx, HTR in VME slot 5

Means and sigmas for fiber 1

    QIE 0  #Data   255 Mean 2.89   Sigma 0.71

    QIE 1  #Data   255 Mean 3.47   Sigma 0.75

    QIE 2  #Data   255 Mean 3.16   Sigma 0.58

Means and sigmas for fiber 2

    QIE 0  #Data   255 Mean 3.46   Sigma 0.68

    QIE 1  #Data   255 Mean 4.20   Sigma 0.62

    QIE 2  #Data   255 Mean 3.56   Sigma 0.58

Means and sigmas for fiber 3

    QIE 0  #Data   255 Mean 3.51   Sigma 0.60

    QIE 1  #Data   255 Mean 3.46   Sigma 0.62

    QIE 2  #Data   255 Mean 3.41   Sigma 0.55

Means and sigmas for fiber 4

    QIE 0  #Data   255 Mean 3.86   Sigma 0.69

    QIE 1  #Data   255 Mean 3.26   Sigma 0.65

    QIE 2  #Data   255 Mean 3.34   Sigma 0.64

Means and sigmas for fiber 5

    QIE 0  #Data   255 Mean 3.40   Sigma 0.64

    QIE 1  #Data   255 Mean 3.52   Sigma 0.59

    QIE 2  #Data   255 Mean 3.40   Sigma 0.59

Means and sigmas for fiber 6

    QIE 0  #Data   255 Mean 3.94   Sigma 0.60

    QIE 1  #Data   255 Mean 3.67   Sigma 0.69

    QIE 2  #Data   255 Mean 3.51   Sigma 0.66

Means and sigmas for fiber 7

    QIE 0 saw no data

    QIE 1 saw no data

    QIE 2 saw no data

Means and sigmas for fiber 8

    QIE 0 saw no data

    QIE 1 saw no data

    QIE 2 saw no data

        •   -L  <file>   LOOP over HTRs in crate, TOP/BOT, load firmware from <file>
          • this allows you to load up the HTR Xilinx flashes, but be careful!!!
        •   -r           LOOP over HTRs in crate, TOP/BOT, issue HARD RESET
          • a hard reset is usually executed by an expert, but is useful to clear link errors (see –e below)
        •   -e           LOOP over HTRs in crate, TOP/BOT, read link errors
          • this will type out all link errors for all fibers for TOP/BOT of all HTRs.