Histogramming Firmware - Rev 3 HTR Boards (2003)

There are 2 different versions of this firmware.  The link provided is a zip file that contains the firmware for the Xilinx FPGA on the HTR. Each fiber input to the HTR contains information from 3 different QIEs, and each QIE has 4 different capacitors.  This makes a total of 12 different inputs which need to be histogrammed on a given fiber.  There are 8 fibers, giving a total of 96 histograms needed.  The Xilinx internal RAM is limited, so we cannot histogram all 12 QIE/Capids from all 8 fibers simultaneously. Also, the 2003 version of the DCC (which has the Slink-64 capability) will not support event sizes greater than around 400 dwords (1600bytes). So for the 2003 testbeam, we have 2 different versions of the firwmare: one version which will make histograms for 4 fibers at a time, send the histograms to the DCC when a L1A is received, then make histograms for the other set of 4, and so on, alternating indefinitly. However, this version will not work with the 2003 DCC. The other version, used for the HF, will only histogram 2 fibers at a time, which will work with the DCC (given firmware changed on July 23, 2003). Instead of the fibers alternating indefinetly (1+2, then 3+4, then 5+6, then 7+8) in this version you have to write to localbus (and VME address space) registers 0xF0 and 0xF4 to set which fibers to histogram. The HTR will then send data corresponding to the histograms to these two fibers. The data has a header which will tell you which fibers are being histogramed in the 2-histogram data block. Note that the header values go from 0 to 7, but often people speak of fibers 1-8. The correspondance is obvious!


Each distinct QIE/CAPID on any given fiber appears once every 4 clock cycles due to the rotation cap id's.  This gives us 4 clock ticks in which to perform the histogram filling.  For each QIE/CAPID pair, 32 16-bit words of distributed RAM are allocated.  When the particular capid appears, the mantissa is used as a lookup into distributed RAM for the frequency of that particular value appearing.  The number retrieved is incremented and restored in the same memory location.  This is implemented with a state machine that does its job in 4 clock ticks, ready for the next appearance of the particular QIE/CAPID.  Each QIE/CAPID distributed RAM (the histogram) is distinct from all others in the firmware implementation.

Note that unlike the 2002 version of the HTR firmware, the 2003 version will do both regular data and histogramming, set by writing 0x1 to the VME control register 0xC (see the HTR FPGA address map).

Powerup:  At powerup, or on a hard reset (VME write of 0x1 to LocalBus CSR, address 0x10 on the LocalBus), histogramming is disabled -- regular data taking is the default.

VME configuration needed to implement histogram:  There are  only 2 things you have to do in order to get histograms to be filled and written to the DCC:



Readout is (at this time) only via the DCC:

Readout via DCC:  At powerup, or on a hard reset (VME write of 0x1 to LocalBus CSR, address 0x10 on the LocalBus), the HTR mode is for regular (non-histogramming) data taking. To start histogramming, issue the proper VME commands as described above - VME_Start and VME_Stop along with setting histogram mode by writing a 0x1 to LocalBus CntrReg 0x10 controls the entire histogramming. Transmission to the DCC is always via receiving L1A. 

Synchronization with source position:  In order to try to synchronize the source posistion with the histogram, the following has funcctionality has been added:

DCC Data Format:  The data sent to the DCC will have exactly the same format as the data sent using the regular firmware, namely a 6-word header followed by data followed by a 2-word trailer, with each word having 16-bits.  The format of each is:

Last modified 7/23/03 Drew Baden