HCAL HTR Pre-Production (Rev3)

Last update: Aug 2004

HTR Main FPGA (Xilinx) Local Bus Address space
NB: there are 2 Main FPGAs per board

Items in green are last added and relevant for TB2003.
A question mark (?) means the register function is still under development.


Loc_AD [exad]	R/W	Name	Notes (for newly added registers, it is reported the firmware version number)
8	R	Sig_Detect[7:0]	Signal Detect bits from O/E devices. One bit per fiber. Useful to check the optical continuity (from v23).
C	R/W	CntrReg	Control register (see Table below)
10	W	WriteOnlyCntrReg	You write a "1" and it generates a pulse-command (see Table below)
14	R	StatusReg	Status register (see Table below)
18	R	FIFO_StatReg	Utility FIFOs Status Register (see Table below)
1C	R	FE_StatReg	Front-End Status Register (see Table below)
20	R/W	HTRsubmodN	HTR sub-module number. It should be initialized to { GA[4..0], T }, with T=1 for Top Xilinx and T=0 for Bottom Xilinx .
24	R	FPGAversionN	Version number of FPGA design
28	R/W	ProgInputDelay[15:0]	Programmable Delay on the 8 input FE-bus (from the 8 fibers), 2 bits per input.
2C ?	R	DataTrig_FIFO_ StatReg[1:0]	{DataTrigFIFOfull, DataTrigFIFOempty }
30	W	DataTrigFIFO ?	Input test pattern/trigger FIFO 512x19 (inject dummy FE_data, flags and L1A)
34	R	InSpyFIFO1	FIFO 511x19 { InSpyFIFO1empty, LinkER, LinkDV, LinkData[15:0]} 80MHz-words
38	R	InSpyFIFO2	FIFO 511x19 { InSpyFIFO2empty, LinkER, LinkDV, LinkData[15:0]} 80MHz-words
3C	R	InSpyFIFO3	FIFO 511x19 { InSpyFIFO3empty, LinkER, LinkDV, LinkData[15:0]} 80MHz-words
40	R	InSpyFIFO4	FIFO 511x19 { InSpyFIFO4empty, LinkER, LinkDV, LinkData[15:0]} 80MHz-words
44	R	InSpyFIFO5	FIFO 511x19 { InSpyFIFO5empty, LinkER, LinkDV, LinkData[15:0]} 80MHz-words
48	R	InSpyFIFO6	FIFO 511x19 { InSpyFIFO6empty, LinkER, LinkDV, LinkData[15:0]} 80MHz-words
4C	R	InSpyFIFO7	FIFO 511x19 { InSpyFIFO7empty, LinkER, LinkDV, LinkData[15:0]} 80MHz-words
50	R	InSpyFIFO8	FIFO 511x19 { InSpyFIFO8empty, LinkER, LinkDV, LinkData[15:0]} 80MHz-words
54	R	L2OutSpyFIFO	FIFO 2047x19 { L2OutSpyFIFOempty, StatusBits, L2Data[15:0] }. Hamming-unencoded data. Use: if not empty, read until empty; wait; repeat.
58	R/W	PipeLength[7:0]	Length (= delay) of the L1A-latency pipelines on DAQ_path. Must be > 2.
70	R	ErrAcc1[15:0]	Accumulator of Link_ER1 since last reset [from v28 it will not wrap, but stop at 65535]
74	R	ErrAcc2[15:0]	Accumulator of Link_ER2 since last reset
78	R	ErrAcc3[15:0]	Accumulator of Link_ER3 since last reset
7C	R	ErrAcc4[15:0]	Accumulator of Link_ER4 since last reset
80	R	ErrAcc5[15:0]	Accumulator of Link_ER5 since last reset
84	R	ErrAcc6[15:0]	Accumulator of Link_ER6 since last reset
88	R	ErrAcc7[15:0]	Accumulator of Link_ER7 since last reset
8C	R	ErrAcc8[15:0]	Accumulator of Link_ER8 since last reset
90	R	Ones’ reg	=”11…11” for testing
94	R	Zeroes’reg	=”00…00” for testing
98	R	BCNofFib1BZero	Arrival time (in BCN) of last BZero from FE fiber
9C	R	BCNofFib2BZero	Arrival time (in BCN) of last BZero from FE fiber
A0	R	BCNofFib3BZero	Arrival time (in BCN) of last BZero from FE fiber
A4	R	BCNofFib4BZero	Arrival time (in BCN) of last BZero from FE fiber
A8	R	BCNofFib5BZero	Arrival time (in BCN) of last BZero from FE fiber
AC	R	BCNofFib6BZero	Arrival time (in BCN) of last BZero from FE fiber
B0	R	BCNofFib7BZero	Arrival time (in BCN) of last BZero from FE fiber
B4	R	BCNofFib8BZero	Arrival time (in BCN) of last BZero from FE fiber
C0	R/W	NTP = bits [15:8] NDD = bits [7:0]	NTP = Number of time-samples of Trigger Primitives, power-on at 0; NDD = Number of time-samples of Daq Data, power-on at 7. Must be 0 ≤ NTP ≤ NDD; 0 < NDD; NTP+NDD < 22
D0	R	ErrorFIFO1	Snapshot of 15 InSpy-words around a link error. Use: if not empty, read until empty; repeat (from v15).
D4	R	ErrorFIFO2	Snapshot of 15 InSpy-words around a link error. Use: if not empty, read until empty; repeat.
D8	R	ErrorFIFO3	Snapshot of 15 InSpy-words around a link error. Use: if not empty, read until empty; repeat.
DC	R	ErrorFIFO4	Snapshot of 15 InSpy-words around a link error. Use: if not empty, read until empty; repeat.
E0	R	ErrorFIFO5	Snapshot of 15 InSpy-words around a link error. Use: if not empty, read until empty; repeat.
E4	R	ErrorFIFO6	Snapshot of 15 InSpy-words around a link error. Use: if not empty, read until empty; repeat.
E8	R	ErrorFIFO7	Snapshot of 15 InSpy-words around a link error. Use: if not empty, read until empty; repeat.
EC	R	ErrorFIFO8	Snapshot of 15 InSpy-words around a link error. Use: if not empty, read until empty; repeat.
F0 ?	R/W	FiberA	select one of the 2 fibers to be histogrammed (from v18)
F4 ?	R/W	FiberB	select the other fiber to be histogrammed (from v18)
F8	R	TTC_EvN[11:0]	Event number (should match with the TTCrx chip)
FC	R	TTC_EvN[23:12]	Event number (should match with the TTCrx chip)
104	R/W	Threshold[4:0]	5-bit mantissa threshold for histogramming (if threshold is enabled, see CntrReg)
108	R/W	MaxCount[15:0]	low 16 bits of 32 bit counter used for histogramming. Set to 0xFFF0 for non-thresholding.
10C	R/W	MaxCount[31:16]	high 16 bits of 32 bit counter used for histogramming. Set to 0x3 for non-thresholding.
100	R	TTC0	Received 0x0 in bits 7,6,5,3 of TTC broadcast bus 7:0 (0 means messages were for FE or reset messges)
110	R	BC0	Received 0x1 in bits 7,6,5,3 of TTC broadcast bus 7:0
120	R	TestEnable	Received 0x2 in bits 7,6,5,3 of TTC broadcast bus 7:0
130	R	ResetOrbitCntr	Received 0x3 in bits 7,6,5,3 of TTC broadcast bus 7:0
140	R	PrivateGap	Received 0x4 in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0x40)
150	R	Resync	Received 0x5 in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0x48)
160	R	PrivateOrbit	Received 0x6 in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0x60)
170	R	Hard_rst	Received 0x7 in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0x68)
180	R	Soft_rst	Received 0x8 in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0x80)
190	R	Start	Received 0x9 in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0x88)
1A0	R	StRq	Received 0xA in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0xA0)
1B0	R	Stop	Received 0xB in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0xA8)
1C0	R	Not defined	Received 0xC in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0xC0)
1D0	R	Not defined	Received 0xD in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0xC8)
1E0	R	Not defined	Received 0xE in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0xE0)
1F0	R	Not defined	Received 0xF in bits 7,6,5,3 of TTC broadcast bus 7:0 (TTC[7:0] = 0xE8)
NB		Addresses > 7FFF	are indirectly accessed over VME, due to a lack of lines
82000	W	Input_LUT1	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
84000	W	Input_LUT2	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
86000	W	Input_LUT3	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
88000	W	Input_LUT4	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
8A000	W	Input_LUT5	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
8C000	W	Input_LUT6	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
8E000	W	Input_LUT7	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
90000	W	Input_LUT8	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
92000	W	Input_LUT9	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
94000	W	Input_LUT10	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
96000	W	Input_LUT11	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
98000	W	Input_LUT12	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
9A000	W	Input_LUT13	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
9C000	W	Input_LUT14	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
9E000	W	Input_LUT15	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
A0000	W	Input_LUT16	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
A2000	W	Input_LUT17	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
A4000	W	Input_LUT18	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
A6000	W	Input_LUT19	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
A8000	W	Input_LUT20	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
AA000	W	Input_LUT21	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
AC000	W	Input_LUT22	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
AE000	W	Input_LUT23	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
B0000	W	Input_LUT24	Base address for configuration of Trigger-path Input-LUT (Linearizer LUT). MemoryLocationAddr = Loc_Ad[9:3]
B2000	W	Output_LUT1	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
B4000	W	Output_LUT2	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
B6000	W	Output_LUT3	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
B8000	W	Output_LUT4	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
BA000	W	Output_LUT5	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
BC000	W	Output_LUT6	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
BE000	W	Output_LUT7	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
C0000	W	Output_LUT8	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
C2000	W	Output_LUT9	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
C4000	W	Output_LUT10	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
C6000	W	Output_LUT11	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
C8000	W	Output_LUT12	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
CA000	W	Output_LUT13	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
CC000	W	Output_LUT14	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
CE000	W	Output_LUT15	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
D0000	W	Output_LUT16	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
D2000	W	Output_LUT17	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
D4000	W	Output_LUT18	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
D6000	W	Output_LUT19	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
D8000	W	Output_LUT20	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
DA000	W	Output_LUT21	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
DC000	W	Output_LUT22	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
DE000	W	Output_LUT23	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]
F0000	W	Output_LUT24	Base address for configuration of Trigger-path Output-LUT (Compression LUT). MemoryLocationAddr = Loc_Ad[12:3]

Any other address	R		returns exadecimal "DEAD"

Note that for a reading of any FIFO, the first word after an empty condition is meaningless (it's a leftover from the previous non-empty condition).

Control-Status Registers Table


Register	Bit	R/W	Description
CntrReg			at address C. IMPORTANT: to change a single bit, write the other ones as they were before!
	[0]	R/W	Histogramming Mode when 1, normal daq when 0 (from v. 13)
	[1]	R/W	Histogramming: auto cycle fibers if 1 (from version 21)
	[2]	R/W	Histogramming: ignore QIE range if 1/histogram only when QIE range=00 if 0 (from version 30)
	[3]	R/W	Histogramming: enable thresholding of all histograms (from version 50)
	[8] ?	R/W	Fake_Input : if 1 DataTrigFIFO enabled, if 0 real data.
	[9]	R/W	Bypass the Trigger-path enery-filter if 1
	[10]	R/W	CounterModeSel. If 1 the DAQ-Data are from an internal counter (byte-wise).
	[11]	R/W	Gate TTC_Start and TTC_Stop commands. It allows the use of TTC with partial readout chains - Jeremy

WriteOnlyCntrReg			at address 10
	[0]	W	Hard reset: Reset all logic (not reconfigure FPGAs), clear configuration registers to default values.
	[1]	W	Soft reset: Reset data, pointers, RAM contents, event# etc do not clear configuration registers.
	[2]	W	Start run: enable TTC L1A .
	[3]	W	Stop run: disable TTC L1A, allow data in pipeline to clear, stop writing into Spy FIFOs
	[4]	W	StatusRequest: set SR flag bit on the following L2-DAQ data frame (useful for DCC ?)
	[5]	W	TTC_Reset: to the TTCrx on the mezzanine (connected only to Top FPGA)
	[6]	W	generate a single L1A trigger
	[15:8]	W	TI_reset[8:1]: individual reset (inverted ENABLE actually) for TI TLK2501 deserializer

StatusReg			at address 14
	[0]	R	DLL locked
	[1]	R	run status (set by a Start, reset by a Stop)
	[7:2]	R	Last TTC broadcast command
	[8]	R	event_buffer_empty (for debugging)
	[9]	R	TTC_Ready (connected only to Top FPGA)
	[12:10]	R	DLL_unlock_counter[2:0]; reset by Hard_rst; Stops at 7. From v29

FIFO_StatReg			Spy FIFOs Status Register at address 18
	[7:0]	R	InSpyFIFO empty flags
	[15:8]	R	InSpyFIFO full flags
	[16]	R	L2OutSpyFIFO empty flag
	[17]	R	L2OutSpyFIFO full flag

FE_StatReg			Front-End link Status Register at address 1C
	[7:0]	R	FE_link_ERR flags
	[15:8]	R	FE_link_DV flags

NB: for a complete reset is reccomended to reconfigure the FPGA.

PROPOSED ALARM CONDITIONS (time-scale for monitoring ~ 1 second)

1) registers 70 to 8C = ErrAcc*[15:0] = MAX VALUE = 65535     (16 register per board)
2) StatusReg[0]=DLL locked=0             (2 register per board)
3) StatusReg[9]=TTC_Ready=0          (1 register per board, 2 copies available, one per xilinx).

There should be the option to mask each condition.

Go back to pre-production HTR page.