//----------------------------------------------------------------------------
// Title : Block Level
// Project : Ultrascale+ RF Data Converter Subsystem
//----------------------------------------------------------------------------
//
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`timescale 1ns / 1ps

//***********************************Entity Declaration************************
(* DowngradeIPIdentifiedWarnings="yes" *)

module Loopback_usp_rf_data_converter_0_0_drp_control(
  input         clk,
  input         reset,
  input         timeout,
  input         bypass,
  input         read_req,
  input         write_req,
  input         drp_gnt,
  input         drp_rdy,
  output        drp_req,
  output        drp_en,
  output        drp_we,
  output        rd_ack,
  output        wr_ack
);

  reg [2:0] state;
  reg       access_type;
  
  // States for the arbiter state machine
  localparam idle            = 3'd0;
  localparam send_enable     = 3'd1;
  localparam wait_rdy        = 3'd2;
  localparam write_done      = 3'd3;
  localparam read_done       = 3'd4;
  
  always @(posedge clk)
  begin
    if (reset == 1'b1) begin
      state        <= idle;
      access_type  <= 1'b0;
    end
    else if (timeout == 1'b1) begin
      state        <= idle;
      access_type  <= 1'b0;
    end
    else begin
      case(state)
      
          idle: begin         
            if (read_req == 1'b1) begin
              state        <= send_enable;
              access_type  <= 1'b0;
            end
            else if (write_req == 1'b1 && bypass == 1'b1) begin  
              state        <= write_done;
            end            
            else if (write_req == 1'b1) begin    
              state        <= send_enable;
              access_type  <= 1'b1;
            end
            else
              state <= idle;
          end
                          
          send_enable: begin
            if (drp_gnt == 1'b1) begin
              state  <= wait_rdy;
            end
            else
              state  <= send_enable;
          end          
          
          wait_rdy: begin
            if (drp_rdy == 1'b1) begin
              if (access_type == 1'b0) begin
                state <= read_done;
              end
              else begin
                state <= write_done;
              end
            end  
            else
              state  <= wait_rdy;            
          end 
          
          write_done: begin     
            if (drp_gnt == 1'b1)
              state <= write_done;
            else begin
              state <= idle;
            end
          end

          read_done: begin  
            if (drp_gnt == 1'b1)
              state <= read_done;
            else begin
              state <= idle;
            end
          end           
                     
      endcase    
    end
  end

  assign drp_req = ((write_req == 1'b1 || read_req == 1'b1) && (state != write_done || state != read_done)) ? 1'b1 : 1'b0;
  assign drp_en  = (state == send_enable) ? 1'b1 : 1'b0;
  assign drp_we  = (state == send_enable && write_req == 1'b1) ? 1'b1 : 1'b0;
  // wait for drp_gnt to go low before de-asserting ack signals.
  assign wr_ack  = ((drp_rdy == 1'b1 && drp_gnt == 1'b1 && access_type == 1'b1) || (write_req == 1'b1 && bypass == 1'b1 && state == idle)) ? 1'b1 : 1'b0;
  assign rd_ack  = (drp_rdy == 1'b1 && drp_gnt == 1'b1 && access_type == 1'b0) ? 1'b1 : 1'b0;
endmodule
