-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
-- Date        : Tue Jul 28 13:52:45 2026
-- Host        : DrewPC2025 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim -rename_top Loopback_smartconnect_0_0 -prefix
--               Loopback_smartconnect_0_0_ Loopback_smartconnect_0_0_sim_netlist.vhdl
-- Design      : Loopback_smartconnect_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xczu48dr-ffvg1517-2-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_cdc_sync is
  port (
    scndry_out : out STD_LOGIC;
    aresetn : in STD_LOGIC;
    aclk : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_cdc_sync;

architecture STRUCTURE of Loopback_smartconnect_0_0_cdc_sync is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  signal Q : STD_LOGIC;
  signal asr_d1 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
  attribute box_type : string;
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "VCC:CE";
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "VCC:CE";
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "VCC:CE";
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => asr_d1,
      Q => Q,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => aresetn,
      O => asr_d1
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => Q,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => scndry_out,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_upcnt_n is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    seq_clr : in STD_LOGIC;
    seq_cnt_en : in STD_LOGIC;
    aclk : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_upcnt_n;

architecture STRUCTURE of Loopback_smartconnect_0_0_upcnt_n is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal clear : STD_LOGIC;
  signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => q_int0(0)
    );
\q_int[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => q_int0(1)
    );
\q_int[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => q_int0(2)
    );
\q_int[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => q_int0(3)
    );
\q_int[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => q_int0(4)
    );
\q_int[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => seq_clr,
      O => clear
    );
\q_int[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => q_int0(5)
    );
\q_int_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk,
      CE => seq_cnt_en,
      D => q_int0(0),
      Q => \^q\(0),
      R => clear
    );
\q_int_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk,
      CE => seq_cnt_en,
      D => q_int0(1),
      Q => \^q\(1),
      R => clear
    );
\q_int_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk,
      CE => seq_cnt_en,
      D => q_int0(2),
      Q => \^q\(2),
      R => clear
    );
\q_int_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk,
      CE => seq_cnt_en,
      D => q_int0(3),
      Q => \^q\(3),
      R => clear
    );
\q_int_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk,
      CE => seq_cnt_en,
      D => q_int0(4),
      Q => \^q\(4),
      R => clear
    );
\q_int_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk,
      CE => seq_cnt_en,
      D => q_int0(5),
      Q => \^q\(5),
      R => clear
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_xpm_cdc_async_rst is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of Loopback_smartconnect_0_0_xpm_cdc_async_rst : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of Loopback_smartconnect_0_0_xpm_cdc_async_rst : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of Loopback_smartconnect_0_0_xpm_cdc_async_rst : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of Loopback_smartconnect_0_0_xpm_cdc_async_rst : entity is "1'b0";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of Loopback_smartconnect_0_0_xpm_cdc_async_rst : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of Loopback_smartconnect_0_0_xpm_cdc_async_rst : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of Loopback_smartconnect_0_0_xpm_cdc_async_rst : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of Loopback_smartconnect_0_0_xpm_cdc_async_rst : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of Loopback_smartconnect_0_0_xpm_cdc_async_rst : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of Loopback_smartconnect_0_0_xpm_cdc_async_rst : entity is "ASYNC_RST";
end Loopback_smartconnect_0_0_xpm_cdc_async_rst;

architecture STRUCTURE of Loopback_smartconnect_0_0_xpm_cdc_async_rst is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__1\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__10\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__11\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__12\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__13\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__14\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__15\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__16\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__17\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__18\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__19\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__2\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__20\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__21\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__22\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__23\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__24\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__25\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__26\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__27\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__28\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__29\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__3\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__30\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__4\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__5\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__6\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__7\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__8\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ : entity is "ASYNC_RST";
end \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_cdc_async_rst__9\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 157 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 157 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 157 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 157 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 5056;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 158;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 160;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ : entity is 160;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_8\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 5056;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 5056;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 112;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 125;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 5056;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 126;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 139;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 5056;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 70;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 83;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 5056;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 84;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 97;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 5056;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 98;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 111;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(157) <= \<const0>\;
  douta(156) <= \<const0>\;
  douta(155) <= \<const0>\;
  douta(154) <= \<const0>\;
  douta(153) <= \<const0>\;
  douta(152) <= \<const0>\;
  douta(151) <= \<const0>\;
  douta(150) <= \<const0>\;
  douta(149) <= \<const0>\;
  douta(148) <= \<const0>\;
  douta(147) <= \<const0>\;
  douta(146) <= \<const0>\;
  douta(145) <= \<const0>\;
  douta(144) <= \<const0>\;
  douta(143) <= \<const0>\;
  douta(142) <= \<const0>\;
  douta(141) <= \<const0>\;
  douta(140) <= \<const0>\;
  douta(139) <= \<const0>\;
  douta(138) <= \<const0>\;
  douta(137) <= \<const0>\;
  douta(136) <= \<const0>\;
  douta(135) <= \<const0>\;
  douta(134) <= \<const0>\;
  douta(133) <= \<const0>\;
  douta(132) <= \<const0>\;
  douta(131) <= \<const0>\;
  douta(130) <= \<const0>\;
  douta(129) <= \<const0>\;
  douta(128) <= \<const0>\;
  douta(127) <= \<const0>\;
  douta(126) <= \<const0>\;
  douta(125) <= \<const0>\;
  douta(124) <= \<const0>\;
  douta(123) <= \<const0>\;
  douta(122) <= \<const0>\;
  douta(121) <= \<const0>\;
  douta(120) <= \<const0>\;
  douta(119) <= \<const0>\;
  douta(118) <= \<const0>\;
  douta(117) <= \<const0>\;
  douta(116) <= \<const0>\;
  douta(115) <= \<const0>\;
  douta(114) <= \<const0>\;
  douta(113) <= \<const0>\;
  douta(112) <= \<const0>\;
  douta(111) <= \<const0>\;
  douta(110) <= \<const0>\;
  douta(109) <= \<const0>\;
  douta(108) <= \<const0>\;
  douta(107) <= \<const0>\;
  douta(106) <= \<const0>\;
  douta(105) <= \<const0>\;
  douta(104) <= \<const0>\;
  douta(103) <= \<const0>\;
  douta(102) <= \<const0>\;
  douta(101) <= \<const0>\;
  douta(100) <= \<const0>\;
  douta(99) <= \<const0>\;
  douta(98) <= \<const0>\;
  douta(97) <= \<const0>\;
  douta(96) <= \<const0>\;
  douta(95) <= \<const0>\;
  douta(94) <= \<const0>\;
  douta(93) <= \<const0>\;
  douta(92) <= \<const0>\;
  douta(91) <= \<const0>\;
  douta(90) <= \<const0>\;
  douta(89) <= \<const0>\;
  douta(88) <= \<const0>\;
  douta(87) <= \<const0>\;
  douta(86) <= \<const0>\;
  douta(85) <= \<const0>\;
  douta(84) <= \<const0>\;
  douta(83) <= \<const0>\;
  douta(82) <= \<const0>\;
  douta(81) <= \<const0>\;
  douta(80) <= \<const0>\;
  douta(79) <= \<const0>\;
  douta(78) <= \<const0>\;
  douta(77) <= \<const0>\;
  douta(76) <= \<const0>\;
  douta(75) <= \<const0>\;
  douta(74) <= \<const0>\;
  douta(73) <= \<const0>\;
  douta(72) <= \<const0>\;
  douta(71) <= \<const0>\;
  douta(70) <= \<const0>\;
  douta(69) <= \<const0>\;
  douta(68) <= \<const0>\;
  douta(67) <= \<const0>\;
  douta(66) <= \<const0>\;
  douta(65) <= \<const0>\;
  douta(64) <= \<const0>\;
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(157) <= \<const0>\;
  doutb(156) <= \<const0>\;
  doutb(155) <= \<const0>\;
  doutb(154) <= \<const0>\;
  doutb(153) <= \<const0>\;
  doutb(152) <= \<const0>\;
  doutb(151) <= \<const0>\;
  doutb(150) <= \<const0>\;
  doutb(149) <= \<const0>\;
  doutb(148) <= \<const0>\;
  doutb(147) <= \<const0>\;
  doutb(146) <= \<const0>\;
  doutb(145) <= \<const0>\;
  doutb(144) <= \<const0>\;
  doutb(143) <= \<const0>\;
  doutb(142) <= \<const0>\;
  doutb(141) <= \<const0>\;
  doutb(140) <= \<const0>\;
  doutb(139 downto 129) <= \^doutb\(139 downto 129);
  doutb(128) <= \<const0>\;
  doutb(127 downto 94) <= \^doutb\(127 downto 94);
  doutb(93) <= \<const0>\;
  doutb(92 downto 86) <= \^doutb\(92 downto 86);
  doutb(85) <= \<const0>\;
  doutb(84) <= \<const0>\;
  doutb(83 downto 73) <= \^doutb\(83 downto 73);
  doutb(72) <= \<const0>\;
  doutb(71) <= \<const0>\;
  doutb(70) <= \<const0>\;
  doutb(69) <= \<const0>\;
  doutb(68) <= \<const0>\;
  doutb(67) <= \<const0>\;
  doutb(66) <= \<const0>\;
  doutb(65) <= \<const0>\;
  doutb(64) <= \<const0>\;
  doutb(63) <= \<const0>\;
  doutb(62) <= \<const0>\;
  doutb(61) <= \<const0>\;
  doutb(60) <= \<const0>\;
  doutb(59) <= \<const0>\;
  doutb(58) <= \<const0>\;
  doutb(57) <= \<const0>\;
  doutb(56) <= \<const0>\;
  doutb(55) <= \<const0>\;
  doutb(54) <= \<const0>\;
  doutb(53) <= \<const0>\;
  doutb(52) <= \<const0>\;
  doutb(51) <= \<const0>\;
  doutb(50) <= \<const0>\;
  doutb(49) <= \<const0>\;
  doutb(48) <= \<const0>\;
  doutb(47) <= \<const0>\;
  doutb(46) <= \<const0>\;
  doutb(45) <= \<const0>\;
  doutb(44) <= \<const0>\;
  doutb(43) <= \<const0>\;
  doutb(42) <= \<const0>\;
  doutb(41) <= \<const0>\;
  doutb(40) <= \<const0>\;
  doutb(39) <= \<const0>\;
  doutb(38) <= \<const0>\;
  doutb(37) <= \<const0>\;
  doutb(36) <= \<const0>\;
  doutb(35) <= \<const0>\;
  doutb(34) <= \<const0>\;
  doutb(33) <= \<const0>\;
  doutb(32) <= \<const0>\;
  doutb(31) <= \<const0>\;
  doutb(30) <= \<const0>\;
  doutb(29) <= \<const0>\;
  doutb(28) <= \<const0>\;
  doutb(27) <= \<const0>\;
  doutb(26) <= \<const0>\;
  doutb(25) <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8 downto 1) <= \^doutb\(8 downto 1);
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(100),
      Q => \^doutb\(100),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101),
      Q => \^doutb\(101),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(102),
      Q => \^doutb\(102),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103),
      Q => \^doutb\(103),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(104),
      Q => \^doutb\(104),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105),
      Q => \^doutb\(105),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(106),
      Q => \^doutb\(106),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107),
      Q => \^doutb\(107),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(108),
      Q => \^doutb\(108),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109),
      Q => \^doutb\(109),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(110),
      Q => \^doutb\(110),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111),
      Q => \^doutb\(111),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(112),
      Q => \^doutb\(112),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113),
      Q => \^doutb\(113),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(114),
      Q => \^doutb\(114),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115),
      Q => \^doutb\(115),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(116),
      Q => \^doutb\(116),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117),
      Q => \^doutb\(117),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(118),
      Q => \^doutb\(118),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119),
      Q => \^doutb\(119),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(120),
      Q => \^doutb\(120),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121),
      Q => \^doutb\(121),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(122),
      Q => \^doutb\(122),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123),
      Q => \^doutb\(123),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(124),
      Q => \^doutb\(124),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125),
      Q => \^doutb\(125),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(126),
      Q => \^doutb\(126),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127),
      Q => \^doutb\(127),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      Q => \^doutb\(129),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(130),
      Q => \^doutb\(130),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131),
      Q => \^doutb\(131),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(132),
      Q => \^doutb\(132),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133),
      Q => \^doutb\(133),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(134),
      Q => \^doutb\(134),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135),
      Q => \^doutb\(135),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(136),
      Q => \^doutb\(136),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137),
      Q => \^doutb\(137),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(138),
      Q => \^doutb\(138),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139),
      Q => \^doutb\(139),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      Q => \^doutb\(1),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      Q => \^doutb\(2),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3),
      Q => \^doutb\(3),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(4),
      Q => \^doutb\(4),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5),
      Q => \^doutb\(5),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(6),
      Q => \^doutb\(6),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      Q => \^doutb\(73),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(74),
      Q => \^doutb\(74),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75),
      Q => \^doutb\(75),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(76),
      Q => \^doutb\(76),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77),
      Q => \^doutb\(77),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(78),
      Q => \^doutb\(78),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79),
      Q => \^doutb\(79),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7),
      Q => \^doutb\(7),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(80),
      Q => \^doutb\(80),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81),
      Q => \^doutb\(81),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(82),
      Q => \^doutb\(82),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83),
      Q => \^doutb\(83),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(86),
      Q => \^doutb\(86),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87),
      Q => \^doutb\(87),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(88),
      Q => \^doutb\(88),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89),
      Q => \^doutb\(89),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(8),
      Q => \^doutb\(8),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(90),
      Q => \^doutb\(90),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91),
      Q => \^doutb\(91),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(92),
      Q => \^doutb\(92),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(94),
      Q => \^doutb\(94),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95),
      Q => \^doutb\(95),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(96),
      Q => \^doutb\(96),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97),
      Q => \^doutb\(97),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(98),
      Q => \^doutb\(98),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99),
      Q => \^doutb\(99),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1) => dina(1),
      DIA(0) => '0',
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => dina(9 downto 8),
      DIF(1 downto 0) => dina(11 downto 10),
      DIG(1 downto 0) => dina(13 downto 12),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\,
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5 downto 4),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7 downto 6),
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\,
      DOE(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(8),
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\,
      DOG(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\,
      DOG(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\,
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(113 downto 112),
      DIB(1 downto 0) => dina(115 downto 114),
      DIC(1 downto 0) => dina(117 downto 116),
      DID(1 downto 0) => dina(119 downto 118),
      DIE(1 downto 0) => dina(121 downto 120),
      DIF(1 downto 0) => dina(123 downto 122),
      DIG(1 downto 0) => dina(125 downto 124),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113 downto 112),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115 downto 114),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117 downto 116),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119 downto 118),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121 downto 120),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123 downto 122),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125 downto 124),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(127 downto 126),
      DIB(1 downto 0) => dina(129 downto 128),
      DIC(1 downto 0) => dina(131 downto 130),
      DID(1 downto 0) => dina(133 downto 132),
      DIE(1 downto 0) => dina(135 downto 134),
      DIF(1 downto 0) => dina(137 downto 136),
      DIG(1 downto 0) => dina(139 downto 138),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127 downto 126),
      DOB(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_n_3\,
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131 downto 130),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133 downto 132),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135 downto 134),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137 downto 136),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139 downto 138),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(71 downto 70),
      DIB(1 downto 0) => dina(73 downto 72),
      DIC(1 downto 0) => dina(75 downto 74),
      DID(1 downto 0) => dina(77 downto 76),
      DIE(1 downto 0) => dina(79 downto 78),
      DIF(1 downto 0) => dina(81 downto 80),
      DIG(1 downto 0) => dina(83 downto 82),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_0\,
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_1\,
      DOB(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_3\,
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75 downto 74),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77 downto 76),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79 downto 78),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81 downto 80),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83 downto 82),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(85 downto 84),
      DIB(1 downto 0) => dina(87 downto 86),
      DIC(1 downto 0) => dina(89 downto 88),
      DID(1 downto 0) => dina(91 downto 90),
      DIE(1 downto 0) => dina(93 downto 92),
      DIF(1 downto 0) => dina(95 downto 94),
      DIG(1 downto 0) => dina(97 downto 96),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_0\,
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_1\,
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87 downto 86),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89 downto 88),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91 downto 90),
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_8\,
      DOE(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(92),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95 downto 94),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97 downto 96),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(99 downto 98),
      DIB(1 downto 0) => dina(101 downto 100),
      DIC(1 downto 0) => dina(103 downto 102),
      DID(1 downto 0) => dina(105 downto 104),
      DIE(1 downto 0) => dina(107 downto 106),
      DIF(1 downto 0) => dina(109 downto 108),
      DIG(1 downto 0) => dina(111 downto 110),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99 downto 98),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101 downto 100),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103 downto 102),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105 downto 104),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107 downto 106),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109 downto 108),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111 downto 110),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 157 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 157 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 157 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 157 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 5056;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 158;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 160;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ : entity is 160;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_2\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_4\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_5\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_6\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_7\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_9\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 5056;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 5056;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 112;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 125;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 5056;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 126;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 139;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 5056;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 70;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 83;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 5056;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 84;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 97;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 5056;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 98;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 111;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(157) <= \<const0>\;
  douta(156) <= \<const0>\;
  douta(155) <= \<const0>\;
  douta(154) <= \<const0>\;
  douta(153) <= \<const0>\;
  douta(152) <= \<const0>\;
  douta(151) <= \<const0>\;
  douta(150) <= \<const0>\;
  douta(149) <= \<const0>\;
  douta(148) <= \<const0>\;
  douta(147) <= \<const0>\;
  douta(146) <= \<const0>\;
  douta(145) <= \<const0>\;
  douta(144) <= \<const0>\;
  douta(143) <= \<const0>\;
  douta(142) <= \<const0>\;
  douta(141) <= \<const0>\;
  douta(140) <= \<const0>\;
  douta(139) <= \<const0>\;
  douta(138) <= \<const0>\;
  douta(137) <= \<const0>\;
  douta(136) <= \<const0>\;
  douta(135) <= \<const0>\;
  douta(134) <= \<const0>\;
  douta(133) <= \<const0>\;
  douta(132) <= \<const0>\;
  douta(131) <= \<const0>\;
  douta(130) <= \<const0>\;
  douta(129) <= \<const0>\;
  douta(128) <= \<const0>\;
  douta(127) <= \<const0>\;
  douta(126) <= \<const0>\;
  douta(125) <= \<const0>\;
  douta(124) <= \<const0>\;
  douta(123) <= \<const0>\;
  douta(122) <= \<const0>\;
  douta(121) <= \<const0>\;
  douta(120) <= \<const0>\;
  douta(119) <= \<const0>\;
  douta(118) <= \<const0>\;
  douta(117) <= \<const0>\;
  douta(116) <= \<const0>\;
  douta(115) <= \<const0>\;
  douta(114) <= \<const0>\;
  douta(113) <= \<const0>\;
  douta(112) <= \<const0>\;
  douta(111) <= \<const0>\;
  douta(110) <= \<const0>\;
  douta(109) <= \<const0>\;
  douta(108) <= \<const0>\;
  douta(107) <= \<const0>\;
  douta(106) <= \<const0>\;
  douta(105) <= \<const0>\;
  douta(104) <= \<const0>\;
  douta(103) <= \<const0>\;
  douta(102) <= \<const0>\;
  douta(101) <= \<const0>\;
  douta(100) <= \<const0>\;
  douta(99) <= \<const0>\;
  douta(98) <= \<const0>\;
  douta(97) <= \<const0>\;
  douta(96) <= \<const0>\;
  douta(95) <= \<const0>\;
  douta(94) <= \<const0>\;
  douta(93) <= \<const0>\;
  douta(92) <= \<const0>\;
  douta(91) <= \<const0>\;
  douta(90) <= \<const0>\;
  douta(89) <= \<const0>\;
  douta(88) <= \<const0>\;
  douta(87) <= \<const0>\;
  douta(86) <= \<const0>\;
  douta(85) <= \<const0>\;
  douta(84) <= \<const0>\;
  douta(83) <= \<const0>\;
  douta(82) <= \<const0>\;
  douta(81) <= \<const0>\;
  douta(80) <= \<const0>\;
  douta(79) <= \<const0>\;
  douta(78) <= \<const0>\;
  douta(77) <= \<const0>\;
  douta(76) <= \<const0>\;
  douta(75) <= \<const0>\;
  douta(74) <= \<const0>\;
  douta(73) <= \<const0>\;
  douta(72) <= \<const0>\;
  douta(71) <= \<const0>\;
  douta(70) <= \<const0>\;
  douta(69) <= \<const0>\;
  douta(68) <= \<const0>\;
  douta(67) <= \<const0>\;
  douta(66) <= \<const0>\;
  douta(65) <= \<const0>\;
  douta(64) <= \<const0>\;
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(157) <= \<const0>\;
  doutb(156) <= \<const0>\;
  doutb(155) <= \<const0>\;
  doutb(154) <= \<const0>\;
  doutb(153) <= \<const0>\;
  doutb(152) <= \<const0>\;
  doutb(151) <= \<const0>\;
  doutb(150) <= \<const0>\;
  doutb(149) <= \<const0>\;
  doutb(148) <= \<const0>\;
  doutb(147) <= \<const0>\;
  doutb(146) <= \<const0>\;
  doutb(145) <= \<const0>\;
  doutb(144) <= \<const0>\;
  doutb(143) <= \<const0>\;
  doutb(142) <= \<const0>\;
  doutb(141) <= \<const0>\;
  doutb(140) <= \<const0>\;
  doutb(139 downto 129) <= \^doutb\(139 downto 129);
  doutb(128) <= \<const0>\;
  doutb(127 downto 94) <= \^doutb\(127 downto 94);
  doutb(93) <= \<const0>\;
  doutb(92) <= \<const0>\;
  doutb(91) <= \<const0>\;
  doutb(90) <= \<const0>\;
  doutb(89) <= \<const0>\;
  doutb(88) <= \<const0>\;
  doutb(87) <= \<const0>\;
  doutb(86) <= \<const0>\;
  doutb(85) <= \<const0>\;
  doutb(84) <= \<const0>\;
  doutb(83 downto 73) <= \^doutb\(83 downto 73);
  doutb(72) <= \<const0>\;
  doutb(71) <= \<const0>\;
  doutb(70) <= \<const0>\;
  doutb(69) <= \<const0>\;
  doutb(68) <= \<const0>\;
  doutb(67) <= \<const0>\;
  doutb(66) <= \<const0>\;
  doutb(65) <= \<const0>\;
  doutb(64) <= \<const0>\;
  doutb(63) <= \<const0>\;
  doutb(62) <= \<const0>\;
  doutb(61) <= \<const0>\;
  doutb(60) <= \<const0>\;
  doutb(59) <= \<const0>\;
  doutb(58) <= \<const0>\;
  doutb(57) <= \<const0>\;
  doutb(56) <= \<const0>\;
  doutb(55) <= \<const0>\;
  doutb(54) <= \<const0>\;
  doutb(53) <= \<const0>\;
  doutb(52) <= \<const0>\;
  doutb(51) <= \<const0>\;
  doutb(50) <= \<const0>\;
  doutb(49) <= \<const0>\;
  doutb(48) <= \<const0>\;
  doutb(47) <= \<const0>\;
  doutb(46) <= \<const0>\;
  doutb(45) <= \<const0>\;
  doutb(44) <= \<const0>\;
  doutb(43) <= \<const0>\;
  doutb(42) <= \<const0>\;
  doutb(41) <= \<const0>\;
  doutb(40) <= \<const0>\;
  doutb(39) <= \<const0>\;
  doutb(38) <= \<const0>\;
  doutb(37) <= \<const0>\;
  doutb(36) <= \<const0>\;
  doutb(35) <= \<const0>\;
  doutb(34) <= \<const0>\;
  doutb(33) <= \<const0>\;
  doutb(32) <= \<const0>\;
  doutb(31) <= \<const0>\;
  doutb(30) <= \<const0>\;
  doutb(29) <= \<const0>\;
  doutb(28) <= \<const0>\;
  doutb(27) <= \<const0>\;
  doutb(26) <= \<const0>\;
  doutb(25) <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8 downto 1) <= \^doutb\(8 downto 1);
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(100),
      Q => \^doutb\(100),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101),
      Q => \^doutb\(101),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(102),
      Q => \^doutb\(102),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103),
      Q => \^doutb\(103),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(104),
      Q => \^doutb\(104),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105),
      Q => \^doutb\(105),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(106),
      Q => \^doutb\(106),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107),
      Q => \^doutb\(107),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(108),
      Q => \^doutb\(108),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109),
      Q => \^doutb\(109),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(110),
      Q => \^doutb\(110),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111),
      Q => \^doutb\(111),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(112),
      Q => \^doutb\(112),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113),
      Q => \^doutb\(113),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(114),
      Q => \^doutb\(114),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115),
      Q => \^doutb\(115),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(116),
      Q => \^doutb\(116),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117),
      Q => \^doutb\(117),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(118),
      Q => \^doutb\(118),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119),
      Q => \^doutb\(119),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(120),
      Q => \^doutb\(120),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121),
      Q => \^doutb\(121),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(122),
      Q => \^doutb\(122),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123),
      Q => \^doutb\(123),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(124),
      Q => \^doutb\(124),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125),
      Q => \^doutb\(125),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(126),
      Q => \^doutb\(126),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127),
      Q => \^doutb\(127),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      Q => \^doutb\(129),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(130),
      Q => \^doutb\(130),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131),
      Q => \^doutb\(131),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(132),
      Q => \^doutb\(132),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133),
      Q => \^doutb\(133),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(134),
      Q => \^doutb\(134),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135),
      Q => \^doutb\(135),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(136),
      Q => \^doutb\(136),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137),
      Q => \^doutb\(137),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(138),
      Q => \^doutb\(138),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139),
      Q => \^doutb\(139),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      Q => \^doutb\(1),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      Q => \^doutb\(2),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3),
      Q => \^doutb\(3),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(4),
      Q => \^doutb\(4),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5),
      Q => \^doutb\(5),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(6),
      Q => \^doutb\(6),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      Q => \^doutb\(73),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(74),
      Q => \^doutb\(74),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75),
      Q => \^doutb\(75),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(76),
      Q => \^doutb\(76),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77),
      Q => \^doutb\(77),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(78),
      Q => \^doutb\(78),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79),
      Q => \^doutb\(79),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7),
      Q => \^doutb\(7),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(80),
      Q => \^doutb\(80),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81),
      Q => \^doutb\(81),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(82),
      Q => \^doutb\(82),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83),
      Q => \^doutb\(83),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(8),
      Q => \^doutb\(8),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(94),
      Q => \^doutb\(94),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95),
      Q => \^doutb\(95),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(96),
      Q => \^doutb\(96),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97),
      Q => \^doutb\(97),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(98),
      Q => \^doutb\(98),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99),
      Q => \^doutb\(99),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1) => dina(1),
      DIA(0) => '0',
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => dina(9 downto 8),
      DIF(1 downto 0) => dina(11 downto 10),
      DIG(1 downto 0) => dina(13 downto 12),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\,
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5 downto 4),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7 downto 6),
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\,
      DOE(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(8),
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\,
      DOG(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\,
      DOG(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\,
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(113 downto 112),
      DIB(1 downto 0) => dina(115 downto 114),
      DIC(1 downto 0) => dina(117 downto 116),
      DID(1 downto 0) => dina(119 downto 118),
      DIE(1 downto 0) => dina(121 downto 120),
      DIF(1 downto 0) => dina(123 downto 122),
      DIG(1 downto 0) => dina(125 downto 124),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113 downto 112),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115 downto 114),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117 downto 116),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119 downto 118),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121 downto 120),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123 downto 122),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125 downto 124),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(127 downto 126),
      DIB(1 downto 0) => dina(129 downto 128),
      DIC(1 downto 0) => dina(131 downto 130),
      DID(1 downto 0) => dina(133 downto 132),
      DIE(1 downto 0) => dina(135 downto 134),
      DIF(1 downto 0) => dina(137 downto 136),
      DIG(1 downto 0) => dina(139 downto 138),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127 downto 126),
      DOB(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_n_3\,
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131 downto 130),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133 downto 132),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135 downto 134),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137 downto 136),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139 downto 138),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(71 downto 70),
      DIB(1 downto 0) => dina(73 downto 72),
      DIC(1 downto 0) => dina(75 downto 74),
      DID(1 downto 0) => dina(77 downto 76),
      DIE(1 downto 0) => dina(79 downto 78),
      DIF(1 downto 0) => dina(81 downto 80),
      DIG(1 downto 0) => dina(83 downto 82),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_0\,
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_1\,
      DOB(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_n_3\,
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75 downto 74),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77 downto 76),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79 downto 78),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81 downto 80),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83 downto 82),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(85 downto 84),
      DIB(1 downto 0) => dina(87 downto 86),
      DIC(1 downto 0) => dina(89 downto 88),
      DID(1 downto 0) => dina(91 downto 90),
      DIE(1 downto 0) => dina(93 downto 92),
      DIF(1 downto 0) => dina(95 downto 94),
      DIG(1 downto 0) => dina(97 downto 96),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_0\,
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_1\,
      DOB(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_2\,
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_3\,
      DOC(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_4\,
      DOC(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_5\,
      DOD(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_6\,
      DOD(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_7\,
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_8\,
      DOE(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_n_9\,
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95 downto 94),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97 downto 96),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(99 downto 98),
      DIB(1 downto 0) => dina(101 downto 100),
      DIC(1 downto 0) => dina(103 downto 102),
      DID(1 downto 0) => dina(105 downto 104),
      DIE(1 downto 0) => dina(107 downto 106),
      DIF(1 downto 0) => dina(109 downto 108),
      DIG(1 downto 0) => dina(111 downto 110),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99 downto 98),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101 downto 100),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103 downto 102),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105 downto 104),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107 downto 106),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109 downto 108),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111 downto 110),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 18 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 18 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 18 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 18 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 608;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 19;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 20;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ : entity is 20;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg[2]_i_1_n_0\ : STD_LOGIC;
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_4\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_5\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_7\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_9\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 608;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \^doutb\(2);
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => \^doutb\(2),
      I1 => enb,
      I2 => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      I3 => rstb,
      O => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg[2]_i_1_n_0\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => '1',
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg[2]_i_1_n_0\,
      Q => \^doutb\(2),
      R => '0'
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1) => dina(1),
      DIA(0) => '1',
      DIB(1) => '0',
      DIB(0) => dina(2),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DIE(1 downto 0) => B"00",
      DIF(1 downto 0) => B"00",
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_0\,
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\,
      DOB(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\,
      DOB(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      DOC(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_4\,
      DOC(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_5\,
      DOD(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\,
      DOD(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_7\,
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\,
      DOE(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_9\,
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\,
      DOG(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\,
      DOG(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\,
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 159 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 159 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 159 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 159 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 5120;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ : entity is 160;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 159 downto 1 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 159 downto 1 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_4\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_5\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_7\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[140]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[141]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[143]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[144]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[145]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[146]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[147]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[148]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[149]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[14]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[150]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[151]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[152]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[153]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[154]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[155]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[156]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[157]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[158]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[159]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[15]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[16]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[17]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[42]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[43]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[44]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[45]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[46]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[47]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[48]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[50]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[51]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[52]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[54]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[55]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[57]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[58]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[59]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[60]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[61]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[62]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[63]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[64]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[65]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[66]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[67]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[68]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[69]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 5120;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 5120;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 112;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 125;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 5120;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 126;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 139;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 5120;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 140;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 153;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 5120;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 14;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 27;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159\ : label is 5120;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159\ : label is "NONE";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159\ : label is 154;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159\ : label is 159;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 5120;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 28;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 41;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 5120;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 42;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 55;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 5120;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 56;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 69;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 5120;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 70;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 83;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 5120;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 84;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 97;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 5120;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 98;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 111;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(159) <= \<const0>\;
  douta(158) <= \<const0>\;
  douta(157) <= \<const0>\;
  douta(156) <= \<const0>\;
  douta(155) <= \<const0>\;
  douta(154) <= \<const0>\;
  douta(153) <= \<const0>\;
  douta(152) <= \<const0>\;
  douta(151) <= \<const0>\;
  douta(150) <= \<const0>\;
  douta(149) <= \<const0>\;
  douta(148) <= \<const0>\;
  douta(147) <= \<const0>\;
  douta(146) <= \<const0>\;
  douta(145) <= \<const0>\;
  douta(144) <= \<const0>\;
  douta(143) <= \<const0>\;
  douta(142) <= \<const0>\;
  douta(141) <= \<const0>\;
  douta(140) <= \<const0>\;
  douta(139) <= \<const0>\;
  douta(138) <= \<const0>\;
  douta(137) <= \<const0>\;
  douta(136) <= \<const0>\;
  douta(135) <= \<const0>\;
  douta(134) <= \<const0>\;
  douta(133) <= \<const0>\;
  douta(132) <= \<const0>\;
  douta(131) <= \<const0>\;
  douta(130) <= \<const0>\;
  douta(129) <= \<const0>\;
  douta(128) <= \<const0>\;
  douta(127) <= \<const0>\;
  douta(126) <= \<const0>\;
  douta(125) <= \<const0>\;
  douta(124) <= \<const0>\;
  douta(123) <= \<const0>\;
  douta(122) <= \<const0>\;
  douta(121) <= \<const0>\;
  douta(120) <= \<const0>\;
  douta(119) <= \<const0>\;
  douta(118) <= \<const0>\;
  douta(117) <= \<const0>\;
  douta(116) <= \<const0>\;
  douta(115) <= \<const0>\;
  douta(114) <= \<const0>\;
  douta(113) <= \<const0>\;
  douta(112) <= \<const0>\;
  douta(111) <= \<const0>\;
  douta(110) <= \<const0>\;
  douta(109) <= \<const0>\;
  douta(108) <= \<const0>\;
  douta(107) <= \<const0>\;
  douta(106) <= \<const0>\;
  douta(105) <= \<const0>\;
  douta(104) <= \<const0>\;
  douta(103) <= \<const0>\;
  douta(102) <= \<const0>\;
  douta(101) <= \<const0>\;
  douta(100) <= \<const0>\;
  douta(99) <= \<const0>\;
  douta(98) <= \<const0>\;
  douta(97) <= \<const0>\;
  douta(96) <= \<const0>\;
  douta(95) <= \<const0>\;
  douta(94) <= \<const0>\;
  douta(93) <= \<const0>\;
  douta(92) <= \<const0>\;
  douta(91) <= \<const0>\;
  douta(90) <= \<const0>\;
  douta(89) <= \<const0>\;
  douta(88) <= \<const0>\;
  douta(87) <= \<const0>\;
  douta(86) <= \<const0>\;
  douta(85) <= \<const0>\;
  douta(84) <= \<const0>\;
  douta(83) <= \<const0>\;
  douta(82) <= \<const0>\;
  douta(81) <= \<const0>\;
  douta(80) <= \<const0>\;
  douta(79) <= \<const0>\;
  douta(78) <= \<const0>\;
  douta(77) <= \<const0>\;
  douta(76) <= \<const0>\;
  douta(75) <= \<const0>\;
  douta(74) <= \<const0>\;
  douta(73) <= \<const0>\;
  douta(72) <= \<const0>\;
  douta(71) <= \<const0>\;
  douta(70) <= \<const0>\;
  douta(69) <= \<const0>\;
  douta(68) <= \<const0>\;
  douta(67) <= \<const0>\;
  douta(66) <= \<const0>\;
  douta(65) <= \<const0>\;
  douta(64) <= \<const0>\;
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(159 downto 14) <= \^doutb\(159 downto 14);
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \^doutb\(8);
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \^doutb\(1);
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(100),
      Q => \^doutb\(100),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101),
      Q => \^doutb\(101),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(102),
      Q => \^doutb\(102),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103),
      Q => \^doutb\(103),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(104),
      Q => \^doutb\(104),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105),
      Q => \^doutb\(105),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(106),
      Q => \^doutb\(106),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107),
      Q => \^doutb\(107),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(108),
      Q => \^doutb\(108),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109),
      Q => \^doutb\(109),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(110),
      Q => \^doutb\(110),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111),
      Q => \^doutb\(111),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(112),
      Q => \^doutb\(112),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113),
      Q => \^doutb\(113),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(114),
      Q => \^doutb\(114),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115),
      Q => \^doutb\(115),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(116),
      Q => \^doutb\(116),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117),
      Q => \^doutb\(117),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(118),
      Q => \^doutb\(118),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119),
      Q => \^doutb\(119),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(120),
      Q => \^doutb\(120),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121),
      Q => \^doutb\(121),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(122),
      Q => \^doutb\(122),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123),
      Q => \^doutb\(123),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(124),
      Q => \^doutb\(124),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125),
      Q => \^doutb\(125),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(126),
      Q => \^doutb\(126),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127),
      Q => \^doutb\(127),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(128),
      Q => \^doutb\(128),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      Q => \^doutb\(129),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(130),
      Q => \^doutb\(130),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131),
      Q => \^doutb\(131),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(132),
      Q => \^doutb\(132),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133),
      Q => \^doutb\(133),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(134),
      Q => \^doutb\(134),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135),
      Q => \^doutb\(135),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(136),
      Q => \^doutb\(136),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137),
      Q => \^doutb\(137),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(138),
      Q => \^doutb\(138),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139),
      Q => \^doutb\(139),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[140]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(140),
      Q => \^doutb\(140),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[141]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(141),
      Q => \^doutb\(141),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(142),
      Q => \^doutb\(142),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[143]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(143),
      Q => \^doutb\(143),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[144]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(144),
      Q => \^doutb\(144),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[145]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(145),
      Q => \^doutb\(145),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[146]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(146),
      Q => \^doutb\(146),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[147]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(147),
      Q => \^doutb\(147),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[148]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(148),
      Q => \^doutb\(148),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[149]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(149),
      Q => \^doutb\(149),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(14),
      Q => \^doutb\(14),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[150]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(150),
      Q => \^doutb\(150),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[151]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(151),
      Q => \^doutb\(151),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[152]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(152),
      Q => \^doutb\(152),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[153]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(153),
      Q => \^doutb\(153),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[154]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(154),
      Q => \^doutb\(154),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[155]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(155),
      Q => \^doutb\(155),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[156]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(156),
      Q => \^doutb\(156),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[157]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(157),
      Q => \^doutb\(157),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[158]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(158),
      Q => \^doutb\(158),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[159]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(159),
      Q => \^doutb\(159),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(15),
      Q => \^doutb\(15),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(16),
      Q => \^doutb\(16),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(17),
      Q => \^doutb\(17),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(18),
      Q => \^doutb\(18),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19),
      Q => \^doutb\(19),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      Q => \^doutb\(1),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(20),
      Q => \^doutb\(20),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21),
      Q => \^doutb\(21),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(22),
      Q => \^doutb\(22),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23),
      Q => \^doutb\(23),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(24),
      Q => \^doutb\(24),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25),
      Q => \^doutb\(25),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(26),
      Q => \^doutb\(26),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27),
      Q => \^doutb\(27),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(28),
      Q => \^doutb\(28),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29),
      Q => \^doutb\(29),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(30),
      Q => \^doutb\(30),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31),
      Q => \^doutb\(31),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(32),
      Q => \^doutb\(32),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33),
      Q => \^doutb\(33),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(34),
      Q => \^doutb\(34),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35),
      Q => \^doutb\(35),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(36),
      Q => \^doutb\(36),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37),
      Q => \^doutb\(37),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(38),
      Q => \^doutb\(38),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39),
      Q => \^doutb\(39),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(40),
      Q => \^doutb\(40),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41),
      Q => \^doutb\(41),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(42),
      Q => \^doutb\(42),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(43),
      Q => \^doutb\(43),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(44),
      Q => \^doutb\(44),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(45),
      Q => \^doutb\(45),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(46),
      Q => \^doutb\(46),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(47),
      Q => \^doutb\(47),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(48),
      Q => \^doutb\(48),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(49),
      Q => \^doutb\(49),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(50),
      Q => \^doutb\(50),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(51),
      Q => \^doutb\(51),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(52),
      Q => \^doutb\(52),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(53),
      Q => \^doutb\(53),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(54),
      Q => \^doutb\(54),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(55),
      Q => \^doutb\(55),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(56),
      Q => \^doutb\(56),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(57),
      Q => \^doutb\(57),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(58),
      Q => \^doutb\(58),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(59),
      Q => \^doutb\(59),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(60),
      Q => \^doutb\(60),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(61),
      Q => \^doutb\(61),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(62),
      Q => \^doutb\(62),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(63),
      Q => \^doutb\(63),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[64]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(64),
      Q => \^doutb\(64),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[65]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(65),
      Q => \^doutb\(65),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[66]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(66),
      Q => \^doutb\(66),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[67]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(67),
      Q => \^doutb\(67),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[68]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(68),
      Q => \^doutb\(68),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[69]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(69),
      Q => \^doutb\(69),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(70),
      Q => \^doutb\(70),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71),
      Q => \^doutb\(71),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(72),
      Q => \^doutb\(72),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      Q => \^doutb\(73),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(74),
      Q => \^doutb\(74),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75),
      Q => \^doutb\(75),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(76),
      Q => \^doutb\(76),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77),
      Q => \^doutb\(77),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(78),
      Q => \^doutb\(78),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79),
      Q => \^doutb\(79),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(80),
      Q => \^doutb\(80),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81),
      Q => \^doutb\(81),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(82),
      Q => \^doutb\(82),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83),
      Q => \^doutb\(83),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(84),
      Q => \^doutb\(84),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85),
      Q => \^doutb\(85),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(86),
      Q => \^doutb\(86),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87),
      Q => \^doutb\(87),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(88),
      Q => \^doutb\(88),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89),
      Q => \^doutb\(89),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(8),
      Q => \^doutb\(8),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(90),
      Q => \^doutb\(90),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91),
      Q => \^doutb\(91),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(92),
      Q => \^doutb\(92),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93),
      Q => \^doutb\(93),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(94),
      Q => \^doutb\(94),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95),
      Q => \^doutb\(95),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(96),
      Q => \^doutb\(96),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97),
      Q => \^doutb\(97),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(98),
      Q => \^doutb\(98),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99),
      Q => \^doutb\(99),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1) => dina(1),
      DIA(0) => '0',
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => dina(9 downto 8),
      DIF(1 downto 0) => dina(11 downto 10),
      DIG(1 downto 0) => dina(13 downto 12),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\,
      DOB(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\,
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_3\,
      DOC(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_4\,
      DOC(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_5\,
      DOD(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\,
      DOD(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_7\,
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\,
      DOE(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(8),
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\,
      DOG(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\,
      DOG(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\,
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(113 downto 112),
      DIB(1 downto 0) => dina(115 downto 114),
      DIC(1 downto 0) => dina(117 downto 116),
      DID(1 downto 0) => dina(119 downto 118),
      DIE(1 downto 0) => dina(121 downto 120),
      DIF(1 downto 0) => dina(123 downto 122),
      DIG(1 downto 0) => dina(125 downto 124),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113 downto 112),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115 downto 114),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117 downto 116),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119 downto 118),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121 downto 120),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123 downto 122),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125 downto 124),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(127 downto 126),
      DIB(1 downto 0) => dina(129 downto 128),
      DIC(1 downto 0) => dina(131 downto 130),
      DID(1 downto 0) => dina(133 downto 132),
      DIE(1 downto 0) => dina(135 downto 134),
      DIF(1 downto 0) => dina(137 downto 136),
      DIG(1 downto 0) => dina(139 downto 138),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127 downto 126),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129 downto 128),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131 downto 130),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133 downto 132),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135 downto 134),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137 downto 136),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139 downto 138),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(141 downto 140),
      DIB(1 downto 0) => dina(143 downto 142),
      DIC(1 downto 0) => dina(145 downto 144),
      DID(1 downto 0) => dina(147 downto 146),
      DIE(1 downto 0) => dina(149 downto 148),
      DIF(1 downto 0) => dina(151 downto 150),
      DIG(1 downto 0) => dina(153 downto 152),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(141 downto 140),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(143 downto 142),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(145 downto 144),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(147 downto 146),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(149 downto 148),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(151 downto 150),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(153 downto 152),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(15 downto 14),
      DIB(1 downto 0) => dina(17 downto 16),
      DIC(1 downto 0) => dina(19 downto 18),
      DID(1 downto 0) => dina(21 downto 20),
      DIE(1 downto 0) => dina(23 downto 22),
      DIF(1 downto 0) => dina(25 downto 24),
      DIG(1 downto 0) => dina(27 downto 26),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(15 downto 14),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(17 downto 16),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19 downto 18),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21 downto 20),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23 downto 22),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25 downto 24),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27 downto 26),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(155 downto 154),
      DIB(1 downto 0) => dina(157 downto 156),
      DIC(1 downto 0) => dina(159 downto 158),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(155 downto 154),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(157 downto 156),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(159 downto 158),
      DOD(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_154_159_DOD_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(29 downto 28),
      DIB(1 downto 0) => dina(31 downto 30),
      DIC(1 downto 0) => dina(33 downto 32),
      DID(1 downto 0) => dina(35 downto 34),
      DIE(1 downto 0) => dina(37 downto 36),
      DIF(1 downto 0) => dina(39 downto 38),
      DIG(1 downto 0) => dina(41 downto 40),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29 downto 28),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31 downto 30),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33 downto 32),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35 downto 34),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37 downto 36),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39 downto 38),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41 downto 40),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(43 downto 42),
      DIB(1 downto 0) => dina(45 downto 44),
      DIC(1 downto 0) => dina(47 downto 46),
      DID(1 downto 0) => dina(49 downto 48),
      DIE(1 downto 0) => dina(51 downto 50),
      DIF(1 downto 0) => dina(53 downto 52),
      DIG(1 downto 0) => dina(55 downto 54),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(43 downto 42),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(45 downto 44),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(47 downto 46),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(49 downto 48),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(51 downto 50),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(53 downto 52),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(55 downto 54),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(57 downto 56),
      DIB(1 downto 0) => dina(59 downto 58),
      DIC(1 downto 0) => dina(61 downto 60),
      DID(1 downto 0) => dina(63 downto 62),
      DIE(1 downto 0) => dina(65 downto 64),
      DIF(1 downto 0) => dina(67 downto 66),
      DIG(1 downto 0) => dina(69 downto 68),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(57 downto 56),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(59 downto 58),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(61 downto 60),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(63 downto 62),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(65 downto 64),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(67 downto 66),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(69 downto 68),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(71 downto 70),
      DIB(1 downto 0) => dina(73 downto 72),
      DIC(1 downto 0) => dina(75 downto 74),
      DID(1 downto 0) => dina(77 downto 76),
      DIE(1 downto 0) => dina(79 downto 78),
      DIF(1 downto 0) => dina(81 downto 80),
      DIG(1 downto 0) => dina(83 downto 82),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71 downto 70),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73 downto 72),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75 downto 74),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77 downto 76),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79 downto 78),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81 downto 80),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83 downto 82),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(85 downto 84),
      DIB(1 downto 0) => dina(87 downto 86),
      DIC(1 downto 0) => dina(89 downto 88),
      DID(1 downto 0) => dina(91 downto 90),
      DIE(1 downto 0) => dina(93 downto 92),
      DIF(1 downto 0) => dina(95 downto 94),
      DIG(1 downto 0) => dina(97 downto 96),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85 downto 84),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87 downto 86),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89 downto 88),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91 downto 90),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93 downto 92),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95 downto 94),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97 downto 96),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(99 downto 98),
      DIB(1 downto 0) => dina(101 downto 100),
      DIC(1 downto 0) => dina(103 downto 102),
      DID(1 downto 0) => dina(105 downto 104),
      DIE(1 downto 0) => dina(107 downto 106),
      DIF(1 downto 0) => dina(109 downto 108),
      DIG(1 downto 0) => dina(111 downto 110),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99 downto 98),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101 downto 100),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103 downto 102),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105 downto 104),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107 downto 106),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109 downto 108),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111 downto 110),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 18 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 18 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 18 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 18 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 608;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 19;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 20;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ : entity is 20;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_4\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_5\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_7\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_9\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 608;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2 downto 1) <= \^doutb\(2 downto 1);
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      Q => \^doutb\(1),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      Q => \^doutb\(2),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(1 downto 0),
      DIB(1) => '0',
      DIB(0) => dina(2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => B"00",
      DIE(1 downto 0) => B"00",
      DIF(1 downto 0) => B"00",
      DIG(1) => '0',
      DIG(0) => dina(12),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\,
      DOB(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\,
      DOB(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      DOC(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_4\,
      DOC(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_5\,
      DOD(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\,
      DOD(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_7\,
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\,
      DOE(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_9\,
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\,
      DOG(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\,
      DOG(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\,
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 6 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 6 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 6 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 6 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 224;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 7;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 8;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ : entity is 8;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_n_1\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_DOE_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_DOF_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_DOG_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6\ : label is 224;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6\ : label is 6;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(6 downto 1) <= \^doutb\(6 downto 1);
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      Q => \^doutb\(1),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      Q => \^doutb\(2),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3),
      Q => \^doutb\(3),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(4),
      Q => \^doutb\(4),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5),
      Q => \^doutb\(5),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(6),
      Q => \^doutb\(6),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => dina(3),
      DIB(0) => '0',
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1) => '0',
      DID(0) => dina(6),
      DIE(1 downto 0) => B"00",
      DIF(1 downto 0) => B"00",
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_n_1\,
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5 downto 4),
      DOD(1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_DOD_UNCONNECTED\(1),
      DOD(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(6),
      DOE(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_DOE_UNCONNECTED\(1 downto 0),
      DOF(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_DOF_UNCONNECTED\(1 downto 0),
      DOG(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_DOG_UNCONNECTED\(1 downto 0),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_6_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 148 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 148 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 148 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 148 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 4768;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 149;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 152;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ : entity is 152;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 148 downto 4 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 148 downto 4 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_7\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_9\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148_DOE_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148_DOF_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148_DOG_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[140]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[141]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[143]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[144]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[145]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[146]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[147]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[148]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[14]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[15]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[16]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[17]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[42]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[43]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[44]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[45]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[46]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[47]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[48]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[50]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[51]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[52]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[54]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[55]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[57]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[58]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[59]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[60]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[61]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[62]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[63]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[64]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[65]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[66]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[67]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[68]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[69]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 4768;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 4768;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 112;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 125;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 4768;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 126;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 139;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148\ : label is 4768;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148\ : label is 140;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148\ : label is 148;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 4768;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 14;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 27;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 4768;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 28;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 41;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 4768;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 42;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 55;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 4768;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 56;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 69;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 4768;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 70;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 83;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 4768;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 84;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 97;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 4768;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 98;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 111;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(148) <= \<const0>\;
  douta(147) <= \<const0>\;
  douta(146) <= \<const0>\;
  douta(145) <= \<const0>\;
  douta(144) <= \<const0>\;
  douta(143) <= \<const0>\;
  douta(142) <= \<const0>\;
  douta(141) <= \<const0>\;
  douta(140) <= \<const0>\;
  douta(139) <= \<const0>\;
  douta(138) <= \<const0>\;
  douta(137) <= \<const0>\;
  douta(136) <= \<const0>\;
  douta(135) <= \<const0>\;
  douta(134) <= \<const0>\;
  douta(133) <= \<const0>\;
  douta(132) <= \<const0>\;
  douta(131) <= \<const0>\;
  douta(130) <= \<const0>\;
  douta(129) <= \<const0>\;
  douta(128) <= \<const0>\;
  douta(127) <= \<const0>\;
  douta(126) <= \<const0>\;
  douta(125) <= \<const0>\;
  douta(124) <= \<const0>\;
  douta(123) <= \<const0>\;
  douta(122) <= \<const0>\;
  douta(121) <= \<const0>\;
  douta(120) <= \<const0>\;
  douta(119) <= \<const0>\;
  douta(118) <= \<const0>\;
  douta(117) <= \<const0>\;
  douta(116) <= \<const0>\;
  douta(115) <= \<const0>\;
  douta(114) <= \<const0>\;
  douta(113) <= \<const0>\;
  douta(112) <= \<const0>\;
  douta(111) <= \<const0>\;
  douta(110) <= \<const0>\;
  douta(109) <= \<const0>\;
  douta(108) <= \<const0>\;
  douta(107) <= \<const0>\;
  douta(106) <= \<const0>\;
  douta(105) <= \<const0>\;
  douta(104) <= \<const0>\;
  douta(103) <= \<const0>\;
  douta(102) <= \<const0>\;
  douta(101) <= \<const0>\;
  douta(100) <= \<const0>\;
  douta(99) <= \<const0>\;
  douta(98) <= \<const0>\;
  douta(97) <= \<const0>\;
  douta(96) <= \<const0>\;
  douta(95) <= \<const0>\;
  douta(94) <= \<const0>\;
  douta(93) <= \<const0>\;
  douta(92) <= \<const0>\;
  douta(91) <= \<const0>\;
  douta(90) <= \<const0>\;
  douta(89) <= \<const0>\;
  douta(88) <= \<const0>\;
  douta(87) <= \<const0>\;
  douta(86) <= \<const0>\;
  douta(85) <= \<const0>\;
  douta(84) <= \<const0>\;
  douta(83) <= \<const0>\;
  douta(82) <= \<const0>\;
  douta(81) <= \<const0>\;
  douta(80) <= \<const0>\;
  douta(79) <= \<const0>\;
  douta(78) <= \<const0>\;
  douta(77) <= \<const0>\;
  douta(76) <= \<const0>\;
  douta(75) <= \<const0>\;
  douta(74) <= \<const0>\;
  douta(73) <= \<const0>\;
  douta(72) <= \<const0>\;
  douta(71) <= \<const0>\;
  douta(70) <= \<const0>\;
  douta(69) <= \<const0>\;
  douta(68) <= \<const0>\;
  douta(67) <= \<const0>\;
  douta(66) <= \<const0>\;
  douta(65) <= \<const0>\;
  douta(64) <= \<const0>\;
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(148 downto 14) <= \^doutb\(148 downto 14);
  doutb(13) <= \<const0>\;
  doutb(12 downto 11) <= \^doutb\(12 downto 11);
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5 downto 4) <= \^doutb\(5 downto 4);
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(100),
      Q => \^doutb\(100),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101),
      Q => \^doutb\(101),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(102),
      Q => \^doutb\(102),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103),
      Q => \^doutb\(103),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(104),
      Q => \^doutb\(104),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105),
      Q => \^doutb\(105),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(106),
      Q => \^doutb\(106),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107),
      Q => \^doutb\(107),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(108),
      Q => \^doutb\(108),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109),
      Q => \^doutb\(109),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(110),
      Q => \^doutb\(110),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111),
      Q => \^doutb\(111),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(112),
      Q => \^doutb\(112),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113),
      Q => \^doutb\(113),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(114),
      Q => \^doutb\(114),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115),
      Q => \^doutb\(115),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(116),
      Q => \^doutb\(116),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117),
      Q => \^doutb\(117),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(118),
      Q => \^doutb\(118),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119),
      Q => \^doutb\(119),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11),
      Q => \^doutb\(11),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(120),
      Q => \^doutb\(120),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121),
      Q => \^doutb\(121),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(122),
      Q => \^doutb\(122),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123),
      Q => \^doutb\(123),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(124),
      Q => \^doutb\(124),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125),
      Q => \^doutb\(125),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(126),
      Q => \^doutb\(126),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127),
      Q => \^doutb\(127),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(128),
      Q => \^doutb\(128),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      Q => \^doutb\(129),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(12),
      Q => \^doutb\(12),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(130),
      Q => \^doutb\(130),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131),
      Q => \^doutb\(131),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(132),
      Q => \^doutb\(132),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133),
      Q => \^doutb\(133),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(134),
      Q => \^doutb\(134),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135),
      Q => \^doutb\(135),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(136),
      Q => \^doutb\(136),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137),
      Q => \^doutb\(137),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(138),
      Q => \^doutb\(138),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139),
      Q => \^doutb\(139),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[140]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(140),
      Q => \^doutb\(140),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[141]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(141),
      Q => \^doutb\(141),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(142),
      Q => \^doutb\(142),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[143]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(143),
      Q => \^doutb\(143),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[144]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(144),
      Q => \^doutb\(144),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[145]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(145),
      Q => \^doutb\(145),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[146]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(146),
      Q => \^doutb\(146),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[147]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(147),
      Q => \^doutb\(147),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[148]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(148),
      Q => \^doutb\(148),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(14),
      Q => \^doutb\(14),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(15),
      Q => \^doutb\(15),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(16),
      Q => \^doutb\(16),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(17),
      Q => \^doutb\(17),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(18),
      Q => \^doutb\(18),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19),
      Q => \^doutb\(19),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(20),
      Q => \^doutb\(20),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21),
      Q => \^doutb\(21),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(22),
      Q => \^doutb\(22),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23),
      Q => \^doutb\(23),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(24),
      Q => \^doutb\(24),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25),
      Q => \^doutb\(25),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(26),
      Q => \^doutb\(26),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27),
      Q => \^doutb\(27),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(28),
      Q => \^doutb\(28),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29),
      Q => \^doutb\(29),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(30),
      Q => \^doutb\(30),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31),
      Q => \^doutb\(31),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(32),
      Q => \^doutb\(32),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33),
      Q => \^doutb\(33),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(34),
      Q => \^doutb\(34),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35),
      Q => \^doutb\(35),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(36),
      Q => \^doutb\(36),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37),
      Q => \^doutb\(37),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(38),
      Q => \^doutb\(38),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39),
      Q => \^doutb\(39),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(40),
      Q => \^doutb\(40),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41),
      Q => \^doutb\(41),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(42),
      Q => \^doutb\(42),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(43),
      Q => \^doutb\(43),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(44),
      Q => \^doutb\(44),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(45),
      Q => \^doutb\(45),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(46),
      Q => \^doutb\(46),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(47),
      Q => \^doutb\(47),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(48),
      Q => \^doutb\(48),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(49),
      Q => \^doutb\(49),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(4),
      Q => \^doutb\(4),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(50),
      Q => \^doutb\(50),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(51),
      Q => \^doutb\(51),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(52),
      Q => \^doutb\(52),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(53),
      Q => \^doutb\(53),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(54),
      Q => \^doutb\(54),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(55),
      Q => \^doutb\(55),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(56),
      Q => \^doutb\(56),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(57),
      Q => \^doutb\(57),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(58),
      Q => \^doutb\(58),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(59),
      Q => \^doutb\(59),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5),
      Q => \^doutb\(5),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(60),
      Q => \^doutb\(60),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(61),
      Q => \^doutb\(61),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(62),
      Q => \^doutb\(62),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(63),
      Q => \^doutb\(63),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[64]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(64),
      Q => \^doutb\(64),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[65]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(65),
      Q => \^doutb\(65),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[66]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(66),
      Q => \^doutb\(66),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[67]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(67),
      Q => \^doutb\(67),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[68]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(68),
      Q => \^doutb\(68),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[69]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(69),
      Q => \^doutb\(69),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(70),
      Q => \^doutb\(70),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71),
      Q => \^doutb\(71),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(72),
      Q => \^doutb\(72),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      Q => \^doutb\(73),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(74),
      Q => \^doutb\(74),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75),
      Q => \^doutb\(75),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(76),
      Q => \^doutb\(76),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77),
      Q => \^doutb\(77),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(78),
      Q => \^doutb\(78),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79),
      Q => \^doutb\(79),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(80),
      Q => \^doutb\(80),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81),
      Q => \^doutb\(81),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(82),
      Q => \^doutb\(82),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83),
      Q => \^doutb\(83),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(84),
      Q => \^doutb\(84),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85),
      Q => \^doutb\(85),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(86),
      Q => \^doutb\(86),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87),
      Q => \^doutb\(87),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(88),
      Q => \^doutb\(88),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89),
      Q => \^doutb\(89),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(90),
      Q => \^doutb\(90),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91),
      Q => \^doutb\(91),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(92),
      Q => \^doutb\(92),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93),
      Q => \^doutb\(93),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(94),
      Q => \^doutb\(94),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95),
      Q => \^doutb\(95),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(96),
      Q => \^doutb\(96),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97),
      Q => \^doutb\(97),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(98),
      Q => \^doutb\(98),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99),
      Q => \^doutb\(99),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => dina(9 downto 8),
      DIF(1 downto 0) => dina(11 downto 10),
      DIG(1 downto 0) => dina(13 downto 12),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_0\,
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\,
      DOB(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\,
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_3\,
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5 downto 4),
      DOD(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\,
      DOD(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_7\,
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\,
      DOE(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_9\,
      DOF(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11),
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\,
      DOG(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\,
      DOG(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(12),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(113 downto 112),
      DIB(1 downto 0) => dina(115 downto 114),
      DIC(1 downto 0) => dina(117 downto 116),
      DID(1 downto 0) => dina(119 downto 118),
      DIE(1 downto 0) => dina(121 downto 120),
      DIF(1 downto 0) => dina(123 downto 122),
      DIG(1 downto 0) => dina(125 downto 124),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113 downto 112),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115 downto 114),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117 downto 116),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119 downto 118),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121 downto 120),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123 downto 122),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125 downto 124),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(127 downto 126),
      DIB(1 downto 0) => dina(129 downto 128),
      DIC(1 downto 0) => dina(131 downto 130),
      DID(1 downto 0) => dina(133 downto 132),
      DIE(1 downto 0) => dina(135 downto 134),
      DIF(1 downto 0) => dina(137 downto 136),
      DIG(1 downto 0) => dina(139 downto 138),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127 downto 126),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129 downto 128),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131 downto 130),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133 downto 132),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135 downto 134),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137 downto 136),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139 downto 138),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(141 downto 140),
      DIB(1 downto 0) => dina(143 downto 142),
      DIC(1 downto 0) => dina(145 downto 144),
      DID(1 downto 0) => dina(147 downto 146),
      DIE(1) => '0',
      DIE(0) => dina(148),
      DIF(1 downto 0) => B"00",
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(141 downto 140),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(143 downto 142),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(145 downto 144),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(147 downto 146),
      DOE(1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148_DOE_UNCONNECTED\(1),
      DOE(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(148),
      DOF(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148_DOF_UNCONNECTED\(1 downto 0),
      DOG(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148_DOG_UNCONNECTED\(1 downto 0),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_148_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(15 downto 14),
      DIB(1 downto 0) => dina(17 downto 16),
      DIC(1 downto 0) => dina(19 downto 18),
      DID(1 downto 0) => dina(21 downto 20),
      DIE(1 downto 0) => dina(23 downto 22),
      DIF(1 downto 0) => dina(25 downto 24),
      DIG(1 downto 0) => dina(27 downto 26),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(15 downto 14),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(17 downto 16),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19 downto 18),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21 downto 20),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23 downto 22),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25 downto 24),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27 downto 26),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(29 downto 28),
      DIB(1 downto 0) => dina(31 downto 30),
      DIC(1 downto 0) => dina(33 downto 32),
      DID(1 downto 0) => dina(35 downto 34),
      DIE(1 downto 0) => dina(37 downto 36),
      DIF(1 downto 0) => dina(39 downto 38),
      DIG(1 downto 0) => dina(41 downto 40),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29 downto 28),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31 downto 30),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33 downto 32),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35 downto 34),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37 downto 36),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39 downto 38),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41 downto 40),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(43 downto 42),
      DIB(1 downto 0) => dina(45 downto 44),
      DIC(1 downto 0) => dina(47 downto 46),
      DID(1 downto 0) => dina(49 downto 48),
      DIE(1 downto 0) => dina(51 downto 50),
      DIF(1 downto 0) => dina(53 downto 52),
      DIG(1 downto 0) => dina(55 downto 54),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(43 downto 42),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(45 downto 44),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(47 downto 46),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(49 downto 48),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(51 downto 50),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(53 downto 52),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(55 downto 54),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(57 downto 56),
      DIB(1 downto 0) => dina(59 downto 58),
      DIC(1 downto 0) => dina(61 downto 60),
      DID(1 downto 0) => dina(63 downto 62),
      DIE(1 downto 0) => dina(65 downto 64),
      DIF(1 downto 0) => dina(67 downto 66),
      DIG(1 downto 0) => dina(69 downto 68),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(57 downto 56),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(59 downto 58),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(61 downto 60),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(63 downto 62),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(65 downto 64),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(67 downto 66),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(69 downto 68),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(71 downto 70),
      DIB(1 downto 0) => dina(73 downto 72),
      DIC(1 downto 0) => dina(75 downto 74),
      DID(1 downto 0) => dina(77 downto 76),
      DIE(1 downto 0) => dina(79 downto 78),
      DIF(1 downto 0) => dina(81 downto 80),
      DIG(1 downto 0) => dina(83 downto 82),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71 downto 70),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73 downto 72),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75 downto 74),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77 downto 76),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79 downto 78),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81 downto 80),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83 downto 82),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(85 downto 84),
      DIB(1 downto 0) => dina(87 downto 86),
      DIC(1 downto 0) => dina(89 downto 88),
      DID(1 downto 0) => dina(91 downto 90),
      DIE(1 downto 0) => dina(93 downto 92),
      DIF(1 downto 0) => dina(95 downto 94),
      DIG(1 downto 0) => dina(97 downto 96),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85 downto 84),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87 downto 86),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89 downto 88),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91 downto 90),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93 downto 92),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95 downto 94),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97 downto 96),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(99 downto 98),
      DIB(1 downto 0) => dina(101 downto 100),
      DIC(1 downto 0) => dina(103 downto 102),
      DID(1 downto 0) => dina(105 downto 104),
      DIE(1 downto 0) => dina(107 downto 106),
      DIF(1 downto 0) => dina(109 downto 108),
      DIG(1 downto 0) => dina(111 downto 110),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99 downto 98),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101 downto 100),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103 downto 102),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105 downto 104),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107 downto 106),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109 downto 108),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111 downto 110),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 0 to 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 0 to 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 0 to 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 0 to 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 2;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 2;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 4;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 4;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 5;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 2;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 2;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 2;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 2;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 4;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ : entity is 4;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\ is
  signal \<const0>\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0_SPO_UNCONNECTED\ : STD_LOGIC;
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\ : label is 4;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\ : label is "RAM_TDP";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\ : label is "RAM16X1D";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\ : label is "GND:DPRA4,A4";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\ : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\ : label is 0;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0\: unisim.vcomponents.RAM32X1D
    generic map(
      INIT => X"00000000"
    )
        port map (
      A0 => addra(0),
      A1 => addra(1),
      A2 => '0',
      A3 => '0',
      A4 => '0',
      D => dina(0),
      DPO => doutb(0),
      DPRA0 => addrb(0),
      DPRA1 => addrb(1),
      DPRA2 => '0',
      DPRA3 => '0',
      DPRA4 => '0',
      SPO => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_0_0_SPO_UNCONNECTED\,
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 177 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 177 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 177 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 177 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 5696;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 178;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 180;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ : entity is 180;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 159 downto 15 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 159 downto 15 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_12\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_13\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_6\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_7\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_9\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[140]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[141]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[143]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[144]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[145]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[146]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[147]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[148]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[149]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[150]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[151]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[152]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[153]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[154]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[155]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[156]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[157]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[158]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[159]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[15]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[16]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[17]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[42]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[43]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[44]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[45]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[46]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[47]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[48]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[50]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[51]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[52]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[54]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[55]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[57]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[58]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[59]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[60]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[61]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[62]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[63]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[64]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[65]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[66]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[67]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[68]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[69]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 5696;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 112;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 125;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 5696;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 126;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 139;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 5696;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 140;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 153;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 5696;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 14;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 27;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 5696;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 154;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 167;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 5696;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 28;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 41;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 5696;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 42;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 55;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 5696;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 56;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 69;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 5696;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 70;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 83;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 5696;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 84;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 97;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 5696;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 98;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 111;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(177) <= \<const0>\;
  douta(176) <= \<const0>\;
  douta(175) <= \<const0>\;
  douta(174) <= \<const0>\;
  douta(173) <= \<const0>\;
  douta(172) <= \<const0>\;
  douta(171) <= \<const0>\;
  douta(170) <= \<const0>\;
  douta(169) <= \<const0>\;
  douta(168) <= \<const0>\;
  douta(167) <= \<const0>\;
  douta(166) <= \<const0>\;
  douta(165) <= \<const0>\;
  douta(164) <= \<const0>\;
  douta(163) <= \<const0>\;
  douta(162) <= \<const0>\;
  douta(161) <= \<const0>\;
  douta(160) <= \<const0>\;
  douta(159) <= \<const0>\;
  douta(158) <= \<const0>\;
  douta(157) <= \<const0>\;
  douta(156) <= \<const0>\;
  douta(155) <= \<const0>\;
  douta(154) <= \<const0>\;
  douta(153) <= \<const0>\;
  douta(152) <= \<const0>\;
  douta(151) <= \<const0>\;
  douta(150) <= \<const0>\;
  douta(149) <= \<const0>\;
  douta(148) <= \<const0>\;
  douta(147) <= \<const0>\;
  douta(146) <= \<const0>\;
  douta(145) <= \<const0>\;
  douta(144) <= \<const0>\;
  douta(143) <= \<const0>\;
  douta(142) <= \<const0>\;
  douta(141) <= \<const0>\;
  douta(140) <= \<const0>\;
  douta(139) <= \<const0>\;
  douta(138) <= \<const0>\;
  douta(137) <= \<const0>\;
  douta(136) <= \<const0>\;
  douta(135) <= \<const0>\;
  douta(134) <= \<const0>\;
  douta(133) <= \<const0>\;
  douta(132) <= \<const0>\;
  douta(131) <= \<const0>\;
  douta(130) <= \<const0>\;
  douta(129) <= \<const0>\;
  douta(128) <= \<const0>\;
  douta(127) <= \<const0>\;
  douta(126) <= \<const0>\;
  douta(125) <= \<const0>\;
  douta(124) <= \<const0>\;
  douta(123) <= \<const0>\;
  douta(122) <= \<const0>\;
  douta(121) <= \<const0>\;
  douta(120) <= \<const0>\;
  douta(119) <= \<const0>\;
  douta(118) <= \<const0>\;
  douta(117) <= \<const0>\;
  douta(116) <= \<const0>\;
  douta(115) <= \<const0>\;
  douta(114) <= \<const0>\;
  douta(113) <= \<const0>\;
  douta(112) <= \<const0>\;
  douta(111) <= \<const0>\;
  douta(110) <= \<const0>\;
  douta(109) <= \<const0>\;
  douta(108) <= \<const0>\;
  douta(107) <= \<const0>\;
  douta(106) <= \<const0>\;
  douta(105) <= \<const0>\;
  douta(104) <= \<const0>\;
  douta(103) <= \<const0>\;
  douta(102) <= \<const0>\;
  douta(101) <= \<const0>\;
  douta(100) <= \<const0>\;
  douta(99) <= \<const0>\;
  douta(98) <= \<const0>\;
  douta(97) <= \<const0>\;
  douta(96) <= \<const0>\;
  douta(95) <= \<const0>\;
  douta(94) <= \<const0>\;
  douta(93) <= \<const0>\;
  douta(92) <= \<const0>\;
  douta(91) <= \<const0>\;
  douta(90) <= \<const0>\;
  douta(89) <= \<const0>\;
  douta(88) <= \<const0>\;
  douta(87) <= \<const0>\;
  douta(86) <= \<const0>\;
  douta(85) <= \<const0>\;
  douta(84) <= \<const0>\;
  douta(83) <= \<const0>\;
  douta(82) <= \<const0>\;
  douta(81) <= \<const0>\;
  douta(80) <= \<const0>\;
  douta(79) <= \<const0>\;
  douta(78) <= \<const0>\;
  douta(77) <= \<const0>\;
  douta(76) <= \<const0>\;
  douta(75) <= \<const0>\;
  douta(74) <= \<const0>\;
  douta(73) <= \<const0>\;
  douta(72) <= \<const0>\;
  douta(71) <= \<const0>\;
  douta(70) <= \<const0>\;
  douta(69) <= \<const0>\;
  douta(68) <= \<const0>\;
  douta(67) <= \<const0>\;
  douta(66) <= \<const0>\;
  douta(65) <= \<const0>\;
  douta(64) <= \<const0>\;
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(177) <= \<const0>\;
  doutb(176) <= \<const0>\;
  doutb(175) <= \<const0>\;
  doutb(174) <= \<const0>\;
  doutb(173) <= \<const0>\;
  doutb(172) <= \<const0>\;
  doutb(171) <= \<const0>\;
  doutb(170) <= \<const0>\;
  doutb(169) <= \<const0>\;
  doutb(168) <= \<const0>\;
  doutb(167) <= \<const0>\;
  doutb(166) <= \<const0>\;
  doutb(165) <= \<const0>\;
  doutb(164) <= \<const0>\;
  doutb(163) <= \<const0>\;
  doutb(162) <= \<const0>\;
  doutb(161) <= \<const0>\;
  doutb(160) <= \<const0>\;
  doutb(159 downto 15) <= \^doutb\(159 downto 15);
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(100),
      Q => \^doutb\(100),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101),
      Q => \^doutb\(101),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(102),
      Q => \^doutb\(102),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103),
      Q => \^doutb\(103),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(104),
      Q => \^doutb\(104),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105),
      Q => \^doutb\(105),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(106),
      Q => \^doutb\(106),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107),
      Q => \^doutb\(107),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(108),
      Q => \^doutb\(108),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109),
      Q => \^doutb\(109),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(110),
      Q => \^doutb\(110),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111),
      Q => \^doutb\(111),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(112),
      Q => \^doutb\(112),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113),
      Q => \^doutb\(113),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(114),
      Q => \^doutb\(114),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115),
      Q => \^doutb\(115),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(116),
      Q => \^doutb\(116),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117),
      Q => \^doutb\(117),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(118),
      Q => \^doutb\(118),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119),
      Q => \^doutb\(119),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(120),
      Q => \^doutb\(120),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121),
      Q => \^doutb\(121),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(122),
      Q => \^doutb\(122),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123),
      Q => \^doutb\(123),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(124),
      Q => \^doutb\(124),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125),
      Q => \^doutb\(125),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(126),
      Q => \^doutb\(126),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127),
      Q => \^doutb\(127),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(128),
      Q => \^doutb\(128),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      Q => \^doutb\(129),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(130),
      Q => \^doutb\(130),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131),
      Q => \^doutb\(131),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(132),
      Q => \^doutb\(132),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133),
      Q => \^doutb\(133),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(134),
      Q => \^doutb\(134),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135),
      Q => \^doutb\(135),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(136),
      Q => \^doutb\(136),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137),
      Q => \^doutb\(137),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(138),
      Q => \^doutb\(138),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139),
      Q => \^doutb\(139),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[140]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(140),
      Q => \^doutb\(140),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[141]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(141),
      Q => \^doutb\(141),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(142),
      Q => \^doutb\(142),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[143]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(143),
      Q => \^doutb\(143),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[144]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(144),
      Q => \^doutb\(144),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[145]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(145),
      Q => \^doutb\(145),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[146]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(146),
      Q => \^doutb\(146),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[147]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(147),
      Q => \^doutb\(147),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[148]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(148),
      Q => \^doutb\(148),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[149]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(149),
      Q => \^doutb\(149),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[150]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(150),
      Q => \^doutb\(150),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[151]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(151),
      Q => \^doutb\(151),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[152]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(152),
      Q => \^doutb\(152),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[153]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(153),
      Q => \^doutb\(153),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[154]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(154),
      Q => \^doutb\(154),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[155]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(155),
      Q => \^doutb\(155),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[156]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(156),
      Q => \^doutb\(156),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[157]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(157),
      Q => \^doutb\(157),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[158]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(158),
      Q => \^doutb\(158),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[159]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(159),
      Q => \^doutb\(159),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(15),
      Q => \^doutb\(15),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(16),
      Q => \^doutb\(16),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(17),
      Q => \^doutb\(17),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(18),
      Q => \^doutb\(18),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19),
      Q => \^doutb\(19),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(20),
      Q => \^doutb\(20),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21),
      Q => \^doutb\(21),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(22),
      Q => \^doutb\(22),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23),
      Q => \^doutb\(23),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(24),
      Q => \^doutb\(24),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25),
      Q => \^doutb\(25),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(26),
      Q => \^doutb\(26),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27),
      Q => \^doutb\(27),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(28),
      Q => \^doutb\(28),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29),
      Q => \^doutb\(29),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(30),
      Q => \^doutb\(30),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31),
      Q => \^doutb\(31),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(32),
      Q => \^doutb\(32),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33),
      Q => \^doutb\(33),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(34),
      Q => \^doutb\(34),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35),
      Q => \^doutb\(35),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(36),
      Q => \^doutb\(36),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37),
      Q => \^doutb\(37),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(38),
      Q => \^doutb\(38),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39),
      Q => \^doutb\(39),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(40),
      Q => \^doutb\(40),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41),
      Q => \^doutb\(41),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(42),
      Q => \^doutb\(42),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(43),
      Q => \^doutb\(43),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(44),
      Q => \^doutb\(44),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(45),
      Q => \^doutb\(45),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(46),
      Q => \^doutb\(46),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(47),
      Q => \^doutb\(47),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(48),
      Q => \^doutb\(48),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(49),
      Q => \^doutb\(49),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(50),
      Q => \^doutb\(50),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(51),
      Q => \^doutb\(51),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(52),
      Q => \^doutb\(52),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(53),
      Q => \^doutb\(53),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(54),
      Q => \^doutb\(54),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(55),
      Q => \^doutb\(55),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(56),
      Q => \^doutb\(56),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(57),
      Q => \^doutb\(57),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(58),
      Q => \^doutb\(58),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(59),
      Q => \^doutb\(59),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(60),
      Q => \^doutb\(60),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(61),
      Q => \^doutb\(61),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(62),
      Q => \^doutb\(62),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(63),
      Q => \^doutb\(63),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[64]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(64),
      Q => \^doutb\(64),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[65]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(65),
      Q => \^doutb\(65),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[66]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(66),
      Q => \^doutb\(66),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[67]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(67),
      Q => \^doutb\(67),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[68]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(68),
      Q => \^doutb\(68),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[69]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(69),
      Q => \^doutb\(69),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(70),
      Q => \^doutb\(70),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71),
      Q => \^doutb\(71),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(72),
      Q => \^doutb\(72),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      Q => \^doutb\(73),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(74),
      Q => \^doutb\(74),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75),
      Q => \^doutb\(75),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(76),
      Q => \^doutb\(76),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77),
      Q => \^doutb\(77),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(78),
      Q => \^doutb\(78),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79),
      Q => \^doutb\(79),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(80),
      Q => \^doutb\(80),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81),
      Q => \^doutb\(81),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(82),
      Q => \^doutb\(82),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83),
      Q => \^doutb\(83),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(84),
      Q => \^doutb\(84),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85),
      Q => \^doutb\(85),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(86),
      Q => \^doutb\(86),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87),
      Q => \^doutb\(87),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(88),
      Q => \^doutb\(88),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89),
      Q => \^doutb\(89),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(90),
      Q => \^doutb\(90),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91),
      Q => \^doutb\(91),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(92),
      Q => \^doutb\(92),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93),
      Q => \^doutb\(93),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(94),
      Q => \^doutb\(94),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95),
      Q => \^doutb\(95),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(96),
      Q => \^doutb\(96),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97),
      Q => \^doutb\(97),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(98),
      Q => \^doutb\(98),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99),
      Q => \^doutb\(99),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(113 downto 112),
      DIB(1 downto 0) => dina(115 downto 114),
      DIC(1 downto 0) => dina(117 downto 116),
      DID(1 downto 0) => dina(119 downto 118),
      DIE(1 downto 0) => dina(121 downto 120),
      DIF(1 downto 0) => dina(123 downto 122),
      DIG(1 downto 0) => dina(125 downto 124),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113 downto 112),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115 downto 114),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117 downto 116),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119 downto 118),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121 downto 120),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123 downto 122),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125 downto 124),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(127 downto 126),
      DIB(1 downto 0) => dina(129 downto 128),
      DIC(1 downto 0) => dina(131 downto 130),
      DID(1 downto 0) => dina(133 downto 132),
      DIE(1 downto 0) => dina(135 downto 134),
      DIF(1 downto 0) => dina(137 downto 136),
      DIG(1 downto 0) => dina(139 downto 138),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127 downto 126),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129 downto 128),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131 downto 130),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133 downto 132),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135 downto 134),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137 downto 136),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139 downto 138),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(141 downto 140),
      DIB(1 downto 0) => dina(143 downto 142),
      DIC(1 downto 0) => dina(145 downto 144),
      DID(1 downto 0) => dina(147 downto 146),
      DIE(1 downto 0) => dina(149 downto 148),
      DIF(1 downto 0) => dina(151 downto 150),
      DIG(1 downto 0) => dina(153 downto 152),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(141 downto 140),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(143 downto 142),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(145 downto 144),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(147 downto 146),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(149 downto 148),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(151 downto 150),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(153 downto 152),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1) => dina(160),
      DIA(0) => dina(14),
      DIB(1 downto 0) => dina(17 downto 16),
      DIC(1 downto 0) => dina(19 downto 18),
      DID(1 downto 0) => dina(21 downto 20),
      DIE(1 downto 0) => dina(23 downto 22),
      DIF(1 downto 0) => dina(25 downto 24),
      DIG(1 downto 0) => dina(27 downto 26),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(15),
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_1\,
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(17 downto 16),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19 downto 18),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21 downto 20),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23 downto 22),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25 downto 24),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27 downto 26),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(155 downto 154),
      DIB(1 downto 0) => dina(157 downto 156),
      DIC(1 downto 0) => dina(159 downto 158),
      DID(1) => '1',
      DID(0) => dina(160),
      DIE(1 downto 0) => dina(163 downto 162),
      DIF(1) => '0',
      DIF(0) => dina(164),
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(155 downto 154),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(157 downto 156),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(159 downto 158),
      DOD(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_6\,
      DOD(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_7\,
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_8\,
      DOE(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_9\,
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_11\,
      DOG(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_12\,
      DOG(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_13\,
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(29 downto 28),
      DIB(1 downto 0) => dina(31 downto 30),
      DIC(1 downto 0) => dina(33 downto 32),
      DID(1 downto 0) => dina(35 downto 34),
      DIE(1 downto 0) => dina(37 downto 36),
      DIF(1 downto 0) => dina(39 downto 38),
      DIG(1 downto 0) => dina(41 downto 40),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29 downto 28),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31 downto 30),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33 downto 32),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35 downto 34),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37 downto 36),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39 downto 38),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41 downto 40),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(43 downto 42),
      DIB(1 downto 0) => dina(45 downto 44),
      DIC(1 downto 0) => dina(47 downto 46),
      DID(1 downto 0) => dina(49 downto 48),
      DIE(1 downto 0) => dina(51 downto 50),
      DIF(1 downto 0) => dina(53 downto 52),
      DIG(1 downto 0) => dina(55 downto 54),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(43 downto 42),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(45 downto 44),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(47 downto 46),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(49 downto 48),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(51 downto 50),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(53 downto 52),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(55 downto 54),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(57 downto 56),
      DIB(1 downto 0) => dina(59 downto 58),
      DIC(1 downto 0) => dina(61 downto 60),
      DID(1 downto 0) => dina(63 downto 62),
      DIE(1 downto 0) => dina(65 downto 64),
      DIF(1 downto 0) => dina(67 downto 66),
      DIG(1 downto 0) => dina(69 downto 68),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(57 downto 56),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(59 downto 58),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(61 downto 60),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(63 downto 62),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(65 downto 64),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(67 downto 66),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(69 downto 68),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(71 downto 70),
      DIB(1 downto 0) => dina(73 downto 72),
      DIC(1 downto 0) => dina(75 downto 74),
      DID(1 downto 0) => dina(77 downto 76),
      DIE(1 downto 0) => dina(79 downto 78),
      DIF(1 downto 0) => dina(81 downto 80),
      DIG(1 downto 0) => dina(83 downto 82),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71 downto 70),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73 downto 72),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75 downto 74),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77 downto 76),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79 downto 78),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81 downto 80),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83 downto 82),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(85 downto 84),
      DIB(1 downto 0) => dina(87 downto 86),
      DIC(1 downto 0) => dina(89 downto 88),
      DID(1 downto 0) => dina(91 downto 90),
      DIE(1 downto 0) => dina(93 downto 92),
      DIF(1 downto 0) => dina(95 downto 94),
      DIG(1 downto 0) => dina(97 downto 96),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85 downto 84),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87 downto 86),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89 downto 88),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91 downto 90),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93 downto 92),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95 downto 94),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97 downto 96),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(99 downto 98),
      DIB(1 downto 0) => dina(101 downto 100),
      DIC(1 downto 0) => dina(103 downto 102),
      DID(1 downto 0) => dina(105 downto 104),
      DIE(1 downto 0) => dina(107 downto 106),
      DIF(1 downto 0) => dina(109 downto 108),
      DIG(1 downto 0) => dina(111 downto 110),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99 downto 98),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101 downto 100),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103 downto 102),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105 downto 104),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107 downto 106),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109 downto 108),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111 downto 110),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 17 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 17 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 17 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 576;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 18;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 20;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ : entity is 20;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_4\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_5\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_7\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_9\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[0]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 576;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \^doutb\(0);
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => \^doutb\(0),
      I1 => enb,
      I2 => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(0),
      I3 => rstb,
      O => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg[0]_i_1_n_0\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => '1',
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg[0]_i_1_n_0\,
      Q => \^doutb\(0),
      R => '0'
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(1 downto 0),
      DIB(1) => dina(3),
      DIB(0) => '0',
      DIC(1) => '0',
      DIC(0) => dina(4),
      DID(1 downto 0) => B"00",
      DIE(1 downto 0) => B"00",
      DIF(1) => dina(11),
      DIF(0) => '0',
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_0\,
      DOA(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(0),
      DOB(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\,
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_3\,
      DOC(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_4\,
      DOC(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_5\,
      DOD(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\,
      DOD(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_7\,
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\,
      DOE(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_9\,
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\,
      DOG(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\,
      DOG(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\,
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 139 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 139 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 139 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 139 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 4480;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ : entity is 140;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[10]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[13]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[9]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 4480;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 112;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 125;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 126;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 139;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 70;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 83;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 84;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 97;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 98;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 111;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(139) <= \<const0>\;
  douta(138) <= \<const0>\;
  douta(137) <= \<const0>\;
  douta(136) <= \<const0>\;
  douta(135) <= \<const0>\;
  douta(134) <= \<const0>\;
  douta(133) <= \<const0>\;
  douta(132) <= \<const0>\;
  douta(131) <= \<const0>\;
  douta(130) <= \<const0>\;
  douta(129) <= \<const0>\;
  douta(128) <= \<const0>\;
  douta(127) <= \<const0>\;
  douta(126) <= \<const0>\;
  douta(125) <= \<const0>\;
  douta(124) <= \<const0>\;
  douta(123) <= \<const0>\;
  douta(122) <= \<const0>\;
  douta(121) <= \<const0>\;
  douta(120) <= \<const0>\;
  douta(119) <= \<const0>\;
  douta(118) <= \<const0>\;
  douta(117) <= \<const0>\;
  douta(116) <= \<const0>\;
  douta(115) <= \<const0>\;
  douta(114) <= \<const0>\;
  douta(113) <= \<const0>\;
  douta(112) <= \<const0>\;
  douta(111) <= \<const0>\;
  douta(110) <= \<const0>\;
  douta(109) <= \<const0>\;
  douta(108) <= \<const0>\;
  douta(107) <= \<const0>\;
  douta(106) <= \<const0>\;
  douta(105) <= \<const0>\;
  douta(104) <= \<const0>\;
  douta(103) <= \<const0>\;
  douta(102) <= \<const0>\;
  douta(101) <= \<const0>\;
  douta(100) <= \<const0>\;
  douta(99) <= \<const0>\;
  douta(98) <= \<const0>\;
  douta(97) <= \<const0>\;
  douta(96) <= \<const0>\;
  douta(95) <= \<const0>\;
  douta(94) <= \<const0>\;
  douta(93) <= \<const0>\;
  douta(92) <= \<const0>\;
  douta(91) <= \<const0>\;
  douta(90) <= \<const0>\;
  douta(89) <= \<const0>\;
  douta(88) <= \<const0>\;
  douta(87) <= \<const0>\;
  douta(86) <= \<const0>\;
  douta(85) <= \<const0>\;
  douta(84) <= \<const0>\;
  douta(83) <= \<const0>\;
  douta(82) <= \<const0>\;
  douta(81) <= \<const0>\;
  douta(80) <= \<const0>\;
  douta(79) <= \<const0>\;
  douta(78) <= \<const0>\;
  douta(77) <= \<const0>\;
  douta(76) <= \<const0>\;
  douta(75) <= \<const0>\;
  douta(74) <= \<const0>\;
  douta(73) <= \<const0>\;
  douta(72) <= \<const0>\;
  douta(71) <= \<const0>\;
  douta(70) <= \<const0>\;
  douta(69) <= \<const0>\;
  douta(68) <= \<const0>\;
  douta(67) <= \<const0>\;
  douta(66) <= \<const0>\;
  douta(65) <= \<const0>\;
  douta(64) <= \<const0>\;
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(139 downto 70) <= \^doutb\(139 downto 70);
  doutb(69) <= \<const0>\;
  doutb(68) <= \<const0>\;
  doutb(67) <= \<const0>\;
  doutb(66) <= \<const0>\;
  doutb(65) <= \<const0>\;
  doutb(64) <= \<const0>\;
  doutb(63) <= \<const0>\;
  doutb(62) <= \<const0>\;
  doutb(61) <= \<const0>\;
  doutb(60) <= \<const0>\;
  doutb(59) <= \<const0>\;
  doutb(58) <= \<const0>\;
  doutb(57) <= \<const0>\;
  doutb(56) <= \<const0>\;
  doutb(55) <= \<const0>\;
  doutb(54) <= \<const0>\;
  doutb(53) <= \<const0>\;
  doutb(52) <= \<const0>\;
  doutb(51) <= \<const0>\;
  doutb(50) <= \<const0>\;
  doutb(49) <= \<const0>\;
  doutb(48) <= \<const0>\;
  doutb(47) <= \<const0>\;
  doutb(46) <= \<const0>\;
  doutb(45) <= \<const0>\;
  doutb(44) <= \<const0>\;
  doutb(43) <= \<const0>\;
  doutb(42) <= \<const0>\;
  doutb(41) <= \<const0>\;
  doutb(40) <= \<const0>\;
  doutb(39) <= \<const0>\;
  doutb(38) <= \<const0>\;
  doutb(37) <= \<const0>\;
  doutb(36) <= \<const0>\;
  doutb(35) <= \<const0>\;
  doutb(34) <= \<const0>\;
  doutb(33) <= \<const0>\;
  doutb(32) <= \<const0>\;
  doutb(31) <= \<const0>\;
  doutb(30) <= \<const0>\;
  doutb(29) <= \<const0>\;
  doutb(28) <= \<const0>\;
  doutb(27) <= \<const0>\;
  doutb(26) <= \<const0>\;
  doutb(25) <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13 downto 1) <= \^doutb\(13 downto 1);
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(100),
      Q => \^doutb\(100),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101),
      Q => \^doutb\(101),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(102),
      Q => \^doutb\(102),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103),
      Q => \^doutb\(103),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(104),
      Q => \^doutb\(104),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105),
      Q => \^doutb\(105),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(106),
      Q => \^doutb\(106),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107),
      Q => \^doutb\(107),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(108),
      Q => \^doutb\(108),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109),
      Q => \^doutb\(109),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(10),
      Q => \^doutb\(10),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(110),
      Q => \^doutb\(110),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111),
      Q => \^doutb\(111),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(112),
      Q => \^doutb\(112),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113),
      Q => \^doutb\(113),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(114),
      Q => \^doutb\(114),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115),
      Q => \^doutb\(115),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(116),
      Q => \^doutb\(116),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117),
      Q => \^doutb\(117),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(118),
      Q => \^doutb\(118),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119),
      Q => \^doutb\(119),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11),
      Q => \^doutb\(11),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(120),
      Q => \^doutb\(120),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121),
      Q => \^doutb\(121),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(122),
      Q => \^doutb\(122),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123),
      Q => \^doutb\(123),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(124),
      Q => \^doutb\(124),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125),
      Q => \^doutb\(125),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(126),
      Q => \^doutb\(126),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127),
      Q => \^doutb\(127),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(128),
      Q => \^doutb\(128),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      Q => \^doutb\(129),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(12),
      Q => \^doutb\(12),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(130),
      Q => \^doutb\(130),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131),
      Q => \^doutb\(131),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(132),
      Q => \^doutb\(132),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133),
      Q => \^doutb\(133),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(134),
      Q => \^doutb\(134),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135),
      Q => \^doutb\(135),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(136),
      Q => \^doutb\(136),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137),
      Q => \^doutb\(137),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(138),
      Q => \^doutb\(138),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139),
      Q => \^doutb\(139),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(13),
      Q => \^doutb\(13),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      Q => \^doutb\(1),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      Q => \^doutb\(2),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3),
      Q => \^doutb\(3),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(4),
      Q => \^doutb\(4),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5),
      Q => \^doutb\(5),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(6),
      Q => \^doutb\(6),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(70),
      Q => \^doutb\(70),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71),
      Q => \^doutb\(71),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(72),
      Q => \^doutb\(72),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      Q => \^doutb\(73),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(74),
      Q => \^doutb\(74),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75),
      Q => \^doutb\(75),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(76),
      Q => \^doutb\(76),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77),
      Q => \^doutb\(77),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(78),
      Q => \^doutb\(78),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79),
      Q => \^doutb\(79),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7),
      Q => \^doutb\(7),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(80),
      Q => \^doutb\(80),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81),
      Q => \^doutb\(81),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(82),
      Q => \^doutb\(82),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83),
      Q => \^doutb\(83),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(84),
      Q => \^doutb\(84),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85),
      Q => \^doutb\(85),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(86),
      Q => \^doutb\(86),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87),
      Q => \^doutb\(87),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(88),
      Q => \^doutb\(88),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89),
      Q => \^doutb\(89),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(8),
      Q => \^doutb\(8),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(90),
      Q => \^doutb\(90),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91),
      Q => \^doutb\(91),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(92),
      Q => \^doutb\(92),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93),
      Q => \^doutb\(93),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(94),
      Q => \^doutb\(94),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95),
      Q => \^doutb\(95),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(96),
      Q => \^doutb\(96),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97),
      Q => \^doutb\(97),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(98),
      Q => \^doutb\(98),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99),
      Q => \^doutb\(99),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(9),
      Q => \^doutb\(9),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1) => dina(1),
      DIA(0) => '0',
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => B"00",
      DIF(1 downto 0) => B"00",
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\,
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5 downto 4),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7 downto 6),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(9 downto 8),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11 downto 10),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(13 downto 12),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(113 downto 112),
      DIB(1 downto 0) => dina(115 downto 114),
      DIC(1 downto 0) => dina(117 downto 116),
      DID(1 downto 0) => dina(119 downto 118),
      DIE(1 downto 0) => dina(121 downto 120),
      DIF(1 downto 0) => dina(123 downto 122),
      DIG(1 downto 0) => dina(125 downto 124),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113 downto 112),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115 downto 114),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117 downto 116),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119 downto 118),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121 downto 120),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123 downto 122),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125 downto 124),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(127 downto 126),
      DIB(1 downto 0) => dina(129 downto 128),
      DIC(1 downto 0) => dina(131 downto 130),
      DID(1 downto 0) => dina(133 downto 132),
      DIE(1 downto 0) => dina(135 downto 134),
      DIF(1 downto 0) => dina(137 downto 136),
      DIG(1 downto 0) => dina(139 downto 138),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127 downto 126),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129 downto 128),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131 downto 130),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133 downto 132),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135 downto 134),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137 downto 136),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139 downto 138),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => dina(73),
      DIB(0) => '0',
      DIC(1 downto 0) => dina(75 downto 74),
      DID(1 downto 0) => dina(77 downto 76),
      DIE(1 downto 0) => dina(79 downto 78),
      DIF(1 downto 0) => dina(81 downto 80),
      DIG(1 downto 0) => dina(83 downto 82),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71 downto 70),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73 downto 72),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75 downto 74),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77 downto 76),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79 downto 78),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81 downto 80),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83 downto 82),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => dina(87 downto 86),
      DIC(1 downto 0) => dina(89 downto 88),
      DID(1 downto 0) => dina(91 downto 90),
      DIE(1) => '0',
      DIE(0) => dina(92),
      DIF(1 downto 0) => B"01",
      DIG(1 downto 0) => dina(97 downto 96),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85 downto 84),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87 downto 86),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89 downto 88),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91 downto 90),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93 downto 92),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95 downto 94),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97 downto 96),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(99 downto 98),
      DIB(1 downto 0) => dina(101 downto 100),
      DIC(1 downto 0) => dina(103 downto 102),
      DID(1 downto 0) => dina(105 downto 104),
      DIE(1 downto 0) => dina(107 downto 106),
      DIF(1 downto 0) => dina(109 downto 108),
      DIG(1 downto 0) => dina(111 downto 110),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99 downto 98),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101 downto 100),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103 downto 102),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105 downto 104),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107 downto 106),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109 downto 108),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111 downto 110),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 139 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 139 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 139 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 139 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 4480;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ : entity is 140;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[10]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[13]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[9]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 4480;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 112;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 125;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 126;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 139;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 70;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 83;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 84;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 97;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 98;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 111;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(139) <= \<const0>\;
  douta(138) <= \<const0>\;
  douta(137) <= \<const0>\;
  douta(136) <= \<const0>\;
  douta(135) <= \<const0>\;
  douta(134) <= \<const0>\;
  douta(133) <= \<const0>\;
  douta(132) <= \<const0>\;
  douta(131) <= \<const0>\;
  douta(130) <= \<const0>\;
  douta(129) <= \<const0>\;
  douta(128) <= \<const0>\;
  douta(127) <= \<const0>\;
  douta(126) <= \<const0>\;
  douta(125) <= \<const0>\;
  douta(124) <= \<const0>\;
  douta(123) <= \<const0>\;
  douta(122) <= \<const0>\;
  douta(121) <= \<const0>\;
  douta(120) <= \<const0>\;
  douta(119) <= \<const0>\;
  douta(118) <= \<const0>\;
  douta(117) <= \<const0>\;
  douta(116) <= \<const0>\;
  douta(115) <= \<const0>\;
  douta(114) <= \<const0>\;
  douta(113) <= \<const0>\;
  douta(112) <= \<const0>\;
  douta(111) <= \<const0>\;
  douta(110) <= \<const0>\;
  douta(109) <= \<const0>\;
  douta(108) <= \<const0>\;
  douta(107) <= \<const0>\;
  douta(106) <= \<const0>\;
  douta(105) <= \<const0>\;
  douta(104) <= \<const0>\;
  douta(103) <= \<const0>\;
  douta(102) <= \<const0>\;
  douta(101) <= \<const0>\;
  douta(100) <= \<const0>\;
  douta(99) <= \<const0>\;
  douta(98) <= \<const0>\;
  douta(97) <= \<const0>\;
  douta(96) <= \<const0>\;
  douta(95) <= \<const0>\;
  douta(94) <= \<const0>\;
  douta(93) <= \<const0>\;
  douta(92) <= \<const0>\;
  douta(91) <= \<const0>\;
  douta(90) <= \<const0>\;
  douta(89) <= \<const0>\;
  douta(88) <= \<const0>\;
  douta(87) <= \<const0>\;
  douta(86) <= \<const0>\;
  douta(85) <= \<const0>\;
  douta(84) <= \<const0>\;
  douta(83) <= \<const0>\;
  douta(82) <= \<const0>\;
  douta(81) <= \<const0>\;
  douta(80) <= \<const0>\;
  douta(79) <= \<const0>\;
  douta(78) <= \<const0>\;
  douta(77) <= \<const0>\;
  douta(76) <= \<const0>\;
  douta(75) <= \<const0>\;
  douta(74) <= \<const0>\;
  douta(73) <= \<const0>\;
  douta(72) <= \<const0>\;
  douta(71) <= \<const0>\;
  douta(70) <= \<const0>\;
  douta(69) <= \<const0>\;
  douta(68) <= \<const0>\;
  douta(67) <= \<const0>\;
  douta(66) <= \<const0>\;
  douta(65) <= \<const0>\;
  douta(64) <= \<const0>\;
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(139 downto 70) <= \^doutb\(139 downto 70);
  doutb(69) <= \<const0>\;
  doutb(68) <= \<const0>\;
  doutb(67) <= \<const0>\;
  doutb(66) <= \<const0>\;
  doutb(65) <= \<const0>\;
  doutb(64) <= \<const0>\;
  doutb(63) <= \<const0>\;
  doutb(62) <= \<const0>\;
  doutb(61) <= \<const0>\;
  doutb(60) <= \<const0>\;
  doutb(59) <= \<const0>\;
  doutb(58) <= \<const0>\;
  doutb(57) <= \<const0>\;
  doutb(56) <= \<const0>\;
  doutb(55) <= \<const0>\;
  doutb(54) <= \<const0>\;
  doutb(53) <= \<const0>\;
  doutb(52) <= \<const0>\;
  doutb(51) <= \<const0>\;
  doutb(50) <= \<const0>\;
  doutb(49) <= \<const0>\;
  doutb(48) <= \<const0>\;
  doutb(47) <= \<const0>\;
  doutb(46) <= \<const0>\;
  doutb(45) <= \<const0>\;
  doutb(44) <= \<const0>\;
  doutb(43) <= \<const0>\;
  doutb(42) <= \<const0>\;
  doutb(41) <= \<const0>\;
  doutb(40) <= \<const0>\;
  doutb(39) <= \<const0>\;
  doutb(38) <= \<const0>\;
  doutb(37) <= \<const0>\;
  doutb(36) <= \<const0>\;
  doutb(35) <= \<const0>\;
  doutb(34) <= \<const0>\;
  doutb(33) <= \<const0>\;
  doutb(32) <= \<const0>\;
  doutb(31) <= \<const0>\;
  doutb(30) <= \<const0>\;
  doutb(29) <= \<const0>\;
  doutb(28) <= \<const0>\;
  doutb(27) <= \<const0>\;
  doutb(26) <= \<const0>\;
  doutb(25) <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13 downto 1) <= \^doutb\(13 downto 1);
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(100),
      Q => \^doutb\(100),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101),
      Q => \^doutb\(101),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(102),
      Q => \^doutb\(102),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103),
      Q => \^doutb\(103),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(104),
      Q => \^doutb\(104),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105),
      Q => \^doutb\(105),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(106),
      Q => \^doutb\(106),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107),
      Q => \^doutb\(107),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(108),
      Q => \^doutb\(108),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109),
      Q => \^doutb\(109),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(10),
      Q => \^doutb\(10),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(110),
      Q => \^doutb\(110),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111),
      Q => \^doutb\(111),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(112),
      Q => \^doutb\(112),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113),
      Q => \^doutb\(113),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(114),
      Q => \^doutb\(114),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115),
      Q => \^doutb\(115),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(116),
      Q => \^doutb\(116),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117),
      Q => \^doutb\(117),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(118),
      Q => \^doutb\(118),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119),
      Q => \^doutb\(119),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11),
      Q => \^doutb\(11),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(120),
      Q => \^doutb\(120),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121),
      Q => \^doutb\(121),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(122),
      Q => \^doutb\(122),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123),
      Q => \^doutb\(123),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(124),
      Q => \^doutb\(124),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125),
      Q => \^doutb\(125),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(126),
      Q => \^doutb\(126),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127),
      Q => \^doutb\(127),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(128),
      Q => \^doutb\(128),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      Q => \^doutb\(129),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(12),
      Q => \^doutb\(12),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(130),
      Q => \^doutb\(130),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131),
      Q => \^doutb\(131),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(132),
      Q => \^doutb\(132),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133),
      Q => \^doutb\(133),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(134),
      Q => \^doutb\(134),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135),
      Q => \^doutb\(135),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(136),
      Q => \^doutb\(136),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137),
      Q => \^doutb\(137),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(138),
      Q => \^doutb\(138),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139),
      Q => \^doutb\(139),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(13),
      Q => \^doutb\(13),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      Q => \^doutb\(1),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      Q => \^doutb\(2),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3),
      Q => \^doutb\(3),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(4),
      Q => \^doutb\(4),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5),
      Q => \^doutb\(5),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(6),
      Q => \^doutb\(6),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(70),
      Q => \^doutb\(70),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71),
      Q => \^doutb\(71),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(72),
      Q => \^doutb\(72),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      Q => \^doutb\(73),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(74),
      Q => \^doutb\(74),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75),
      Q => \^doutb\(75),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(76),
      Q => \^doutb\(76),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77),
      Q => \^doutb\(77),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(78),
      Q => \^doutb\(78),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79),
      Q => \^doutb\(79),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7),
      Q => \^doutb\(7),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(80),
      Q => \^doutb\(80),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81),
      Q => \^doutb\(81),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(82),
      Q => \^doutb\(82),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83),
      Q => \^doutb\(83),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(84),
      Q => \^doutb\(84),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85),
      Q => \^doutb\(85),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(86),
      Q => \^doutb\(86),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87),
      Q => \^doutb\(87),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(88),
      Q => \^doutb\(88),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89),
      Q => \^doutb\(89),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(8),
      Q => \^doutb\(8),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(90),
      Q => \^doutb\(90),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91),
      Q => \^doutb\(91),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(92),
      Q => \^doutb\(92),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93),
      Q => \^doutb\(93),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(94),
      Q => \^doutb\(94),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95),
      Q => \^doutb\(95),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(96),
      Q => \^doutb\(96),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97),
      Q => \^doutb\(97),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(98),
      Q => \^doutb\(98),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99),
      Q => \^doutb\(99),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(9),
      Q => \^doutb\(9),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1) => dina(1),
      DIA(0) => '0',
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => B"00",
      DIF(1 downto 0) => B"00",
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\,
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5 downto 4),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7 downto 6),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(9 downto 8),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11 downto 10),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(13 downto 12),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(113 downto 112),
      DIB(1 downto 0) => dina(115 downto 114),
      DIC(1 downto 0) => dina(117 downto 116),
      DID(1 downto 0) => dina(119 downto 118),
      DIE(1 downto 0) => dina(121 downto 120),
      DIF(1 downto 0) => dina(123 downto 122),
      DIG(1 downto 0) => dina(125 downto 124),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113 downto 112),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115 downto 114),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117 downto 116),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119 downto 118),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121 downto 120),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123 downto 122),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125 downto 124),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(127 downto 126),
      DIB(1 downto 0) => dina(129 downto 128),
      DIC(1 downto 0) => dina(131 downto 130),
      DID(1 downto 0) => dina(133 downto 132),
      DIE(1 downto 0) => dina(135 downto 134),
      DIF(1 downto 0) => dina(137 downto 136),
      DIG(1 downto 0) => dina(139 downto 138),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127 downto 126),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129 downto 128),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131 downto 130),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133 downto 132),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135 downto 134),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137 downto 136),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139 downto 138),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => dina(73),
      DIB(0) => '0',
      DIC(1 downto 0) => dina(75 downto 74),
      DID(1 downto 0) => dina(77 downto 76),
      DIE(1 downto 0) => dina(79 downto 78),
      DIF(1 downto 0) => dina(81 downto 80),
      DIG(1 downto 0) => dina(83 downto 82),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71 downto 70),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73 downto 72),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75 downto 74),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77 downto 76),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79 downto 78),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81 downto 80),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83 downto 82),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => dina(87 downto 86),
      DIC(1 downto 0) => dina(89 downto 88),
      DID(1 downto 0) => dina(91 downto 90),
      DIE(1) => '0',
      DIE(0) => dina(92),
      DIF(1 downto 0) => B"10",
      DIG(1 downto 0) => dina(97 downto 96),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85 downto 84),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87 downto 86),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89 downto 88),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91 downto 90),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93 downto 92),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95 downto 94),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97 downto 96),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(99 downto 98),
      DIB(1 downto 0) => dina(101 downto 100),
      DIC(1 downto 0) => dina(103 downto 102),
      DID(1 downto 0) => dina(105 downto 104),
      DIE(1 downto 0) => dina(107 downto 106),
      DIF(1 downto 0) => dina(109 downto 108),
      DIG(1 downto 0) => dina(111 downto 110),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99 downto 98),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101 downto 100),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103 downto 102),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105 downto 104),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107 downto 106),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109 downto 108),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111 downto 110),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 139 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 139 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 139 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 139 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 4480;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ : entity is 140;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[10]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[13]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[9]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 4480;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 112;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 125;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 126;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 139;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 70;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 83;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 84;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 97;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 4480;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 98;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 111;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(139) <= \<const0>\;
  douta(138) <= \<const0>\;
  douta(137) <= \<const0>\;
  douta(136) <= \<const0>\;
  douta(135) <= \<const0>\;
  douta(134) <= \<const0>\;
  douta(133) <= \<const0>\;
  douta(132) <= \<const0>\;
  douta(131) <= \<const0>\;
  douta(130) <= \<const0>\;
  douta(129) <= \<const0>\;
  douta(128) <= \<const0>\;
  douta(127) <= \<const0>\;
  douta(126) <= \<const0>\;
  douta(125) <= \<const0>\;
  douta(124) <= \<const0>\;
  douta(123) <= \<const0>\;
  douta(122) <= \<const0>\;
  douta(121) <= \<const0>\;
  douta(120) <= \<const0>\;
  douta(119) <= \<const0>\;
  douta(118) <= \<const0>\;
  douta(117) <= \<const0>\;
  douta(116) <= \<const0>\;
  douta(115) <= \<const0>\;
  douta(114) <= \<const0>\;
  douta(113) <= \<const0>\;
  douta(112) <= \<const0>\;
  douta(111) <= \<const0>\;
  douta(110) <= \<const0>\;
  douta(109) <= \<const0>\;
  douta(108) <= \<const0>\;
  douta(107) <= \<const0>\;
  douta(106) <= \<const0>\;
  douta(105) <= \<const0>\;
  douta(104) <= \<const0>\;
  douta(103) <= \<const0>\;
  douta(102) <= \<const0>\;
  douta(101) <= \<const0>\;
  douta(100) <= \<const0>\;
  douta(99) <= \<const0>\;
  douta(98) <= \<const0>\;
  douta(97) <= \<const0>\;
  douta(96) <= \<const0>\;
  douta(95) <= \<const0>\;
  douta(94) <= \<const0>\;
  douta(93) <= \<const0>\;
  douta(92) <= \<const0>\;
  douta(91) <= \<const0>\;
  douta(90) <= \<const0>\;
  douta(89) <= \<const0>\;
  douta(88) <= \<const0>\;
  douta(87) <= \<const0>\;
  douta(86) <= \<const0>\;
  douta(85) <= \<const0>\;
  douta(84) <= \<const0>\;
  douta(83) <= \<const0>\;
  douta(82) <= \<const0>\;
  douta(81) <= \<const0>\;
  douta(80) <= \<const0>\;
  douta(79) <= \<const0>\;
  douta(78) <= \<const0>\;
  douta(77) <= \<const0>\;
  douta(76) <= \<const0>\;
  douta(75) <= \<const0>\;
  douta(74) <= \<const0>\;
  douta(73) <= \<const0>\;
  douta(72) <= \<const0>\;
  douta(71) <= \<const0>\;
  douta(70) <= \<const0>\;
  douta(69) <= \<const0>\;
  douta(68) <= \<const0>\;
  douta(67) <= \<const0>\;
  douta(66) <= \<const0>\;
  douta(65) <= \<const0>\;
  douta(64) <= \<const0>\;
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(139 downto 70) <= \^doutb\(139 downto 70);
  doutb(69) <= \<const0>\;
  doutb(68) <= \<const0>\;
  doutb(67) <= \<const0>\;
  doutb(66) <= \<const0>\;
  doutb(65) <= \<const0>\;
  doutb(64) <= \<const0>\;
  doutb(63) <= \<const0>\;
  doutb(62) <= \<const0>\;
  doutb(61) <= \<const0>\;
  doutb(60) <= \<const0>\;
  doutb(59) <= \<const0>\;
  doutb(58) <= \<const0>\;
  doutb(57) <= \<const0>\;
  doutb(56) <= \<const0>\;
  doutb(55) <= \<const0>\;
  doutb(54) <= \<const0>\;
  doutb(53) <= \<const0>\;
  doutb(52) <= \<const0>\;
  doutb(51) <= \<const0>\;
  doutb(50) <= \<const0>\;
  doutb(49) <= \<const0>\;
  doutb(48) <= \<const0>\;
  doutb(47) <= \<const0>\;
  doutb(46) <= \<const0>\;
  doutb(45) <= \<const0>\;
  doutb(44) <= \<const0>\;
  doutb(43) <= \<const0>\;
  doutb(42) <= \<const0>\;
  doutb(41) <= \<const0>\;
  doutb(40) <= \<const0>\;
  doutb(39) <= \<const0>\;
  doutb(38) <= \<const0>\;
  doutb(37) <= \<const0>\;
  doutb(36) <= \<const0>\;
  doutb(35) <= \<const0>\;
  doutb(34) <= \<const0>\;
  doutb(33) <= \<const0>\;
  doutb(32) <= \<const0>\;
  doutb(31) <= \<const0>\;
  doutb(30) <= \<const0>\;
  doutb(29) <= \<const0>\;
  doutb(28) <= \<const0>\;
  doutb(27) <= \<const0>\;
  doutb(26) <= \<const0>\;
  doutb(25) <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13 downto 1) <= \^doutb\(13 downto 1);
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(100),
      Q => \^doutb\(100),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101),
      Q => \^doutb\(101),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(102),
      Q => \^doutb\(102),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103),
      Q => \^doutb\(103),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(104),
      Q => \^doutb\(104),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105),
      Q => \^doutb\(105),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(106),
      Q => \^doutb\(106),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107),
      Q => \^doutb\(107),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(108),
      Q => \^doutb\(108),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109),
      Q => \^doutb\(109),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(10),
      Q => \^doutb\(10),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(110),
      Q => \^doutb\(110),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111),
      Q => \^doutb\(111),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(112),
      Q => \^doutb\(112),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113),
      Q => \^doutb\(113),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(114),
      Q => \^doutb\(114),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115),
      Q => \^doutb\(115),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(116),
      Q => \^doutb\(116),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117),
      Q => \^doutb\(117),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(118),
      Q => \^doutb\(118),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119),
      Q => \^doutb\(119),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11),
      Q => \^doutb\(11),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(120),
      Q => \^doutb\(120),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121),
      Q => \^doutb\(121),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(122),
      Q => \^doutb\(122),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123),
      Q => \^doutb\(123),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(124),
      Q => \^doutb\(124),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125),
      Q => \^doutb\(125),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(126),
      Q => \^doutb\(126),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127),
      Q => \^doutb\(127),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(128),
      Q => \^doutb\(128),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      Q => \^doutb\(129),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(12),
      Q => \^doutb\(12),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(130),
      Q => \^doutb\(130),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131),
      Q => \^doutb\(131),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(132),
      Q => \^doutb\(132),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133),
      Q => \^doutb\(133),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(134),
      Q => \^doutb\(134),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135),
      Q => \^doutb\(135),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(136),
      Q => \^doutb\(136),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137),
      Q => \^doutb\(137),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(138),
      Q => \^doutb\(138),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139),
      Q => \^doutb\(139),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(13),
      Q => \^doutb\(13),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      Q => \^doutb\(1),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      Q => \^doutb\(2),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3),
      Q => \^doutb\(3),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(4),
      Q => \^doutb\(4),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5),
      Q => \^doutb\(5),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(6),
      Q => \^doutb\(6),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(70),
      Q => \^doutb\(70),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71),
      Q => \^doutb\(71),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(72),
      Q => \^doutb\(72),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      Q => \^doutb\(73),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(74),
      Q => \^doutb\(74),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75),
      Q => \^doutb\(75),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(76),
      Q => \^doutb\(76),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77),
      Q => \^doutb\(77),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(78),
      Q => \^doutb\(78),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79),
      Q => \^doutb\(79),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7),
      Q => \^doutb\(7),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(80),
      Q => \^doutb\(80),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81),
      Q => \^doutb\(81),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(82),
      Q => \^doutb\(82),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83),
      Q => \^doutb\(83),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(84),
      Q => \^doutb\(84),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85),
      Q => \^doutb\(85),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(86),
      Q => \^doutb\(86),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87),
      Q => \^doutb\(87),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(88),
      Q => \^doutb\(88),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89),
      Q => \^doutb\(89),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(8),
      Q => \^doutb\(8),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(90),
      Q => \^doutb\(90),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91),
      Q => \^doutb\(91),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(92),
      Q => \^doutb\(92),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93),
      Q => \^doutb\(93),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(94),
      Q => \^doutb\(94),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95),
      Q => \^doutb\(95),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(96),
      Q => \^doutb\(96),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97),
      Q => \^doutb\(97),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(98),
      Q => \^doutb\(98),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99),
      Q => \^doutb\(99),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(9),
      Q => \^doutb\(9),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1) => dina(1),
      DIA(0) => '0',
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => B"00",
      DIF(1 downto 0) => B"00",
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\,
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5 downto 4),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7 downto 6),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(9 downto 8),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11 downto 10),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(13 downto 12),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(113 downto 112),
      DIB(1 downto 0) => dina(115 downto 114),
      DIC(1 downto 0) => dina(117 downto 116),
      DID(1 downto 0) => dina(119 downto 118),
      DIE(1 downto 0) => dina(121 downto 120),
      DIF(1 downto 0) => dina(123 downto 122),
      DIG(1 downto 0) => dina(125 downto 124),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113 downto 112),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115 downto 114),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117 downto 116),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119 downto 118),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121 downto 120),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123 downto 122),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125 downto 124),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(127 downto 126),
      DIB(1 downto 0) => dina(129 downto 128),
      DIC(1 downto 0) => dina(131 downto 130),
      DID(1 downto 0) => dina(133 downto 132),
      DIE(1 downto 0) => dina(135 downto 134),
      DIF(1 downto 0) => dina(137 downto 136),
      DIG(1 downto 0) => dina(139 downto 138),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127 downto 126),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129 downto 128),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131 downto 130),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133 downto 132),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135 downto 134),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137 downto 136),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139 downto 138),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => dina(73),
      DIB(0) => '0',
      DIC(1 downto 0) => dina(75 downto 74),
      DID(1 downto 0) => dina(77 downto 76),
      DIE(1 downto 0) => dina(79 downto 78),
      DIF(1 downto 0) => dina(81 downto 80),
      DIG(1 downto 0) => dina(83 downto 82),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71 downto 70),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73 downto 72),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75 downto 74),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77 downto 76),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79 downto 78),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81 downto 80),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83 downto 82),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => dina(87 downto 86),
      DIC(1 downto 0) => dina(89 downto 88),
      DID(1 downto 0) => dina(91 downto 90),
      DIE(1) => '0',
      DIE(0) => dina(92),
      DIF(1 downto 0) => B"10",
      DIG(1 downto 0) => dina(97 downto 96),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85 downto 84),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87 downto 86),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89 downto 88),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91 downto 90),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93 downto 92),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95 downto 94),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97 downto 96),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(99 downto 98),
      DIB(1 downto 0) => dina(101 downto 100),
      DIC(1 downto 0) => dina(103 downto 102),
      DID(1 downto 0) => dina(105 downto 104),
      DIE(1 downto 0) => dina(107 downto 106),
      DIF(1 downto 0) => dina(109 downto 108),
      DIG(1 downto 0) => dina(111 downto 110),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99 downto 98),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101 downto 100),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103 downto 102),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105 downto 104),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107 downto 106),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109 downto 108),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111 downto 110),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 167 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 167 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 167 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 167 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 5376;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ : entity is 168;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 155 downto 18 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 155 downto 18 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_2\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_12\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_13\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_2\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_4\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_5\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_6\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_7\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_9\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[140]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[141]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[143]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[144]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[145]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[146]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[147]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[148]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[152]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[153]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[154]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[155]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[42]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[43]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[44]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[45]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[46]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[47]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[48]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[50]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[51]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[52]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[54]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[55]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[57]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[58]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[59]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[60]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[61]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[62]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[63]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[64]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[65]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[66]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[67]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[68]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[69]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 5376;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 112;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 125;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 126;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 139;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 140;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 153;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 14;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 27;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 154;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 167;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 28;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 41;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 42;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 55;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 56;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 69;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 70;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 83;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 84;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 97;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 98;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 111;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(167) <= \<const0>\;
  douta(166) <= \<const0>\;
  douta(165) <= \<const0>\;
  douta(164) <= \<const0>\;
  douta(163) <= \<const0>\;
  douta(162) <= \<const0>\;
  douta(161) <= \<const0>\;
  douta(160) <= \<const0>\;
  douta(159) <= \<const0>\;
  douta(158) <= \<const0>\;
  douta(157) <= \<const0>\;
  douta(156) <= \<const0>\;
  douta(155) <= \<const0>\;
  douta(154) <= \<const0>\;
  douta(153) <= \<const0>\;
  douta(152) <= \<const0>\;
  douta(151) <= \<const0>\;
  douta(150) <= \<const0>\;
  douta(149) <= \<const0>\;
  douta(148) <= \<const0>\;
  douta(147) <= \<const0>\;
  douta(146) <= \<const0>\;
  douta(145) <= \<const0>\;
  douta(144) <= \<const0>\;
  douta(143) <= \<const0>\;
  douta(142) <= \<const0>\;
  douta(141) <= \<const0>\;
  douta(140) <= \<const0>\;
  douta(139) <= \<const0>\;
  douta(138) <= \<const0>\;
  douta(137) <= \<const0>\;
  douta(136) <= \<const0>\;
  douta(135) <= \<const0>\;
  douta(134) <= \<const0>\;
  douta(133) <= \<const0>\;
  douta(132) <= \<const0>\;
  douta(131) <= \<const0>\;
  douta(130) <= \<const0>\;
  douta(129) <= \<const0>\;
  douta(128) <= \<const0>\;
  douta(127) <= \<const0>\;
  douta(126) <= \<const0>\;
  douta(125) <= \<const0>\;
  douta(124) <= \<const0>\;
  douta(123) <= \<const0>\;
  douta(122) <= \<const0>\;
  douta(121) <= \<const0>\;
  douta(120) <= \<const0>\;
  douta(119) <= \<const0>\;
  douta(118) <= \<const0>\;
  douta(117) <= \<const0>\;
  douta(116) <= \<const0>\;
  douta(115) <= \<const0>\;
  douta(114) <= \<const0>\;
  douta(113) <= \<const0>\;
  douta(112) <= \<const0>\;
  douta(111) <= \<const0>\;
  douta(110) <= \<const0>\;
  douta(109) <= \<const0>\;
  douta(108) <= \<const0>\;
  douta(107) <= \<const0>\;
  douta(106) <= \<const0>\;
  douta(105) <= \<const0>\;
  douta(104) <= \<const0>\;
  douta(103) <= \<const0>\;
  douta(102) <= \<const0>\;
  douta(101) <= \<const0>\;
  douta(100) <= \<const0>\;
  douta(99) <= \<const0>\;
  douta(98) <= \<const0>\;
  douta(97) <= \<const0>\;
  douta(96) <= \<const0>\;
  douta(95) <= \<const0>\;
  douta(94) <= \<const0>\;
  douta(93) <= \<const0>\;
  douta(92) <= \<const0>\;
  douta(91) <= \<const0>\;
  douta(90) <= \<const0>\;
  douta(89) <= \<const0>\;
  douta(88) <= \<const0>\;
  douta(87) <= \<const0>\;
  douta(86) <= \<const0>\;
  douta(85) <= \<const0>\;
  douta(84) <= \<const0>\;
  douta(83) <= \<const0>\;
  douta(82) <= \<const0>\;
  douta(81) <= \<const0>\;
  douta(80) <= \<const0>\;
  douta(79) <= \<const0>\;
  douta(78) <= \<const0>\;
  douta(77) <= \<const0>\;
  douta(76) <= \<const0>\;
  douta(75) <= \<const0>\;
  douta(74) <= \<const0>\;
  douta(73) <= \<const0>\;
  douta(72) <= \<const0>\;
  douta(71) <= \<const0>\;
  douta(70) <= \<const0>\;
  douta(69) <= \<const0>\;
  douta(68) <= \<const0>\;
  douta(67) <= \<const0>\;
  douta(66) <= \<const0>\;
  douta(65) <= \<const0>\;
  douta(64) <= \<const0>\;
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(167) <= \<const0>\;
  doutb(166) <= \<const0>\;
  doutb(165) <= \<const0>\;
  doutb(164) <= \<const0>\;
  doutb(163) <= \<const0>\;
  doutb(162) <= \<const0>\;
  doutb(161) <= \<const0>\;
  doutb(160) <= \<const0>\;
  doutb(159) <= \<const0>\;
  doutb(158) <= \<const0>\;
  doutb(157) <= \<const0>\;
  doutb(156) <= \<const0>\;
  doutb(155 downto 152) <= \^doutb\(155 downto 152);
  doutb(151) <= \<const0>\;
  doutb(150) <= \<const0>\;
  doutb(149) <= \<const0>\;
  doutb(148 downto 18) <= \^doutb\(148 downto 18);
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(100),
      Q => \^doutb\(100),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101),
      Q => \^doutb\(101),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(102),
      Q => \^doutb\(102),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103),
      Q => \^doutb\(103),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(104),
      Q => \^doutb\(104),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105),
      Q => \^doutb\(105),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(106),
      Q => \^doutb\(106),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107),
      Q => \^doutb\(107),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(108),
      Q => \^doutb\(108),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109),
      Q => \^doutb\(109),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(110),
      Q => \^doutb\(110),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111),
      Q => \^doutb\(111),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(112),
      Q => \^doutb\(112),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113),
      Q => \^doutb\(113),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(114),
      Q => \^doutb\(114),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115),
      Q => \^doutb\(115),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(116),
      Q => \^doutb\(116),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117),
      Q => \^doutb\(117),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(118),
      Q => \^doutb\(118),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119),
      Q => \^doutb\(119),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(120),
      Q => \^doutb\(120),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121),
      Q => \^doutb\(121),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(122),
      Q => \^doutb\(122),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123),
      Q => \^doutb\(123),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(124),
      Q => \^doutb\(124),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125),
      Q => \^doutb\(125),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(126),
      Q => \^doutb\(126),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127),
      Q => \^doutb\(127),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(128),
      Q => \^doutb\(128),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      Q => \^doutb\(129),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(130),
      Q => \^doutb\(130),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131),
      Q => \^doutb\(131),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(132),
      Q => \^doutb\(132),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133),
      Q => \^doutb\(133),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(134),
      Q => \^doutb\(134),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135),
      Q => \^doutb\(135),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(136),
      Q => \^doutb\(136),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137),
      Q => \^doutb\(137),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(138),
      Q => \^doutb\(138),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139),
      Q => \^doutb\(139),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[140]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(140),
      Q => \^doutb\(140),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[141]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(141),
      Q => \^doutb\(141),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(142),
      Q => \^doutb\(142),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[143]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(143),
      Q => \^doutb\(143),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[144]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(144),
      Q => \^doutb\(144),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[145]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(145),
      Q => \^doutb\(145),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[146]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(146),
      Q => \^doutb\(146),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[147]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(147),
      Q => \^doutb\(147),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[148]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(148),
      Q => \^doutb\(148),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[152]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(152),
      Q => \^doutb\(152),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[153]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(153),
      Q => \^doutb\(153),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[154]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(154),
      Q => \^doutb\(154),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[155]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(155),
      Q => \^doutb\(155),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(18),
      Q => \^doutb\(18),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19),
      Q => \^doutb\(19),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(20),
      Q => \^doutb\(20),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21),
      Q => \^doutb\(21),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(22),
      Q => \^doutb\(22),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23),
      Q => \^doutb\(23),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(24),
      Q => \^doutb\(24),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25),
      Q => \^doutb\(25),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(26),
      Q => \^doutb\(26),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27),
      Q => \^doutb\(27),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(28),
      Q => \^doutb\(28),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29),
      Q => \^doutb\(29),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(30),
      Q => \^doutb\(30),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31),
      Q => \^doutb\(31),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(32),
      Q => \^doutb\(32),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33),
      Q => \^doutb\(33),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(34),
      Q => \^doutb\(34),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35),
      Q => \^doutb\(35),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(36),
      Q => \^doutb\(36),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37),
      Q => \^doutb\(37),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(38),
      Q => \^doutb\(38),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39),
      Q => \^doutb\(39),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(40),
      Q => \^doutb\(40),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41),
      Q => \^doutb\(41),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(42),
      Q => \^doutb\(42),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(43),
      Q => \^doutb\(43),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(44),
      Q => \^doutb\(44),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(45),
      Q => \^doutb\(45),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(46),
      Q => \^doutb\(46),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(47),
      Q => \^doutb\(47),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(48),
      Q => \^doutb\(48),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(49),
      Q => \^doutb\(49),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(50),
      Q => \^doutb\(50),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(51),
      Q => \^doutb\(51),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(52),
      Q => \^doutb\(52),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(53),
      Q => \^doutb\(53),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(54),
      Q => \^doutb\(54),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(55),
      Q => \^doutb\(55),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(56),
      Q => \^doutb\(56),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(57),
      Q => \^doutb\(57),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(58),
      Q => \^doutb\(58),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(59),
      Q => \^doutb\(59),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(60),
      Q => \^doutb\(60),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(61),
      Q => \^doutb\(61),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(62),
      Q => \^doutb\(62),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(63),
      Q => \^doutb\(63),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[64]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(64),
      Q => \^doutb\(64),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[65]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(65),
      Q => \^doutb\(65),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[66]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(66),
      Q => \^doutb\(66),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[67]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(67),
      Q => \^doutb\(67),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[68]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(68),
      Q => \^doutb\(68),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[69]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(69),
      Q => \^doutb\(69),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(70),
      Q => \^doutb\(70),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71),
      Q => \^doutb\(71),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(72),
      Q => \^doutb\(72),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      Q => \^doutb\(73),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(74),
      Q => \^doutb\(74),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75),
      Q => \^doutb\(75),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(76),
      Q => \^doutb\(76),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77),
      Q => \^doutb\(77),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(78),
      Q => \^doutb\(78),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79),
      Q => \^doutb\(79),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(80),
      Q => \^doutb\(80),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81),
      Q => \^doutb\(81),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(82),
      Q => \^doutb\(82),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83),
      Q => \^doutb\(83),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(84),
      Q => \^doutb\(84),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85),
      Q => \^doutb\(85),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(86),
      Q => \^doutb\(86),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87),
      Q => \^doutb\(87),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(88),
      Q => \^doutb\(88),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89),
      Q => \^doutb\(89),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(90),
      Q => \^doutb\(90),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91),
      Q => \^doutb\(91),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(92),
      Q => \^doutb\(92),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93),
      Q => \^doutb\(93),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(94),
      Q => \^doutb\(94),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95),
      Q => \^doutb\(95),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(96),
      Q => \^doutb\(96),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97),
      Q => \^doutb\(97),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(98),
      Q => \^doutb\(98),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99),
      Q => \^doutb\(99),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(113 downto 112),
      DIB(1 downto 0) => dina(115 downto 114),
      DIC(1 downto 0) => dina(117 downto 116),
      DID(1 downto 0) => dina(119 downto 118),
      DIE(1 downto 0) => dina(121 downto 120),
      DIF(1 downto 0) => dina(123 downto 122),
      DIG(1 downto 0) => dina(125 downto 124),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113 downto 112),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115 downto 114),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117 downto 116),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119 downto 118),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121 downto 120),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123 downto 122),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125 downto 124),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(127 downto 126),
      DIB(1 downto 0) => dina(129 downto 128),
      DIC(1 downto 0) => dina(131 downto 130),
      DID(1 downto 0) => dina(133 downto 132),
      DIE(1 downto 0) => dina(135 downto 134),
      DIF(1 downto 0) => dina(137 downto 136),
      DIG(1 downto 0) => dina(139 downto 138),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127 downto 126),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129 downto 128),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131 downto 130),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133 downto 132),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135 downto 134),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137 downto 136),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139 downto 138),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(141 downto 140),
      DIB(1 downto 0) => dina(143 downto 142),
      DIC(1 downto 0) => dina(145 downto 144),
      DID(1 downto 0) => dina(147 downto 146),
      DIE(1) => dina(20),
      DIE(0) => dina(148),
      DIF(1 downto 0) => B"01",
      DIG(1 downto 0) => dina(153 downto 152),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(141 downto 140),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(143 downto 142),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(145 downto 144),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(147 downto 146),
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_8\,
      DOE(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(148),
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_11\,
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(153 downto 152),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(15 downto 14),
      DIB(1 downto 0) => dina(17 downto 16),
      DIC(1 downto 0) => dina(19 downto 18),
      DID(1 downto 0) => dina(21 downto 20),
      DIE(1 downto 0) => dina(23 downto 22),
      DIF(1 downto 0) => dina(25 downto 24),
      DIG(1 downto 0) => dina(27 downto 26),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_0\,
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_1\,
      DOB(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_2\,
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_3\,
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19 downto 18),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21 downto 20),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23 downto 22),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25 downto 24),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27 downto 26),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(155 downto 154),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1) => dina(161),
      DID(0) => '0',
      DIE(1) => '0',
      DIE(0) => dina(162),
      DIF(1 downto 0) => B"00",
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(155 downto 154),
      DOB(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_2\,
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_3\,
      DOC(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_4\,
      DOC(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_5\,
      DOD(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_6\,
      DOD(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_7\,
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_8\,
      DOE(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_9\,
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_11\,
      DOG(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_12\,
      DOG(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_13\,
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(29 downto 28),
      DIB(1 downto 0) => dina(31 downto 30),
      DIC(1 downto 0) => dina(33 downto 32),
      DID(1 downto 0) => dina(35 downto 34),
      DIE(1 downto 0) => dina(37 downto 36),
      DIF(1 downto 0) => dina(39 downto 38),
      DIG(1 downto 0) => dina(41 downto 40),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29 downto 28),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31 downto 30),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33 downto 32),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35 downto 34),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37 downto 36),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39 downto 38),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41 downto 40),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(43 downto 42),
      DIB(1 downto 0) => dina(45 downto 44),
      DIC(1 downto 0) => dina(47 downto 46),
      DID(1 downto 0) => dina(49 downto 48),
      DIE(1 downto 0) => dina(51 downto 50),
      DIF(1 downto 0) => dina(53 downto 52),
      DIG(1 downto 0) => dina(55 downto 54),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(43 downto 42),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(45 downto 44),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(47 downto 46),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(49 downto 48),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(51 downto 50),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(53 downto 52),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(55 downto 54),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(57 downto 56),
      DIB(1 downto 0) => dina(59 downto 58),
      DIC(1 downto 0) => dina(61 downto 60),
      DID(1 downto 0) => dina(63 downto 62),
      DIE(1 downto 0) => dina(65 downto 64),
      DIF(1 downto 0) => dina(67 downto 66),
      DIG(1 downto 0) => dina(69 downto 68),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(57 downto 56),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(59 downto 58),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(61 downto 60),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(63 downto 62),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(65 downto 64),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(67 downto 66),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(69 downto 68),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(71 downto 70),
      DIB(1 downto 0) => dina(73 downto 72),
      DIC(1 downto 0) => dina(75 downto 74),
      DID(1 downto 0) => dina(77 downto 76),
      DIE(1 downto 0) => dina(79 downto 78),
      DIF(1 downto 0) => dina(81 downto 80),
      DIG(1 downto 0) => dina(83 downto 82),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71 downto 70),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73 downto 72),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75 downto 74),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77 downto 76),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79 downto 78),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81 downto 80),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83 downto 82),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(85 downto 84),
      DIB(1 downto 0) => dina(87 downto 86),
      DIC(1 downto 0) => dina(89 downto 88),
      DID(1 downto 0) => dina(91 downto 90),
      DIE(1 downto 0) => dina(93 downto 92),
      DIF(1 downto 0) => dina(95 downto 94),
      DIG(1 downto 0) => dina(97 downto 96),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85 downto 84),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87 downto 86),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89 downto 88),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91 downto 90),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93 downto 92),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95 downto 94),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97 downto 96),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(99 downto 98),
      DIB(1 downto 0) => dina(101 downto 100),
      DIC(1 downto 0) => dina(103 downto 102),
      DID(1 downto 0) => dina(105 downto 104),
      DIE(1 downto 0) => dina(107 downto 106),
      DIF(1 downto 0) => dina(109 downto 108),
      DIG(1 downto 0) => dina(111 downto 110),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99 downto 98),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101 downto 100),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103 downto 102),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105 downto 104),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107 downto 106),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109 downto 108),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111 downto 110),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 167 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 167 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 167 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 167 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 5376;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ : entity is 168;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 155 downto 18 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 155 downto 18 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_2\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_12\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_13\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_2\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_4\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_5\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_6\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_7\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_9\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[140]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[141]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[143]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[144]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[145]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[146]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[147]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[148]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[152]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[153]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[154]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[155]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[42]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[43]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[44]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[45]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[46]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[47]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[48]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[50]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[51]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[52]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[54]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[55]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[57]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[58]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[59]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[60]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[61]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[62]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[63]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[64]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[65]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[66]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[67]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[68]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[69]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 5376;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 112;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\ : label is 125;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 126;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\ : label is 139;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 140;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\ : label is 153;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 14;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 27;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 154;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\ : label is 167;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 28;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 41;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 42;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\ : label is 55;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 56;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\ : label is 69;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 70;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\ : label is 83;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 84;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\ : label is 97;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 5376;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 98;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\ : label is 111;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(167) <= \<const0>\;
  douta(166) <= \<const0>\;
  douta(165) <= \<const0>\;
  douta(164) <= \<const0>\;
  douta(163) <= \<const0>\;
  douta(162) <= \<const0>\;
  douta(161) <= \<const0>\;
  douta(160) <= \<const0>\;
  douta(159) <= \<const0>\;
  douta(158) <= \<const0>\;
  douta(157) <= \<const0>\;
  douta(156) <= \<const0>\;
  douta(155) <= \<const0>\;
  douta(154) <= \<const0>\;
  douta(153) <= \<const0>\;
  douta(152) <= \<const0>\;
  douta(151) <= \<const0>\;
  douta(150) <= \<const0>\;
  douta(149) <= \<const0>\;
  douta(148) <= \<const0>\;
  douta(147) <= \<const0>\;
  douta(146) <= \<const0>\;
  douta(145) <= \<const0>\;
  douta(144) <= \<const0>\;
  douta(143) <= \<const0>\;
  douta(142) <= \<const0>\;
  douta(141) <= \<const0>\;
  douta(140) <= \<const0>\;
  douta(139) <= \<const0>\;
  douta(138) <= \<const0>\;
  douta(137) <= \<const0>\;
  douta(136) <= \<const0>\;
  douta(135) <= \<const0>\;
  douta(134) <= \<const0>\;
  douta(133) <= \<const0>\;
  douta(132) <= \<const0>\;
  douta(131) <= \<const0>\;
  douta(130) <= \<const0>\;
  douta(129) <= \<const0>\;
  douta(128) <= \<const0>\;
  douta(127) <= \<const0>\;
  douta(126) <= \<const0>\;
  douta(125) <= \<const0>\;
  douta(124) <= \<const0>\;
  douta(123) <= \<const0>\;
  douta(122) <= \<const0>\;
  douta(121) <= \<const0>\;
  douta(120) <= \<const0>\;
  douta(119) <= \<const0>\;
  douta(118) <= \<const0>\;
  douta(117) <= \<const0>\;
  douta(116) <= \<const0>\;
  douta(115) <= \<const0>\;
  douta(114) <= \<const0>\;
  douta(113) <= \<const0>\;
  douta(112) <= \<const0>\;
  douta(111) <= \<const0>\;
  douta(110) <= \<const0>\;
  douta(109) <= \<const0>\;
  douta(108) <= \<const0>\;
  douta(107) <= \<const0>\;
  douta(106) <= \<const0>\;
  douta(105) <= \<const0>\;
  douta(104) <= \<const0>\;
  douta(103) <= \<const0>\;
  douta(102) <= \<const0>\;
  douta(101) <= \<const0>\;
  douta(100) <= \<const0>\;
  douta(99) <= \<const0>\;
  douta(98) <= \<const0>\;
  douta(97) <= \<const0>\;
  douta(96) <= \<const0>\;
  douta(95) <= \<const0>\;
  douta(94) <= \<const0>\;
  douta(93) <= \<const0>\;
  douta(92) <= \<const0>\;
  douta(91) <= \<const0>\;
  douta(90) <= \<const0>\;
  douta(89) <= \<const0>\;
  douta(88) <= \<const0>\;
  douta(87) <= \<const0>\;
  douta(86) <= \<const0>\;
  douta(85) <= \<const0>\;
  douta(84) <= \<const0>\;
  douta(83) <= \<const0>\;
  douta(82) <= \<const0>\;
  douta(81) <= \<const0>\;
  douta(80) <= \<const0>\;
  douta(79) <= \<const0>\;
  douta(78) <= \<const0>\;
  douta(77) <= \<const0>\;
  douta(76) <= \<const0>\;
  douta(75) <= \<const0>\;
  douta(74) <= \<const0>\;
  douta(73) <= \<const0>\;
  douta(72) <= \<const0>\;
  douta(71) <= \<const0>\;
  douta(70) <= \<const0>\;
  douta(69) <= \<const0>\;
  douta(68) <= \<const0>\;
  douta(67) <= \<const0>\;
  douta(66) <= \<const0>\;
  douta(65) <= \<const0>\;
  douta(64) <= \<const0>\;
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(167) <= \<const0>\;
  doutb(166) <= \<const0>\;
  doutb(165) <= \<const0>\;
  doutb(164) <= \<const0>\;
  doutb(163) <= \<const0>\;
  doutb(162) <= \<const0>\;
  doutb(161) <= \<const0>\;
  doutb(160) <= \<const0>\;
  doutb(159) <= \<const0>\;
  doutb(158) <= \<const0>\;
  doutb(157) <= \<const0>\;
  doutb(156) <= \<const0>\;
  doutb(155 downto 152) <= \^doutb\(155 downto 152);
  doutb(151) <= \<const0>\;
  doutb(150) <= \<const0>\;
  doutb(149) <= \<const0>\;
  doutb(148 downto 18) <= \^doutb\(148 downto 18);
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(100),
      Q => \^doutb\(100),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101),
      Q => \^doutb\(101),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[102]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(102),
      Q => \^doutb\(102),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[103]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103),
      Q => \^doutb\(103),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[104]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(104),
      Q => \^doutb\(104),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[105]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105),
      Q => \^doutb\(105),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[106]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(106),
      Q => \^doutb\(106),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[107]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107),
      Q => \^doutb\(107),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[108]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(108),
      Q => \^doutb\(108),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[109]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109),
      Q => \^doutb\(109),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[110]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(110),
      Q => \^doutb\(110),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[111]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111),
      Q => \^doutb\(111),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[112]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(112),
      Q => \^doutb\(112),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[113]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113),
      Q => \^doutb\(113),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[114]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(114),
      Q => \^doutb\(114),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[115]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115),
      Q => \^doutb\(115),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[116]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(116),
      Q => \^doutb\(116),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[117]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117),
      Q => \^doutb\(117),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[118]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(118),
      Q => \^doutb\(118),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[119]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119),
      Q => \^doutb\(119),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[120]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(120),
      Q => \^doutb\(120),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[121]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121),
      Q => \^doutb\(121),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[122]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(122),
      Q => \^doutb\(122),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[123]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123),
      Q => \^doutb\(123),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[124]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(124),
      Q => \^doutb\(124),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[125]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125),
      Q => \^doutb\(125),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[126]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(126),
      Q => \^doutb\(126),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127),
      Q => \^doutb\(127),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[128]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(128),
      Q => \^doutb\(128),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129),
      Q => \^doutb\(129),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[130]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(130),
      Q => \^doutb\(130),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[131]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131),
      Q => \^doutb\(131),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(132),
      Q => \^doutb\(132),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[133]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133),
      Q => \^doutb\(133),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[134]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(134),
      Q => \^doutb\(134),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[135]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135),
      Q => \^doutb\(135),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[136]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(136),
      Q => \^doutb\(136),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[137]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137),
      Q => \^doutb\(137),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[138]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(138),
      Q => \^doutb\(138),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[139]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139),
      Q => \^doutb\(139),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[140]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(140),
      Q => \^doutb\(140),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[141]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(141),
      Q => \^doutb\(141),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[142]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(142),
      Q => \^doutb\(142),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[143]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(143),
      Q => \^doutb\(143),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[144]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(144),
      Q => \^doutb\(144),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[145]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(145),
      Q => \^doutb\(145),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[146]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(146),
      Q => \^doutb\(146),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[147]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(147),
      Q => \^doutb\(147),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[148]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(148),
      Q => \^doutb\(148),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[152]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(152),
      Q => \^doutb\(152),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[153]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(153),
      Q => \^doutb\(153),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[154]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(154),
      Q => \^doutb\(154),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[155]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(155),
      Q => \^doutb\(155),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(18),
      Q => \^doutb\(18),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19),
      Q => \^doutb\(19),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(20),
      Q => \^doutb\(20),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21),
      Q => \^doutb\(21),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(22),
      Q => \^doutb\(22),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23),
      Q => \^doutb\(23),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(24),
      Q => \^doutb\(24),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25),
      Q => \^doutb\(25),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(26),
      Q => \^doutb\(26),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27),
      Q => \^doutb\(27),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(28),
      Q => \^doutb\(28),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29),
      Q => \^doutb\(29),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(30),
      Q => \^doutb\(30),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31),
      Q => \^doutb\(31),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(32),
      Q => \^doutb\(32),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33),
      Q => \^doutb\(33),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(34),
      Q => \^doutb\(34),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35),
      Q => \^doutb\(35),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(36),
      Q => \^doutb\(36),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37),
      Q => \^doutb\(37),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(38),
      Q => \^doutb\(38),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39),
      Q => \^doutb\(39),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(40),
      Q => \^doutb\(40),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41),
      Q => \^doutb\(41),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(42),
      Q => \^doutb\(42),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(43),
      Q => \^doutb\(43),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(44),
      Q => \^doutb\(44),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(45),
      Q => \^doutb\(45),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(46),
      Q => \^doutb\(46),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(47),
      Q => \^doutb\(47),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(48),
      Q => \^doutb\(48),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(49),
      Q => \^doutb\(49),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(50),
      Q => \^doutb\(50),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(51),
      Q => \^doutb\(51),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(52),
      Q => \^doutb\(52),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(53),
      Q => \^doutb\(53),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(54),
      Q => \^doutb\(54),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(55),
      Q => \^doutb\(55),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(56),
      Q => \^doutb\(56),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(57),
      Q => \^doutb\(57),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(58),
      Q => \^doutb\(58),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(59),
      Q => \^doutb\(59),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(60),
      Q => \^doutb\(60),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(61),
      Q => \^doutb\(61),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(62),
      Q => \^doutb\(62),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(63),
      Q => \^doutb\(63),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[64]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(64),
      Q => \^doutb\(64),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[65]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(65),
      Q => \^doutb\(65),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[66]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(66),
      Q => \^doutb\(66),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[67]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(67),
      Q => \^doutb\(67),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[68]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(68),
      Q => \^doutb\(68),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[69]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(69),
      Q => \^doutb\(69),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[70]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(70),
      Q => \^doutb\(70),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71),
      Q => \^doutb\(71),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(72),
      Q => \^doutb\(72),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73),
      Q => \^doutb\(73),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[74]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(74),
      Q => \^doutb\(74),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[75]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75),
      Q => \^doutb\(75),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[76]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(76),
      Q => \^doutb\(76),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[77]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77),
      Q => \^doutb\(77),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[78]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(78),
      Q => \^doutb\(78),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[79]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79),
      Q => \^doutb\(79),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[80]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(80),
      Q => \^doutb\(80),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[81]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81),
      Q => \^doutb\(81),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[82]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(82),
      Q => \^doutb\(82),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[83]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83),
      Q => \^doutb\(83),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(84),
      Q => \^doutb\(84),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85),
      Q => \^doutb\(85),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[86]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(86),
      Q => \^doutb\(86),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[87]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87),
      Q => \^doutb\(87),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[88]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(88),
      Q => \^doutb\(88),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[89]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89),
      Q => \^doutb\(89),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(90),
      Q => \^doutb\(90),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[91]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91),
      Q => \^doutb\(91),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[92]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(92),
      Q => \^doutb\(92),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[93]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93),
      Q => \^doutb\(93),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[94]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(94),
      Q => \^doutb\(94),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95),
      Q => \^doutb\(95),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[96]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(96),
      Q => \^doutb\(96),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[97]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97),
      Q => \^doutb\(97),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[98]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(98),
      Q => \^doutb\(98),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[99]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99),
      Q => \^doutb\(99),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(113 downto 112),
      DIB(1 downto 0) => dina(115 downto 114),
      DIC(1 downto 0) => dina(117 downto 116),
      DID(1 downto 0) => dina(119 downto 118),
      DIE(1 downto 0) => dina(121 downto 120),
      DIF(1 downto 0) => dina(123 downto 122),
      DIG(1 downto 0) => dina(125 downto 124),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(113 downto 112),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(115 downto 114),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(117 downto 116),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(119 downto 118),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(121 downto 120),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(123 downto 122),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(125 downto 124),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(127 downto 126),
      DIB(1 downto 0) => dina(129 downto 128),
      DIC(1 downto 0) => dina(131 downto 130),
      DID(1 downto 0) => dina(133 downto 132),
      DIE(1 downto 0) => dina(135 downto 134),
      DIF(1 downto 0) => dina(137 downto 136),
      DIG(1 downto 0) => dina(139 downto 138),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(127 downto 126),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(129 downto 128),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(131 downto 130),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(133 downto 132),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(135 downto 134),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(137 downto 136),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(139 downto 138),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(141 downto 140),
      DIB(1 downto 0) => dina(143 downto 142),
      DIC(1 downto 0) => dina(145 downto 144),
      DID(1 downto 0) => dina(147 downto 146),
      DIE(1) => dina(20),
      DIE(0) => dina(148),
      DIF(1 downto 0) => B"01",
      DIG(1 downto 0) => dina(153 downto 152),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(141 downto 140),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(143 downto 142),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(145 downto 144),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(147 downto 146),
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_8\,
      DOE(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(148),
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_n_11\,
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(153 downto 152),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(15 downto 14),
      DIB(1 downto 0) => dina(17 downto 16),
      DIC(1 downto 0) => dina(19 downto 18),
      DID(1 downto 0) => dina(21 downto 20),
      DIE(1 downto 0) => dina(23 downto 22),
      DIF(1 downto 0) => dina(25 downto 24),
      DIG(1 downto 0) => dina(27 downto 26),
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_0\,
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_1\,
      DOB(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_2\,
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_n_3\,
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19 downto 18),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21 downto 20),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23 downto 22),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25 downto 24),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27 downto 26),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(155 downto 154),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1) => dina(161),
      DID(0) => '0',
      DIE(1) => '0',
      DIE(0) => dina(162),
      DIF(1 downto 0) => B"00",
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(155 downto 154),
      DOB(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_2\,
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_3\,
      DOC(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_4\,
      DOC(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_5\,
      DOD(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_6\,
      DOD(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_7\,
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_8\,
      DOE(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_9\,
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_11\,
      DOG(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_12\,
      DOG(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_n_13\,
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(29 downto 28),
      DIB(1 downto 0) => dina(31 downto 30),
      DIC(1 downto 0) => dina(33 downto 32),
      DID(1 downto 0) => dina(35 downto 34),
      DIE(1 downto 0) => dina(37 downto 36),
      DIF(1 downto 0) => dina(39 downto 38),
      DIG(1 downto 0) => dina(41 downto 40),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29 downto 28),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31 downto 30),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33 downto 32),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35 downto 34),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37 downto 36),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39 downto 38),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41 downto 40),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(43 downto 42),
      DIB(1 downto 0) => dina(45 downto 44),
      DIC(1 downto 0) => dina(47 downto 46),
      DID(1 downto 0) => dina(49 downto 48),
      DIE(1 downto 0) => dina(51 downto 50),
      DIF(1 downto 0) => dina(53 downto 52),
      DIG(1 downto 0) => dina(55 downto 54),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(43 downto 42),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(45 downto 44),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(47 downto 46),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(49 downto 48),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(51 downto 50),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(53 downto 52),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(55 downto 54),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(57 downto 56),
      DIB(1 downto 0) => dina(59 downto 58),
      DIC(1 downto 0) => dina(61 downto 60),
      DID(1 downto 0) => dina(63 downto 62),
      DIE(1 downto 0) => dina(65 downto 64),
      DIF(1 downto 0) => dina(67 downto 66),
      DIG(1 downto 0) => dina(69 downto 68),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(57 downto 56),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(59 downto 58),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(61 downto 60),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(63 downto 62),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(65 downto 64),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(67 downto 66),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(69 downto 68),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(71 downto 70),
      DIB(1 downto 0) => dina(73 downto 72),
      DIC(1 downto 0) => dina(75 downto 74),
      DID(1 downto 0) => dina(77 downto 76),
      DIE(1 downto 0) => dina(79 downto 78),
      DIF(1 downto 0) => dina(81 downto 80),
      DIG(1 downto 0) => dina(83 downto 82),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(71 downto 70),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(73 downto 72),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(75 downto 74),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(77 downto 76),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(79 downto 78),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(81 downto 80),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(83 downto 82),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(85 downto 84),
      DIB(1 downto 0) => dina(87 downto 86),
      DIC(1 downto 0) => dina(89 downto 88),
      DID(1 downto 0) => dina(91 downto 90),
      DIE(1 downto 0) => dina(93 downto 92),
      DIF(1 downto 0) => dina(95 downto 94),
      DIG(1 downto 0) => dina(97 downto 96),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(85 downto 84),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(87 downto 86),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(89 downto 88),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(91 downto 90),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(93 downto 92),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(95 downto 94),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(97 downto 96),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(99 downto 98),
      DIB(1 downto 0) => dina(101 downto 100),
      DIC(1 downto 0) => dina(103 downto 102),
      DID(1 downto 0) => dina(105 downto 104),
      DIE(1 downto 0) => dina(107 downto 106),
      DIF(1 downto 0) => dina(109 downto 108),
      DIG(1 downto 0) => dina(111 downto 110),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(99 downto 98),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(101 downto 100),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(103 downto 102),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(105 downto 104),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(107 downto 106),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(109 downto 108),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(111 downto 110),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 24 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 24 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 24 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 24 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 800;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 25;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 28;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ : entity is 28;
end \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 6 downto 5 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 6 downto 5 );
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_3\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_5\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_9\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 800;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6 downto 5) <= \^doutb\(6 downto 5);
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5),
      Q => \^doutb\(5),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(6),
      Q => \^doutb\(6),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1) => '0',
      DIA(0) => dina(0),
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1) => '1',
      DID(0) => dina(6),
      DIE(1 downto 0) => B"01",
      DIF(1 downto 0) => B"00",
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_0\,
      DOA(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_1\,
      DOB(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_2\,
      DOB(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_3\,
      DOC(1) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5),
      DOC(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_5\,
      DOD(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_6\,
      DOD(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(6),
      DOE(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_8\,
      DOE(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_9\,
      DOF(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_10\,
      DOF(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_11\,
      DOG(1) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_12\,
      DOG(0) => \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_n_13\,
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => wea(0)
    );
end STRUCTURE;
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lTwA
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_m00s2a_0 is
  port (
    m_sc_r_send : out STD_LOGIC;
    m_sc_r_payld : out STD_LOGIC_VECTOR ( 148 downto 0 );
    m_sc_b_send : out STD_LOGIC;
    m_sc_b_payld : out STD_LOGIC_VECTOR ( 5 downto 0 );
    s_sc_ar_recv : out STD_LOGIC;
    s_sc_aw_recv : out STD_LOGIC;
    s_sc_w_recv : out STD_LOGIC;
    m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awuser : out STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axi_awvalid : out STD_LOGIC;
    m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
    m_axi_wlast : out STD_LOGIC;
    m_axi_wvalid : out STD_LOGIC;
    m_axi_bready : out STD_LOGIC;
    m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : out STD_LOGIC_VECTOR ( 17 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_rready : out STD_LOGIC;
    S_SC_R_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_B_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_payld : in STD_LOGIC_VECTOR ( 70 downto 0 );
    M_SC_AW_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AW_payld : in STD_LOGIC_VECTOR ( 63 downto 0 );
    M_SC_W_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_payld : in STD_LOGIC_VECTOR ( 144 downto 0 );
    s_axi_awready : in STD_LOGIC;
    s_axi_wready : in STD_LOGIC;
    s_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_buser : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : in STD_LOGIC;
    s_axi_arready : in STD_LOGIC;
    s_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    s_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : in STD_LOGIC;
    s_axi_ruser : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_axi_rvalid : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_m00s2a_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_m00s2a_0 is
  signal NLW_inst_m_sc_b_req_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_sc_r_req_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_sc_b_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_b_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_inst_m_sc_r_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_ARPAYLD_WIDTH : integer;
  attribute C_ARPAYLD_WIDTH of inst : label is 140;
  attribute C_AWPAYLD_WIDTH : integer;
  attribute C_AWPAYLD_WIDTH of inst : label is 140;
  attribute C_AXI_ADDR_WIDTH : integer;
  attribute C_AXI_ADDR_WIDTH of inst : label is 32;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of inst : label is 2;
  attribute C_AXI_RDATA_WIDTH : integer;
  attribute C_AXI_RDATA_WIDTH of inst : label is 128;
  attribute C_AXI_WDATA_WIDTH : integer;
  attribute C_AXI_WDATA_WIDTH of inst : label is 128;
  attribute C_BPAYLD_WIDTH : integer;
  attribute C_BPAYLD_WIDTH of inst : label is 7;
  attribute C_MSC_ROUTE_WIDTH : integer;
  attribute C_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute C_RPAYLD_WIDTH : integer;
  attribute C_RPAYLD_WIDTH of inst : label is 149;
  attribute C_SC_ADDR_WIDTH : integer;
  attribute C_SC_ADDR_WIDTH of inst : label is 32;
  attribute C_SC_ARUSER_WIDTH : integer;
  attribute C_SC_ARUSER_WIDTH of inst : label is 0;
  attribute C_SC_AWUSER_WIDTH : integer;
  attribute C_SC_AWUSER_WIDTH of inst : label is 0;
  attribute C_SC_BUSER_WIDTH : integer;
  attribute C_SC_BUSER_WIDTH of inst : label is 0;
  attribute C_SC_ID_WIDTH : integer;
  attribute C_SC_ID_WIDTH of inst : label is 2;
  attribute C_SC_RDATA_WIDTH : integer;
  attribute C_SC_RDATA_WIDTH of inst : label is 128;
  attribute C_SC_RUSER_BITS_PER_BYTE : integer;
  attribute C_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_SC_WDATA_WIDTH : integer;
  attribute C_SC_WDATA_WIDTH of inst : label is 128;
  attribute C_SC_WUSER_BITS_PER_BYTE : integer;
  attribute C_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_SSC_ROUTE_WIDTH : integer;
  attribute C_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute C_WPAYLD_WIDTH : integer;
  attribute C_WPAYLD_WIDTH of inst : label is 160;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_NZ_AXI_ID_WIDTH : integer;
  attribute LP_NZ_AXI_ID_WIDTH of inst : label is 2;
  attribute LP_NZ_RUBPB : integer;
  attribute LP_NZ_RUBPB of inst : label is 1;
  attribute LP_NZ_WUBPB : integer;
  attribute LP_NZ_WUBPB of inst : label is 1;
  attribute LP_RUSER_INDEX : integer;
  attribute LP_RUSER_INDEX of inst : label is 0;
  attribute LP_WUSER_INDEX : integer;
  attribute LP_WUSER_INDEX of inst : label is 0;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 1;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 1;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 1;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.Loopback_smartconnect_0_0_sc_sc2axi_v1_0_10_top
     port map (
      aclk => '0',
      m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      m_axi_arid(1 downto 0) => m_axi_arid(1 downto 0),
      m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
      m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
      m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      m_axi_arready => s_axi_arready,
      m_axi_aruser(1023 downto 186) => NLW_inst_m_axi_aruser_UNCONNECTED(1023 downto 186),
      m_axi_aruser(185 downto 179) => m_axi_aruser(17 downto 11),
      m_axi_aruser(178 downto 147) => NLW_inst_m_axi_aruser_UNCONNECTED(178 downto 147),
      m_axi_aruser(146 downto 136) => m_axi_aruser(10 downto 0),
      m_axi_aruser(135 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(135 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
      m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
      m_axi_awid(1 downto 0) => m_axi_awid(1 downto 0),
      m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
      m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
      m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
      m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
      m_axi_awready => s_axi_awready,
      m_axi_awuser(1023 downto 147) => NLW_inst_m_axi_awuser_UNCONNECTED(1023 downto 147),
      m_axi_awuser(146 downto 136) => m_axi_awuser(10 downto 0),
      m_axi_awuser(135 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(135 downto 0),
      m_axi_awvalid => m_axi_awvalid,
      m_axi_bid(1 downto 0) => s_axi_bid(1 downto 0),
      m_axi_bready => m_axi_bready,
      m_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
      m_axi_buser(1023 downto 2) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_buser(1 downto 0) => s_axi_buser(1 downto 0),
      m_axi_bvalid => s_axi_bvalid,
      m_axi_rdata(127 downto 0) => s_axi_rdata(127 downto 0),
      m_axi_rid(1 downto 0) => s_axi_rid(1 downto 0),
      m_axi_rlast => s_axi_rlast,
      m_axi_rready => m_axi_rready,
      m_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      m_axi_ruser(1023 downto 78) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_ruser(77 downto 64) => s_axi_ruser(15 downto 2),
      m_axi_ruser(63 downto 2) => B"00000000000000000000000000000000000000000000000000000000000000",
      m_axi_ruser(1 downto 0) => s_axi_ruser(1 downto 0),
      m_axi_rvalid => s_axi_rvalid,
      m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
      m_axi_wlast => m_axi_wlast,
      m_axi_wready => s_axi_wready,
      m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
      m_axi_wuser(1023 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(1023 downto 0),
      m_axi_wvalid => m_axi_wvalid,
      m_sc_b_info(0) => NLW_inst_m_sc_b_info_UNCONNECTED(0),
      m_sc_b_payld(6 downto 3) => m_sc_b_payld(5 downto 2),
      m_sc_b_payld(2) => NLW_inst_m_sc_b_payld_UNCONNECTED(2),
      m_sc_b_payld(1 downto 0) => m_sc_b_payld(1 downto 0),
      m_sc_b_recv => S_SC_B_recv(0),
      m_sc_b_req => NLW_inst_m_sc_b_req_UNCONNECTED,
      m_sc_b_send => m_sc_b_send,
      m_sc_r_info(0) => NLW_inst_m_sc_r_info_UNCONNECTED(0),
      m_sc_r_payld(148 downto 0) => m_sc_r_payld(148 downto 0),
      m_sc_r_recv => S_SC_R_recv(0),
      m_sc_r_req => NLW_inst_m_sc_r_req_UNCONNECTED,
      m_sc_r_send => m_sc_r_send,
      s_sc_ar_info(0) => '0',
      s_sc_ar_payld(139 downto 129) => M_SC_AR_payld(70 downto 60),
      s_sc_ar_payld(128) => '0',
      s_sc_ar_payld(127 downto 94) => M_SC_AR_payld(59 downto 26),
      s_sc_ar_payld(93) => '0',
      s_sc_ar_payld(92 downto 86) => M_SC_AR_payld(25 downto 19),
      s_sc_ar_payld(85 downto 84) => B"00",
      s_sc_ar_payld(83 downto 73) => M_SC_AR_payld(18 downto 8),
      s_sc_ar_payld(72 downto 9) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_sc_ar_payld(8 downto 1) => M_SC_AR_payld(7 downto 0),
      s_sc_ar_payld(0) => '0',
      s_sc_ar_recv => s_sc_ar_recv,
      s_sc_ar_req => '0',
      s_sc_ar_send => M_SC_AR_send(0),
      s_sc_aw_info(0) => '0',
      s_sc_aw_payld(139 downto 129) => M_SC_AW_payld(63 downto 53),
      s_sc_aw_payld(128) => '0',
      s_sc_aw_payld(127 downto 94) => M_SC_AW_payld(52 downto 19),
      s_sc_aw_payld(93 downto 84) => B"0000000000",
      s_sc_aw_payld(83 downto 73) => M_SC_AW_payld(18 downto 8),
      s_sc_aw_payld(72 downto 9) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_sc_aw_payld(8 downto 1) => M_SC_AW_payld(7 downto 0),
      s_sc_aw_payld(0) => '0',
      s_sc_aw_recv => s_sc_aw_recv,
      s_sc_aw_req => '0',
      s_sc_aw_send => M_SC_AW_send(0),
      s_sc_w_info(0) => '0',
      s_sc_w_payld(159 downto 15) => M_SC_W_payld(144 downto 0),
      s_sc_w_payld(14 downto 0) => B"000000000000000",
      s_sc_w_recv => s_sc_w_recv,
      s_sc_w_req => '0',
      s_sc_w_send => M_SC_W_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_s00a2s_0 is
  port (
    M_SC_R_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_payld : out STD_LOGIC_VECTOR ( 68 downto 0 );
    s_axi_arready : out STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : out STD_LOGIC;
    s_axi_rvalid : out STD_LOGIC;
    M_SC_R_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_payld : in STD_LOGIC_VECTOR ( 34 downto 0 );
    S_SC_AR_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : in STD_LOGIC_VECTOR ( 24 downto 0 );
    m_axi_arvalid : in STD_LOGIC;
    m_axi_rready : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_s00a2s_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_s00a2s_0 is
  signal NLW_inst_m_sc_ar_req_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_sc_aw_req_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_sc_aw_send_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_sc_w_req_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_sc_w_send_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_sc_b_recv_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_sc_ar_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_ar_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 0 );
  signal NLW_inst_m_sc_aw_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_aw_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 139 downto 0 );
  signal NLW_inst_m_sc_w_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_w_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 159 downto 0 );
  signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  attribute C_ARPAYLD_WIDTH : integer;
  attribute C_ARPAYLD_WIDTH of inst : label is 140;
  attribute C_AWPAYLD_WIDTH : integer;
  attribute C_AWPAYLD_WIDTH of inst : label is 140;
  attribute C_AXI_ADDR_WIDTH : integer;
  attribute C_AXI_ADDR_WIDTH of inst : label is 32;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of inst : label is 2;
  attribute C_AXI_RDATA_WIDTH : integer;
  attribute C_AXI_RDATA_WIDTH of inst : label is 32;
  attribute C_AXI_WDATA_WIDTH : integer;
  attribute C_AXI_WDATA_WIDTH of inst : label is 32;
  attribute C_BPAYLD_WIDTH : integer;
  attribute C_BPAYLD_WIDTH of inst : label is 7;
  attribute C_MSC_ROUTE_WIDTH : integer;
  attribute C_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute C_RPAYLD_WIDTH : integer;
  attribute C_RPAYLD_WIDTH of inst : label is 149;
  attribute C_SC_ADDR_WIDTH : integer;
  attribute C_SC_ADDR_WIDTH of inst : label is 32;
  attribute C_SC_ARUSER_WIDTH : integer;
  attribute C_SC_ARUSER_WIDTH of inst : label is 0;
  attribute C_SC_AWUSER_WIDTH : integer;
  attribute C_SC_AWUSER_WIDTH of inst : label is 0;
  attribute C_SC_BUSER_WIDTH : integer;
  attribute C_SC_BUSER_WIDTH of inst : label is 0;
  attribute C_SC_ID_WIDTH : integer;
  attribute C_SC_ID_WIDTH of inst : label is 2;
  attribute C_SC_RDATA_WIDTH : integer;
  attribute C_SC_RDATA_WIDTH of inst : label is 128;
  attribute C_SC_RUSER_BITS_PER_BYTE : integer;
  attribute C_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_SC_WDATA_WIDTH : integer;
  attribute C_SC_WDATA_WIDTH of inst : label is 128;
  attribute C_SC_WUSER_BITS_PER_BYTE : integer;
  attribute C_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_SSC_ROUTE_WIDTH : integer;
  attribute C_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute C_WPAYLD_WIDTH : integer;
  attribute C_WPAYLD_WIDTH of inst : label is 160;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_NZ_AXI_ID_WIDTH : integer;
  attribute LP_NZ_AXI_ID_WIDTH of inst : label is 2;
  attribute LP_NZ_RUBPB : integer;
  attribute LP_NZ_RUBPB of inst : label is 1;
  attribute LP_NZ_WUBPB : integer;
  attribute LP_NZ_WUBPB of inst : label is 1;
  attribute LP_RUSER_INDEX : integer;
  attribute LP_RUSER_INDEX of inst : label is 0;
  attribute LP_WUSER_INDEX : integer;
  attribute LP_WUSER_INDEX of inst : label is 0;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 1;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 1;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 1;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.Loopback_smartconnect_0_0_sc_axi2sc_v1_0_10_top
     port map (
      aclk => '0',
      m_sc_ar_info(0) => NLW_inst_m_sc_ar_info_UNCONNECTED(0),
      m_sc_ar_payld(139 downto 96) => S_SC_AR_payld(68 downto 25),
      m_sc_ar_payld(95 downto 93) => NLW_inst_m_sc_ar_payld_UNCONNECTED(95 downto 93),
      m_sc_ar_payld(92 downto 86) => S_SC_AR_payld(24 downto 18),
      m_sc_ar_payld(85 downto 84) => NLW_inst_m_sc_ar_payld_UNCONNECTED(85 downto 84),
      m_sc_ar_payld(83 downto 73) => S_SC_AR_payld(17 downto 7),
      m_sc_ar_payld(72 downto 8) => NLW_inst_m_sc_ar_payld_UNCONNECTED(72 downto 8),
      m_sc_ar_payld(7 downto 1) => S_SC_AR_payld(6 downto 0),
      m_sc_ar_payld(0) => NLW_inst_m_sc_ar_payld_UNCONNECTED(0),
      m_sc_ar_recv => S_SC_AR_recv(0),
      m_sc_ar_req => NLW_inst_m_sc_ar_req_UNCONNECTED,
      m_sc_ar_send => S_SC_AR_send(0),
      m_sc_aw_info(0) => NLW_inst_m_sc_aw_info_UNCONNECTED(0),
      m_sc_aw_payld(139 downto 0) => NLW_inst_m_sc_aw_payld_UNCONNECTED(139 downto 0),
      m_sc_aw_recv => '0',
      m_sc_aw_req => NLW_inst_m_sc_aw_req_UNCONNECTED,
      m_sc_aw_send => NLW_inst_m_sc_aw_send_UNCONNECTED,
      m_sc_w_info(0) => NLW_inst_m_sc_w_info_UNCONNECTED(0),
      m_sc_w_payld(159 downto 0) => NLW_inst_m_sc_w_payld_UNCONNECTED(159 downto 0),
      m_sc_w_recv => '0',
      m_sc_w_req => NLW_inst_m_sc_w_req_UNCONNECTED,
      m_sc_w_send => NLW_inst_m_sc_w_send_UNCONNECTED,
      s_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      s_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      s_axi_arid(1 downto 0) => B"01",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arlock(0) => m_axi_arlock(0),
      s_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      s_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      s_axi_arready => s_axi_arready,
      s_axi_aruser(1023 downto 186) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_aruser(185 downto 179) => m_axi_aruser(24 downto 18),
      s_axi_aruser(178 downto 147) => B"00000000000000000000000000000000",
      s_axi_aruser(146 downto 136) => m_axi_aruser(17 downto 7),
      s_axi_aruser(135 downto 71) => B"00000000000000000000000000000000000000000000000000000000000000000",
      s_axi_aruser(70 downto 64) => m_axi_aruser(6 downto 0),
      s_axi_aruser(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_arvalid => m_axi_arvalid,
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awcache(3 downto 0) => B"0000",
      s_axi_awid(1 downto 0) => B"00",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awlock(0) => '0',
      s_axi_awprot(2 downto 0) => B"000",
      s_axi_awqos(3 downto 0) => B"0000",
      s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED,
      s_axi_awuser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awvalid => '0',
      s_axi_bid(1 downto 0) => NLW_inst_s_axi_bid_UNCONNECTED(1 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_buser(1023 downto 0) => NLW_inst_s_axi_buser_UNCONNECTED(1023 downto 0),
      s_axi_bvalid => NLW_inst_s_axi_bvalid_UNCONNECTED,
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rid(1 downto 0) => NLW_inst_s_axi_rid_UNCONNECTED(1 downto 0),
      s_axi_rlast => s_axi_rlast,
      s_axi_rready => m_axi_rready,
      s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      s_axi_ruser(1023 downto 0) => NLW_inst_s_axi_ruser_UNCONNECTED(1023 downto 0),
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wlast => '1',
      s_axi_wready => NLW_inst_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(3 downto 0) => B"1111",
      s_axi_wuser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wvalid => '0',
      s_sc_b_info(0) => '0',
      s_sc_b_payld(6 downto 0) => B"0000000",
      s_sc_b_recv => NLW_inst_s_sc_b_recv_UNCONNECTED,
      s_sc_b_req => '0',
      s_sc_b_send => '0',
      s_sc_r_info(0) => '0',
      s_sc_r_payld(148 downto 53) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_sc_r_payld(52 downto 18) => M_SC_R_payld(34 downto 0),
      s_sc_r_payld(17 downto 0) => B"000000000000000000",
      s_sc_r_recv => M_SC_R_recv(0),
      s_sc_r_req => '0',
      s_sc_r_send => M_SC_R_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_s01a2s_0 is
  port (
    M_SC_R_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_B_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_payld : out STD_LOGIC_VECTOR ( 68 downto 0 );
    S_SC_AW_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AW_payld : out STD_LOGIC_VECTOR ( 68 downto 0 );
    S_SC_W_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_W_payld : out STD_LOGIC_VECTOR ( 50 downto 0 );
    s_axi_awready : out STD_LOGIC;
    s_axi_wready : out STD_LOGIC;
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC;
    s_axi_arready : out STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : out STD_LOGIC;
    s_axi_rvalid : out STD_LOGIC;
    M_SC_R_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_payld : in STD_LOGIC_VECTOR ( 34 downto 0 );
    M_SC_B_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_B_payld : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S_SC_AR_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AW_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_W_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awuser : in STD_LOGIC_VECTOR ( 24 downto 0 );
    m_axi_awvalid : in STD_LOGIC;
    m_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_wlast : in STD_LOGIC;
    m_axi_wuser : in STD_LOGIC_VECTOR ( 13 downto 0 );
    m_axi_wvalid : in STD_LOGIC;
    m_axi_bready : in STD_LOGIC;
    m_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : in STD_LOGIC_VECTOR ( 24 downto 0 );
    m_axi_arvalid : in STD_LOGIC;
    m_axi_rready : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_s01a2s_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_s01a2s_0 is
  signal NLW_inst_m_sc_ar_req_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_sc_aw_req_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_sc_w_req_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_sc_ar_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_ar_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 0 );
  signal NLW_inst_m_sc_aw_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_aw_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 0 );
  signal NLW_inst_m_sc_w_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_w_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 159 downto 0 );
  signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  attribute C_ARPAYLD_WIDTH : integer;
  attribute C_ARPAYLD_WIDTH of inst : label is 140;
  attribute C_AWPAYLD_WIDTH : integer;
  attribute C_AWPAYLD_WIDTH of inst : label is 140;
  attribute C_AXI_ADDR_WIDTH : integer;
  attribute C_AXI_ADDR_WIDTH of inst : label is 32;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of inst : label is 2;
  attribute C_AXI_RDATA_WIDTH : integer;
  attribute C_AXI_RDATA_WIDTH of inst : label is 32;
  attribute C_AXI_WDATA_WIDTH : integer;
  attribute C_AXI_WDATA_WIDTH of inst : label is 32;
  attribute C_BPAYLD_WIDTH : integer;
  attribute C_BPAYLD_WIDTH of inst : label is 7;
  attribute C_MSC_ROUTE_WIDTH : integer;
  attribute C_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute C_RPAYLD_WIDTH : integer;
  attribute C_RPAYLD_WIDTH of inst : label is 149;
  attribute C_SC_ADDR_WIDTH : integer;
  attribute C_SC_ADDR_WIDTH of inst : label is 32;
  attribute C_SC_ARUSER_WIDTH : integer;
  attribute C_SC_ARUSER_WIDTH of inst : label is 0;
  attribute C_SC_AWUSER_WIDTH : integer;
  attribute C_SC_AWUSER_WIDTH of inst : label is 0;
  attribute C_SC_BUSER_WIDTH : integer;
  attribute C_SC_BUSER_WIDTH of inst : label is 0;
  attribute C_SC_ID_WIDTH : integer;
  attribute C_SC_ID_WIDTH of inst : label is 2;
  attribute C_SC_RDATA_WIDTH : integer;
  attribute C_SC_RDATA_WIDTH of inst : label is 128;
  attribute C_SC_RUSER_BITS_PER_BYTE : integer;
  attribute C_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_SC_WDATA_WIDTH : integer;
  attribute C_SC_WDATA_WIDTH of inst : label is 128;
  attribute C_SC_WUSER_BITS_PER_BYTE : integer;
  attribute C_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_SSC_ROUTE_WIDTH : integer;
  attribute C_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute C_WPAYLD_WIDTH : integer;
  attribute C_WPAYLD_WIDTH of inst : label is 160;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_NZ_AXI_ID_WIDTH : integer;
  attribute LP_NZ_AXI_ID_WIDTH of inst : label is 2;
  attribute LP_NZ_RUBPB : integer;
  attribute LP_NZ_RUBPB of inst : label is 1;
  attribute LP_NZ_WUBPB : integer;
  attribute LP_NZ_WUBPB of inst : label is 1;
  attribute LP_RUSER_INDEX : integer;
  attribute LP_RUSER_INDEX of inst : label is 0;
  attribute LP_WUSER_INDEX : integer;
  attribute LP_WUSER_INDEX of inst : label is 0;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 1;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 1;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 1;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_axi2sc_v1_0_10_top__1\
     port map (
      aclk => '0',
      m_sc_ar_info(0) => NLW_inst_m_sc_ar_info_UNCONNECTED(0),
      m_sc_ar_payld(139 downto 96) => S_SC_AR_payld(68 downto 25),
      m_sc_ar_payld(95 downto 93) => NLW_inst_m_sc_ar_payld_UNCONNECTED(95 downto 93),
      m_sc_ar_payld(92 downto 86) => S_SC_AR_payld(24 downto 18),
      m_sc_ar_payld(85 downto 84) => NLW_inst_m_sc_ar_payld_UNCONNECTED(85 downto 84),
      m_sc_ar_payld(83 downto 73) => S_SC_AR_payld(17 downto 7),
      m_sc_ar_payld(72 downto 8) => NLW_inst_m_sc_ar_payld_UNCONNECTED(72 downto 8),
      m_sc_ar_payld(7 downto 1) => S_SC_AR_payld(6 downto 0),
      m_sc_ar_payld(0) => NLW_inst_m_sc_ar_payld_UNCONNECTED(0),
      m_sc_ar_recv => S_SC_AR_recv(0),
      m_sc_ar_req => NLW_inst_m_sc_ar_req_UNCONNECTED,
      m_sc_ar_send => S_SC_AR_send(0),
      m_sc_aw_info(0) => NLW_inst_m_sc_aw_info_UNCONNECTED(0),
      m_sc_aw_payld(139 downto 96) => S_SC_AW_payld(68 downto 25),
      m_sc_aw_payld(95 downto 93) => NLW_inst_m_sc_aw_payld_UNCONNECTED(95 downto 93),
      m_sc_aw_payld(92 downto 86) => S_SC_AW_payld(24 downto 18),
      m_sc_aw_payld(85 downto 84) => NLW_inst_m_sc_aw_payld_UNCONNECTED(85 downto 84),
      m_sc_aw_payld(83 downto 73) => S_SC_AW_payld(17 downto 7),
      m_sc_aw_payld(72 downto 8) => NLW_inst_m_sc_aw_payld_UNCONNECTED(72 downto 8),
      m_sc_aw_payld(7 downto 1) => S_SC_AW_payld(6 downto 0),
      m_sc_aw_payld(0) => NLW_inst_m_sc_aw_payld_UNCONNECTED(0),
      m_sc_aw_recv => S_SC_AW_recv(0),
      m_sc_aw_req => NLW_inst_m_sc_aw_req_UNCONNECTED,
      m_sc_aw_send => S_SC_AW_send(0),
      m_sc_w_info(0) => NLW_inst_m_sc_w_info_UNCONNECTED(0),
      m_sc_w_payld(159 downto 52) => NLW_inst_m_sc_w_payld_UNCONNECTED(159 downto 52),
      m_sc_w_payld(51 downto 1) => S_SC_W_payld(50 downto 0),
      m_sc_w_payld(0) => NLW_inst_m_sc_w_payld_UNCONNECTED(0),
      m_sc_w_recv => S_SC_W_recv(0),
      m_sc_w_req => NLW_inst_m_sc_w_req_UNCONNECTED,
      m_sc_w_send => S_SC_W_send(0),
      s_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      s_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      s_axi_arid(1 downto 0) => B"10",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arlock(0) => m_axi_arlock(0),
      s_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      s_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      s_axi_arready => s_axi_arready,
      s_axi_aruser(1023 downto 186) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_aruser(185 downto 179) => m_axi_aruser(24 downto 18),
      s_axi_aruser(178 downto 147) => B"00000000000000000000000000000000",
      s_axi_aruser(146 downto 136) => m_axi_aruser(17 downto 7),
      s_axi_aruser(135 downto 71) => B"00000000000000000000000000000000000000000000000000000000000000000",
      s_axi_aruser(70 downto 64) => m_axi_aruser(6 downto 0),
      s_axi_aruser(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_arvalid => m_axi_arvalid,
      s_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
      s_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
      s_axi_awid(1 downto 0) => B"10",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awlock(0) => m_axi_awlock(0),
      s_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
      s_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
      s_axi_awready => s_axi_awready,
      s_axi_awuser(1023 downto 186) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awuser(185 downto 179) => m_axi_awuser(24 downto 18),
      s_axi_awuser(178 downto 147) => B"00000000000000000000000000000000",
      s_axi_awuser(146 downto 136) => m_axi_awuser(17 downto 7),
      s_axi_awuser(135 downto 71) => B"00000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awuser(70 downto 64) => m_axi_awuser(6 downto 0),
      s_axi_awuser(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awvalid => m_axi_awvalid,
      s_axi_bid(1 downto 0) => NLW_inst_s_axi_bid_UNCONNECTED(1 downto 0),
      s_axi_bready => m_axi_bready,
      s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
      s_axi_buser(1023 downto 0) => NLW_inst_s_axi_buser_UNCONNECTED(1023 downto 0),
      s_axi_bvalid => s_axi_bvalid,
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rid(1 downto 0) => NLW_inst_s_axi_rid_UNCONNECTED(1 downto 0),
      s_axi_rlast => s_axi_rlast,
      s_axi_rready => m_axi_rready,
      s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      s_axi_ruser(1023 downto 0) => NLW_inst_s_axi_ruser_UNCONNECTED(1023 downto 0),
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
      s_axi_wlast => m_axi_wlast,
      s_axi_wready => s_axi_wready,
      s_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
      s_axi_wuser(1023 downto 78) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wuser(77 downto 64) => m_axi_wuser(13 downto 0),
      s_axi_wuser(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wvalid => m_axi_wvalid,
      s_sc_b_info(0) => '0',
      s_sc_b_payld(6 downto 5) => M_SC_B_payld(1 downto 0),
      s_sc_b_payld(4 downto 0) => B"00000",
      s_sc_b_recv => M_SC_B_recv(0),
      s_sc_b_req => '0',
      s_sc_b_send => M_SC_B_send(0),
      s_sc_r_info(0) => '0',
      s_sc_r_payld(148 downto 53) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_sc_r_payld(52 downto 18) => M_SC_R_payld(34 downto 0),
      s_sc_r_payld(17 downto 0) => B"000000000000000000",
      s_sc_r_recv => M_SC_R_recv(0),
      s_sc_r_req => '0',
      s_sc_r_send => M_SC_R_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_lpf is
  port (
    lpf_int : out STD_LOGIC;
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_lpf;

architecture STRUCTURE of Loopback_smartconnect_0_0_lpf is
  signal Q : STD_LOGIC;
  signal lpf_asr : STD_LOGIC;
  signal lpf_int0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of POR_SRL_I : label is "VCC:CE";
  attribute box_type : string;
  attribute box_type of POR_SRL_I : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of POR_SRL_I : label is "inst/\clk_map/psr_aclk/U0/EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.Loopback_smartconnect_0_0_cdc_sync
     port map (
      aclk => aclk,
      aresetn => aresetn,
      scndry_out => p_0_in
    );
POR_SRL_I: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"FFFF"
    )
        port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => aclk,
      D => '0',
      Q => Q
    );
lpf_asr_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => p_0_in,
      Q => lpf_asr,
      R => '0'
    );
lpf_int_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => Q,
      I1 => lpf_asr,
      O => lpf_int0
    );
lpf_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => lpf_int0,
      Q => lpf_int,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_sequence_psr is
  port (
    bsr_reg_0 : out STD_LOGIC;
    lpf_int : in STD_LOGIC;
    aclk : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_sequence_psr;

architecture STRUCTURE of Loopback_smartconnect_0_0_sequence_psr is
  signal Bsr_out : STD_LOGIC;
  signal Core_i_1_n_0 : STD_LOGIC;
  signal MB_out : STD_LOGIC;
  signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
  signal \bsr_dec_reg_n_0_[1]\ : STD_LOGIC;
  signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
  signal bsr_i_1_n_0 : STD_LOGIC;
  signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
  signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
  signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
  signal from_sys_i_1_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \pr_dec0__0\ : STD_LOGIC;
  signal seq_clr : STD_LOGIC;
  signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal seq_cnt_en : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \bsr_dec[0]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => Bsr_out,
      O => bsr_reg_0
    );
Core_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MB_out,
      I1 => p_0_in,
      O => Core_i_1_n_0
    );
Core_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk,
      CE => '1',
      D => Core_i_1_n_0,
      Q => MB_out,
      S => lpf_int
    );
SEQ_COUNTER: entity work.Loopback_smartconnect_0_0_upcnt_n
     port map (
      Q(5 downto 0) => seq_cnt(5 downto 0),
      aclk => aclk,
      seq_clr => seq_clr,
      seq_cnt_en => seq_cnt_en
    );
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0090"
    )
        port map (
      I0 => seq_cnt_en,
      I1 => seq_cnt(4),
      I2 => seq_cnt(3),
      I3 => seq_cnt(5),
      O => p_5_out(0)
    );
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \bsr_dec_reg_n_0_[1]\,
      I1 => \bsr_dec_reg_n_0_[0]\,
      O => p_5_out(2)
    );
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => p_5_out(0),
      Q => \bsr_dec_reg_n_0_[0]\,
      R => '0'
    );
\bsr_dec_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \pr_dec0__0\,
      Q => \bsr_dec_reg_n_0_[1]\,
      R => '0'
    );
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => p_5_out(2),
      Q => \bsr_dec_reg_n_0_[2]\,
      R => '0'
    );
bsr_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Bsr_out,
      I1 => \bsr_dec_reg_n_0_[2]\,
      O => bsr_i_1_n_0
    );
bsr_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk,
      CE => '1',
      D => bsr_i_1_n_0,
      Q => Bsr_out,
      S => lpf_int
    );
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9000"
    )
        port map (
      I0 => seq_cnt_en,
      I1 => seq_cnt(4),
      I2 => seq_cnt(3),
      I3 => seq_cnt(5),
      O => \core_dec[0]_i_1_n_0\
    );
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \bsr_dec_reg_n_0_[1]\,
      I1 => \core_dec_reg_n_0_[0]\,
      O => \core_dec[2]_i_1_n_0\
    );
\core_dec_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \core_dec[0]_i_1_n_0\,
      Q => \core_dec_reg_n_0_[0]\,
      R => '0'
    );
\core_dec_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \core_dec[2]_i_1_n_0\,
      Q => p_0_in,
      R => '0'
    );
from_sys_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => MB_out,
      I1 => seq_cnt_en,
      O => from_sys_i_1_n_0
    );
from_sys_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => from_sys_i_1_n_0,
      Q => seq_cnt_en,
      S => lpf_int
    );
pr_dec0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => seq_cnt_en,
      I1 => seq_cnt(0),
      I2 => seq_cnt(2),
      I3 => seq_cnt(1),
      O => \pr_dec0__0\
    );
seq_clr_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => '1',
      Q => seq_clr,
      R => lpf_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 157 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 157 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 158;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 5056;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 158;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 158;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 157 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 157 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 158;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 158;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 5056;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 158;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 158;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 158;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 158;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 158;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 158;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 158;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 158;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 158;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 158;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 158;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 160;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 160;
begin
  dbiterrb <= \<const0>\;
  doutb(157) <= \<const0>\;
  doutb(156) <= \<const0>\;
  doutb(155) <= \<const0>\;
  doutb(154) <= \<const0>\;
  doutb(153) <= \<const0>\;
  doutb(152) <= \<const0>\;
  doutb(151) <= \<const0>\;
  doutb(150) <= \<const0>\;
  doutb(149) <= \<const0>\;
  doutb(148) <= \<const0>\;
  doutb(147) <= \<const0>\;
  doutb(146) <= \<const0>\;
  doutb(145) <= \<const0>\;
  doutb(144) <= \<const0>\;
  doutb(143) <= \<const0>\;
  doutb(142) <= \<const0>\;
  doutb(141) <= \<const0>\;
  doutb(140) <= \<const0>\;
  doutb(139 downto 129) <= \^doutb\(139 downto 129);
  doutb(128) <= \<const0>\;
  doutb(127 downto 94) <= \^doutb\(127 downto 94);
  doutb(93) <= \<const0>\;
  doutb(92 downto 86) <= \^doutb\(92 downto 86);
  doutb(85) <= \<const0>\;
  doutb(84) <= \<const0>\;
  doutb(83 downto 73) <= \^doutb\(83 downto 73);
  doutb(72) <= \<const0>\;
  doutb(71) <= \<const0>\;
  doutb(70) <= \<const0>\;
  doutb(69) <= \<const0>\;
  doutb(68) <= \<const0>\;
  doutb(67) <= \<const0>\;
  doutb(66) <= \<const0>\;
  doutb(65) <= \<const0>\;
  doutb(64) <= \<const0>\;
  doutb(63) <= \<const0>\;
  doutb(62) <= \<const0>\;
  doutb(61) <= \<const0>\;
  doutb(60) <= \<const0>\;
  doutb(59) <= \<const0>\;
  doutb(58) <= \<const0>\;
  doutb(57) <= \<const0>\;
  doutb(56) <= \<const0>\;
  doutb(55) <= \<const0>\;
  doutb(54) <= \<const0>\;
  doutb(53) <= \<const0>\;
  doutb(52) <= \<const0>\;
  doutb(51) <= \<const0>\;
  doutb(50) <= \<const0>\;
  doutb(49) <= \<const0>\;
  doutb(48) <= \<const0>\;
  doutb(47) <= \<const0>\;
  doutb(46) <= \<const0>\;
  doutb(45) <= \<const0>\;
  doutb(44) <= \<const0>\;
  doutb(43) <= \<const0>\;
  doutb(42) <= \<const0>\;
  doutb(41) <= \<const0>\;
  doutb(40) <= \<const0>\;
  doutb(39) <= \<const0>\;
  doutb(38) <= \<const0>\;
  doutb(37) <= \<const0>\;
  doutb(36) <= \<const0>\;
  doutb(35) <= \<const0>\;
  doutb(34) <= \<const0>\;
  doutb(33) <= \<const0>\;
  doutb(32) <= \<const0>\;
  doutb(31) <= \<const0>\;
  doutb(30) <= \<const0>\;
  doutb(29) <= \<const0>\;
  doutb(28) <= \<const0>\;
  doutb(27) <= \<const0>\;
  doutb(26) <= \<const0>\;
  doutb(25) <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8 downto 1) <= \^doutb\(8 downto 1);
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized0\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(157 downto 140) => B"000000000000000000",
      dina(139 downto 70) => dina(139 downto 70),
      dina(69 downto 14) => B"00000000000000000000000000000000000000000000000000000000",
      dina(13 downto 1) => dina(13 downto 1),
      dina(0) => '0',
      dinb(157 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(157 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(157 downto 0),
      doutb(157 downto 140) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(157 downto 140),
      doutb(139 downto 129) => \^doutb\(139 downto 129),
      doutb(128) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(128),
      doutb(127 downto 94) => \^doutb\(127 downto 94),
      doutb(93) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(93),
      doutb(92 downto 86) => \^doutb\(92 downto 86),
      doutb(85 downto 84) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(85 downto 84),
      doutb(83 downto 73) => \^doutb\(83 downto 73),
      doutb(72 downto 9) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(72 downto 9),
      doutb(8 downto 1) => \^doutb\(8 downto 1),
      doutb(0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 157 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 157 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 158;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 5056;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 158;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 158;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized0__2\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 157 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 157 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 158;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 158;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 5056;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 158;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 158;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 158;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 158;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 158;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 158;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 158;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 158;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 158;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 158;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 158;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 160;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 160;
begin
  dbiterrb <= \<const0>\;
  doutb(157) <= \<const0>\;
  doutb(156) <= \<const0>\;
  doutb(155) <= \<const0>\;
  doutb(154) <= \<const0>\;
  doutb(153) <= \<const0>\;
  doutb(152) <= \<const0>\;
  doutb(151) <= \<const0>\;
  doutb(150) <= \<const0>\;
  doutb(149) <= \<const0>\;
  doutb(148) <= \<const0>\;
  doutb(147) <= \<const0>\;
  doutb(146) <= \<const0>\;
  doutb(145) <= \<const0>\;
  doutb(144) <= \<const0>\;
  doutb(143) <= \<const0>\;
  doutb(142) <= \<const0>\;
  doutb(141) <= \<const0>\;
  doutb(140) <= \<const0>\;
  doutb(139 downto 129) <= \^doutb\(139 downto 129);
  doutb(128) <= \<const0>\;
  doutb(127 downto 94) <= \^doutb\(127 downto 94);
  doutb(93) <= \<const0>\;
  doutb(92) <= \<const0>\;
  doutb(91) <= \<const0>\;
  doutb(90) <= \<const0>\;
  doutb(89) <= \<const0>\;
  doutb(88) <= \<const0>\;
  doutb(87) <= \<const0>\;
  doutb(86) <= \<const0>\;
  doutb(85) <= \<const0>\;
  doutb(84) <= \<const0>\;
  doutb(83 downto 73) <= \^doutb\(83 downto 73);
  doutb(72) <= \<const0>\;
  doutb(71) <= \<const0>\;
  doutb(70) <= \<const0>\;
  doutb(69) <= \<const0>\;
  doutb(68) <= \<const0>\;
  doutb(67) <= \<const0>\;
  doutb(66) <= \<const0>\;
  doutb(65) <= \<const0>\;
  doutb(64) <= \<const0>\;
  doutb(63) <= \<const0>\;
  doutb(62) <= \<const0>\;
  doutb(61) <= \<const0>\;
  doutb(60) <= \<const0>\;
  doutb(59) <= \<const0>\;
  doutb(58) <= \<const0>\;
  doutb(57) <= \<const0>\;
  doutb(56) <= \<const0>\;
  doutb(55) <= \<const0>\;
  doutb(54) <= \<const0>\;
  doutb(53) <= \<const0>\;
  doutb(52) <= \<const0>\;
  doutb(51) <= \<const0>\;
  doutb(50) <= \<const0>\;
  doutb(49) <= \<const0>\;
  doutb(48) <= \<const0>\;
  doutb(47) <= \<const0>\;
  doutb(46) <= \<const0>\;
  doutb(45) <= \<const0>\;
  doutb(44) <= \<const0>\;
  doutb(43) <= \<const0>\;
  doutb(42) <= \<const0>\;
  doutb(41) <= \<const0>\;
  doutb(40) <= \<const0>\;
  doutb(39) <= \<const0>\;
  doutb(38) <= \<const0>\;
  doutb(37) <= \<const0>\;
  doutb(36) <= \<const0>\;
  doutb(35) <= \<const0>\;
  doutb(34) <= \<const0>\;
  doutb(33) <= \<const0>\;
  doutb(32) <= \<const0>\;
  doutb(31) <= \<const0>\;
  doutb(30) <= \<const0>\;
  doutb(29) <= \<const0>\;
  doutb(28) <= \<const0>\;
  doutb(27) <= \<const0>\;
  doutb(26) <= \<const0>\;
  doutb(25) <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8 downto 1) <= \^doutb\(8 downto 1);
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized0__2\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(157 downto 140) => B"000000000000000000",
      dina(139 downto 70) => dina(139 downto 70),
      dina(69 downto 14) => B"00000000000000000000000000000000000000000000000000000000",
      dina(13 downto 1) => dina(13 downto 1),
      dina(0) => '0',
      dinb(157 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(157 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(157 downto 0),
      doutb(157 downto 140) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(157 downto 140),
      doutb(139 downto 129) => \^doutb\(139 downto 129),
      doutb(128) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(128),
      doutb(127 downto 94) => \^doutb\(127 downto 94),
      doutb(93 downto 84) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(93 downto 84),
      doutb(83 downto 73) => \^doutb\(83 downto 73),
      doutb(72 downto 9) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(72 downto 9),
      doutb(8 downto 1) => \^doutb\(8 downto 1),
      doutb(0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 18 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 18 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 19;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 608;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 19;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 19;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 18 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 19;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 19;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 608;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 19;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 19;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 19;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 19;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 19;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 19;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 19;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 19;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 19;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 19;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 19;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 20;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 20;
begin
  dbiterrb <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \^doutb\(2);
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized1\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(18 downto 3) => B"0000000000000000",
      dina(2 downto 1) => dina(2 downto 1),
      dina(0) => '1',
      dinb(18 downto 0) => B"0000000000000000000",
      douta(18 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(18 downto 0),
      doutb(18 downto 3) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(18 downto 3),
      doutb(2) => \^doutb\(2),
      doutb(1 downto 0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(1 downto 0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 159 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 159 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 160;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 5120;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 160;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 160;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized10\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 159 downto 1 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 159 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 160;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 160;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 5120;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 160;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 160;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 160;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 160;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 160;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 160;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 160;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 160;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 160;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 160;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 160;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 160;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 160;
begin
  dbiterrb <= \<const0>\;
  doutb(159 downto 14) <= \^doutb\(159 downto 14);
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \^doutb\(8);
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \^doutb\(1);
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized10\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(159 downto 1) => dina(159 downto 1),
      dina(0) => '0',
      dinb(159 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(159 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(159 downto 0),
      doutb(159 downto 14) => \^doutb\(159 downto 14),
      doutb(13 downto 9) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(13 downto 9),
      doutb(8) => \^doutb\(8),
      doutb(7 downto 2) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(7 downto 2),
      doutb(1) => \^doutb\(1),
      doutb(0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 18 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 18 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 19;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 608;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 19;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 19;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized1__2\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 18 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 19;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 19;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 608;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 19;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 19;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 19;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 19;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 19;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 19;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 19;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 19;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 19;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 19;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 19;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 20;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 20;
begin
  dbiterrb <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2 downto 1) <= \^doutb\(2 downto 1);
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized1__2\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(18 downto 13) => B"000000",
      dina(12) => dina(12),
      dina(11 downto 6) => B"000000",
      dina(5 downto 4) => dina(5 downto 4),
      dina(3) => '0',
      dina(2 downto 0) => dina(2 downto 0),
      dinb(18 downto 0) => B"0000000000000000000",
      douta(18 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(18 downto 0),
      doutb(18 downto 3) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(18 downto 3),
      doutb(2 downto 1) => \^doutb\(2 downto 1),
      doutb(0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 6 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 6 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 7;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 224;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 7;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 7;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized2\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 7;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 7;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 224;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 7;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 7;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 7;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 7;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 7;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 7;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 7;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 7;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 7;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 7;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 7;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 8;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 8;
begin
  dbiterrb <= \<const0>\;
  doutb(6 downto 1) <= \^doutb\(6 downto 1);
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized2\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(6 downto 3) => dina(6 downto 3),
      dina(2 downto 0) => B"000",
      dinb(6 downto 0) => B"0000000",
      douta(6 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(6 downto 0),
      doutb(6 downto 1) => \^doutb\(6 downto 1),
      doutb(0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 148 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 148 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 149;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 4768;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 149;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 149;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized3\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 148 downto 4 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 148 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 149;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 149;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 4768;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 149;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 149;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 149;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 149;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 149;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 149;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 149;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 149;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 149;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 149;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 149;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 152;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 152;
begin
  dbiterrb <= \<const0>\;
  doutb(148 downto 14) <= \^doutb\(148 downto 14);
  doutb(13) <= \<const0>\;
  doutb(12 downto 11) <= \^doutb\(12 downto 11);
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5 downto 4) <= \^doutb\(5 downto 4);
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized3\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(148 downto 2) => dina(148 downto 2),
      dina(1 downto 0) => B"00",
      dinb(148 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(148 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(148 downto 0),
      doutb(148 downto 14) => \^doutb\(148 downto 14),
      doutb(13) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(13),
      doutb(12 downto 11) => \^doutb\(12 downto 11),
      doutb(10 downto 6) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(10 downto 6),
      doutb(5 downto 4) => \^doutb\(5 downto 4),
      doutb(3 downto 0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(3 downto 0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 0 to 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 0 to 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 2;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 2;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 1;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 4;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 1;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 1;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized4__2\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 2;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 2;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 1;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 1;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 4;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 4;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 1;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 1;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 1;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 1;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 1;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 5;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 2;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 2;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 2;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 2;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 1;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 1;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 0;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 4;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 4;
begin
  dbiterrb <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized4__2\
     port map (
      addra(1 downto 0) => addra(1 downto 0),
      addrb(1 downto 0) => addrb(1 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(0) => dina(0),
      dinb(0) => '0',
      douta(0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(0),
      doutb(0) => doutb(0),
      ena => '1',
      enb => '0',
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => '0',
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 177 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 177 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 178;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 5696;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 178;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 178;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized5\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 159 downto 15 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 177 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 177 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 178;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 178;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 5696;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 178;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 178;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 178;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 178;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 178;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 178;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 178;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 178;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 178;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 178;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 178;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 180;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 180;
begin
  dbiterrb <= \<const0>\;
  doutb(177) <= \<const0>\;
  doutb(176) <= \<const0>\;
  doutb(175) <= \<const0>\;
  doutb(174) <= \<const0>\;
  doutb(173) <= \<const0>\;
  doutb(172) <= \<const0>\;
  doutb(171) <= \<const0>\;
  doutb(170) <= \<const0>\;
  doutb(169) <= \<const0>\;
  doutb(168) <= \<const0>\;
  doutb(167) <= \<const0>\;
  doutb(166) <= \<const0>\;
  doutb(165) <= \<const0>\;
  doutb(164) <= \<const0>\;
  doutb(163) <= \<const0>\;
  doutb(162) <= \<const0>\;
  doutb(161) <= \<const0>\;
  doutb(160) <= \<const0>\;
  doutb(159 downto 15) <= \^doutb\(159 downto 15);
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized5\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(177 downto 165) => B"0000000000000",
      dina(164 downto 162) => dina(164 downto 162),
      dina(161) => '1',
      dina(160 downto 16) => dina(160 downto 16),
      dina(15) => '0',
      dina(14) => dina(14),
      dina(13 downto 0) => B"00000000000000",
      dinb(177 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(177 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(177 downto 0),
      doutb(177 downto 160) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(177 downto 160),
      doutb(159 downto 15) => \^doutb\(159 downto 15),
      doutb(14 downto 0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(14 downto 0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 17 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 17 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 18;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 576;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 18;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 18;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized6__3\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 1 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 18;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 18;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 576;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 18;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 18;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 18;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 18;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 18;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 18;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 18;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 18;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 18;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 18;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 18;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 20;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 20;
begin
  dbiterrb <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \^doutb\(0);
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized6__3\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(17 downto 12) => B"000000",
      dina(11) => dina(11),
      dina(10 downto 5) => B"000000",
      dina(4 downto 3) => dina(4 downto 3),
      dina(2) => '0',
      dina(1 downto 0) => dina(1 downto 0),
      dinb(17 downto 0) => B"000000000000000000",
      douta(17 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(17 downto 0),
      doutb(17 downto 1) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(17 downto 1),
      doutb(0) => \^doutb\(0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 139 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 139 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 140;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 4480;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 140;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 140;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 139 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 69 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 140;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 140;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 4480;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 140;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 140;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 140;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 140;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 140;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 140;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 140;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 140;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 140;
begin
  dbiterrb <= \<const0>\;
  doutb(139 downto 70) <= \^doutb\(139 downto 70);
  doutb(69) <= \<const0>\;
  doutb(68) <= \<const0>\;
  doutb(67) <= \<const0>\;
  doutb(66) <= \<const0>\;
  doutb(65) <= \<const0>\;
  doutb(64) <= \<const0>\;
  doutb(63) <= \<const0>\;
  doutb(62) <= \<const0>\;
  doutb(61) <= \<const0>\;
  doutb(60) <= \<const0>\;
  doutb(59) <= \<const0>\;
  doutb(58) <= \<const0>\;
  doutb(57) <= \<const0>\;
  doutb(56) <= \<const0>\;
  doutb(55) <= \<const0>\;
  doutb(54) <= \<const0>\;
  doutb(53) <= \<const0>\;
  doutb(52) <= \<const0>\;
  doutb(51) <= \<const0>\;
  doutb(50) <= \<const0>\;
  doutb(49) <= \<const0>\;
  doutb(48) <= \<const0>\;
  doutb(47) <= \<const0>\;
  doutb(46) <= \<const0>\;
  doutb(45) <= \<const0>\;
  doutb(44) <= \<const0>\;
  doutb(43) <= \<const0>\;
  doutb(42) <= \<const0>\;
  doutb(41) <= \<const0>\;
  doutb(40) <= \<const0>\;
  doutb(39) <= \<const0>\;
  doutb(38) <= \<const0>\;
  doutb(37) <= \<const0>\;
  doutb(36) <= \<const0>\;
  doutb(35) <= \<const0>\;
  doutb(34) <= \<const0>\;
  doutb(33) <= \<const0>\;
  doutb(32) <= \<const0>\;
  doutb(31) <= \<const0>\;
  doutb(30) <= \<const0>\;
  doutb(29) <= \<const0>\;
  doutb(28) <= \<const0>\;
  doutb(27) <= \<const0>\;
  doutb(26) <= \<const0>\;
  doutb(25) <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13 downto 1) <= \^doutb\(13 downto 1);
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized7\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(139 downto 96) => dina(139 downto 96),
      dina(95 downto 93) => B"010",
      dina(92 downto 86) => dina(92 downto 86),
      dina(85 downto 84) => B"00",
      dina(83 downto 73) => dina(83 downto 73),
      dina(72 downto 8) => B"00000000000000000000000000000000000000000000000000000000000000000",
      dina(7 downto 1) => dina(7 downto 1),
      dina(0) => '0',
      dinb(139 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(139 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(139 downto 0),
      doutb(139 downto 70) => \^doutb\(139 downto 70),
      doutb(69 downto 14) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(69 downto 14),
      doutb(13 downto 1) => \^doutb\(13 downto 1),
      doutb(0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 139 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 139 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 140;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 4480;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 140;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 140;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__3\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 139 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 69 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 140;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 140;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 4480;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 140;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 140;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 140;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 140;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 140;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 140;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 140;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 140;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 140;
begin
  dbiterrb <= \<const0>\;
  doutb(139 downto 70) <= \^doutb\(139 downto 70);
  doutb(69) <= \<const0>\;
  doutb(68) <= \<const0>\;
  doutb(67) <= \<const0>\;
  doutb(66) <= \<const0>\;
  doutb(65) <= \<const0>\;
  doutb(64) <= \<const0>\;
  doutb(63) <= \<const0>\;
  doutb(62) <= \<const0>\;
  doutb(61) <= \<const0>\;
  doutb(60) <= \<const0>\;
  doutb(59) <= \<const0>\;
  doutb(58) <= \<const0>\;
  doutb(57) <= \<const0>\;
  doutb(56) <= \<const0>\;
  doutb(55) <= \<const0>\;
  doutb(54) <= \<const0>\;
  doutb(53) <= \<const0>\;
  doutb(52) <= \<const0>\;
  doutb(51) <= \<const0>\;
  doutb(50) <= \<const0>\;
  doutb(49) <= \<const0>\;
  doutb(48) <= \<const0>\;
  doutb(47) <= \<const0>\;
  doutb(46) <= \<const0>\;
  doutb(45) <= \<const0>\;
  doutb(44) <= \<const0>\;
  doutb(43) <= \<const0>\;
  doutb(42) <= \<const0>\;
  doutb(41) <= \<const0>\;
  doutb(40) <= \<const0>\;
  doutb(39) <= \<const0>\;
  doutb(38) <= \<const0>\;
  doutb(37) <= \<const0>\;
  doutb(36) <= \<const0>\;
  doutb(35) <= \<const0>\;
  doutb(34) <= \<const0>\;
  doutb(33) <= \<const0>\;
  doutb(32) <= \<const0>\;
  doutb(31) <= \<const0>\;
  doutb(30) <= \<const0>\;
  doutb(29) <= \<const0>\;
  doutb(28) <= \<const0>\;
  doutb(27) <= \<const0>\;
  doutb(26) <= \<const0>\;
  doutb(25) <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13 downto 1) <= \^doutb\(13 downto 1);
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__3\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(139 downto 96) => dina(139 downto 96),
      dina(95 downto 93) => B"100",
      dina(92 downto 86) => dina(92 downto 86),
      dina(85 downto 84) => B"00",
      dina(83 downto 73) => dina(83 downto 73),
      dina(72 downto 8) => B"00000000000000000000000000000000000000000000000000000000000000000",
      dina(7 downto 1) => dina(7 downto 1),
      dina(0) => '0',
      dinb(139 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(139 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(139 downto 0),
      doutb(139 downto 70) => \^doutb\(139 downto 70),
      doutb(69 downto 14) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(69 downto 14),
      doutb(13 downto 1) => \^doutb\(13 downto 1),
      doutb(0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 139 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 139 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 140;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 4480;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 140;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 140;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized7__4\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 139 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 69 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 140;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 140;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 4480;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 140;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 140;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 140;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 140;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 140;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 140;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 140;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 140;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 140;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 140;
begin
  dbiterrb <= \<const0>\;
  doutb(139 downto 70) <= \^doutb\(139 downto 70);
  doutb(69) <= \<const0>\;
  doutb(68) <= \<const0>\;
  doutb(67) <= \<const0>\;
  doutb(66) <= \<const0>\;
  doutb(65) <= \<const0>\;
  doutb(64) <= \<const0>\;
  doutb(63) <= \<const0>\;
  doutb(62) <= \<const0>\;
  doutb(61) <= \<const0>\;
  doutb(60) <= \<const0>\;
  doutb(59) <= \<const0>\;
  doutb(58) <= \<const0>\;
  doutb(57) <= \<const0>\;
  doutb(56) <= \<const0>\;
  doutb(55) <= \<const0>\;
  doutb(54) <= \<const0>\;
  doutb(53) <= \<const0>\;
  doutb(52) <= \<const0>\;
  doutb(51) <= \<const0>\;
  doutb(50) <= \<const0>\;
  doutb(49) <= \<const0>\;
  doutb(48) <= \<const0>\;
  doutb(47) <= \<const0>\;
  doutb(46) <= \<const0>\;
  doutb(45) <= \<const0>\;
  doutb(44) <= \<const0>\;
  doutb(43) <= \<const0>\;
  doutb(42) <= \<const0>\;
  doutb(41) <= \<const0>\;
  doutb(40) <= \<const0>\;
  doutb(39) <= \<const0>\;
  doutb(38) <= \<const0>\;
  doutb(37) <= \<const0>\;
  doutb(36) <= \<const0>\;
  doutb(35) <= \<const0>\;
  doutb(34) <= \<const0>\;
  doutb(33) <= \<const0>\;
  doutb(32) <= \<const0>\;
  doutb(31) <= \<const0>\;
  doutb(30) <= \<const0>\;
  doutb(29) <= \<const0>\;
  doutb(28) <= \<const0>\;
  doutb(27) <= \<const0>\;
  doutb(26) <= \<const0>\;
  doutb(25) <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13 downto 1) <= \^doutb\(13 downto 1);
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized7__4\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(139 downto 96) => dina(139 downto 96),
      dina(95 downto 93) => B"100",
      dina(92 downto 86) => dina(92 downto 86),
      dina(85 downto 84) => B"00",
      dina(83 downto 73) => dina(83 downto 73),
      dina(72 downto 8) => B"00000000000000000000000000000000000000000000000000000000000000000",
      dina(7 downto 1) => dina(7 downto 1),
      dina(0) => '0',
      dinb(139 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(139 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(139 downto 0),
      doutb(139 downto 70) => \^doutb\(139 downto 70),
      doutb(69 downto 14) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(69 downto 14),
      doutb(13 downto 1) => \^doutb\(13 downto 1),
      doutb(0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 167 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 167 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 168;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 5376;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 168;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 168;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 155 downto 18 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 167 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 167 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 168;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 168;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 5376;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 168;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 168;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 168;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 168;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 168;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 168;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 168;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 168;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 168;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 168;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 168;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 168;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 168;
begin
  dbiterrb <= \<const0>\;
  doutb(167) <= \<const0>\;
  doutb(166) <= \<const0>\;
  doutb(165) <= \<const0>\;
  doutb(164) <= \<const0>\;
  doutb(163) <= \<const0>\;
  doutb(162) <= \<const0>\;
  doutb(161) <= \<const0>\;
  doutb(160) <= \<const0>\;
  doutb(159) <= \<const0>\;
  doutb(158) <= \<const0>\;
  doutb(157) <= \<const0>\;
  doutb(156) <= \<const0>\;
  doutb(155 downto 152) <= \^doutb\(155 downto 152);
  doutb(151) <= \<const0>\;
  doutb(150) <= \<const0>\;
  doutb(149) <= \<const0>\;
  doutb(148 downto 18) <= \^doutb\(148 downto 18);
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized8\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(167 downto 163) => B"00000",
      dina(162 downto 161) => dina(162 downto 161),
      dina(160 downto 156) => B"00000",
      dina(155 downto 152) => dina(155 downto 152),
      dina(151 downto 149) => B"010",
      dina(148 downto 14) => dina(148 downto 14),
      dina(13 downto 0) => B"00000000000000",
      dinb(167 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(167 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(167 downto 0),
      doutb(167 downto 156) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(167 downto 156),
      doutb(155 downto 152) => \^doutb\(155 downto 152),
      doutb(151 downto 149) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(151 downto 149),
      doutb(148 downto 18) => \^doutb\(148 downto 18),
      doutb(17 downto 0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(17 downto 0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 167 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 167 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 168;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 5376;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 168;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 168;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized8__2\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 155 downto 18 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 167 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 167 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 168;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 168;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 5376;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 168;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 168;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 168;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 168;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 168;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 168;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 168;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 168;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 168;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 168;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 168;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 168;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 168;
begin
  dbiterrb <= \<const0>\;
  doutb(167) <= \<const0>\;
  doutb(166) <= \<const0>\;
  doutb(165) <= \<const0>\;
  doutb(164) <= \<const0>\;
  doutb(163) <= \<const0>\;
  doutb(162) <= \<const0>\;
  doutb(161) <= \<const0>\;
  doutb(160) <= \<const0>\;
  doutb(159) <= \<const0>\;
  doutb(158) <= \<const0>\;
  doutb(157) <= \<const0>\;
  doutb(156) <= \<const0>\;
  doutb(155 downto 152) <= \^doutb\(155 downto 152);
  doutb(151) <= \<const0>\;
  doutb(150) <= \<const0>\;
  doutb(149) <= \<const0>\;
  doutb(148 downto 18) <= \^doutb\(148 downto 18);
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6) <= \<const0>\;
  doutb(5) <= \<const0>\;
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized8__2\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(167 downto 163) => B"00000",
      dina(162 downto 161) => dina(162 downto 161),
      dina(160 downto 156) => B"00000",
      dina(155 downto 152) => dina(155 downto 152),
      dina(151 downto 149) => B"010",
      dina(148 downto 14) => dina(148 downto 14),
      dina(13 downto 0) => B"00000000000000",
      dinb(167 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(167 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(167 downto 0),
      doutb(167 downto 156) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(167 downto 156),
      doutb(155 downto 152) => \^doutb\(155 downto 152),
      doutb(151 downto 149) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(151 downto 149),
      doutb(148 downto 18) => \^doutb\(148 downto 18),
      doutb(17 downto 0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(17 downto 0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 24 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 24 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 25;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 800;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "xpm_memory_sdpram";
  attribute P_CLOCKING_MODE : integer;
  attribute P_CLOCKING_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute P_MEMORY_OPTIMIZATION : integer;
  attribute P_MEMORY_OPTIMIZATION of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 1;
  attribute P_MEMORY_PRIMITIVE : integer;
  attribute P_MEMORY_PRIMITIVE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute P_WRITE_MODE_B : integer;
  attribute P_WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 1;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "auto";
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 25;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 1;
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 25;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ : entity is "true";
end \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\;

architecture STRUCTURE of \Loopback_smartconnect_0_0_xpm_memory_sdpram__parameterized9\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 6 downto 5 );
  signal NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_memory_base_inst_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_xpm_memory_base_inst_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 5;
  attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 5;
  attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
  attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 25;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 25;
  attribute CASCADE_HEIGHT of xpm_memory_base_inst : label is 0;
  attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_BIT_RANGE of xpm_memory_base_inst : label is "[7:0]";
  attribute ECC_MODE of xpm_memory_base_inst : label is 0;
  attribute ECC_TYPE of xpm_memory_base_inst : label is "NONE";
  attribute IGNORE_INIT_SYNTH of xpm_memory_base_inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of xpm_memory_base_inst : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
  attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
  attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
  attribute MEMORY_OPTIMIZATION of xpm_memory_base_inst : label is "true";
  attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 1;
  attribute MEMORY_SIZE of xpm_memory_base_inst : label is 800;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of xpm_memory_base_inst : label is 1;
  attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
  attribute P_ECC_MODE_string : string;
  attribute P_ECC_MODE_string of xpm_memory_base_inst : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of xpm_memory_base_inst : label is "yes";
  attribute P_MEMORY_PRIMITIVE_string : string;
  attribute P_MEMORY_PRIMITIVE_string of xpm_memory_base_inst : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 25;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 25;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 25;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 25;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 25;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 25;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 25;
  attribute RAM_DECOMP of xpm_memory_base_inst : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 25;
  attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 25;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of xpm_memory_base_inst : label is 2;
  attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
  attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
  attribute RST_MODE_A of xpm_memory_base_inst : label is "SYNC";
  attribute RST_MODE_B of xpm_memory_base_inst : label is "SYNC";
  attribute SIM_ASSERT_CHK of xpm_memory_base_inst : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT of xpm_memory_base_inst : label is 0;
  attribute USE_MEM_INIT_MMI of xpm_memory_base_inst : label is 0;
  attribute VERSION : integer;
  attribute VERSION of xpm_memory_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
  attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 25;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 25;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
  attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
  attribute WRITE_PROTECT of xpm_memory_base_inst : label is 1;
  attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of xpm_memory_base_inst : label is 28;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of xpm_memory_base_inst : label is 28;
begin
  dbiterrb <= \<const0>\;
  doutb(24) <= \<const0>\;
  doutb(23) <= \<const0>\;
  doutb(22) <= \<const0>\;
  doutb(21) <= \<const0>\;
  doutb(20) <= \<const0>\;
  doutb(19) <= \<const0>\;
  doutb(18) <= \<const0>\;
  doutb(17) <= \<const0>\;
  doutb(16) <= \<const0>\;
  doutb(15) <= \<const0>\;
  doutb(14) <= \<const0>\;
  doutb(13) <= \<const0>\;
  doutb(12) <= \<const0>\;
  doutb(11) <= \<const0>\;
  doutb(10) <= \<const0>\;
  doutb(9) <= \<const0>\;
  doutb(8) <= \<const0>\;
  doutb(7) <= \<const0>\;
  doutb(6 downto 5) <= \^doutb\(6 downto 5);
  doutb(4) <= \<const0>\;
  doutb(3) <= \<const0>\;
  doutb(2) <= \<const0>\;
  doutb(1) <= \<const0>\;
  doutb(0) <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_memory_base_inst: entity work.\Loopback_smartconnect_0_0_xpm_memory_base__parameterized9\
     port map (
      addra(4 downto 0) => addra(4 downto 0),
      addrb(4 downto 0) => addrb(4 downto 0),
      clka => clka,
      clkb => '0',
      dbiterra => NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED,
      dbiterrb => NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED,
      dina(24 downto 7) => B"000000000000000011",
      dina(6 downto 2) => dina(6 downto 2),
      dina(1) => '0',
      dina(0) => dina(0),
      dinb(24 downto 0) => B"0000000000000000000000000",
      douta(24 downto 0) => NLW_xpm_memory_base_inst_douta_UNCONNECTED(24 downto 0),
      doutb(24 downto 7) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(24 downto 7),
      doutb(6 downto 5) => \^doutb\(6 downto 5),
      doutb(4 downto 0) => NLW_xpm_memory_base_inst_doutb_UNCONNECTED(4 downto 0),
      ena => '1',
      enb => enb,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => rstb,
      sbiterra => NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED,
      sbiterrb => NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED,
      sleep => sleep,
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_arsw_0 is
  port (
    s_sc_recv : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_SC_AR_send : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_SC_AR_req : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_SC_AR_payld : out STD_LOGIC_VECTOR ( 82 downto 0 );
    aclk : in STD_LOGIC;
    s_sc_send : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_sc_req : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_sc_payld : in STD_LOGIC_VECTOR ( 165 downto 0 );
    M00_SC_AR_recv : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_arsw_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_arsw_0 is
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 69 downto 0 );
  attribute C_CONNECTIVITY : string;
  attribute C_CONNECTIVITY of inst : label is "2'b11";
  attribute C_M_PIPELINES : string;
  attribute C_M_PIPELINES of inst : label is "32'b00000000000000000000000000000001";
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 2;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 140;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 0;
  attribute C_S_PIPELINES : string;
  attribute C_S_PIPELINES of inst : label is "32'b00000000000000000000000000000000";
  attribute C_TESTING_MODE : integer;
  attribute C_TESTING_MODE of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute K_MAX_INFO_WIDTH : integer;
  attribute K_MAX_INFO_WIDTH of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_MUX_IMPL : string;
  attribute LP_MUX_IMPL of inst : label is "32'b00000000000000000000000000000000";
  attribute LP_M_SC_SEL_MI_PIPELINE_DEPTH : string;
  attribute LP_M_SC_SEL_MI_PIPELINE_DEPTH of inst : label is "32'b00000000000000000000000000000000";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.Loopback_smartconnect_0_0_sc_switchboard_v1_0_8_top
     port map (
      aclk => aclk,
      aclken => '1',
      connectivity(1 downto 0) => B"11",
      m_sc_info(1 downto 0) => NLW_inst_m_sc_info_UNCONNECTED(1 downto 0),
      m_sc_payld(139 downto 70) => M00_SC_AR_payld(82 downto 13),
      m_sc_payld(69 downto 14) => NLW_inst_m_sc_payld_UNCONNECTED(69 downto 14),
      m_sc_payld(13 downto 1) => M00_SC_AR_payld(12 downto 0),
      m_sc_payld(0) => NLW_inst_m_sc_payld_UNCONNECTED(0),
      m_sc_recv(1 downto 0) => M00_SC_AR_recv(1 downto 0),
      m_sc_req(1 downto 0) => M00_SC_AR_req(1 downto 0),
      m_sc_send(1 downto 0) => M00_SC_AR_send(1 downto 0),
      s_sc_info(1 downto 0) => B"00",
      s_sc_payld(279 downto 210) => s_sc_payld(165 downto 96),
      s_sc_payld(209 downto 154) => B"00000000000000000000000000000000000000000000000000000000",
      s_sc_payld(153 downto 141) => s_sc_payld(95 downto 83),
      s_sc_payld(140) => '0',
      s_sc_payld(139 downto 70) => s_sc_payld(82 downto 13),
      s_sc_payld(69 downto 14) => B"00000000000000000000000000000000000000000000000000000000",
      s_sc_payld(13 downto 1) => s_sc_payld(12 downto 0),
      s_sc_payld(0) => '0',
      s_sc_recv(1 downto 0) => s_sc_recv(1 downto 0),
      s_sc_req(1 downto 0) => s_sc_req(1 downto 0),
      s_sc_send(1 downto 0) => s_sc_send(1 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_awsw_0 is
  port (
    S01_SC_AW_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_payld : out STD_LOGIC_VECTOR ( 82 downto 0 );
    aclk : in STD_LOGIC;
    S01_SC_AW_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_SC_AW_req : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_SC_AW_payld : in STD_LOGIC_VECTOR ( 82 downto 0 );
    M00_SC_AW_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_awsw_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_awsw_0 is
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 69 downto 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_send_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_sc_recv_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_CONNECTIVITY : string;
  attribute C_CONNECTIVITY of inst : label is "2'b11";
  attribute C_M_PIPELINES : string;
  attribute C_M_PIPELINES of inst : label is "32'b00000000000000000000000000000001";
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 2;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 140;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 0;
  attribute C_S_PIPELINES : string;
  attribute C_S_PIPELINES of inst : label is "32'b00000000000000000000000000000000";
  attribute C_TESTING_MODE : integer;
  attribute C_TESTING_MODE of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute K_MAX_INFO_WIDTH : integer;
  attribute K_MAX_INFO_WIDTH of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_MUX_IMPL : string;
  attribute LP_MUX_IMPL of inst : label is "32'b00000000000000000000000000000000";
  attribute LP_M_SC_SEL_MI_PIPELINE_DEPTH : string;
  attribute LP_M_SC_SEL_MI_PIPELINE_DEPTH of inst : label is "32'b00000000000000000000000000000000";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_switchboard_v1_0_8_top__1\
     port map (
      aclk => aclk,
      aclken => '1',
      connectivity(1 downto 0) => B"11",
      m_sc_info(1 downto 0) => NLW_inst_m_sc_info_UNCONNECTED(1 downto 0),
      m_sc_payld(139 downto 70) => M00_SC_AW_payld(82 downto 13),
      m_sc_payld(69 downto 14) => NLW_inst_m_sc_payld_UNCONNECTED(69 downto 14),
      m_sc_payld(13 downto 1) => M00_SC_AW_payld(12 downto 0),
      m_sc_payld(0) => NLW_inst_m_sc_payld_UNCONNECTED(0),
      m_sc_recv(1) => M00_SC_AW_recv(0),
      m_sc_recv(0) => '0',
      m_sc_req(1) => M00_SC_AW_req(0),
      m_sc_req(0) => NLW_inst_m_sc_req_UNCONNECTED(0),
      m_sc_send(1) => M00_SC_AW_send(0),
      m_sc_send(0) => NLW_inst_m_sc_send_UNCONNECTED(0),
      s_sc_info(1 downto 0) => B"00",
      s_sc_payld(279 downto 210) => S01_SC_AW_payld(82 downto 13),
      s_sc_payld(209 downto 154) => B"00000000000000000000000000000000000000000000000000000000",
      s_sc_payld(153 downto 141) => S01_SC_AW_payld(12 downto 0),
      s_sc_payld(140 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_sc_recv(1) => S01_SC_AW_recv(0),
      s_sc_recv(0) => NLW_inst_s_sc_recv_UNCONNECTED(0),
      s_sc_req(1) => S01_SC_AW_req(0),
      s_sc_req(0) => '0',
      s_sc_send(1) => S01_SC_AW_send(0),
      s_sc_send(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_bsw_0 is
  port (
    S00_SC_B_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_B_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_B_payld : out STD_LOGIC_VECTOR ( 5 downto 0 );
    aclk : in STD_LOGIC;
    S00_SC_B_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_SC_B_payld : in STD_LOGIC_VECTOR ( 5 downto 0 );
    M01_SC_B_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_bsw_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_bsw_0 is
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_sc_send_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_sc_recv_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_CONNECTIVITY : string;
  attribute C_CONNECTIVITY of inst : label is "2'b11";
  attribute C_M_PIPELINES : string;
  attribute C_M_PIPELINES of inst : label is "32'b00000000000000000000000000000001";
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 2;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 1;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 7;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 0;
  attribute C_S_PIPELINES : string;
  attribute C_S_PIPELINES of inst : label is "32'b00000000000000000000000000000000";
  attribute C_TESTING_MODE : integer;
  attribute C_TESTING_MODE of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute K_MAX_INFO_WIDTH : integer;
  attribute K_MAX_INFO_WIDTH of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_MUX_IMPL : string;
  attribute LP_MUX_IMPL of inst : label is "32'b00000000000000000000000000000000";
  attribute LP_M_SC_SEL_MI_PIPELINE_DEPTH : string;
  attribute LP_M_SC_SEL_MI_PIPELINE_DEPTH of inst : label is "32'b00000000000000000000000000000000";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_switchboard_v1_0_8_top__parameterized0\
     port map (
      aclk => aclk,
      aclken => '1',
      connectivity(1 downto 0) => B"11",
      m_sc_info(1 downto 0) => NLW_inst_m_sc_info_UNCONNECTED(1 downto 0),
      m_sc_payld(13 downto 8) => M01_SC_B_payld(5 downto 0),
      m_sc_payld(7 downto 0) => NLW_inst_m_sc_payld_UNCONNECTED(7 downto 0),
      m_sc_recv(1) => M01_SC_B_recv(0),
      m_sc_recv(0) => '0',
      m_sc_req(1 downto 0) => NLW_inst_m_sc_req_UNCONNECTED(1 downto 0),
      m_sc_send(1) => M01_SC_B_send(0),
      m_sc_send(0) => NLW_inst_m_sc_send_UNCONNECTED(0),
      s_sc_info(1 downto 0) => B"00",
      s_sc_payld(6 downto 1) => S00_SC_B_payld(5 downto 0),
      s_sc_payld(0) => '0',
      s_sc_recv(1) => S00_SC_B_recv(0),
      s_sc_recv(0) => NLW_inst_s_sc_recv_UNCONNECTED(0),
      s_sc_req(1 downto 0) => B"00",
      s_sc_send(1) => S00_SC_B_send(0),
      s_sc_send(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_rsw_0 is
  port (
    S00_SC_R_recv : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_sc_send : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_sc_payld : out STD_LOGIC_VECTOR ( 277 downto 0 );
    aclk : in STD_LOGIC;
    S00_SC_R_send : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_SC_R_payld : in STD_LOGIC_VECTOR ( 138 downto 0 );
    m_sc_recv : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_rsw_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_rsw_0 is
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 162 downto 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_CONNECTIVITY : string;
  attribute C_CONNECTIVITY of inst : label is "2'b11";
  attribute C_M_PIPELINES : string;
  attribute C_M_PIPELINES of inst : label is "32'b00000000000000000000000000000001";
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 2;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 1;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 149;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 0;
  attribute C_S_PIPELINES : string;
  attribute C_S_PIPELINES of inst : label is "32'b00000000000000000000000000000000";
  attribute C_TESTING_MODE : integer;
  attribute C_TESTING_MODE of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute K_MAX_INFO_WIDTH : integer;
  attribute K_MAX_INFO_WIDTH of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_MUX_IMPL : string;
  attribute LP_MUX_IMPL of inst : label is "32'b00000000000000000000000000000000";
  attribute LP_M_SC_SEL_MI_PIPELINE_DEPTH : string;
  attribute LP_M_SC_SEL_MI_PIPELINE_DEPTH of inst : label is "32'b00000000000000000000000000000000";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_switchboard_v1_0_8_top__parameterized1\
     port map (
      aclk => aclk,
      aclken => '1',
      connectivity(1 downto 0) => B"11",
      m_sc_info(1 downto 0) => NLW_inst_m_sc_info_UNCONNECTED(1 downto 0),
      m_sc_payld(297 downto 163) => m_sc_payld(277 downto 143),
      m_sc_payld(162) => NLW_inst_m_sc_payld_UNCONNECTED(162),
      m_sc_payld(161 downto 160) => m_sc_payld(142 downto 141),
      m_sc_payld(159 downto 155) => NLW_inst_m_sc_payld_UNCONNECTED(159 downto 155),
      m_sc_payld(154 downto 153) => m_sc_payld(140 downto 139),
      m_sc_payld(152 downto 149) => NLW_inst_m_sc_payld_UNCONNECTED(152 downto 149),
      m_sc_payld(148 downto 14) => m_sc_payld(138 downto 4),
      m_sc_payld(13) => NLW_inst_m_sc_payld_UNCONNECTED(13),
      m_sc_payld(12 downto 11) => m_sc_payld(3 downto 2),
      m_sc_payld(10 downto 6) => NLW_inst_m_sc_payld_UNCONNECTED(10 downto 6),
      m_sc_payld(5 downto 4) => m_sc_payld(1 downto 0),
      m_sc_payld(3 downto 0) => NLW_inst_m_sc_payld_UNCONNECTED(3 downto 0),
      m_sc_recv(1 downto 0) => m_sc_recv(1 downto 0),
      m_sc_req(1 downto 0) => NLW_inst_m_sc_req_UNCONNECTED(1 downto 0),
      m_sc_send(1 downto 0) => m_sc_send(1 downto 0),
      s_sc_info(1 downto 0) => B"00",
      s_sc_payld(148 downto 14) => S00_SC_R_payld(138 downto 4),
      s_sc_payld(13) => '0',
      s_sc_payld(12 downto 11) => S00_SC_R_payld(3 downto 2),
      s_sc_payld(10 downto 6) => B"00000",
      s_sc_payld(5 downto 4) => S00_SC_R_payld(1 downto 0),
      s_sc_payld(3 downto 0) => B"0000",
      s_sc_recv(1 downto 0) => S00_SC_R_recv(1 downto 0),
      s_sc_req(1 downto 0) => B"00",
      s_sc_send(1 downto 0) => S00_SC_R_send(1 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_s00mmu_0 is
  port (
    S00_AXI_arready : out STD_LOGIC;
    S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_rlast : out STD_LOGIC;
    S00_AXI_rvalid : out STD_LOGIC;
    m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arsize : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : out STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_rready : out STD_LOGIC;
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arvalid : in STD_LOGIC;
    S00_AXI_rready : in STD_LOGIC;
    s_axi_arready : in STD_LOGIC;
    s_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : in STD_LOGIC;
    s_axi_rvalid : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_s00mmu_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_s00mmu_0 is
  signal NLW_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "1'b1";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 0;
  attribute C_IS_CASCADED : integer;
  attribute C_IS_CASCADED of inst : label is 0;
  attribute C_MSC_ROUTE_ARRAY : string;
  attribute C_MSC_ROUTE_ARRAY of inst : label is "1'b1";
  attribute C_MSC_ROUTE_WIDTH : integer;
  attribute C_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute C_NUM_MSC : integer;
  attribute C_NUM_MSC of inst : label is 1;
  attribute C_NUM_READ_OUTSTANDING : integer;
  attribute C_NUM_READ_OUTSTANDING of inst : label is 16;
  attribute C_NUM_SEG : integer;
  attribute C_NUM_SEG of inst : label is 1;
  attribute C_NUM_WRITE_OUTSTANDING : integer;
  attribute C_NUM_WRITE_OUTSTANDING of inst : label is 2;
  attribute C_RDATA_WIDTH : integer;
  attribute C_RDATA_WIDTH of inst : label is 32;
  attribute C_READ_ACCEPTANCE : integer;
  attribute C_READ_ACCEPTANCE of inst : label is 32;
  attribute C_SEG_BASE_ADDR_ARRAY : string;
  attribute C_SEG_BASE_ADDR_ARRAY of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_SEG_SECURE_READ_ARRAY : string;
  attribute C_SEG_SECURE_READ_ARRAY of inst : label is "1'b0";
  attribute C_SEG_SECURE_WRITE_ARRAY : string;
  attribute C_SEG_SECURE_WRITE_ARRAY of inst : label is "1'b0";
  attribute C_SEG_SEP_ROUTE_ARRAY : string;
  attribute C_SEG_SEP_ROUTE_ARRAY of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_SEG_SIZE_ARRAY : integer;
  attribute C_SEG_SIZE_ARRAY of inst : label is 31;
  attribute C_SEG_SUPPORTS_READ_ARRAY : string;
  attribute C_SEG_SUPPORTS_READ_ARRAY of inst : label is "1'b1";
  attribute C_SEG_SUPPORTS_WRITE_ARRAY : string;
  attribute C_SEG_SUPPORTS_WRITE_ARRAY of inst : label is "1'b1";
  attribute C_SINGLE_ISSUING : integer;
  attribute C_SINGLE_ISSUING of inst : label is 0;
  attribute C_SUPPORTS_NARROW : integer;
  attribute C_SUPPORTS_NARROW of inst : label is 0;
  attribute C_SUPPORTS_READ_DECERR : integer;
  attribute C_SUPPORTS_READ_DECERR of inst : label is 1;
  attribute C_SUPPORTS_WRAP : integer;
  attribute C_SUPPORTS_WRAP of inst : label is 1;
  attribute C_SUPPORTS_WRITE_DECERR : integer;
  attribute C_SUPPORTS_WRITE_DECERR of inst : label is 1;
  attribute C_S_ARUSER_WIDTH : integer;
  attribute C_S_ARUSER_WIDTH of inst : label is 0;
  attribute C_S_AWUSER_WIDTH : integer;
  attribute C_S_AWUSER_WIDTH of inst : label is 0;
  attribute C_S_BUSER_WIDTH : integer;
  attribute C_S_BUSER_WIDTH of inst : label is 0;
  attribute C_S_PROTOCOL : integer;
  attribute C_S_PROTOCOL of inst : label is 0;
  attribute C_S_RUSER_WIDTH : integer;
  attribute C_S_RUSER_WIDTH of inst : label is 0;
  attribute C_S_WUSER_WIDTH : integer;
  attribute C_S_WUSER_WIDTH of inst : label is 0;
  attribute C_WDATA_WIDTH : integer;
  attribute C_WDATA_WIDTH of inst : label is 32;
  attribute C_WRITE_ACCEPTANCE : integer;
  attribute C_WRITE_ACCEPTANCE of inst : label is 32;
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute P_AXI3 : integer;
  attribute P_AXI3 of inst : label is 1;
  attribute P_AXI4 : integer;
  attribute P_AXI4 of inst : label is 0;
  attribute P_AXILITE : integer;
  attribute P_AXILITE of inst : label is 2;
  attribute P_BYPASS : integer;
  attribute P_BYPASS of inst : label is 0;
  attribute P_DECERR : string;
  attribute P_DECERR of inst : label is "2'b11";
  attribute P_FIXED : string;
  attribute P_FIXED of inst : label is "2'b00";
  attribute P_FULLY_PIPELINED : integer;
  attribute P_FULLY_PIPELINED of inst : label is 2;
  attribute P_INCR : string;
  attribute P_INCR of inst : label is "2'b01";
  attribute P_NUM_MSC_LOG : integer;
  attribute P_NUM_MSC_LOG of inst : label is 1;
  attribute P_NUM_SEG_LOG : integer;
  attribute P_NUM_SEG_LOG of inst : label is 1;
  attribute P_R_DWBYTES : integer;
  attribute P_R_DWBYTES of inst : label is 4;
  attribute P_R_DWSIZE : integer;
  attribute P_R_DWSIZE of inst : label is 2;
  attribute P_R_QUEUE_SIZE : integer;
  attribute P_R_QUEUE_SIZE of inst : label is 4;
  attribute P_WRAP : string;
  attribute P_WRAP of inst : label is "2'b10";
  attribute P_W_DWBYTES : integer;
  attribute P_W_DWBYTES of inst : label is 4;
  attribute P_W_DWSIZE : integer;
  attribute P_W_DWSIZE of inst : label is 2;
  attribute P_W_QUEUE_SIZE : integer;
  attribute P_W_QUEUE_SIZE of inst : label is 4;
  attribute P_ZERO_LATENCY : integer;
  attribute P_ZERO_LATENCY of inst : label is 1;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.Loopback_smartconnect_0_0_sc_mmu_v1_0_14_top
     port map (
      aclk => aclk,
      aclken => '1',
      aresetn => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
      m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      m_axi_arid(0) => NLW_inst_m_axi_arid_UNCONNECTED(0),
      m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
      m_axi_arlock(0) => m_axi_arlock(0),
      m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      m_axi_arready => s_axi_arready,
      m_axi_arsize(2) => NLW_inst_m_axi_arsize_UNCONNECTED(2),
      m_axi_arsize(1 downto 0) => m_axi_arsize(1 downto 0),
      m_axi_aruser(1023 downto 147) => NLW_inst_m_axi_aruser_UNCONNECTED(1023 downto 147),
      m_axi_aruser(146 downto 136) => m_axi_aruser(10 downto 0),
      m_axi_aruser(135 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(135 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_awaddr(31 downto 0) => NLW_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
      m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
      m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
      m_axi_awid(0) => NLW_inst_m_axi_awid_UNCONNECTED(0),
      m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
      m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
      m_axi_awprot(2 downto 0) => NLW_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
      m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
      m_axi_awready => '0',
      m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
      m_axi_awuser(1023 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(1023 downto 0),
      m_axi_awvalid => NLW_inst_m_axi_awvalid_UNCONNECTED,
      m_axi_bid(0) => '0',
      m_axi_bready => NLW_inst_m_axi_bready_UNCONNECTED,
      m_axi_bresp(1 downto 0) => B"00",
      m_axi_buser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_bvalid => '0',
      m_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      m_axi_rid(0) => '0',
      m_axi_rlast => s_axi_rlast,
      m_axi_rready => m_axi_rready,
      m_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      m_axi_ruser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_rvalid => s_axi_rvalid,
      m_axi_wdata(31 downto 0) => NLW_inst_m_axi_wdata_UNCONNECTED(31 downto 0),
      m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
      m_axi_wready => '0',
      m_axi_wstrb(3 downto 0) => NLW_inst_m_axi_wstrb_UNCONNECTED(3 downto 0),
      m_axi_wuser(1023 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(1023 downto 0),
      m_axi_wvalid => NLW_inst_m_axi_wvalid_UNCONNECTED,
      s_axi_araddr(31 downto 0) => S00_AXI_araddr(31 downto 0),
      s_axi_arburst(1 downto 0) => S00_AXI_arburst(1 downto 0),
      s_axi_arcache(3 downto 0) => S00_AXI_arcache(3 downto 0),
      s_axi_arid(0) => '0',
      s_axi_arlen(7 downto 0) => S00_AXI_arlen(7 downto 0),
      s_axi_arlock(0) => S00_AXI_arlock(0),
      s_axi_arprot(2 downto 0) => S00_AXI_arprot(2 downto 0),
      s_axi_arqos(3 downto 0) => S00_AXI_arqos(3 downto 0),
      s_axi_arready => S00_AXI_arready,
      s_axi_arsize(2 downto 0) => S00_AXI_arsize(2 downto 0),
      s_axi_aruser(0) => '0',
      s_axi_arvalid => S00_AXI_arvalid,
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"01",
      s_axi_awcache(3 downto 0) => B"0000",
      s_axi_awid(0) => '0',
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awlock(0) => '0',
      s_axi_awprot(2 downto 0) => B"000",
      s_axi_awqos(3 downto 0) => B"0000",
      s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awuser(0) => '0',
      s_axi_awvalid => '0',
      s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
      s_axi_bvalid => NLW_inst_s_axi_bvalid_UNCONNECTED,
      s_axi_rdata(31 downto 0) => S00_AXI_rdata(31 downto 0),
      s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
      s_axi_rlast => S00_AXI_rlast,
      s_axi_rready => S00_AXI_rready,
      s_axi_rresp(1 downto 0) => S00_AXI_rresp(1 downto 0),
      s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
      s_axi_rvalid => S00_AXI_rvalid,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wid(0) => '0',
      s_axi_wlast => '1',
      s_axi_wready => NLW_inst_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(3 downto 0) => B"1111",
      s_axi_wuser(0) => '0',
      s_axi_wvalid => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_s00sic_0 is
  port (
    s_axi_arready : out STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : out STD_LOGIC;
    s_axi_rvalid : out STD_LOGIC;
    m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : out STD_LOGIC_VECTOR ( 24 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_rready : out STD_LOGIC;
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \count_r_reg[5]\ : in STD_LOGIC;
    \count_r_reg[5]_0\ : in STD_LOGIC;
    \m_vector_i[1092]_i_3\ : in STD_LOGIC;
    \skid_buffer_reg[1090]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \skid_buffer_reg[1057]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \skid_buffer_reg[1058]\ : in STD_LOGIC;
    \gen_endpoint.r_cnt_reg[0]\ : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_s00sic_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_s00sic_0 is
  signal NLW_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_AXILITE_CONV : integer;
  attribute C_AXILITE_CONV of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "1'b1";
  attribute C_HAS_BURST : integer;
  attribute C_HAS_BURST of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_IS_CASCADED : integer;
  attribute C_IS_CASCADED of inst : label is 0;
  attribute C_LIMIT_READ_LENGTH : integer;
  attribute C_LIMIT_READ_LENGTH of inst : label is 0;
  attribute C_LIMIT_WRITE_LENGTH : integer;
  attribute C_LIMIT_WRITE_LENGTH of inst : label is 0;
  attribute C_MAX_RUSER_BITS_PER_BYTE : integer;
  attribute C_MAX_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_MAX_WUSER_BITS_PER_BYTE : integer;
  attribute C_MAX_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_MEP_IDENTIFIER_WIDTH : integer;
  attribute C_MEP_IDENTIFIER_WIDTH of inst : label is 2;
  attribute C_MSC_RDATA_WIDTH_ARRAY : integer;
  attribute C_MSC_RDATA_WIDTH_ARRAY of inst : label is 128;
  attribute C_MSC_WDATA_WIDTH_ARRAY : integer;
  attribute C_MSC_WDATA_WIDTH_ARRAY of inst : label is 128;
  attribute C_NUM_MSC : integer;
  attribute C_NUM_MSC of inst : label is 1;
  attribute C_NUM_READ_OUTSTANDING : integer;
  attribute C_NUM_READ_OUTSTANDING of inst : label is 16;
  attribute C_NUM_READ_THREADS : integer;
  attribute C_NUM_READ_THREADS of inst : label is 1;
  attribute C_NUM_SEG : integer;
  attribute C_NUM_SEG of inst : label is 1;
  attribute C_NUM_WRITE_OUTSTANDING : integer;
  attribute C_NUM_WRITE_OUTSTANDING of inst : label is 2;
  attribute C_NUM_WRITE_THREADS : integer;
  attribute C_NUM_WRITE_THREADS of inst : label is 1;
  attribute C_RDATA_WIDTH : integer;
  attribute C_RDATA_WIDTH of inst : label is 32;
  attribute C_READ_ACCEPTANCE : integer;
  attribute C_READ_ACCEPTANCE of inst : label is 32;
  attribute C_READ_WATERMARK : integer;
  attribute C_READ_WATERMARK of inst : label is 0;
  attribute C_SEP_PROTOCOL_ARRAY : integer;
  attribute C_SEP_PROTOCOL_ARRAY of inst : label is 0;
  attribute C_SEP_RDATA_WIDTH_ARRAY : integer;
  attribute C_SEP_RDATA_WIDTH_ARRAY of inst : label is 128;
  attribute C_SEP_WDATA_WIDTH_ARRAY : integer;
  attribute C_SEP_WDATA_WIDTH_ARRAY of inst : label is 128;
  attribute C_SINGLE_ISSUING : integer;
  attribute C_SINGLE_ISSUING of inst : label is 0;
  attribute C_SUPPORTS_NARROW : integer;
  attribute C_SUPPORTS_NARROW of inst : label is 0;
  attribute C_S_RUSER_BITS_PER_BYTE : integer;
  attribute C_S_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_S_WUSER_BITS_PER_BYTE : integer;
  attribute C_S_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_WDATA_WIDTH : integer;
  attribute C_WDATA_WIDTH of inst : label is 32;
  attribute C_WRITE_ACCEPTANCE : integer;
  attribute C_WRITE_ACCEPTANCE of inst : label is 32;
  attribute C_WRITE_WATERMARK : integer;
  attribute C_WRITE_WATERMARK of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute P_EXOK : string;
  attribute P_EXOK of inst : label is "2'b01";
  attribute P_FULLY_PIPELINED : integer;
  attribute P_FULLY_PIPELINED of inst : label is 2;
  attribute P_ID_WIDTH : integer;
  attribute P_ID_WIDTH of inst : label is 2;
  attribute P_MAX_RUSER_BITS_PER_BYTE : integer;
  attribute P_MAX_RUSER_BITS_PER_BYTE of inst : label is 1;
  attribute P_MAX_WUSER_BITS_PER_BYTE : integer;
  attribute P_MAX_WUSER_BITS_PER_BYTE of inst : label is 1;
  attribute P_NUM_READ_OUTSTANDING : integer;
  attribute P_NUM_READ_OUTSTANDING of inst : label is 16;
  attribute P_NUM_WRITE_OUTSTANDING : integer;
  attribute P_NUM_WRITE_OUTSTANDING of inst : label is 16;
  attribute P_R_DWBYTES : integer;
  attribute P_R_DWBYTES of inst : label is 4;
  attribute P_R_DWSIZE : integer;
  attribute P_R_DWSIZE of inst : label is 2;
  attribute P_S_RUSER_BITS_PER_BYTE : integer;
  attribute P_S_RUSER_BITS_PER_BYTE of inst : label is 1;
  attribute P_S_WUSER_BITS_PER_BYTE : integer;
  attribute P_S_WUSER_BITS_PER_BYTE of inst : label is 1;
  attribute P_W_DWBYTES : integer;
  attribute P_W_DWBYTES of inst : label is 4;
  attribute P_W_DWSIZE : integer;
  attribute P_W_DWSIZE of inst : label is 2;
  attribute P_ZERO_LATENCY : integer;
  attribute P_ZERO_LATENCY of inst : label is 1;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.Loopback_smartconnect_0_0_sc_si_converter_v1_0_14_top
     port map (
      aclk => aclk,
      aclken => '1',
      aresetn => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      m_axi_arid(1 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(1 downto 0),
      m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
      m_axi_arlock(0) => m_axi_arlock(0),
      m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      m_axi_arready => \m_vector_i[1092]_i_3\,
      m_axi_aruser(1023 downto 186) => NLW_inst_m_axi_aruser_UNCONNECTED(1023 downto 186),
      m_axi_aruser(185 downto 179) => m_axi_aruser(24 downto 18),
      m_axi_aruser(178 downto 147) => NLW_inst_m_axi_aruser_UNCONNECTED(178 downto 147),
      m_axi_aruser(146 downto 136) => m_axi_aruser(17 downto 7),
      m_axi_aruser(135 downto 71) => NLW_inst_m_axi_aruser_UNCONNECTED(135 downto 71),
      m_axi_aruser(70 downto 64) => m_axi_aruser(6 downto 0),
      m_axi_aruser(63 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(63 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_awaddr(31 downto 0) => NLW_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
      m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
      m_axi_awid(1 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(1 downto 0),
      m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
      m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
      m_axi_awprot(2 downto 0) => NLW_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
      m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
      m_axi_awready => '0',
      m_axi_awuser(1023 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(1023 downto 0),
      m_axi_awvalid => NLW_inst_m_axi_awvalid_UNCONNECTED,
      m_axi_bid(1 downto 0) => B"00",
      m_axi_bready => NLW_inst_m_axi_bready_UNCONNECTED,
      m_axi_bresp(1 downto 0) => B"00",
      m_axi_buser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_bvalid => '0',
      m_axi_rdata(31 downto 0) => \skid_buffer_reg[1090]\(31 downto 0),
      m_axi_rid(1 downto 0) => B"00",
      m_axi_rlast => \skid_buffer_reg[1058]\,
      m_axi_rready => m_axi_rready,
      m_axi_rresp(1 downto 0) => \skid_buffer_reg[1057]\(1 downto 0),
      m_axi_ruser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_rvalid => \gen_endpoint.r_cnt_reg[0]\,
      m_axi_wdata(31 downto 0) => NLW_inst_m_axi_wdata_UNCONNECTED(31 downto 0),
      m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
      m_axi_wready => '0',
      m_axi_wstrb(3 downto 0) => NLW_inst_m_axi_wstrb_UNCONNECTED(3 downto 0),
      m_axi_wuser(1023 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(1023 downto 0),
      m_axi_wvalid => NLW_inst_m_axi_wvalid_UNCONNECTED,
      s_axi_araddr(31 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\(31 downto 0),
      s_axi_arburst(1 downto 0) => B"01",
      s_axi_arcache(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\(3 downto 0),
      s_axi_arid(1 downto 0) => B"01",
      s_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
      s_axi_arlock(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\(0),
      s_axi_arprot(2 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\(2 downto 0),
      s_axi_arqos(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\(3 downto 0),
      s_axi_arready => s_axi_arready,
      s_axi_arsize(2) => '0',
      s_axi_arsize(1 downto 0) => m_axi_arsize(1 downto 0),
      s_axi_aruser(1023 downto 147) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_aruser(146 downto 136) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\(10 downto 0),
      s_axi_aruser(135 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_arvalid => \count_r_reg[5]\,
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"01",
      s_axi_awcache(3 downto 0) => B"0000",
      s_axi_awid(1 downto 0) => B"00",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awlock(0) => '0',
      s_axi_awprot(2 downto 0) => B"000",
      s_axi_awqos(3 downto 0) => B"0000",
      s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awuser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awvalid => '0',
      s_axi_bid(1 downto 0) => NLW_inst_s_axi_bid_UNCONNECTED(1 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_buser(1023 downto 0) => NLW_inst_s_axi_buser_UNCONNECTED(1023 downto 0),
      s_axi_bvalid => NLW_inst_s_axi_bvalid_UNCONNECTED,
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rid(1 downto 0) => NLW_inst_s_axi_rid_UNCONNECTED(1 downto 0),
      s_axi_rlast => s_axi_rlast,
      s_axi_rready => \count_r_reg[5]_0\,
      s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      s_axi_ruser(1023 downto 0) => NLW_inst_s_axi_ruser_UNCONNECTED(1023 downto 0),
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wlast => '1',
      s_axi_wready => NLW_inst_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(3 downto 0) => B"1111",
      s_axi_wuser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wvalid => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_s00tr_0 is
  port (
    s_axi_arready : out STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : out STD_LOGIC;
    s_axi_rvalid : out STD_LOGIC;
    m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arsize : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : out STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_rready : out STD_LOGIC;
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \count_r_reg[5]\ : in STD_LOGIC;
    \count_r_reg[5]_0\ : in STD_LOGIC;
    \state_reg[s_ready_i]\ : in STD_LOGIC;
    \skid_buffer_reg[1090]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \skid_buffer_reg[1057]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \skid_buffer_reg[1058]\ : in STD_LOGIC;
    \gen_endpoint.r_cnt_reg[0]\ : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_s00tr_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_s00tr_0 is
  signal NLW_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "1'b1";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_IS_CASCADED : integer;
  attribute C_IS_CASCADED of inst : label is 0;
  attribute C_MEP_IDENTIFIER : string;
  attribute C_MEP_IDENTIFIER of inst : label is "2'b01";
  attribute C_MEP_IDENTIFIER_WIDTH : integer;
  attribute C_MEP_IDENTIFIER_WIDTH of inst : label is 2;
  attribute C_M_ID_WIDTH : integer;
  attribute C_M_ID_WIDTH of inst : label is 2;
  attribute C_NUM_READ_OUTSTANDING : integer;
  attribute C_NUM_READ_OUTSTANDING of inst : label is 16;
  attribute C_NUM_READ_THREADS : integer;
  attribute C_NUM_READ_THREADS of inst : label is 1;
  attribute C_NUM_WRITE_OUTSTANDING : integer;
  attribute C_NUM_WRITE_OUTSTANDING of inst : label is 2;
  attribute C_NUM_WRITE_THREADS : integer;
  attribute C_NUM_WRITE_THREADS of inst : label is 1;
  attribute C_RDATA_WIDTH : integer;
  attribute C_RDATA_WIDTH of inst : label is 32;
  attribute C_READ_ACCEPTANCE : integer;
  attribute C_READ_ACCEPTANCE of inst : label is 32;
  attribute C_SEP_ROUTE_WIDTH : integer;
  attribute C_SEP_ROUTE_WIDTH of inst : label is 1;
  attribute C_SINGLE_ISSUING : integer;
  attribute C_SINGLE_ISSUING of inst : label is 0;
  attribute C_SUPPORTS_READ_DEADLOCK : integer;
  attribute C_SUPPORTS_READ_DEADLOCK of inst : label is 0;
  attribute C_SUPPORTS_WRITE_DEADLOCK : integer;
  attribute C_SUPPORTS_WRITE_DEADLOCK of inst : label is 0;
  attribute C_S_ID_WIDTH : integer;
  attribute C_S_ID_WIDTH of inst : label is 0;
  attribute C_WDATA_WIDTH : integer;
  attribute C_WDATA_WIDTH of inst : label is 32;
  attribute C_WRITE_ACCEPTANCE : integer;
  attribute C_WRITE_ACCEPTANCE of inst : label is 32;
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute P_FULLY_PIPELINED : integer;
  attribute P_FULLY_PIPELINED of inst : label is 2;
  attribute P_ID_BUFFER_WIDTH : integer;
  attribute P_ID_BUFFER_WIDTH of inst : label is 1;
  attribute P_M_THREAD_ID_WIDTH : integer;
  attribute P_M_THREAD_ID_WIDTH of inst : label is 1;
  attribute P_NUM_READ_OUTSTANDING : integer;
  attribute P_NUM_READ_OUTSTANDING of inst : label is 16;
  attribute P_NUM_WRITE_OUTSTANDING : integer;
  attribute P_NUM_WRITE_OUTSTANDING of inst : label is 16;
  attribute P_R_QUEUE_SIZE : integer;
  attribute P_R_QUEUE_SIZE of inst : label is 4;
  attribute P_S_ID_WIDTH : integer;
  attribute P_S_ID_WIDTH of inst : label is 1;
  attribute P_W_QUEUE_SIZE : integer;
  attribute P_W_QUEUE_SIZE of inst : label is 4;
  attribute P_ZERO_LATENCY : integer;
  attribute P_ZERO_LATENCY of inst : label is 1;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.Loopback_smartconnect_0_0_sc_transaction_regulator_v1_0_11_top
     port map (
      aclk => aclk,
      aclken => '1',
      aresetn => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
      m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      m_axi_arid(1 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(1 downto 0),
      m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
      m_axi_arlock(0) => m_axi_arlock(0),
      m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      m_axi_arready => \state_reg[s_ready_i]\,
      m_axi_arsize(2) => NLW_inst_m_axi_arsize_UNCONNECTED(2),
      m_axi_arsize(1 downto 0) => m_axi_arsize(1 downto 0),
      m_axi_aruser(1023 downto 147) => NLW_inst_m_axi_aruser_UNCONNECTED(1023 downto 147),
      m_axi_aruser(146 downto 136) => m_axi_aruser(10 downto 0),
      m_axi_aruser(135 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(135 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_awaddr(31 downto 0) => NLW_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
      m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
      m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
      m_axi_awid(1 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(1 downto 0),
      m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
      m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
      m_axi_awprot(2 downto 0) => NLW_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
      m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
      m_axi_awready => '0',
      m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
      m_axi_awuser(1023 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(1023 downto 0),
      m_axi_awvalid => NLW_inst_m_axi_awvalid_UNCONNECTED,
      m_axi_bid(1 downto 0) => B"00",
      m_axi_bready => NLW_inst_m_axi_bready_UNCONNECTED,
      m_axi_bresp(1 downto 0) => B"00",
      m_axi_buser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_bvalid => '0',
      m_axi_rdata(31 downto 0) => \skid_buffer_reg[1090]\(31 downto 0),
      m_axi_rid(1 downto 0) => B"00",
      m_axi_rlast => \skid_buffer_reg[1058]\,
      m_axi_rready => m_axi_rready,
      m_axi_rresp(1 downto 0) => \skid_buffer_reg[1057]\(1 downto 0),
      m_axi_ruser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_rvalid => \gen_endpoint.r_cnt_reg[0]\,
      m_axi_wdata(31 downto 0) => NLW_inst_m_axi_wdata_UNCONNECTED(31 downto 0),
      m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
      m_axi_wready => '0',
      m_axi_wstrb(3 downto 0) => NLW_inst_m_axi_wstrb_UNCONNECTED(3 downto 0),
      m_axi_wuser(1023 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(1023 downto 0),
      m_axi_wvalid => NLW_inst_m_axi_wvalid_UNCONNECTED,
      mep_identifier(1 downto 0) => B"01",
      s_axi_araddr(31 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\(31 downto 0),
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arcache(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\(3 downto 0),
      s_axi_arid(0) => '0',
      s_axi_arlen(7 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\(7 downto 0),
      s_axi_arlock(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\(0),
      s_axi_arprot(2 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\(2 downto 0),
      s_axi_arqos(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\(3 downto 0),
      s_axi_arready => s_axi_arready,
      s_axi_arsize(2) => '0',
      s_axi_arsize(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\(1 downto 0),
      s_axi_aruser(1023 downto 147) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_aruser(146 downto 136) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\(10 downto 0),
      s_axi_aruser(135 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_arvalid => \count_r_reg[5]\,
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"01",
      s_axi_awcache(3 downto 0) => B"0000",
      s_axi_awid(0) => '0',
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awlock(0) => '0',
      s_axi_awprot(2 downto 0) => B"000",
      s_axi_awqos(3 downto 0) => B"0000",
      s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awuser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awvalid => '0',
      s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_buser(1023 downto 0) => NLW_inst_s_axi_buser_UNCONNECTED(1023 downto 0),
      s_axi_bvalid => NLW_inst_s_axi_bvalid_UNCONNECTED,
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
      s_axi_rlast => s_axi_rlast,
      s_axi_rready => \count_r_reg[5]_0\,
      s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      s_axi_ruser(1023 downto 0) => NLW_inst_s_axi_ruser_UNCONNECTED(1023 downto 0),
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wlast => '1',
      s_axi_wready => NLW_inst_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(3 downto 0) => B"1111",
      s_axi_wuser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wvalid => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_s01mmu_0 is
  port (
    S01_AXI_awready : out STD_LOGIC;
    S01_AXI_wready : out STD_LOGIC;
    S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_bvalid : out STD_LOGIC;
    S01_AXI_arready : out STD_LOGIC;
    S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_rlast : out STD_LOGIC;
    S01_AXI_rvalid : out STD_LOGIC;
    m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_awsize : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awuser : out STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axi_awvalid : out STD_LOGIC;
    m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_wlast : out STD_LOGIC;
    m_axi_wvalid : out STD_LOGIC;
    m_axi_bready : out STD_LOGIC;
    m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arsize : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : out STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_rready : out STD_LOGIC;
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awvalid : in STD_LOGIC;
    S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_wlast : in STD_LOGIC;
    S01_AXI_wvalid : in STD_LOGIC;
    S01_AXI_bready : in STD_LOGIC;
    S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arvalid : in STD_LOGIC;
    S01_AXI_rready : in STD_LOGIC;
    s_axi_awready : in STD_LOGIC;
    s_axi_wready : in STD_LOGIC;
    s_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : in STD_LOGIC;
    s_axi_arready : in STD_LOGIC;
    s_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : in STD_LOGIC;
    s_axi_rvalid : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_s01mmu_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_s01mmu_0 is
  signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "1'b1";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 0;
  attribute C_IS_CASCADED : integer;
  attribute C_IS_CASCADED of inst : label is 0;
  attribute C_MSC_ROUTE_ARRAY : string;
  attribute C_MSC_ROUTE_ARRAY of inst : label is "1'b1";
  attribute C_MSC_ROUTE_WIDTH : integer;
  attribute C_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute C_NUM_MSC : integer;
  attribute C_NUM_MSC of inst : label is 1;
  attribute C_NUM_READ_OUTSTANDING : integer;
  attribute C_NUM_READ_OUTSTANDING of inst : label is 2;
  attribute C_NUM_SEG : integer;
  attribute C_NUM_SEG of inst : label is 1;
  attribute C_NUM_WRITE_OUTSTANDING : integer;
  attribute C_NUM_WRITE_OUTSTANDING of inst : label is 2;
  attribute C_RDATA_WIDTH : integer;
  attribute C_RDATA_WIDTH of inst : label is 32;
  attribute C_READ_ACCEPTANCE : integer;
  attribute C_READ_ACCEPTANCE of inst : label is 32;
  attribute C_SEG_BASE_ADDR_ARRAY : string;
  attribute C_SEG_BASE_ADDR_ARRAY of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_SEG_SECURE_READ_ARRAY : string;
  attribute C_SEG_SECURE_READ_ARRAY of inst : label is "1'b0";
  attribute C_SEG_SECURE_WRITE_ARRAY : string;
  attribute C_SEG_SECURE_WRITE_ARRAY of inst : label is "1'b0";
  attribute C_SEG_SEP_ROUTE_ARRAY : string;
  attribute C_SEG_SEP_ROUTE_ARRAY of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_SEG_SIZE_ARRAY : integer;
  attribute C_SEG_SIZE_ARRAY of inst : label is 31;
  attribute C_SEG_SUPPORTS_READ_ARRAY : string;
  attribute C_SEG_SUPPORTS_READ_ARRAY of inst : label is "1'b1";
  attribute C_SEG_SUPPORTS_WRITE_ARRAY : string;
  attribute C_SEG_SUPPORTS_WRITE_ARRAY of inst : label is "1'b1";
  attribute C_SINGLE_ISSUING : integer;
  attribute C_SINGLE_ISSUING of inst : label is 0;
  attribute C_SUPPORTS_NARROW : integer;
  attribute C_SUPPORTS_NARROW of inst : label is 0;
  attribute C_SUPPORTS_READ_DECERR : integer;
  attribute C_SUPPORTS_READ_DECERR of inst : label is 1;
  attribute C_SUPPORTS_WRAP : integer;
  attribute C_SUPPORTS_WRAP of inst : label is 1;
  attribute C_SUPPORTS_WRITE_DECERR : integer;
  attribute C_SUPPORTS_WRITE_DECERR of inst : label is 1;
  attribute C_S_ARUSER_WIDTH : integer;
  attribute C_S_ARUSER_WIDTH of inst : label is 0;
  attribute C_S_AWUSER_WIDTH : integer;
  attribute C_S_AWUSER_WIDTH of inst : label is 0;
  attribute C_S_BUSER_WIDTH : integer;
  attribute C_S_BUSER_WIDTH of inst : label is 0;
  attribute C_S_PROTOCOL : integer;
  attribute C_S_PROTOCOL of inst : label is 0;
  attribute C_S_RUSER_WIDTH : integer;
  attribute C_S_RUSER_WIDTH of inst : label is 0;
  attribute C_S_WUSER_WIDTH : integer;
  attribute C_S_WUSER_WIDTH of inst : label is 0;
  attribute C_WDATA_WIDTH : integer;
  attribute C_WDATA_WIDTH of inst : label is 32;
  attribute C_WRITE_ACCEPTANCE : integer;
  attribute C_WRITE_ACCEPTANCE of inst : label is 32;
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute P_AXI3 : integer;
  attribute P_AXI3 of inst : label is 1;
  attribute P_AXI4 : integer;
  attribute P_AXI4 of inst : label is 0;
  attribute P_AXILITE : integer;
  attribute P_AXILITE of inst : label is 2;
  attribute P_BYPASS : integer;
  attribute P_BYPASS of inst : label is 0;
  attribute P_DECERR : string;
  attribute P_DECERR of inst : label is "2'b11";
  attribute P_FIXED : string;
  attribute P_FIXED of inst : label is "2'b00";
  attribute P_FULLY_PIPELINED : integer;
  attribute P_FULLY_PIPELINED of inst : label is 2;
  attribute P_INCR : string;
  attribute P_INCR of inst : label is "2'b01";
  attribute P_NUM_MSC_LOG : integer;
  attribute P_NUM_MSC_LOG of inst : label is 1;
  attribute P_NUM_SEG_LOG : integer;
  attribute P_NUM_SEG_LOG of inst : label is 1;
  attribute P_R_DWBYTES : integer;
  attribute P_R_DWBYTES of inst : label is 4;
  attribute P_R_DWSIZE : integer;
  attribute P_R_DWSIZE of inst : label is 2;
  attribute P_R_QUEUE_SIZE : integer;
  attribute P_R_QUEUE_SIZE of inst : label is 4;
  attribute P_WRAP : string;
  attribute P_WRAP of inst : label is "2'b10";
  attribute P_W_DWBYTES : integer;
  attribute P_W_DWBYTES of inst : label is 4;
  attribute P_W_DWSIZE : integer;
  attribute P_W_DWSIZE of inst : label is 2;
  attribute P_W_QUEUE_SIZE : integer;
  attribute P_W_QUEUE_SIZE of inst : label is 4;
  attribute P_ZERO_LATENCY : integer;
  attribute P_ZERO_LATENCY of inst : label is 1;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_mmu_v1_0_14_top__parameterized0\
     port map (
      aclk => aclk,
      aclken => '1',
      aresetn => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
      m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      m_axi_arid(0) => NLW_inst_m_axi_arid_UNCONNECTED(0),
      m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
      m_axi_arlock(0) => m_axi_arlock(0),
      m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      m_axi_arready => s_axi_arready,
      m_axi_arsize(2) => NLW_inst_m_axi_arsize_UNCONNECTED(2),
      m_axi_arsize(1 downto 0) => m_axi_arsize(1 downto 0),
      m_axi_aruser(1023 downto 147) => NLW_inst_m_axi_aruser_UNCONNECTED(1023 downto 147),
      m_axi_aruser(146 downto 136) => m_axi_aruser(10 downto 0),
      m_axi_aruser(135 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(135 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
      m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
      m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
      m_axi_awid(0) => NLW_inst_m_axi_awid_UNCONNECTED(0),
      m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
      m_axi_awlock(0) => m_axi_awlock(0),
      m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
      m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
      m_axi_awready => s_axi_awready,
      m_axi_awsize(2) => NLW_inst_m_axi_awsize_UNCONNECTED(2),
      m_axi_awsize(1 downto 0) => m_axi_awsize(1 downto 0),
      m_axi_awuser(1023 downto 147) => NLW_inst_m_axi_awuser_UNCONNECTED(1023 downto 147),
      m_axi_awuser(146 downto 136) => m_axi_awuser(10 downto 0),
      m_axi_awuser(135 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(135 downto 0),
      m_axi_awvalid => m_axi_awvalid,
      m_axi_bid(0) => '0',
      m_axi_bready => m_axi_bready,
      m_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
      m_axi_buser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_bvalid => s_axi_bvalid,
      m_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      m_axi_rid(0) => '0',
      m_axi_rlast => s_axi_rlast,
      m_axi_rready => m_axi_rready,
      m_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      m_axi_ruser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_rvalid => s_axi_rvalid,
      m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
      m_axi_wlast => m_axi_wlast,
      m_axi_wready => s_axi_wready,
      m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
      m_axi_wuser(1023 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(1023 downto 0),
      m_axi_wvalid => m_axi_wvalid,
      s_axi_araddr(31 downto 0) => S01_AXI_araddr(31 downto 0),
      s_axi_arburst(1 downto 0) => S01_AXI_arburst(1 downto 0),
      s_axi_arcache(3 downto 0) => S01_AXI_arcache(3 downto 0),
      s_axi_arid(0) => '0',
      s_axi_arlen(7 downto 0) => S01_AXI_arlen(7 downto 0),
      s_axi_arlock(0) => S01_AXI_arlock(0),
      s_axi_arprot(2 downto 0) => S01_AXI_arprot(2 downto 0),
      s_axi_arqos(3 downto 0) => S01_AXI_arqos(3 downto 0),
      s_axi_arready => S01_AXI_arready,
      s_axi_arsize(2 downto 0) => S01_AXI_arsize(2 downto 0),
      s_axi_aruser(0) => '0',
      s_axi_arvalid => S01_AXI_arvalid,
      s_axi_awaddr(31 downto 0) => S01_AXI_awaddr(31 downto 0),
      s_axi_awburst(1 downto 0) => S01_AXI_awburst(1 downto 0),
      s_axi_awcache(3 downto 0) => S01_AXI_awcache(3 downto 0),
      s_axi_awid(0) => '0',
      s_axi_awlen(7 downto 0) => S01_AXI_awlen(7 downto 0),
      s_axi_awlock(0) => S01_AXI_awlock(0),
      s_axi_awprot(2 downto 0) => S01_AXI_awprot(2 downto 0),
      s_axi_awqos(3 downto 0) => S01_AXI_awqos(3 downto 0),
      s_axi_awready => S01_AXI_awready,
      s_axi_awsize(2 downto 0) => S01_AXI_awsize(2 downto 0),
      s_axi_awuser(0) => '0',
      s_axi_awvalid => S01_AXI_awvalid,
      s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
      s_axi_bready => S01_AXI_bready,
      s_axi_bresp(1 downto 0) => S01_AXI_bresp(1 downto 0),
      s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
      s_axi_bvalid => S01_AXI_bvalid,
      s_axi_rdata(31 downto 0) => S01_AXI_rdata(31 downto 0),
      s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
      s_axi_rlast => S01_AXI_rlast,
      s_axi_rready => S01_AXI_rready,
      s_axi_rresp(1 downto 0) => S01_AXI_rresp(1 downto 0),
      s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
      s_axi_rvalid => S01_AXI_rvalid,
      s_axi_wdata(31 downto 0) => S01_AXI_wdata(31 downto 0),
      s_axi_wid(0) => '0',
      s_axi_wlast => S01_AXI_wlast,
      s_axi_wready => S01_AXI_wready,
      s_axi_wstrb(3 downto 0) => S01_AXI_wstrb(3 downto 0),
      s_axi_wuser(0) => '0',
      s_axi_wvalid => S01_AXI_wvalid
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_s01tr_0 is
  port (
    s_axi_awready : out STD_LOGIC;
    s_axi_wready : out STD_LOGIC;
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC;
    s_axi_arready : out STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : out STD_LOGIC;
    s_axi_rvalid : out STD_LOGIC;
    m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_awsize : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awuser : out STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axi_awvalid : out STD_LOGIC;
    m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_wlast : out STD_LOGIC;
    m_axi_wvalid : out STD_LOGIC;
    m_axi_bready : out STD_LOGIC;
    m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arsize : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : out STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_rready : out STD_LOGIC;
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \gen_pipelined.mesg_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \gen_pipelined.state_reg[0]\ : in STD_LOGIC;
    \gen_w_ch.accum_reg[bytes][11][userdata][7]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \gen_w_ch.accum_reg[bytes][3][strb]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_pipe[1].pipe_reg[1][0]\ : in STD_LOGIC;
    \gen_pipelined.mesg_reg_reg[13]\ : in STD_LOGIC;
    \count_r_reg[1]\ : in STD_LOGIC;
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_4\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_7\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \count_r_reg[5]\ : in STD_LOGIC;
    \count_r_reg[5]_0\ : in STD_LOGIC;
    \m_vector_i_reg[138]\ : in STD_LOGIC;
    \gen_endpoint.w_enable_reg\ : in STD_LOGIC;
    \skid_buffer_reg[1057]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_endpoint.b_cnt_reg[0]\ : in STD_LOGIC;
    \state_reg[s_ready_i]\ : in STD_LOGIC;
    \skid_buffer_reg[1090]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \skid_buffer_reg[1057]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \skid_buffer_reg[1058]\ : in STD_LOGIC;
    \gen_endpoint.r_cnt_reg[0]\ : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_s01tr_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_s01tr_0 is
  signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "1'b1";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_IS_CASCADED : integer;
  attribute C_IS_CASCADED of inst : label is 0;
  attribute C_MEP_IDENTIFIER : string;
  attribute C_MEP_IDENTIFIER of inst : label is "2'b10";
  attribute C_MEP_IDENTIFIER_WIDTH : integer;
  attribute C_MEP_IDENTIFIER_WIDTH of inst : label is 2;
  attribute C_M_ID_WIDTH : integer;
  attribute C_M_ID_WIDTH of inst : label is 2;
  attribute C_NUM_READ_OUTSTANDING : integer;
  attribute C_NUM_READ_OUTSTANDING of inst : label is 2;
  attribute C_NUM_READ_THREADS : integer;
  attribute C_NUM_READ_THREADS of inst : label is 1;
  attribute C_NUM_WRITE_OUTSTANDING : integer;
  attribute C_NUM_WRITE_OUTSTANDING of inst : label is 2;
  attribute C_NUM_WRITE_THREADS : integer;
  attribute C_NUM_WRITE_THREADS of inst : label is 1;
  attribute C_RDATA_WIDTH : integer;
  attribute C_RDATA_WIDTH of inst : label is 32;
  attribute C_READ_ACCEPTANCE : integer;
  attribute C_READ_ACCEPTANCE of inst : label is 32;
  attribute C_SEP_ROUTE_WIDTH : integer;
  attribute C_SEP_ROUTE_WIDTH of inst : label is 1;
  attribute C_SINGLE_ISSUING : integer;
  attribute C_SINGLE_ISSUING of inst : label is 0;
  attribute C_SUPPORTS_READ_DEADLOCK : integer;
  attribute C_SUPPORTS_READ_DEADLOCK of inst : label is 0;
  attribute C_SUPPORTS_WRITE_DEADLOCK : integer;
  attribute C_SUPPORTS_WRITE_DEADLOCK of inst : label is 0;
  attribute C_S_ID_WIDTH : integer;
  attribute C_S_ID_WIDTH of inst : label is 0;
  attribute C_WDATA_WIDTH : integer;
  attribute C_WDATA_WIDTH of inst : label is 32;
  attribute C_WRITE_ACCEPTANCE : integer;
  attribute C_WRITE_ACCEPTANCE of inst : label is 32;
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute P_FULLY_PIPELINED : integer;
  attribute P_FULLY_PIPELINED of inst : label is 2;
  attribute P_ID_BUFFER_WIDTH : integer;
  attribute P_ID_BUFFER_WIDTH of inst : label is 1;
  attribute P_M_THREAD_ID_WIDTH : integer;
  attribute P_M_THREAD_ID_WIDTH of inst : label is 1;
  attribute P_NUM_READ_OUTSTANDING : integer;
  attribute P_NUM_READ_OUTSTANDING of inst : label is 16;
  attribute P_NUM_WRITE_OUTSTANDING : integer;
  attribute P_NUM_WRITE_OUTSTANDING of inst : label is 16;
  attribute P_R_QUEUE_SIZE : integer;
  attribute P_R_QUEUE_SIZE of inst : label is 4;
  attribute P_S_ID_WIDTH : integer;
  attribute P_S_ID_WIDTH of inst : label is 1;
  attribute P_W_QUEUE_SIZE : integer;
  attribute P_W_QUEUE_SIZE of inst : label is 4;
  attribute P_ZERO_LATENCY : integer;
  attribute P_ZERO_LATENCY of inst : label is 1;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_transaction_regulator_v1_0_11_top__parameterized0\
     port map (
      aclk => aclk,
      aclken => '1',
      aresetn => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
      m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      m_axi_arid(1 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(1 downto 0),
      m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
      m_axi_arlock(0) => m_axi_arlock(0),
      m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      m_axi_arready => \state_reg[s_ready_i]\,
      m_axi_arsize(2) => NLW_inst_m_axi_arsize_UNCONNECTED(2),
      m_axi_arsize(1 downto 0) => m_axi_arsize(1 downto 0),
      m_axi_aruser(1023 downto 147) => NLW_inst_m_axi_aruser_UNCONNECTED(1023 downto 147),
      m_axi_aruser(146 downto 136) => m_axi_aruser(10 downto 0),
      m_axi_aruser(135 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(135 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
      m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
      m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
      m_axi_awid(1 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(1 downto 0),
      m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
      m_axi_awlock(0) => m_axi_awlock(0),
      m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
      m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
      m_axi_awready => \m_vector_i_reg[138]\,
      m_axi_awsize(2) => NLW_inst_m_axi_awsize_UNCONNECTED(2),
      m_axi_awsize(1 downto 0) => m_axi_awsize(1 downto 0),
      m_axi_awuser(1023 downto 147) => NLW_inst_m_axi_awuser_UNCONNECTED(1023 downto 147),
      m_axi_awuser(146 downto 136) => m_axi_awuser(10 downto 0),
      m_axi_awuser(135 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(135 downto 0),
      m_axi_awvalid => m_axi_awvalid,
      m_axi_bid(1 downto 0) => B"00",
      m_axi_bready => m_axi_bready,
      m_axi_bresp(1 downto 0) => \skid_buffer_reg[1057]\(1 downto 0),
      m_axi_buser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_bvalid => \gen_endpoint.b_cnt_reg[0]\,
      m_axi_rdata(31 downto 0) => \skid_buffer_reg[1090]\(31 downto 0),
      m_axi_rid(1 downto 0) => B"00",
      m_axi_rlast => \skid_buffer_reg[1058]\,
      m_axi_rready => m_axi_rready,
      m_axi_rresp(1 downto 0) => \skid_buffer_reg[1057]_0\(1 downto 0),
      m_axi_ruser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_rvalid => \gen_endpoint.r_cnt_reg[0]\,
      m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
      m_axi_wlast => m_axi_wlast,
      m_axi_wready => \gen_endpoint.w_enable_reg\,
      m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
      m_axi_wuser(1023 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(1023 downto 0),
      m_axi_wvalid => m_axi_wvalid,
      mep_identifier(1 downto 0) => B"10",
      s_axi_araddr(31 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_4\(31 downto 0),
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arcache(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_6\(3 downto 0),
      s_axi_arid(0) => '0',
      s_axi_arlen(7 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]_0\(7 downto 0),
      s_axi_arlock(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_5\(0),
      s_axi_arprot(2 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_7\(2 downto 0),
      s_axi_arqos(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_8\(3 downto 0),
      s_axi_arready => s_axi_arready,
      s_axi_arsize(2) => '0',
      s_axi_arsize(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\(1 downto 0),
      s_axi_aruser(1023 downto 147) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_aruser(146 downto 136) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]_0\(10 downto 0),
      s_axi_aruser(135 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_arvalid => \count_r_reg[5]\,
      s_axi_awaddr(31 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\(31 downto 0),
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awcache(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\(3 downto 0),
      s_axi_awid(0) => '0',
      s_axi_awlen(7 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\(7 downto 0),
      s_axi_awlock(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\(0),
      s_axi_awprot(2 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\(2 downto 0),
      s_axi_awqos(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\(3 downto 0),
      s_axi_awready => s_axi_awready,
      s_axi_awsize(2) => '0',
      s_axi_awsize(1 downto 0) => \gen_pipelined.mesg_reg_reg[0]\(1 downto 0),
      s_axi_awuser(1023 downto 147) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awuser(146 downto 136) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\(10 downto 0),
      s_axi_awuser(135 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awvalid => \gen_pipelined.state_reg[0]\,
      s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
      s_axi_bready => \count_r_reg[1]\,
      s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
      s_axi_buser(1023 downto 0) => NLW_inst_s_axi_buser_UNCONNECTED(1023 downto 0),
      s_axi_bvalid => s_axi_bvalid,
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
      s_axi_rlast => s_axi_rlast,
      s_axi_rready => \count_r_reg[5]_0\,
      s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      s_axi_ruser(1023 downto 0) => NLW_inst_s_axi_ruser_UNCONNECTED(1023 downto 0),
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(31 downto 0) => \gen_w_ch.accum_reg[bytes][11][userdata][7]\(31 downto 0),
      s_axi_wlast => \gen_pipe[1].pipe_reg[1][0]\,
      s_axi_wready => s_axi_wready,
      s_axi_wstrb(3 downto 0) => \gen_w_ch.accum_reg[bytes][3][strb]\(3 downto 0),
      s_axi_wuser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
      s_axi_wvalid => \gen_pipelined.mesg_reg_reg[13]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_wsw_0 is
  port (
    S01_SC_W_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_info : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_payld : out STD_LOGIC_VECTOR ( 147 downto 0 );
    aclk : in STD_LOGIC;
    S01_SC_W_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_SC_W_req : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_SC_W_info : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_SC_W_payld : in STD_LOGIC_VECTOR ( 147 downto 0 );
    M00_SC_W_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_wsw_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_wsw_0 is
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_send_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_sc_recv_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_CONNECTIVITY : string;
  attribute C_CONNECTIVITY of inst : label is "2'b11";
  attribute C_M_PIPELINES : string;
  attribute C_M_PIPELINES of inst : label is "32'b00000000000000000000000000000001";
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 2;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 160;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 0;
  attribute C_S_PIPELINES : string;
  attribute C_S_PIPELINES of inst : label is "32'b00000000000000000000000000000000";
  attribute C_TESTING_MODE : integer;
  attribute C_TESTING_MODE of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute K_MAX_INFO_WIDTH : integer;
  attribute K_MAX_INFO_WIDTH of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_MUX_IMPL : string;
  attribute LP_MUX_IMPL of inst : label is "32'b00000000000000000000000000000000";
  attribute LP_M_SC_SEL_MI_PIPELINE_DEPTH : string;
  attribute LP_M_SC_SEL_MI_PIPELINE_DEPTH of inst : label is "32'b00000000000000000000000000000000";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_switchboard_v1_0_8_top__parameterized2\
     port map (
      aclk => aclk,
      aclken => '1',
      connectivity(1 downto 0) => B"11",
      m_sc_info(1) => M00_SC_W_info(0),
      m_sc_info(0) => NLW_inst_m_sc_info_UNCONNECTED(0),
      m_sc_payld(159 downto 14) => M00_SC_W_payld(147 downto 2),
      m_sc_payld(13 downto 9) => NLW_inst_m_sc_payld_UNCONNECTED(13 downto 9),
      m_sc_payld(8) => M00_SC_W_payld(1),
      m_sc_payld(7 downto 2) => NLW_inst_m_sc_payld_UNCONNECTED(7 downto 2),
      m_sc_payld(1) => M00_SC_W_payld(0),
      m_sc_payld(0) => NLW_inst_m_sc_payld_UNCONNECTED(0),
      m_sc_recv(1) => M00_SC_W_recv(0),
      m_sc_recv(0) => '0',
      m_sc_req(1) => M00_SC_W_req(0),
      m_sc_req(0) => NLW_inst_m_sc_req_UNCONNECTED(0),
      m_sc_send(1) => M00_SC_W_send(0),
      m_sc_send(0) => NLW_inst_m_sc_send_UNCONNECTED(0),
      s_sc_info(1) => S01_SC_W_info(0),
      s_sc_info(0) => '0',
      s_sc_payld(319 downto 174) => S01_SC_W_payld(147 downto 2),
      s_sc_payld(173 downto 169) => B"00000",
      s_sc_payld(168) => S01_SC_W_payld(1),
      s_sc_payld(167 downto 162) => B"000000",
      s_sc_payld(161) => S01_SC_W_payld(0),
      s_sc_payld(160 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_sc_recv(1) => S01_SC_W_recv(0),
      s_sc_recv(0) => NLW_inst_s_sc_recv_UNCONNECTED(0),
      s_sc_req(1) => S01_SC_W_req(0),
      s_sc_req(0) => '0',
      s_sc_send(1) => S01_SC_W_send(0),
      s_sc_send(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_proc_sys_reset is
  port (
    interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_proc_sys_reset;

architecture STRUCTURE of Loopback_smartconnect_0_0_proc_sys_reset is
  signal SEQ_n_0 : STD_LOGIC;
  signal lpf_int : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => SEQ_n_0,
      Q => interconnect_aresetn(0),
      R => '0'
    );
EXT_LPF: entity work.Loopback_smartconnect_0_0_lpf
     port map (
      aclk => aclk,
      aresetn => aresetn,
      lpf_int => lpf_int
    );
SEQ: entity work.Loopback_smartconnect_0_0_sequence_psr
     port map (
      aclk => aclk,
      bsr_reg_0 => SEQ_n_0,
      lpf_int => lpf_int
    );
end STRUCTURE;
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`protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Xilinx", key_keyname="xilinxt_2023_11", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`protect key_block
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`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 262608)
`protect data_block
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_psr_aclk_0 is
  port (
    interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_psr_aclk_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_psr_aclk_0 is
begin
U0: entity work.Loopback_smartconnect_0_0_proc_sys_reset
     port map (
      aclk => aclk,
      aresetn => aresetn,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_s00_entry_pipeline_imp_5Y6K3Z is
  port (
    S00_AXI_arready : out STD_LOGIC;
    S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_rlast : out STD_LOGIC;
    S00_AXI_rvalid : out STD_LOGIC;
    m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : out STD_LOGIC_VECTOR ( 24 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_rready : out STD_LOGIC;
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arvalid : in STD_LOGIC;
    S00_AXI_rready : in STD_LOGIC;
    s_axi_arready : in STD_LOGIC;
    s_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : in STD_LOGIC;
    s_axi_rvalid : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_s00_entry_pipeline_imp_5Y6K3Z;

architecture STRUCTURE of Loopback_smartconnect_0_0_s00_entry_pipeline_imp_5Y6K3Z is
  signal s00_mmu_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s00_mmu_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s00_mmu_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal s00_mmu_M_AXI_ARLOCK : STD_LOGIC;
  signal s00_mmu_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal s00_mmu_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s00_mmu_M_AXI_ARREADY : STD_LOGIC;
  signal s00_mmu_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s00_mmu_M_AXI_ARUSER : STD_LOGIC_VECTOR ( 146 downto 136 );
  signal s00_mmu_M_AXI_ARVALID : STD_LOGIC;
  signal s00_mmu_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s00_mmu_M_AXI_RLAST : STD_LOGIC;
  signal s00_mmu_M_AXI_RREADY : STD_LOGIC;
  signal s00_mmu_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s00_mmu_M_AXI_RVALID : STD_LOGIC;
  signal s00_transaction_regulator_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s00_transaction_regulator_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s00_transaction_regulator_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal s00_transaction_regulator_M_AXI_ARLOCK : STD_LOGIC;
  signal s00_transaction_regulator_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal s00_transaction_regulator_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s00_transaction_regulator_M_AXI_ARREADY : STD_LOGIC;
  signal s00_transaction_regulator_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s00_transaction_regulator_M_AXI_ARUSER : STD_LOGIC_VECTOR ( 146 downto 136 );
  signal s00_transaction_regulator_M_AXI_ARVALID : STD_LOGIC;
  signal s00_transaction_regulator_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s00_transaction_regulator_M_AXI_RLAST : STD_LOGIC;
  signal s00_transaction_regulator_M_AXI_RREADY : STD_LOGIC;
  signal s00_transaction_regulator_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s00_transaction_regulator_M_AXI_RVALID : STD_LOGIC;
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of s00_mmu : label is "sc_mmu_v1_0_14_top,Vivado 2024.2";
  attribute X_CORE_INFO of s00_si_converter : label is "sc_si_converter_v1_0_14_top,Vivado 2024.2";
  attribute X_CORE_INFO of s00_transaction_regulator : label is "sc_transaction_regulator_v1_0_11_top,Vivado 2024.2";
begin
s00_mmu: entity work.Loopback_smartconnect_0_0_bd_e34c_s00mmu_0
     port map (
      S00_AXI_araddr(31 downto 0) => S00_AXI_araddr(31 downto 0),
      S00_AXI_arburst(1 downto 0) => S00_AXI_arburst(1 downto 0),
      S00_AXI_arcache(3 downto 0) => S00_AXI_arcache(3 downto 0),
      S00_AXI_arlen(7 downto 0) => S00_AXI_arlen(7 downto 0),
      S00_AXI_arlock(0) => S00_AXI_arlock(0),
      S00_AXI_arprot(2 downto 0) => S00_AXI_arprot(2 downto 0),
      S00_AXI_arqos(3 downto 0) => S00_AXI_arqos(3 downto 0),
      S00_AXI_arready => S00_AXI_arready,
      S00_AXI_arsize(2 downto 0) => S00_AXI_arsize(2 downto 0),
      S00_AXI_arvalid => S00_AXI_arvalid,
      S00_AXI_rdata(31 downto 0) => S00_AXI_rdata(31 downto 0),
      S00_AXI_rlast => S00_AXI_rlast,
      S00_AXI_rready => S00_AXI_rready,
      S00_AXI_rresp(1 downto 0) => S00_AXI_rresp(1 downto 0),
      S00_AXI_rvalid => S00_AXI_rvalid,
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => s00_mmu_M_AXI_ARADDR(31 downto 0),
      m_axi_arcache(3 downto 0) => s00_mmu_M_AXI_ARCACHE(3 downto 0),
      m_axi_arlen(7 downto 0) => s00_mmu_M_AXI_ARLEN(7 downto 0),
      m_axi_arlock(0) => s00_mmu_M_AXI_ARLOCK,
      m_axi_arprot(2 downto 0) => s00_mmu_M_AXI_ARPROT(2 downto 0),
      m_axi_arqos(3 downto 0) => s00_mmu_M_AXI_ARQOS(3 downto 0),
      m_axi_arsize(1 downto 0) => s00_mmu_M_AXI_ARSIZE(1 downto 0),
      m_axi_aruser(10 downto 0) => s00_mmu_M_AXI_ARUSER(146 downto 136),
      m_axi_arvalid => s00_mmu_M_AXI_ARVALID,
      m_axi_rready => s00_mmu_M_AXI_RREADY,
      s_axi_arready => s00_mmu_M_AXI_ARREADY,
      s_axi_rdata(31 downto 0) => s00_mmu_M_AXI_RDATA(31 downto 0),
      s_axi_rlast => s00_mmu_M_AXI_RLAST,
      s_axi_rresp(1 downto 0) => s00_mmu_M_AXI_RRESP(1 downto 0),
      s_axi_rvalid => s00_mmu_M_AXI_RVALID
    );
s00_si_converter: entity work.Loopback_smartconnect_0_0_bd_e34c_s00sic_0
     port map (
      aclk => aclk,
      \count_r_reg[5]\ => s00_transaction_regulator_M_AXI_ARVALID,
      \count_r_reg[5]_0\ => s00_transaction_regulator_M_AXI_RREADY,
      \gen_endpoint.r_cnt_reg[0]\ => s_axi_rvalid,
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\(31 downto 0) => s00_transaction_regulator_M_AXI_ARADDR(31 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\(0) => s00_transaction_regulator_M_AXI_ARLOCK,
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\(3 downto 0) => s00_transaction_regulator_M_AXI_ARCACHE(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\(2 downto 0) => s00_transaction_regulator_M_AXI_ARPROT(2 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\(3 downto 0) => s00_transaction_regulator_M_AXI_ARQOS(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\(10 downto 0) => s00_transaction_regulator_M_AXI_ARUSER(146 downto 136),
      interconnect_aresetn(0) => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      m_axi_arlen(7 downto 0) => s00_transaction_regulator_M_AXI_ARLEN(7 downto 0),
      m_axi_arlock(0) => m_axi_arlock(0),
      m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      m_axi_arsize(1 downto 0) => s00_transaction_regulator_M_AXI_ARSIZE(1 downto 0),
      m_axi_aruser(24 downto 0) => m_axi_aruser(24 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_rready => m_axi_rready,
      \m_vector_i[1092]_i_3\ => s_axi_arready,
      s_axi_arready => s00_transaction_regulator_M_AXI_ARREADY,
      s_axi_rdata(31 downto 0) => s00_transaction_regulator_M_AXI_RDATA(31 downto 0),
      s_axi_rlast => s00_transaction_regulator_M_AXI_RLAST,
      s_axi_rresp(1 downto 0) => s00_transaction_regulator_M_AXI_RRESP(1 downto 0),
      s_axi_rvalid => s00_transaction_regulator_M_AXI_RVALID,
      \skid_buffer_reg[1057]\(1 downto 0) => s_axi_rresp(1 downto 0),
      \skid_buffer_reg[1058]\ => s_axi_rlast,
      \skid_buffer_reg[1090]\(31 downto 0) => s_axi_rdata(31 downto 0)
    );
s00_transaction_regulator: entity work.Loopback_smartconnect_0_0_bd_e34c_s00tr_0
     port map (
      aclk => aclk,
      \count_r_reg[5]\ => s00_mmu_M_AXI_ARVALID,
      \count_r_reg[5]_0\ => s00_mmu_M_AXI_RREADY,
      \gen_endpoint.r_cnt_reg[0]\ => s00_transaction_regulator_M_AXI_RVALID,
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\(31 downto 0) => s00_mmu_M_AXI_ARADDR(31 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\(0) => s00_mmu_M_AXI_ARLOCK,
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\(3 downto 0) => s00_mmu_M_AXI_ARCACHE(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\(2 downto 0) => s00_mmu_M_AXI_ARPROT(2 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\(3 downto 0) => s00_mmu_M_AXI_ARQOS(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\(7 downto 0) => s00_mmu_M_AXI_ARLEN(7 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\(10 downto 0) => s00_mmu_M_AXI_ARUSER(146 downto 136),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\(1 downto 0) => s00_mmu_M_AXI_ARSIZE(1 downto 0),
      interconnect_aresetn(0) => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => s00_transaction_regulator_M_AXI_ARADDR(31 downto 0),
      m_axi_arcache(3 downto 0) => s00_transaction_regulator_M_AXI_ARCACHE(3 downto 0),
      m_axi_arlen(7 downto 0) => s00_transaction_regulator_M_AXI_ARLEN(7 downto 0),
      m_axi_arlock(0) => s00_transaction_regulator_M_AXI_ARLOCK,
      m_axi_arprot(2 downto 0) => s00_transaction_regulator_M_AXI_ARPROT(2 downto 0),
      m_axi_arqos(3 downto 0) => s00_transaction_regulator_M_AXI_ARQOS(3 downto 0),
      m_axi_arsize(1 downto 0) => s00_transaction_regulator_M_AXI_ARSIZE(1 downto 0),
      m_axi_aruser(10 downto 0) => s00_transaction_regulator_M_AXI_ARUSER(146 downto 136),
      m_axi_arvalid => s00_transaction_regulator_M_AXI_ARVALID,
      m_axi_rready => s00_transaction_regulator_M_AXI_RREADY,
      s_axi_arready => s00_mmu_M_AXI_ARREADY,
      s_axi_rdata(31 downto 0) => s00_mmu_M_AXI_RDATA(31 downto 0),
      s_axi_rlast => s00_mmu_M_AXI_RLAST,
      s_axi_rresp(1 downto 0) => s00_mmu_M_AXI_RRESP(1 downto 0),
      s_axi_rvalid => s00_mmu_M_AXI_RVALID,
      \skid_buffer_reg[1057]\(1 downto 0) => s00_transaction_regulator_M_AXI_RRESP(1 downto 0),
      \skid_buffer_reg[1058]\ => s00_transaction_regulator_M_AXI_RLAST,
      \skid_buffer_reg[1090]\(31 downto 0) => s00_transaction_regulator_M_AXI_RDATA(31 downto 0),
      \state_reg[s_ready_i]\ => s00_transaction_regulator_M_AXI_ARREADY
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_switchboards_imp_TR9R9D is
  port (
    s_sc_recv : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_SC_AR_send : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_SC_AR_req : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_SC_AR_payld : out STD_LOGIC_VECTOR ( 82 downto 0 );
    S01_SC_AW_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_payld : out STD_LOGIC_VECTOR ( 82 downto 0 );
    S00_SC_B_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_B_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_B_payld : out STD_LOGIC_VECTOR ( 5 downto 0 );
    S00_SC_R_recv : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_sc_send : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_sc_payld : out STD_LOGIC_VECTOR ( 277 downto 0 );
    S01_SC_W_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_info : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_payld : out STD_LOGIC_VECTOR ( 147 downto 0 );
    aclk : in STD_LOGIC;
    s_sc_send : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_sc_req : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_sc_payld : in STD_LOGIC_VECTOR ( 165 downto 0 );
    M00_SC_AR_recv : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_SC_AW_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_SC_AW_req : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_SC_AW_payld : in STD_LOGIC_VECTOR ( 82 downto 0 );
    M00_SC_AW_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_SC_B_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_SC_B_payld : in STD_LOGIC_VECTOR ( 5 downto 0 );
    M01_SC_B_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_SC_R_send : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_SC_R_payld : in STD_LOGIC_VECTOR ( 138 downto 0 );
    m_sc_recv : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_SC_W_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_SC_W_req : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_SC_W_info : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_SC_W_payld : in STD_LOGIC_VECTOR ( 147 downto 0 );
    M00_SC_W_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_switchboards_imp_TR9R9D;

architecture STRUCTURE of Loopback_smartconnect_0_0_switchboards_imp_TR9R9D is
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of ar_switchboard : label is "sc_switchboard_v1_0_8_top,Vivado 2024.2";
  attribute X_CORE_INFO of aw_switchboard : label is "sc_switchboard_v1_0_8_top,Vivado 2024.2";
  attribute X_CORE_INFO of b_switchboard : label is "sc_switchboard_v1_0_8_top,Vivado 2024.2";
  attribute X_CORE_INFO of r_switchboard : label is "sc_switchboard_v1_0_8_top,Vivado 2024.2";
  attribute X_CORE_INFO of w_switchboard : label is "sc_switchboard_v1_0_8_top,Vivado 2024.2";
begin
ar_switchboard: entity work.Loopback_smartconnect_0_0_bd_e34c_arsw_0
     port map (
      M00_SC_AR_payld(82 downto 0) => M00_SC_AR_payld(82 downto 0),
      M00_SC_AR_recv(1 downto 0) => M00_SC_AR_recv(1 downto 0),
      M00_SC_AR_req(1 downto 0) => M00_SC_AR_req(1 downto 0),
      M00_SC_AR_send(1 downto 0) => M00_SC_AR_send(1 downto 0),
      aclk => aclk,
      s_sc_payld(165 downto 0) => s_sc_payld(165 downto 0),
      s_sc_recv(1 downto 0) => s_sc_recv(1 downto 0),
      s_sc_req(1 downto 0) => s_sc_req(1 downto 0),
      s_sc_send(1 downto 0) => s_sc_send(1 downto 0)
    );
aw_switchboard: entity work.Loopback_smartconnect_0_0_bd_e34c_awsw_0
     port map (
      M00_SC_AW_payld(82 downto 0) => M00_SC_AW_payld(82 downto 0),
      M00_SC_AW_recv(0) => M00_SC_AW_recv(0),
      M00_SC_AW_req(0) => M00_SC_AW_req(0),
      M00_SC_AW_send(0) => M00_SC_AW_send(0),
      S01_SC_AW_payld(82 downto 0) => S01_SC_AW_payld(82 downto 0),
      S01_SC_AW_recv(0) => S01_SC_AW_recv(0),
      S01_SC_AW_req(0) => S01_SC_AW_req(0),
      S01_SC_AW_send(0) => S01_SC_AW_send(0),
      aclk => aclk
    );
b_switchboard: entity work.Loopback_smartconnect_0_0_bd_e34c_bsw_0
     port map (
      M01_SC_B_payld(5 downto 0) => M01_SC_B_payld(5 downto 0),
      M01_SC_B_recv(0) => M01_SC_B_recv(0),
      M01_SC_B_send(0) => M01_SC_B_send(0),
      S00_SC_B_payld(5 downto 0) => S00_SC_B_payld(5 downto 0),
      S00_SC_B_recv(0) => S00_SC_B_recv(0),
      S00_SC_B_send(0) => S00_SC_B_send(0),
      aclk => aclk
    );
r_switchboard: entity work.Loopback_smartconnect_0_0_bd_e34c_rsw_0
     port map (
      S00_SC_R_payld(138 downto 0) => S00_SC_R_payld(138 downto 0),
      S00_SC_R_recv(1 downto 0) => S00_SC_R_recv(1 downto 0),
      S00_SC_R_send(1 downto 0) => S00_SC_R_send(1 downto 0),
      aclk => aclk,
      m_sc_payld(277 downto 0) => m_sc_payld(277 downto 0),
      m_sc_recv(1 downto 0) => m_sc_recv(1 downto 0),
      m_sc_send(1 downto 0) => m_sc_send(1 downto 0)
    );
w_switchboard: entity work.Loopback_smartconnect_0_0_bd_e34c_wsw_0
     port map (
      M00_SC_W_info(0) => M00_SC_W_info(0),
      M00_SC_W_payld(147 downto 0) => M00_SC_W_payld(147 downto 0),
      M00_SC_W_recv(0) => M00_SC_W_recv(0),
      M00_SC_W_req(0) => M00_SC_W_req(0),
      M00_SC_W_send(0) => M00_SC_W_send(0),
      S01_SC_W_info(0) => S01_SC_W_info(0),
      S01_SC_W_payld(147 downto 0) => S01_SC_W_payld(147 downto 0),
      S01_SC_W_recv(0) => S01_SC_W_recv(0),
      S01_SC_W_req(0) => S01_SC_W_req(0),
      S01_SC_W_send(0) => S01_SC_W_send(0),
      aclk => aclk
    );
end STRUCTURE;
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_m00e_0 is
  port (
    s_axi_awready : out STD_LOGIC;
    s_axi_wready : out STD_LOGIC;
    s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_buser : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC;
    s_axi_arready : out STD_LOGIC;
    s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : out STD_LOGIC;
    s_axi_ruser : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_axi_rvalid : out STD_LOGIC;
    M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awvalid : out STD_LOGIC;
    M00_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
    M00_AXI_wlast : out STD_LOGIC;
    M00_AXI_wvalid : out STD_LOGIC;
    M00_AXI_bready : out STD_LOGIC;
    M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arvalid : out STD_LOGIC;
    M00_AXI_rready : out STD_LOGIC;
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awuser : in STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axi_awvalid : in STD_LOGIC;
    m_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    m_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
    m_axi_wlast : in STD_LOGIC;
    m_axi_wvalid : in STD_LOGIC;
    m_axi_bready : in STD_LOGIC;
    m_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    m_axi_arvalid : in STD_LOGIC;
    m_axi_rready : in STD_LOGIC;
    M00_AXI_awready : in STD_LOGIC;
    M00_AXI_wready : in STD_LOGIC;
    M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_bvalid : in STD_LOGIC;
    M00_AXI_arready : in STD_LOGIC;
    M00_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_rlast : in STD_LOGIC;
    M00_AXI_rvalid : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_m00e_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_m00e_0 is
  signal NLW_inst_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 48 downto 32 );
  signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 48 downto 32 );
  signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 2 );
  signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 2 );
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 49;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "1'b1";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_HAS_LOCK : integer;
  attribute C_HAS_LOCK of inst : label is 0;
  attribute C_IS_CASCADED : integer;
  attribute C_IS_CASCADED of inst : label is 0;
  attribute C_MAX_RUSER_BITS_PER_BYTE : integer;
  attribute C_MAX_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_MAX_WUSER_BITS_PER_BYTE : integer;
  attribute C_MAX_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_MEP_IDENTIFIER_WIDTH : integer;
  attribute C_MEP_IDENTIFIER_WIDTH of inst : label is 2;
  attribute C_M_ARUSER_WIDTH : integer;
  attribute C_M_ARUSER_WIDTH of inst : label is 0;
  attribute C_M_AWUSER_WIDTH : integer;
  attribute C_M_AWUSER_WIDTH of inst : label is 0;
  attribute C_M_BUSER_WIDTH : integer;
  attribute C_M_BUSER_WIDTH of inst : label is 0;
  attribute C_M_ID_WIDTH : integer;
  attribute C_M_ID_WIDTH of inst : label is 0;
  attribute C_M_LIMIT_READ_LENGTH : integer;
  attribute C_M_LIMIT_READ_LENGTH of inst : label is 4;
  attribute C_M_LIMIT_WRITE_LENGTH : integer;
  attribute C_M_LIMIT_WRITE_LENGTH of inst : label is 4;
  attribute C_M_PROTOCOL : integer;
  attribute C_M_PROTOCOL of inst : label is 0;
  attribute C_M_RUSER_BITS_PER_BYTE : integer;
  attribute C_M_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_M_RUSER_WIDTH : integer;
  attribute C_M_RUSER_WIDTH of inst : label is 0;
  attribute C_M_WUSER_BITS_PER_BYTE : integer;
  attribute C_M_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_M_WUSER_WIDTH : integer;
  attribute C_M_WUSER_WIDTH of inst : label is 0;
  attribute C_NUM_MSC : integer;
  attribute C_NUM_MSC of inst : label is 1;
  attribute C_NUM_READ_OUTSTANDING : integer;
  attribute C_NUM_READ_OUTSTANDING of inst : label is 16;
  attribute C_NUM_READ_THREADS : integer;
  attribute C_NUM_READ_THREADS of inst : label is 1;
  attribute C_NUM_WRITE_OUTSTANDING : integer;
  attribute C_NUM_WRITE_OUTSTANDING of inst : label is 2;
  attribute C_NUM_WRITE_THREADS : integer;
  attribute C_NUM_WRITE_THREADS of inst : label is 1;
  attribute C_RDATA_WIDTH : integer;
  attribute C_RDATA_WIDTH of inst : label is 128;
  attribute C_READ_ACCEPTANCE : integer;
  attribute C_READ_ACCEPTANCE of inst : label is 32;
  attribute C_SINGLE_ISSUING : integer;
  attribute C_SINGLE_ISSUING of inst : label is 0;
  attribute C_SSC_ROUTE_ARRAY : string;
  attribute C_SSC_ROUTE_ARRAY of inst : label is "8'b00100100";
  attribute C_SSC_ROUTE_WIDTH : integer;
  attribute C_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute C_S_ID_WIDTH : integer;
  attribute C_S_ID_WIDTH of inst : label is 2;
  attribute C_WDATA_WIDTH : integer;
  attribute C_WDATA_WIDTH of inst : label is 128;
  attribute C_WRITE_ACCEPTANCE : integer;
  attribute C_WRITE_ACCEPTANCE of inst : label is 32;
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute P_BYPASS : integer;
  attribute P_BYPASS of inst : label is 0;
  attribute P_FULLY_PIPELINED : integer;
  attribute P_FULLY_PIPELINED of inst : label is 2;
  attribute P_NUM_READ_OUTSTANDING : integer;
  attribute P_NUM_READ_OUTSTANDING of inst : label is 16;
  attribute P_NUM_WRITE_OUTSTANDING : integer;
  attribute P_NUM_WRITE_OUTSTANDING of inst : label is 16;
  attribute P_SINGLE_THREAD_R : integer;
  attribute P_SINGLE_THREAD_R of inst : label is 0;
  attribute P_SINGLE_THREAD_W : integer;
  attribute P_SINGLE_THREAD_W of inst : label is 0;
  attribute P_ZERO_LATENCY : integer;
  attribute P_ZERO_LATENCY of inst : label is 1;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.Loopback_smartconnect_0_0_sc_exit_v1_0_16_top
     port map (
      aclk => aclk,
      aclken => '1',
      aresetn => interconnect_aresetn(0),
      m_axi_araddr(48 downto 32) => NLW_inst_m_axi_araddr_UNCONNECTED(48 downto 32),
      m_axi_araddr(31 downto 0) => M00_AXI_araddr(31 downto 0),
      m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
      m_axi_arcache(3 downto 0) => M00_AXI_arcache(3 downto 0),
      m_axi_arid(0) => NLW_inst_m_axi_arid_UNCONNECTED(0),
      m_axi_arlen(7 downto 0) => M00_AXI_arlen(7 downto 0),
      m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
      m_axi_arprot(2 downto 0) => M00_AXI_arprot(2 downto 0),
      m_axi_arqos(3 downto 0) => M00_AXI_arqos(3 downto 0),
      m_axi_arready => M00_AXI_arready,
      m_axi_arsize(2 downto 0) => M00_AXI_arsize(2 downto 0),
      m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
      m_axi_arvalid => M00_AXI_arvalid,
      m_axi_awaddr(48 downto 32) => NLW_inst_m_axi_awaddr_UNCONNECTED(48 downto 32),
      m_axi_awaddr(31 downto 0) => M00_AXI_awaddr(31 downto 0),
      m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
      m_axi_awcache(3 downto 0) => M00_AXI_awcache(3 downto 0),
      m_axi_awid(0) => NLW_inst_m_axi_awid_UNCONNECTED(0),
      m_axi_awlen(7 downto 0) => M00_AXI_awlen(7 downto 0),
      m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
      m_axi_awprot(2 downto 0) => M00_AXI_awprot(2 downto 0),
      m_axi_awqos(3 downto 0) => M00_AXI_awqos(3 downto 0),
      m_axi_awready => M00_AXI_awready,
      m_axi_awsize(2 downto 0) => M00_AXI_awsize(2 downto 0),
      m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
      m_axi_awvalid => M00_AXI_awvalid,
      m_axi_bid(0) => '0',
      m_axi_bready => M00_AXI_bready,
      m_axi_bresp(1 downto 0) => M00_AXI_bresp(1 downto 0),
      m_axi_buser(0) => '0',
      m_axi_bvalid => M00_AXI_bvalid,
      m_axi_rdata(127 downto 0) => M00_AXI_rdata(127 downto 0),
      m_axi_rid(0) => '0',
      m_axi_rlast => M00_AXI_rlast,
      m_axi_rready => M00_AXI_rready,
      m_axi_rresp(1 downto 0) => M00_AXI_rresp(1 downto 0),
      m_axi_ruser(0) => '0',
      m_axi_rvalid => M00_AXI_rvalid,
      m_axi_wdata(127 downto 0) => M00_AXI_wdata(127 downto 0),
      m_axi_wid(0) => NLW_inst_m_axi_wid_UNCONNECTED(0),
      m_axi_wlast => M00_AXI_wlast,
      m_axi_wready => M00_AXI_wready,
      m_axi_wstrb(15 downto 0) => M00_AXI_wstrb(15 downto 0),
      m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
      m_axi_wvalid => M00_AXI_wvalid,
      s_axi_araddr(48 downto 32) => B"00000000000000000",
      s_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      s_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      s_axi_arid(1 downto 0) => m_axi_arid(1 downto 0),
      s_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
      s_axi_arlock(0) => '0',
      s_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      s_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      s_axi_arready => s_axi_arready,
      s_axi_aruser(1023 downto 186) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_aruser(185 downto 179) => m_axi_aruser(17 downto 11),
      s_axi_aruser(178 downto 147) => B"00000000000000000000000000000000",
      s_axi_aruser(146 downto 136) => m_axi_aruser(10 downto 0),
      s_axi_aruser(135 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_arvalid => m_axi_arvalid,
      s_axi_awaddr(48 downto 32) => B"00000000000000000",
      s_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
      s_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
      s_axi_awid(1 downto 0) => m_axi_awid(1 downto 0),
      s_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
      s_axi_awlock(0) => '0',
      s_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
      s_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
      s_axi_awready => s_axi_awready,
      s_axi_awuser(1023 downto 147) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awuser(146 downto 136) => m_axi_awuser(10 downto 0),
      s_axi_awuser(135 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awvalid => m_axi_awvalid,
      s_axi_bid(1 downto 0) => s_axi_bid(1 downto 0),
      s_axi_bready => m_axi_bready,
      s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
      s_axi_buser(1023 downto 2) => NLW_inst_s_axi_buser_UNCONNECTED(1023 downto 2),
      s_axi_buser(1 downto 0) => s_axi_buser(1 downto 0),
      s_axi_bvalid => s_axi_bvalid,
      s_axi_rdata(127 downto 0) => s_axi_rdata(127 downto 0),
      s_axi_rid(1 downto 0) => s_axi_rid(1 downto 0),
      s_axi_rlast => s_axi_rlast,
      s_axi_rready => m_axi_rready,
      s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      s_axi_ruser(1023 downto 78) => NLW_inst_s_axi_ruser_UNCONNECTED(1023 downto 78),
      s_axi_ruser(77 downto 64) => s_axi_ruser(15 downto 2),
      s_axi_ruser(63 downto 2) => NLW_inst_s_axi_ruser_UNCONNECTED(63 downto 2),
      s_axi_ruser(1 downto 0) => s_axi_ruser(1 downto 0),
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
      s_axi_wlast => m_axi_wlast,
      s_axi_wready => s_axi_wready,
      s_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
      s_axi_wuser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wvalid => m_axi_wvalid
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_s01sic_0 is
  port (
    s_axi_awready : out STD_LOGIC;
    s_axi_wready : out STD_LOGIC;
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC;
    s_axi_arready : out STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : out STD_LOGIC;
    s_axi_rvalid : out STD_LOGIC;
    m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awuser : out STD_LOGIC_VECTOR ( 24 downto 0 );
    m_axi_awvalid : out STD_LOGIC;
    m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_wlast : out STD_LOGIC;
    m_axi_wuser : out STD_LOGIC_VECTOR ( 13 downto 0 );
    m_axi_wvalid : out STD_LOGIC;
    m_axi_bready : out STD_LOGIC;
    m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : out STD_LOGIC_VECTOR ( 24 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_rready : out STD_LOGIC;
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \gen_pipelined.state_reg[0]\ : in STD_LOGIC;
    \gen_w_ch.accum_reg[bytes][11][userdata][7]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \gen_w_ch.accum_reg[bytes][3][strb]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_pipe[1].pipe_reg[1][0]\ : in STD_LOGIC;
    \gen_pipelined.mesg_reg_reg[13]\ : in STD_LOGIC;
    \count_r_reg[1]\ : in STD_LOGIC;
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_4\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_7\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \count_r_reg[5]\ : in STD_LOGIC;
    \count_r_reg[5]_0\ : in STD_LOGIC;
    \gen_pipelined.state_reg[0]_0\ : in STD_LOGIC;
    \gen_pipelined.mesg_reg_reg[13]_0\ : in STD_LOGIC;
    \skid_buffer_reg[1057]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_endpoint.b_cnt_reg[0]\ : in STD_LOGIC;
    \m_vector_i[1092]_i_3\ : in STD_LOGIC;
    \skid_buffer_reg[1090]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \skid_buffer_reg[1057]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \skid_buffer_reg[1058]\ : in STD_LOGIC;
    \gen_endpoint.r_cnt_reg[0]\ : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_s01sic_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_s01sic_0 is
  signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1023 downto 0 );
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_AXILITE_CONV : integer;
  attribute C_AXILITE_CONV of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "1'b1";
  attribute C_HAS_BURST : integer;
  attribute C_HAS_BURST of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_IS_CASCADED : integer;
  attribute C_IS_CASCADED of inst : label is 0;
  attribute C_LIMIT_READ_LENGTH : integer;
  attribute C_LIMIT_READ_LENGTH of inst : label is 0;
  attribute C_LIMIT_WRITE_LENGTH : integer;
  attribute C_LIMIT_WRITE_LENGTH of inst : label is 0;
  attribute C_MAX_RUSER_BITS_PER_BYTE : integer;
  attribute C_MAX_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_MAX_WUSER_BITS_PER_BYTE : integer;
  attribute C_MAX_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_MEP_IDENTIFIER_WIDTH : integer;
  attribute C_MEP_IDENTIFIER_WIDTH of inst : label is 2;
  attribute C_MSC_RDATA_WIDTH_ARRAY : integer;
  attribute C_MSC_RDATA_WIDTH_ARRAY of inst : label is 128;
  attribute C_MSC_WDATA_WIDTH_ARRAY : integer;
  attribute C_MSC_WDATA_WIDTH_ARRAY of inst : label is 128;
  attribute C_NUM_MSC : integer;
  attribute C_NUM_MSC of inst : label is 1;
  attribute C_NUM_READ_OUTSTANDING : integer;
  attribute C_NUM_READ_OUTSTANDING of inst : label is 2;
  attribute C_NUM_READ_THREADS : integer;
  attribute C_NUM_READ_THREADS of inst : label is 1;
  attribute C_NUM_SEG : integer;
  attribute C_NUM_SEG of inst : label is 1;
  attribute C_NUM_WRITE_OUTSTANDING : integer;
  attribute C_NUM_WRITE_OUTSTANDING of inst : label is 2;
  attribute C_NUM_WRITE_THREADS : integer;
  attribute C_NUM_WRITE_THREADS of inst : label is 1;
  attribute C_RDATA_WIDTH : integer;
  attribute C_RDATA_WIDTH of inst : label is 32;
  attribute C_READ_ACCEPTANCE : integer;
  attribute C_READ_ACCEPTANCE of inst : label is 32;
  attribute C_READ_WATERMARK : integer;
  attribute C_READ_WATERMARK of inst : label is 0;
  attribute C_SEP_PROTOCOL_ARRAY : integer;
  attribute C_SEP_PROTOCOL_ARRAY of inst : label is 0;
  attribute C_SEP_RDATA_WIDTH_ARRAY : integer;
  attribute C_SEP_RDATA_WIDTH_ARRAY of inst : label is 128;
  attribute C_SEP_WDATA_WIDTH_ARRAY : integer;
  attribute C_SEP_WDATA_WIDTH_ARRAY of inst : label is 128;
  attribute C_SINGLE_ISSUING : integer;
  attribute C_SINGLE_ISSUING of inst : label is 0;
  attribute C_SUPPORTS_NARROW : integer;
  attribute C_SUPPORTS_NARROW of inst : label is 0;
  attribute C_S_RUSER_BITS_PER_BYTE : integer;
  attribute C_S_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_S_WUSER_BITS_PER_BYTE : integer;
  attribute C_S_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute C_WDATA_WIDTH : integer;
  attribute C_WDATA_WIDTH of inst : label is 32;
  attribute C_WRITE_ACCEPTANCE : integer;
  attribute C_WRITE_ACCEPTANCE of inst : label is 32;
  attribute C_WRITE_WATERMARK : integer;
  attribute C_WRITE_WATERMARK of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute P_EXOK : string;
  attribute P_EXOK of inst : label is "2'b01";
  attribute P_FULLY_PIPELINED : integer;
  attribute P_FULLY_PIPELINED of inst : label is 2;
  attribute P_ID_WIDTH : integer;
  attribute P_ID_WIDTH of inst : label is 2;
  attribute P_MAX_RUSER_BITS_PER_BYTE : integer;
  attribute P_MAX_RUSER_BITS_PER_BYTE of inst : label is 1;
  attribute P_MAX_WUSER_BITS_PER_BYTE : integer;
  attribute P_MAX_WUSER_BITS_PER_BYTE of inst : label is 1;
  attribute P_NUM_READ_OUTSTANDING : integer;
  attribute P_NUM_READ_OUTSTANDING of inst : label is 16;
  attribute P_NUM_WRITE_OUTSTANDING : integer;
  attribute P_NUM_WRITE_OUTSTANDING of inst : label is 16;
  attribute P_R_DWBYTES : integer;
  attribute P_R_DWBYTES of inst : label is 4;
  attribute P_R_DWSIZE : integer;
  attribute P_R_DWSIZE of inst : label is 2;
  attribute P_S_RUSER_BITS_PER_BYTE : integer;
  attribute P_S_RUSER_BITS_PER_BYTE of inst : label is 1;
  attribute P_S_WUSER_BITS_PER_BYTE : integer;
  attribute P_S_WUSER_BITS_PER_BYTE of inst : label is 1;
  attribute P_W_DWBYTES : integer;
  attribute P_W_DWBYTES of inst : label is 4;
  attribute P_W_DWSIZE : integer;
  attribute P_W_DWSIZE of inst : label is 2;
  attribute P_ZERO_LATENCY : integer;
  attribute P_ZERO_LATENCY of inst : label is 1;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_si_converter_v1_0_14_top__parameterized0\
     port map (
      aclk => aclk,
      aclken => '1',
      aresetn => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      m_axi_arid(1 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(1 downto 0),
      m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
      m_axi_arlock(0) => m_axi_arlock(0),
      m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      m_axi_arready => \m_vector_i[1092]_i_3\,
      m_axi_aruser(1023 downto 186) => NLW_inst_m_axi_aruser_UNCONNECTED(1023 downto 186),
      m_axi_aruser(185 downto 179) => m_axi_aruser(24 downto 18),
      m_axi_aruser(178 downto 147) => NLW_inst_m_axi_aruser_UNCONNECTED(178 downto 147),
      m_axi_aruser(146 downto 136) => m_axi_aruser(17 downto 7),
      m_axi_aruser(135 downto 71) => NLW_inst_m_axi_aruser_UNCONNECTED(135 downto 71),
      m_axi_aruser(70 downto 64) => m_axi_aruser(6 downto 0),
      m_axi_aruser(63 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(63 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
      m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
      m_axi_awid(1 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(1 downto 0),
      m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
      m_axi_awlock(0) => m_axi_awlock(0),
      m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
      m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
      m_axi_awready => \gen_pipelined.state_reg[0]_0\,
      m_axi_awuser(1023 downto 186) => NLW_inst_m_axi_awuser_UNCONNECTED(1023 downto 186),
      m_axi_awuser(185 downto 179) => m_axi_awuser(24 downto 18),
      m_axi_awuser(178 downto 147) => NLW_inst_m_axi_awuser_UNCONNECTED(178 downto 147),
      m_axi_awuser(146 downto 136) => m_axi_awuser(17 downto 7),
      m_axi_awuser(135 downto 71) => NLW_inst_m_axi_awuser_UNCONNECTED(135 downto 71),
      m_axi_awuser(70 downto 64) => m_axi_awuser(6 downto 0),
      m_axi_awuser(63 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(63 downto 0),
      m_axi_awvalid => m_axi_awvalid,
      m_axi_bid(1 downto 0) => B"00",
      m_axi_bready => m_axi_bready,
      m_axi_bresp(1 downto 0) => \skid_buffer_reg[1057]\(1 downto 0),
      m_axi_buser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_bvalid => \gen_endpoint.b_cnt_reg[0]\,
      m_axi_rdata(31 downto 0) => \skid_buffer_reg[1090]\(31 downto 0),
      m_axi_rid(1 downto 0) => B"00",
      m_axi_rlast => \skid_buffer_reg[1058]\,
      m_axi_rready => m_axi_rready,
      m_axi_rresp(1 downto 0) => \skid_buffer_reg[1057]_0\(1 downto 0),
      m_axi_ruser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axi_rvalid => \gen_endpoint.r_cnt_reg[0]\,
      m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
      m_axi_wlast => m_axi_wlast,
      m_axi_wready => \gen_pipelined.mesg_reg_reg[13]_0\,
      m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
      m_axi_wuser(1023 downto 78) => NLW_inst_m_axi_wuser_UNCONNECTED(1023 downto 78),
      m_axi_wuser(77 downto 64) => m_axi_wuser(13 downto 0),
      m_axi_wuser(63 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(63 downto 0),
      m_axi_wvalid => m_axi_wvalid,
      s_axi_araddr(31 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_4\(31 downto 0),
      s_axi_arburst(1 downto 0) => B"01",
      s_axi_arcache(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_6\(3 downto 0),
      s_axi_arid(1 downto 0) => B"10",
      s_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
      s_axi_arlock(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_5\(0),
      s_axi_arprot(2 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_7\(2 downto 0),
      s_axi_arqos(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_8\(3 downto 0),
      s_axi_arready => s_axi_arready,
      s_axi_arsize(2) => '0',
      s_axi_arsize(1 downto 0) => m_axi_arsize(1 downto 0),
      s_axi_aruser(1023 downto 147) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_aruser(146 downto 136) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]_0\(10 downto 0),
      s_axi_aruser(135 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_arvalid => \count_r_reg[5]\,
      s_axi_awaddr(31 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\(31 downto 0),
      s_axi_awburst(1 downto 0) => B"01",
      s_axi_awcache(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\(3 downto 0),
      s_axi_awid(1 downto 0) => B"10",
      s_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
      s_axi_awlock(0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\(0),
      s_axi_awprot(2 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\(2 downto 0),
      s_axi_awqos(3 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\(3 downto 0),
      s_axi_awready => s_axi_awready,
      s_axi_awsize(2) => '0',
      s_axi_awsize(1 downto 0) => m_axi_awsize(1 downto 0),
      s_axi_awuser(1023 downto 147) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awuser(146 downto 136) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\(10 downto 0),
      s_axi_awuser(135 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awvalid => \gen_pipelined.state_reg[0]\,
      s_axi_bid(1 downto 0) => NLW_inst_s_axi_bid_UNCONNECTED(1 downto 0),
      s_axi_bready => \count_r_reg[1]\,
      s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
      s_axi_buser(1023 downto 0) => NLW_inst_s_axi_buser_UNCONNECTED(1023 downto 0),
      s_axi_bvalid => s_axi_bvalid,
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rid(1 downto 0) => NLW_inst_s_axi_rid_UNCONNECTED(1 downto 0),
      s_axi_rlast => s_axi_rlast,
      s_axi_rready => \count_r_reg[5]_0\,
      s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      s_axi_ruser(1023 downto 0) => NLW_inst_s_axi_ruser_UNCONNECTED(1023 downto 0),
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(31 downto 0) => \gen_w_ch.accum_reg[bytes][11][userdata][7]\(31 downto 0),
      s_axi_wlast => \gen_pipe[1].pipe_reg[1][0]\,
      s_axi_wready => s_axi_wready,
      s_axi_wstrb(3 downto 0) => \gen_w_ch.accum_reg[bytes][3][strb]\(3 downto 0),
      s_axi_wuser(1023 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wvalid => \gen_pipelined.mesg_reg_reg[13]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_clk_map_imp_USF1QV is
  port (
    interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_clk_map_imp_USF1QV;

architecture STRUCTURE of Loopback_smartconnect_0_0_clk_map_imp_USF1QV is
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of psr_aclk : label is "proc_sys_reset,Vivado 2024.2";
begin
psr_aclk: entity work.Loopback_smartconnect_0_0_bd_e34c_psr_aclk_0
     port map (
      aclk => aclk,
      aresetn => aresetn,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
end STRUCTURE;
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_m00_exit_pipeline_imp_15PRL8S is
  port (
    s_axi_awready : out STD_LOGIC;
    s_axi_wready : out STD_LOGIC;
    s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_buser : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC;
    s_axi_arready : out STD_LOGIC;
    s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : out STD_LOGIC;
    s_axi_ruser : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_axi_rvalid : out STD_LOGIC;
    M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awvalid : out STD_LOGIC;
    M00_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
    M00_AXI_wlast : out STD_LOGIC;
    M00_AXI_wvalid : out STD_LOGIC;
    M00_AXI_bready : out STD_LOGIC;
    M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arvalid : out STD_LOGIC;
    M00_AXI_rready : out STD_LOGIC;
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awuser : in STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axi_awvalid : in STD_LOGIC;
    m_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    m_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
    m_axi_wlast : in STD_LOGIC;
    m_axi_wvalid : in STD_LOGIC;
    m_axi_bready : in STD_LOGIC;
    m_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    m_axi_arvalid : in STD_LOGIC;
    m_axi_rready : in STD_LOGIC;
    M00_AXI_awready : in STD_LOGIC;
    M00_AXI_wready : in STD_LOGIC;
    M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_bvalid : in STD_LOGIC;
    M00_AXI_arready : in STD_LOGIC;
    M00_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_rlast : in STD_LOGIC;
    M00_AXI_rvalid : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_m00_exit_pipeline_imp_15PRL8S;

architecture STRUCTURE of Loopback_smartconnect_0_0_m00_exit_pipeline_imp_15PRL8S is
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of m00_exit : label is "sc_exit_v1_0_16_top,Vivado 2024.2";
begin
m00_exit: entity work.Loopback_smartconnect_0_0_bd_e34c_m00e_0
     port map (
      M00_AXI_araddr(31 downto 0) => M00_AXI_araddr(31 downto 0),
      M00_AXI_arcache(3 downto 0) => M00_AXI_arcache(3 downto 0),
      M00_AXI_arlen(7 downto 0) => M00_AXI_arlen(7 downto 0),
      M00_AXI_arprot(2 downto 0) => M00_AXI_arprot(2 downto 0),
      M00_AXI_arqos(3 downto 0) => M00_AXI_arqos(3 downto 0),
      M00_AXI_arready => M00_AXI_arready,
      M00_AXI_arsize(2 downto 0) => M00_AXI_arsize(2 downto 0),
      M00_AXI_arvalid => M00_AXI_arvalid,
      M00_AXI_awaddr(31 downto 0) => M00_AXI_awaddr(31 downto 0),
      M00_AXI_awcache(3 downto 0) => M00_AXI_awcache(3 downto 0),
      M00_AXI_awlen(7 downto 0) => M00_AXI_awlen(7 downto 0),
      M00_AXI_awprot(2 downto 0) => M00_AXI_awprot(2 downto 0),
      M00_AXI_awqos(3 downto 0) => M00_AXI_awqos(3 downto 0),
      M00_AXI_awready => M00_AXI_awready,
      M00_AXI_awsize(2 downto 0) => M00_AXI_awsize(2 downto 0),
      M00_AXI_awvalid => M00_AXI_awvalid,
      M00_AXI_bready => M00_AXI_bready,
      M00_AXI_bresp(1 downto 0) => M00_AXI_bresp(1 downto 0),
      M00_AXI_bvalid => M00_AXI_bvalid,
      M00_AXI_rdata(127 downto 0) => M00_AXI_rdata(127 downto 0),
      M00_AXI_rlast => M00_AXI_rlast,
      M00_AXI_rready => M00_AXI_rready,
      M00_AXI_rresp(1 downto 0) => M00_AXI_rresp(1 downto 0),
      M00_AXI_rvalid => M00_AXI_rvalid,
      M00_AXI_wdata(127 downto 0) => M00_AXI_wdata(127 downto 0),
      M00_AXI_wlast => M00_AXI_wlast,
      M00_AXI_wready => M00_AXI_wready,
      M00_AXI_wstrb(15 downto 0) => M00_AXI_wstrb(15 downto 0),
      M00_AXI_wvalid => M00_AXI_wvalid,
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      m_axi_arid(1 downto 0) => m_axi_arid(1 downto 0),
      m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
      m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      m_axi_aruser(17 downto 0) => m_axi_aruser(17 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
      m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
      m_axi_awid(1 downto 0) => m_axi_awid(1 downto 0),
      m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
      m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
      m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
      m_axi_awuser(10 downto 0) => m_axi_awuser(10 downto 0),
      m_axi_awvalid => m_axi_awvalid,
      m_axi_bready => m_axi_bready,
      m_axi_rready => m_axi_rready,
      m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
      m_axi_wlast => m_axi_wlast,
      m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
      m_axi_wvalid => m_axi_wvalid,
      s_axi_arready => s_axi_arready,
      s_axi_awready => s_axi_awready,
      s_axi_bid(1 downto 0) => s_axi_bid(1 downto 0),
      s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
      s_axi_buser(1 downto 0) => s_axi_buser(1 downto 0),
      s_axi_bvalid => s_axi_bvalid,
      s_axi_rdata(127 downto 0) => s_axi_rdata(127 downto 0),
      s_axi_rid(1 downto 0) => s_axi_rid(1 downto 0),
      s_axi_rlast => s_axi_rlast,
      s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
      s_axi_ruser(15 downto 0) => s_axi_ruser(15 downto 0),
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wready => s_axi_wready
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_s01_entry_pipeline_imp_13EI3DN is
  port (
    S01_AXI_awready : out STD_LOGIC;
    S01_AXI_wready : out STD_LOGIC;
    S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_bvalid : out STD_LOGIC;
    S01_AXI_arready : out STD_LOGIC;
    S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_rlast : out STD_LOGIC;
    S01_AXI_rvalid : out STD_LOGIC;
    m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awuser : out STD_LOGIC_VECTOR ( 24 downto 0 );
    m_axi_awvalid : out STD_LOGIC;
    m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_wlast : out STD_LOGIC;
    m_axi_wuser : out STD_LOGIC_VECTOR ( 13 downto 0 );
    m_axi_wvalid : out STD_LOGIC;
    m_axi_bready : out STD_LOGIC;
    m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_aruser : out STD_LOGIC_VECTOR ( 24 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_rready : out STD_LOGIC;
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awvalid : in STD_LOGIC;
    S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_wlast : in STD_LOGIC;
    S01_AXI_wvalid : in STD_LOGIC;
    S01_AXI_bready : in STD_LOGIC;
    S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arvalid : in STD_LOGIC;
    S01_AXI_rready : in STD_LOGIC;
    s_axi_awready : in STD_LOGIC;
    s_axi_wready : in STD_LOGIC;
    s_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : in STD_LOGIC;
    s_axi_arready : in STD_LOGIC;
    s_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rlast : in STD_LOGIC;
    s_axi_rvalid : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_s01_entry_pipeline_imp_13EI3DN;

architecture STRUCTURE of Loopback_smartconnect_0_0_s01_entry_pipeline_imp_13EI3DN is
  signal s01_mmu_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_mmu_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_mmu_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal s01_mmu_M_AXI_ARLOCK : STD_LOGIC;
  signal s01_mmu_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal s01_mmu_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_mmu_M_AXI_ARREADY : STD_LOGIC;
  signal s01_mmu_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s01_mmu_M_AXI_ARUSER : STD_LOGIC_VECTOR ( 146 downto 136 );
  signal s01_mmu_M_AXI_ARVALID : STD_LOGIC;
  signal s01_mmu_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_mmu_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_mmu_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal s01_mmu_M_AXI_AWLOCK : STD_LOGIC;
  signal s01_mmu_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal s01_mmu_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_mmu_M_AXI_AWREADY : STD_LOGIC;
  signal s01_mmu_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s01_mmu_M_AXI_AWUSER : STD_LOGIC_VECTOR ( 146 downto 136 );
  signal s01_mmu_M_AXI_AWVALID : STD_LOGIC;
  signal s01_mmu_M_AXI_BREADY : STD_LOGIC;
  signal s01_mmu_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s01_mmu_M_AXI_BVALID : STD_LOGIC;
  signal s01_mmu_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_mmu_M_AXI_RLAST : STD_LOGIC;
  signal s01_mmu_M_AXI_RREADY : STD_LOGIC;
  signal s01_mmu_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s01_mmu_M_AXI_RVALID : STD_LOGIC;
  signal s01_mmu_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_mmu_M_AXI_WLAST : STD_LOGIC;
  signal s01_mmu_M_AXI_WREADY : STD_LOGIC;
  signal s01_mmu_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_mmu_M_AXI_WVALID : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_transaction_regulator_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_transaction_regulator_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal s01_transaction_regulator_M_AXI_ARLOCK : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal s01_transaction_regulator_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_transaction_regulator_M_AXI_ARREADY : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s01_transaction_regulator_M_AXI_ARUSER : STD_LOGIC_VECTOR ( 146 downto 136 );
  signal s01_transaction_regulator_M_AXI_ARVALID : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_transaction_regulator_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_transaction_regulator_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal s01_transaction_regulator_M_AXI_AWLOCK : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal s01_transaction_regulator_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_transaction_regulator_M_AXI_AWREADY : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s01_transaction_regulator_M_AXI_AWUSER : STD_LOGIC_VECTOR ( 146 downto 136 );
  signal s01_transaction_regulator_M_AXI_AWVALID : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_BREADY : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s01_transaction_regulator_M_AXI_BVALID : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_transaction_regulator_M_AXI_RLAST : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_RREADY : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s01_transaction_regulator_M_AXI_RVALID : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_transaction_regulator_M_AXI_WLAST : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_WREADY : STD_LOGIC;
  signal s01_transaction_regulator_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_transaction_regulator_M_AXI_WVALID : STD_LOGIC;
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of s01_mmu : label is "sc_mmu_v1_0_14_top,Vivado 2024.2";
  attribute X_CORE_INFO of s01_si_converter : label is "sc_si_converter_v1_0_14_top,Vivado 2024.2";
  attribute X_CORE_INFO of s01_transaction_regulator : label is "sc_transaction_regulator_v1_0_11_top,Vivado 2024.2";
begin
s01_mmu: entity work.Loopback_smartconnect_0_0_bd_e34c_s01mmu_0
     port map (
      S01_AXI_araddr(31 downto 0) => S01_AXI_araddr(31 downto 0),
      S01_AXI_arburst(1 downto 0) => S01_AXI_arburst(1 downto 0),
      S01_AXI_arcache(3 downto 0) => S01_AXI_arcache(3 downto 0),
      S01_AXI_arlen(7 downto 0) => S01_AXI_arlen(7 downto 0),
      S01_AXI_arlock(0) => S01_AXI_arlock(0),
      S01_AXI_arprot(2 downto 0) => S01_AXI_arprot(2 downto 0),
      S01_AXI_arqos(3 downto 0) => S01_AXI_arqos(3 downto 0),
      S01_AXI_arready => S01_AXI_arready,
      S01_AXI_arsize(2 downto 0) => S01_AXI_arsize(2 downto 0),
      S01_AXI_arvalid => S01_AXI_arvalid,
      S01_AXI_awaddr(31 downto 0) => S01_AXI_awaddr(31 downto 0),
      S01_AXI_awburst(1 downto 0) => S01_AXI_awburst(1 downto 0),
      S01_AXI_awcache(3 downto 0) => S01_AXI_awcache(3 downto 0),
      S01_AXI_awlen(7 downto 0) => S01_AXI_awlen(7 downto 0),
      S01_AXI_awlock(0) => S01_AXI_awlock(0),
      S01_AXI_awprot(2 downto 0) => S01_AXI_awprot(2 downto 0),
      S01_AXI_awqos(3 downto 0) => S01_AXI_awqos(3 downto 0),
      S01_AXI_awready => S01_AXI_awready,
      S01_AXI_awsize(2 downto 0) => S01_AXI_awsize(2 downto 0),
      S01_AXI_awvalid => S01_AXI_awvalid,
      S01_AXI_bready => S01_AXI_bready,
      S01_AXI_bresp(1 downto 0) => S01_AXI_bresp(1 downto 0),
      S01_AXI_bvalid => S01_AXI_bvalid,
      S01_AXI_rdata(31 downto 0) => S01_AXI_rdata(31 downto 0),
      S01_AXI_rlast => S01_AXI_rlast,
      S01_AXI_rready => S01_AXI_rready,
      S01_AXI_rresp(1 downto 0) => S01_AXI_rresp(1 downto 0),
      S01_AXI_rvalid => S01_AXI_rvalid,
      S01_AXI_wdata(31 downto 0) => S01_AXI_wdata(31 downto 0),
      S01_AXI_wlast => S01_AXI_wlast,
      S01_AXI_wready => S01_AXI_wready,
      S01_AXI_wstrb(3 downto 0) => S01_AXI_wstrb(3 downto 0),
      S01_AXI_wvalid => S01_AXI_wvalid,
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => s01_mmu_M_AXI_ARADDR(31 downto 0),
      m_axi_arcache(3 downto 0) => s01_mmu_M_AXI_ARCACHE(3 downto 0),
      m_axi_arlen(7 downto 0) => s01_mmu_M_AXI_ARLEN(7 downto 0),
      m_axi_arlock(0) => s01_mmu_M_AXI_ARLOCK,
      m_axi_arprot(2 downto 0) => s01_mmu_M_AXI_ARPROT(2 downto 0),
      m_axi_arqos(3 downto 0) => s01_mmu_M_AXI_ARQOS(3 downto 0),
      m_axi_arsize(1 downto 0) => s01_mmu_M_AXI_ARSIZE(1 downto 0),
      m_axi_aruser(10 downto 0) => s01_mmu_M_AXI_ARUSER(146 downto 136),
      m_axi_arvalid => s01_mmu_M_AXI_ARVALID,
      m_axi_awaddr(31 downto 0) => s01_mmu_M_AXI_AWADDR(31 downto 0),
      m_axi_awcache(3 downto 0) => s01_mmu_M_AXI_AWCACHE(3 downto 0),
      m_axi_awlen(7 downto 0) => s01_mmu_M_AXI_AWLEN(7 downto 0),
      m_axi_awlock(0) => s01_mmu_M_AXI_AWLOCK,
      m_axi_awprot(2 downto 0) => s01_mmu_M_AXI_AWPROT(2 downto 0),
      m_axi_awqos(3 downto 0) => s01_mmu_M_AXI_AWQOS(3 downto 0),
      m_axi_awsize(1 downto 0) => s01_mmu_M_AXI_AWSIZE(1 downto 0),
      m_axi_awuser(10 downto 0) => s01_mmu_M_AXI_AWUSER(146 downto 136),
      m_axi_awvalid => s01_mmu_M_AXI_AWVALID,
      m_axi_bready => s01_mmu_M_AXI_BREADY,
      m_axi_rready => s01_mmu_M_AXI_RREADY,
      m_axi_wdata(31 downto 0) => s01_mmu_M_AXI_WDATA(31 downto 0),
      m_axi_wlast => s01_mmu_M_AXI_WLAST,
      m_axi_wstrb(3 downto 0) => s01_mmu_M_AXI_WSTRB(3 downto 0),
      m_axi_wvalid => s01_mmu_M_AXI_WVALID,
      s_axi_arready => s01_mmu_M_AXI_ARREADY,
      s_axi_awready => s01_mmu_M_AXI_AWREADY,
      s_axi_bresp(1 downto 0) => s01_mmu_M_AXI_BRESP(1 downto 0),
      s_axi_bvalid => s01_mmu_M_AXI_BVALID,
      s_axi_rdata(31 downto 0) => s01_mmu_M_AXI_RDATA(31 downto 0),
      s_axi_rlast => s01_mmu_M_AXI_RLAST,
      s_axi_rresp(1 downto 0) => s01_mmu_M_AXI_RRESP(1 downto 0),
      s_axi_rvalid => s01_mmu_M_AXI_RVALID,
      s_axi_wready => s01_mmu_M_AXI_WREADY
    );
s01_si_converter: entity work.Loopback_smartconnect_0_0_bd_e34c_s01sic_0
     port map (
      aclk => aclk,
      \count_r_reg[1]\ => s01_transaction_regulator_M_AXI_BREADY,
      \count_r_reg[5]\ => s01_transaction_regulator_M_AXI_ARVALID,
      \count_r_reg[5]_0\ => s01_transaction_regulator_M_AXI_RREADY,
      \gen_endpoint.b_cnt_reg[0]\ => s_axi_bvalid,
      \gen_endpoint.r_cnt_reg[0]\ => s_axi_rvalid,
      \gen_pipe[1].pipe_reg[1][0]\ => s01_transaction_regulator_M_AXI_WLAST,
      \gen_pipelined.mesg_reg_reg[13]\ => s01_transaction_regulator_M_AXI_WVALID,
      \gen_pipelined.mesg_reg_reg[13]_0\ => s_axi_wready,
      \gen_pipelined.state_reg[0]\ => s01_transaction_regulator_M_AXI_AWVALID,
      \gen_pipelined.state_reg[0]_0\ => s_axi_awready,
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\(31 downto 0) => s01_transaction_regulator_M_AXI_AWADDR(31 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\(0) => s01_transaction_regulator_M_AXI_AWLOCK,
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\(3 downto 0) => s01_transaction_regulator_M_AXI_AWCACHE(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\(2 downto 0) => s01_transaction_regulator_M_AXI_AWPROT(2 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\(3 downto 0) => s01_transaction_regulator_M_AXI_AWQOS(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_4\(31 downto 0) => s01_transaction_regulator_M_AXI_ARADDR(31 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_5\(0) => s01_transaction_regulator_M_AXI_ARLOCK,
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_6\(3 downto 0) => s01_transaction_regulator_M_AXI_ARCACHE(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_7\(2 downto 0) => s01_transaction_regulator_M_AXI_ARPROT(2 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_8\(3 downto 0) => s01_transaction_regulator_M_AXI_ARQOS(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\(10 downto 0) => s01_transaction_regulator_M_AXI_AWUSER(146 downto 136),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]_0\(10 downto 0) => s01_transaction_regulator_M_AXI_ARUSER(146 downto 136),
      \gen_w_ch.accum_reg[bytes][11][userdata][7]\(31 downto 0) => s01_transaction_regulator_M_AXI_WDATA(31 downto 0),
      \gen_w_ch.accum_reg[bytes][3][strb]\(3 downto 0) => s01_transaction_regulator_M_AXI_WSTRB(3 downto 0),
      interconnect_aresetn(0) => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
      m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      m_axi_arlen(7 downto 0) => s01_transaction_regulator_M_AXI_ARLEN(7 downto 0),
      m_axi_arlock(0) => m_axi_arlock(0),
      m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
      m_axi_arsize(1 downto 0) => s01_transaction_regulator_M_AXI_ARSIZE(1 downto 0),
      m_axi_aruser(24 downto 0) => m_axi_aruser(24 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
      m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
      m_axi_awlen(7 downto 0) => s01_transaction_regulator_M_AXI_AWLEN(7 downto 0),
      m_axi_awlock(0) => m_axi_awlock(0),
      m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
      m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
      m_axi_awsize(1 downto 0) => s01_transaction_regulator_M_AXI_AWSIZE(1 downto 0),
      m_axi_awuser(24 downto 0) => m_axi_awuser(24 downto 0),
      m_axi_awvalid => m_axi_awvalid,
      m_axi_bready => m_axi_bready,
      m_axi_rready => m_axi_rready,
      m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
      m_axi_wlast => m_axi_wlast,
      m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
      m_axi_wuser(13 downto 0) => m_axi_wuser(13 downto 0),
      m_axi_wvalid => m_axi_wvalid,
      \m_vector_i[1092]_i_3\ => s_axi_arready,
      s_axi_arready => s01_transaction_regulator_M_AXI_ARREADY,
      s_axi_awready => s01_transaction_regulator_M_AXI_AWREADY,
      s_axi_bresp(1 downto 0) => s01_transaction_regulator_M_AXI_BRESP(1 downto 0),
      s_axi_bvalid => s01_transaction_regulator_M_AXI_BVALID,
      s_axi_rdata(31 downto 0) => s01_transaction_regulator_M_AXI_RDATA(31 downto 0),
      s_axi_rlast => s01_transaction_regulator_M_AXI_RLAST,
      s_axi_rresp(1 downto 0) => s01_transaction_regulator_M_AXI_RRESP(1 downto 0),
      s_axi_rvalid => s01_transaction_regulator_M_AXI_RVALID,
      s_axi_wready => s01_transaction_regulator_M_AXI_WREADY,
      \skid_buffer_reg[1057]\(1 downto 0) => s_axi_bresp(1 downto 0),
      \skid_buffer_reg[1057]_0\(1 downto 0) => s_axi_rresp(1 downto 0),
      \skid_buffer_reg[1058]\ => s_axi_rlast,
      \skid_buffer_reg[1090]\(31 downto 0) => s_axi_rdata(31 downto 0)
    );
s01_transaction_regulator: entity work.Loopback_smartconnect_0_0_bd_e34c_s01tr_0
     port map (
      aclk => aclk,
      \count_r_reg[1]\ => s01_mmu_M_AXI_BREADY,
      \count_r_reg[5]\ => s01_mmu_M_AXI_ARVALID,
      \count_r_reg[5]_0\ => s01_mmu_M_AXI_RREADY,
      \gen_endpoint.b_cnt_reg[0]\ => s01_transaction_regulator_M_AXI_BVALID,
      \gen_endpoint.r_cnt_reg[0]\ => s01_transaction_regulator_M_AXI_RVALID,
      \gen_endpoint.w_enable_reg\ => s01_transaction_regulator_M_AXI_WREADY,
      \gen_pipe[1].pipe_reg[1][0]\ => s01_mmu_M_AXI_WLAST,
      \gen_pipelined.mesg_reg_reg[0]\(1 downto 0) => s01_mmu_M_AXI_AWSIZE(1 downto 0),
      \gen_pipelined.mesg_reg_reg[13]\ => s01_mmu_M_AXI_WVALID,
      \gen_pipelined.state_reg[0]\ => s01_mmu_M_AXI_AWVALID,
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]\(31 downto 0) => s01_mmu_M_AXI_AWADDR(31 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_0\(0) => s01_mmu_M_AXI_AWLOCK,
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_1\(3 downto 0) => s01_mmu_M_AXI_AWCACHE(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_2\(2 downto 0) => s01_mmu_M_AXI_AWPROT(2 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_3\(3 downto 0) => s01_mmu_M_AXI_AWQOS(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_4\(31 downto 0) => s01_mmu_M_AXI_ARADDR(31 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_5\(0) => s01_mmu_M_AXI_ARLOCK,
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_6\(3 downto 0) => s01_mmu_M_AXI_ARCACHE(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_7\(2 downto 0) => s01_mmu_M_AXI_ARPROT(2 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[127]_8\(3 downto 0) => s01_mmu_M_AXI_ARQOS(3 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\(7 downto 0) => s01_mmu_M_AXI_AWLEN(7 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]_0\(7 downto 0) => s01_mmu_M_AXI_ARLEN(7 downto 0),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]\(10 downto 0) => s01_mmu_M_AXI_AWUSER(146 downto 136),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[71]_0\(10 downto 0) => s01_mmu_M_AXI_ARUSER(146 downto 136),
      \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[85]\(1 downto 0) => s01_mmu_M_AXI_ARSIZE(1 downto 0),
      \gen_w_ch.accum_reg[bytes][11][userdata][7]\(31 downto 0) => s01_mmu_M_AXI_WDATA(31 downto 0),
      \gen_w_ch.accum_reg[bytes][3][strb]\(3 downto 0) => s01_mmu_M_AXI_WSTRB(3 downto 0),
      interconnect_aresetn(0) => interconnect_aresetn(0),
      m_axi_araddr(31 downto 0) => s01_transaction_regulator_M_AXI_ARADDR(31 downto 0),
      m_axi_arcache(3 downto 0) => s01_transaction_regulator_M_AXI_ARCACHE(3 downto 0),
      m_axi_arlen(7 downto 0) => s01_transaction_regulator_M_AXI_ARLEN(7 downto 0),
      m_axi_arlock(0) => s01_transaction_regulator_M_AXI_ARLOCK,
      m_axi_arprot(2 downto 0) => s01_transaction_regulator_M_AXI_ARPROT(2 downto 0),
      m_axi_arqos(3 downto 0) => s01_transaction_regulator_M_AXI_ARQOS(3 downto 0),
      m_axi_arsize(1 downto 0) => s01_transaction_regulator_M_AXI_ARSIZE(1 downto 0),
      m_axi_aruser(10 downto 0) => s01_transaction_regulator_M_AXI_ARUSER(146 downto 136),
      m_axi_arvalid => s01_transaction_regulator_M_AXI_ARVALID,
      m_axi_awaddr(31 downto 0) => s01_transaction_regulator_M_AXI_AWADDR(31 downto 0),
      m_axi_awcache(3 downto 0) => s01_transaction_regulator_M_AXI_AWCACHE(3 downto 0),
      m_axi_awlen(7 downto 0) => s01_transaction_regulator_M_AXI_AWLEN(7 downto 0),
      m_axi_awlock(0) => s01_transaction_regulator_M_AXI_AWLOCK,
      m_axi_awprot(2 downto 0) => s01_transaction_regulator_M_AXI_AWPROT(2 downto 0),
      m_axi_awqos(3 downto 0) => s01_transaction_regulator_M_AXI_AWQOS(3 downto 0),
      m_axi_awsize(1 downto 0) => s01_transaction_regulator_M_AXI_AWSIZE(1 downto 0),
      m_axi_awuser(10 downto 0) => s01_transaction_regulator_M_AXI_AWUSER(146 downto 136),
      m_axi_awvalid => s01_transaction_regulator_M_AXI_AWVALID,
      m_axi_bready => s01_transaction_regulator_M_AXI_BREADY,
      m_axi_rready => s01_transaction_regulator_M_AXI_RREADY,
      m_axi_wdata(31 downto 0) => s01_transaction_regulator_M_AXI_WDATA(31 downto 0),
      m_axi_wlast => s01_transaction_regulator_M_AXI_WLAST,
      m_axi_wstrb(3 downto 0) => s01_transaction_regulator_M_AXI_WSTRB(3 downto 0),
      m_axi_wvalid => s01_transaction_regulator_M_AXI_WVALID,
      \m_vector_i_reg[138]\ => s01_transaction_regulator_M_AXI_AWREADY,
      s_axi_arready => s01_mmu_M_AXI_ARREADY,
      s_axi_awready => s01_mmu_M_AXI_AWREADY,
      s_axi_bresp(1 downto 0) => s01_mmu_M_AXI_BRESP(1 downto 0),
      s_axi_bvalid => s01_mmu_M_AXI_BVALID,
      s_axi_rdata(31 downto 0) => s01_mmu_M_AXI_RDATA(31 downto 0),
      s_axi_rlast => s01_mmu_M_AXI_RLAST,
      s_axi_rresp(1 downto 0) => s01_mmu_M_AXI_RRESP(1 downto 0),
      s_axi_rvalid => s01_mmu_M_AXI_RVALID,
      s_axi_wready => s01_mmu_M_AXI_WREADY,
      \skid_buffer_reg[1057]\(1 downto 0) => s01_transaction_regulator_M_AXI_BRESP(1 downto 0),
      \skid_buffer_reg[1057]_0\(1 downto 0) => s01_transaction_regulator_M_AXI_RRESP(1 downto 0),
      \skid_buffer_reg[1058]\ => s01_transaction_regulator_M_AXI_RLAST,
      \skid_buffer_reg[1090]\(31 downto 0) => s01_transaction_regulator_M_AXI_RDATA(31 downto 0),
      \state_reg[s_ready_i]\ => s01_transaction_regulator_M_AXI_ARREADY
    );
end STRUCTURE;
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`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 243280)
`protect data_block
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_m00arn_0 is
  port (
    S_SC_AR_recv : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_SC_AR_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_payld : out STD_LOGIC_VECTOR ( 70 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AR_req : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_SC_AR_send : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_SC_AR_payld : in STD_LOGIC_VECTOR ( 82 downto 0 );
    M_SC_AR_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_m00arn_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_m00arn_0 is
  signal NLW_inst_m_axis_arb_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_arb_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 128 downto 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 2;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 0;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 16;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 2;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 140;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "2'b00";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 1;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 1;
  attribute C_S_NUM_BYTES_ARRAY : string;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is "64'b0000000000000000000000000001000000000000000000000000000000010000";
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 1;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 7;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 1;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 0;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 1;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 4;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 0;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 0;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 0;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.Loopback_smartconnect_0_0_sc_node_v1_0_17_top
     port map (
      m_axis_arb_tdata(15 downto 0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 0),
      m_axis_arb_tready => '1',
      m_axis_arb_tvalid => NLW_inst_m_axis_arb_tvalid_UNCONNECTED,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(0) => NLW_inst_m_sc_info_UNCONNECTED(0),
      m_sc_payld(139 downto 129) => M_SC_AR_payld(70 downto 60),
      m_sc_payld(128) => NLW_inst_m_sc_payld_UNCONNECTED(128),
      m_sc_payld(127 downto 94) => M_SC_AR_payld(59 downto 26),
      m_sc_payld(93) => NLW_inst_m_sc_payld_UNCONNECTED(93),
      m_sc_payld(92 downto 86) => M_SC_AR_payld(25 downto 19),
      m_sc_payld(85 downto 84) => NLW_inst_m_sc_payld_UNCONNECTED(85 downto 84),
      m_sc_payld(83 downto 73) => M_SC_AR_payld(18 downto 8),
      m_sc_payld(72 downto 9) => NLW_inst_m_sc_payld_UNCONNECTED(72 downto 9),
      m_sc_payld(8 downto 1) => M_SC_AR_payld(7 downto 0),
      m_sc_payld(0) => NLW_inst_m_sc_payld_UNCONNECTED(0),
      m_sc_recv(0) => M_SC_AR_recv(0),
      m_sc_req(0) => NLW_inst_m_sc_req_UNCONNECTED(0),
      m_sc_send(0) => M_SC_AR_send(0),
      s_axis_arb_tdata(15 downto 0) => B"0000000000000000",
      s_axis_arb_tready => NLW_inst_s_axis_arb_tready_UNCONNECTED,
      s_axis_arb_tvalid => '0',
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(1 downto 0) => B"00",
      s_sc_payld(139 downto 70) => M00_SC_AR_payld(82 downto 13),
      s_sc_payld(69 downto 14) => B"00000000000000000000000000000000000000000000000000000000",
      s_sc_payld(13 downto 1) => M00_SC_AR_payld(12 downto 0),
      s_sc_payld(0) => '0',
      s_sc_recv(1 downto 0) => S_SC_AR_recv(1 downto 0),
      s_sc_req(1 downto 0) => M00_SC_AR_req(1 downto 0),
      s_sc_send(1 downto 0) => M00_SC_AR_send(1 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_m00awn_0 is
  port (
    S_SC_AW_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AW_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AW_payld : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_arb_tvalid : out STD_LOGIC;
    m_axis_arb_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_req : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_payld : in STD_LOGIC_VECTOR ( 82 downto 0 );
    M_SC_AW_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_arb_tready : in STD_LOGIC
  );
end Loopback_smartconnect_0_0_bd_e34c_m00awn_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_m00awn_0 is
  signal NLW_inst_s_axis_arb_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 128 downto 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_sc_recv_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 3;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 0;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 2;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 2;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 140;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "2'b00";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 1;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 1;
  attribute C_S_NUM_BYTES_ARRAY : string;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is "64'b0000000000000000000000000001000000000000000000000000000000010000";
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 1;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 7;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 1;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 0;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 1;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 1;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 0;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 0;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 0;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_node_v1_0_17_top__parameterized0\
     port map (
      m_axis_arb_tdata(15 downto 2) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 2),
      m_axis_arb_tdata(1) => m_axis_arb_tdata(0),
      m_axis_arb_tdata(0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(0),
      m_axis_arb_tready => s_axis_arb_tready,
      m_axis_arb_tvalid => m_axis_arb_tvalid,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(0) => NLW_inst_m_sc_info_UNCONNECTED(0),
      m_sc_payld(139 downto 129) => M_SC_AW_payld(63 downto 53),
      m_sc_payld(128) => NLW_inst_m_sc_payld_UNCONNECTED(128),
      m_sc_payld(127 downto 94) => M_SC_AW_payld(52 downto 19),
      m_sc_payld(93 downto 84) => NLW_inst_m_sc_payld_UNCONNECTED(93 downto 84),
      m_sc_payld(83 downto 73) => M_SC_AW_payld(18 downto 8),
      m_sc_payld(72 downto 9) => NLW_inst_m_sc_payld_UNCONNECTED(72 downto 9),
      m_sc_payld(8 downto 1) => M_SC_AW_payld(7 downto 0),
      m_sc_payld(0) => NLW_inst_m_sc_payld_UNCONNECTED(0),
      m_sc_recv(0) => M_SC_AW_recv(0),
      m_sc_req(0) => NLW_inst_m_sc_req_UNCONNECTED(0),
      m_sc_send(0) => M_SC_AW_send(0),
      s_axis_arb_tdata(15 downto 0) => B"0000000000000000",
      s_axis_arb_tready => NLW_inst_s_axis_arb_tready_UNCONNECTED,
      s_axis_arb_tvalid => '0',
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(1 downto 0) => B"00",
      s_sc_payld(139 downto 70) => M00_SC_AW_payld(82 downto 13),
      s_sc_payld(69 downto 14) => B"00000000000000000000000000000000000000000000000000000000",
      s_sc_payld(13 downto 1) => M00_SC_AW_payld(12 downto 0),
      s_sc_payld(0) => '0',
      s_sc_recv(1) => S_SC_AW_recv(0),
      s_sc_recv(0) => NLW_inst_s_sc_recv_UNCONNECTED(0),
      s_sc_req(1) => M00_SC_AW_req(0),
      s_sc_req(0) => '0',
      s_sc_send(1) => M00_SC_AW_send(0),
      s_sc_send(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_m00bn_0 is
  port (
    S_SC_B_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_B_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_B_payld : out STD_LOGIC_VECTOR ( 5 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_B_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_B_payld : in STD_LOGIC_VECTOR ( 5 downto 0 );
    S00_SC_B_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_m00bn_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_m00bn_0 is
  signal NLW_inst_m_axis_arb_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_arb_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_sc_send_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 4;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 1;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 2;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 2;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 1;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 7;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "1'b0";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 2;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 0;
  attribute C_S_NUM_BYTES_ARRAY : integer;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 1;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 7;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 2;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 0;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 1;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 1;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 0;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 0;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 0;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_node_v1_0_17_top__parameterized1\
     port map (
      m_axis_arb_tdata(15 downto 0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 0),
      m_axis_arb_tready => '1',
      m_axis_arb_tvalid => NLW_inst_m_axis_arb_tvalid_UNCONNECTED,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(1 downto 0) => NLW_inst_m_sc_info_UNCONNECTED(1 downto 0),
      m_sc_payld(6 downto 1) => M_SC_B_payld(5 downto 0),
      m_sc_payld(0) => NLW_inst_m_sc_payld_UNCONNECTED(0),
      m_sc_recv(1) => S00_SC_B_recv(0),
      m_sc_recv(0) => '0',
      m_sc_req(1 downto 0) => NLW_inst_m_sc_req_UNCONNECTED(1 downto 0),
      m_sc_send(1) => M_SC_B_send(0),
      m_sc_send(0) => NLW_inst_m_sc_send_UNCONNECTED(0),
      s_axis_arb_tdata(15 downto 0) => B"0000000000000000",
      s_axis_arb_tready => NLW_inst_s_axis_arb_tready_UNCONNECTED,
      s_axis_arb_tvalid => '0',
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(0) => '0',
      s_sc_payld(6 downto 3) => S_SC_B_payld(5 downto 2),
      s_sc_payld(2) => '0',
      s_sc_payld(1 downto 0) => S_SC_B_payld(1 downto 0),
      s_sc_recv(0) => S_SC_B_recv(0),
      s_sc_req(0) => '0',
      s_sc_send(0) => S_SC_B_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_m00rn_0 is
  port (
    S_SC_R_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_send : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_SC_R_payld : out STD_LOGIC_VECTOR ( 138 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_R_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_R_payld : in STD_LOGIC_VECTOR ( 148 downto 0 );
    S00_SC_R_recv : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_m00rn_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_m00rn_0 is
  signal NLW_inst_m_axis_arb_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_arb_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 0;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 1;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 2;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 16;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 1;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 149;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "1'b0";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 2;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 0;
  attribute C_S_NUM_BYTES_ARRAY : integer;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 1;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 1;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 2;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 1;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 1;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 4;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 1;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 1;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 1;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_node_v1_0_17_top__parameterized2\
     port map (
      m_axis_arb_tdata(15 downto 0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 0),
      m_axis_arb_tready => '1',
      m_axis_arb_tvalid => NLW_inst_m_axis_arb_tvalid_UNCONNECTED,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(1 downto 0) => NLW_inst_m_sc_info_UNCONNECTED(1 downto 0),
      m_sc_payld(148 downto 14) => M_SC_R_payld(138 downto 4),
      m_sc_payld(13) => NLW_inst_m_sc_payld_UNCONNECTED(13),
      m_sc_payld(12 downto 11) => M_SC_R_payld(3 downto 2),
      m_sc_payld(10 downto 6) => NLW_inst_m_sc_payld_UNCONNECTED(10 downto 6),
      m_sc_payld(5 downto 4) => M_SC_R_payld(1 downto 0),
      m_sc_payld(3 downto 0) => NLW_inst_m_sc_payld_UNCONNECTED(3 downto 0),
      m_sc_recv(1 downto 0) => S00_SC_R_recv(1 downto 0),
      m_sc_req(1 downto 0) => NLW_inst_m_sc_req_UNCONNECTED(1 downto 0),
      m_sc_send(1 downto 0) => M_SC_R_send(1 downto 0),
      s_axis_arb_tdata(15 downto 0) => B"0000000000000000",
      s_axis_arb_tready => NLW_inst_s_axis_arb_tready_UNCONNECTED,
      s_axis_arb_tvalid => '0',
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(0) => '0',
      s_sc_payld(148 downto 0) => S_SC_R_payld(148 downto 0),
      s_sc_recv(0) => S_SC_R_recv(0),
      s_sc_req(0) => '0',
      s_sc_send(0) => S_SC_R_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_m00wn_0 is
  port (
    S_SC_W_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_payld : out STD_LOGIC_VECTOR ( 144 downto 0 );
    s_axis_arb_tready : out STD_LOGIC;
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_req : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_info : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_payld : in STD_LOGIC_VECTOR ( 147 downto 0 );
    M_SC_W_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_arb_tvalid : in STD_LOGIC;
    m_axis_arb_tdata : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_m00wn_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_m00wn_0 is
  signal NLW_inst_m_axis_arb_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_s_sc_recv_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 1;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 0;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 2;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 2;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 160;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "2'b00";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 1;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 1;
  attribute C_S_NUM_BYTES_ARRAY : string;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is "64'b0000000000000000000000000001000000000000000000000000000000010000";
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 2;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 1;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 1;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 1;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 1;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 1;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 1;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 1;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 1;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_node_v1_0_17_top__parameterized3\
     port map (
      m_axis_arb_tdata(15 downto 0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 0),
      m_axis_arb_tready => '1',
      m_axis_arb_tvalid => NLW_inst_m_axis_arb_tvalid_UNCONNECTED,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(0) => NLW_inst_m_sc_info_UNCONNECTED(0),
      m_sc_payld(159 downto 15) => M_SC_W_payld(144 downto 0),
      m_sc_payld(14 downto 0) => NLW_inst_m_sc_payld_UNCONNECTED(14 downto 0),
      m_sc_recv(0) => M_SC_W_recv(0),
      m_sc_req(0) => NLW_inst_m_sc_req_UNCONNECTED(0),
      m_sc_send(0) => M_SC_W_send(0),
      s_axis_arb_tdata(15 downto 2) => B"00000000000000",
      s_axis_arb_tdata(1) => m_axis_arb_tdata(0),
      s_axis_arb_tdata(0) => '0',
      s_axis_arb_tready => s_axis_arb_tready,
      s_axis_arb_tvalid => m_axis_arb_tvalid,
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(1) => M00_SC_W_info(0),
      s_sc_info(0) => '0',
      s_sc_payld(159 downto 14) => M00_SC_W_payld(147 downto 2),
      s_sc_payld(13 downto 9) => B"00000",
      s_sc_payld(8) => M00_SC_W_payld(1),
      s_sc_payld(7 downto 2) => B"000000",
      s_sc_payld(1) => M00_SC_W_payld(0),
      s_sc_payld(0) => '0',
      s_sc_recv(1) => S_SC_W_recv(0),
      s_sc_recv(0) => NLW_inst_s_sc_recv_UNCONNECTED(0),
      s_sc_req(1) => M00_SC_W_req(0),
      s_sc_req(0) => '0',
      s_sc_send(1) => M00_SC_W_send(0),
      s_sc_send(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_sarn_0 is
  port (
    S_SC_AR_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_payld : out STD_LOGIC_VECTOR ( 82 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_payld : in STD_LOGIC_VECTOR ( 68 downto 0 );
    S00_SC_AR_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_sarn_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_sarn_0 is
  signal NLW_inst_m_axis_arb_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_arb_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 69 downto 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 2;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 1;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 16;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 1;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 140;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "1'b0";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 1;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 0;
  attribute C_S_NUM_BYTES_ARRAY : integer;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is 4;
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 1;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 7;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 1;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 0;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 4;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 4;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 1;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 4;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 0;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 0;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 0;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_node_v1_0_17_top__parameterized4\
     port map (
      m_axis_arb_tdata(15 downto 0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 0),
      m_axis_arb_tready => '1',
      m_axis_arb_tvalid => NLW_inst_m_axis_arb_tvalid_UNCONNECTED,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(0) => NLW_inst_m_sc_info_UNCONNECTED(0),
      m_sc_payld(139 downto 70) => M_SC_AR_payld(82 downto 13),
      m_sc_payld(69 downto 14) => NLW_inst_m_sc_payld_UNCONNECTED(69 downto 14),
      m_sc_payld(13 downto 1) => M_SC_AR_payld(12 downto 0),
      m_sc_payld(0) => NLW_inst_m_sc_payld_UNCONNECTED(0),
      m_sc_recv(0) => S00_SC_AR_recv(0),
      m_sc_req(0) => M_SC_AR_req(0),
      m_sc_send(0) => M_SC_AR_send(0),
      s_axis_arb_tdata(15 downto 0) => B"0000000000000000",
      s_axis_arb_tready => NLW_inst_s_axis_arb_tready_UNCONNECTED,
      s_axis_arb_tvalid => '0',
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(0) => '0',
      s_sc_payld(139 downto 96) => S_SC_AR_payld(68 downto 25),
      s_sc_payld(95 downto 93) => B"010",
      s_sc_payld(92 downto 86) => S_SC_AR_payld(24 downto 18),
      s_sc_payld(85 downto 84) => B"00",
      s_sc_payld(83 downto 73) => S_SC_AR_payld(17 downto 7),
      s_sc_payld(72 downto 8) => B"00000000000000000000000000000000000000000000000000000000000000000",
      s_sc_payld(7 downto 1) => S_SC_AR_payld(6 downto 0),
      s_sc_payld(0) => '0',
      s_sc_recv(0) => S_SC_AR_recv(0),
      s_sc_req(0) => '0',
      s_sc_send(0) => S_SC_AR_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_sarn_1 is
  port (
    S_SC_AR_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_payld : out STD_LOGIC_VECTOR ( 82 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_payld : in STD_LOGIC_VECTOR ( 68 downto 0 );
    S01_SC_AR_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_sarn_1;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_sarn_1 is
  signal NLW_inst_m_axis_arb_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_arb_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 69 downto 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 2;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 1;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 2;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 1;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 140;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "1'b0";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 1;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 0;
  attribute C_S_NUM_BYTES_ARRAY : integer;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is 4;
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 1;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 7;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 1;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 0;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 4;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 4;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 1;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 1;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 0;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 0;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 0;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_node_v1_0_17_top__parameterized6\
     port map (
      m_axis_arb_tdata(15 downto 0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 0),
      m_axis_arb_tready => '1',
      m_axis_arb_tvalid => NLW_inst_m_axis_arb_tvalid_UNCONNECTED,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(0) => NLW_inst_m_sc_info_UNCONNECTED(0),
      m_sc_payld(139 downto 70) => M_SC_AR_payld(82 downto 13),
      m_sc_payld(69 downto 14) => NLW_inst_m_sc_payld_UNCONNECTED(69 downto 14),
      m_sc_payld(13 downto 1) => M_SC_AR_payld(12 downto 0),
      m_sc_payld(0) => NLW_inst_m_sc_payld_UNCONNECTED(0),
      m_sc_recv(0) => S01_SC_AR_recv(0),
      m_sc_req(0) => M_SC_AR_req(0),
      m_sc_send(0) => M_SC_AR_send(0),
      s_axis_arb_tdata(15 downto 0) => B"0000000000000000",
      s_axis_arb_tready => NLW_inst_s_axis_arb_tready_UNCONNECTED,
      s_axis_arb_tvalid => '0',
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(0) => '0',
      s_sc_payld(139 downto 96) => S_SC_AR_payld(68 downto 25),
      s_sc_payld(95 downto 93) => B"100",
      s_sc_payld(92 downto 86) => S_SC_AR_payld(24 downto 18),
      s_sc_payld(85 downto 84) => B"00",
      s_sc_payld(83 downto 73) => S_SC_AR_payld(17 downto 7),
      s_sc_payld(72 downto 8) => B"00000000000000000000000000000000000000000000000000000000000000000",
      s_sc_payld(7 downto 1) => S_SC_AR_payld(6 downto 0),
      s_sc_payld(0) => '0',
      s_sc_recv(0) => S_SC_AR_recv(0),
      s_sc_req(0) => '0',
      s_sc_send(0) => S_SC_AR_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_sawn_0 is
  port (
    S_SC_AW_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AW_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AW_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AW_payld : out STD_LOGIC_VECTOR ( 82 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AW_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AW_payld : in STD_LOGIC_VECTOR ( 68 downto 0 );
    S01_SC_AW_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_sawn_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_sawn_0 is
  signal NLW_inst_m_axis_arb_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_arb_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 69 downto 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 3;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 1;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 2;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 1;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 140;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "1'b0";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 1;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 0;
  attribute C_S_NUM_BYTES_ARRAY : integer;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is 4;
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 1;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 7;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 1;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 0;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 4;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 4;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 1;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 1;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 0;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 0;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 0;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_node_v1_0_17_top__parameterized7\
     port map (
      m_axis_arb_tdata(15 downto 0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 0),
      m_axis_arb_tready => '1',
      m_axis_arb_tvalid => NLW_inst_m_axis_arb_tvalid_UNCONNECTED,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(0) => NLW_inst_m_sc_info_UNCONNECTED(0),
      m_sc_payld(139 downto 70) => M_SC_AW_payld(82 downto 13),
      m_sc_payld(69 downto 14) => NLW_inst_m_sc_payld_UNCONNECTED(69 downto 14),
      m_sc_payld(13 downto 1) => M_SC_AW_payld(12 downto 0),
      m_sc_payld(0) => NLW_inst_m_sc_payld_UNCONNECTED(0),
      m_sc_recv(0) => S01_SC_AW_recv(0),
      m_sc_req(0) => M_SC_AW_req(0),
      m_sc_send(0) => M_SC_AW_send(0),
      s_axis_arb_tdata(15 downto 0) => B"0000000000000000",
      s_axis_arb_tready => NLW_inst_s_axis_arb_tready_UNCONNECTED,
      s_axis_arb_tvalid => '0',
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(0) => '0',
      s_sc_payld(139 downto 96) => S_SC_AW_payld(68 downto 25),
      s_sc_payld(95 downto 93) => B"100",
      s_sc_payld(92 downto 86) => S_SC_AW_payld(24 downto 18),
      s_sc_payld(85 downto 84) => B"00",
      s_sc_payld(83 downto 73) => S_SC_AW_payld(17 downto 7),
      s_sc_payld(72 downto 8) => B"00000000000000000000000000000000000000000000000000000000000000000",
      s_sc_payld(7 downto 1) => S_SC_AW_payld(6 downto 0),
      s_sc_payld(0) => '0',
      s_sc_recv(0) => S_SC_AW_recv(0),
      s_sc_req(0) => '0',
      s_sc_send(0) => S_SC_AW_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_sbn_0 is
  port (
    S_SC_B_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_B_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_B_payld : out STD_LOGIC_VECTOR ( 1 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_B_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_B_payld : in STD_LOGIC_VECTOR ( 5 downto 0 );
    M_SC_B_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_sbn_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_sbn_0 is
  signal NLW_inst_m_axis_arb_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_arb_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 4;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 4;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 0;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 2;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 1;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 7;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "1'b0";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 2;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 1;
  attribute C_S_NUM_BYTES_ARRAY : integer;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 0;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 1;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 7;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 4;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 4;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 2;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 0;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 0;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 1;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 0;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 0;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 0;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_node_v1_0_17_top__parameterized8\
     port map (
      m_axis_arb_tdata(15 downto 0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 0),
      m_axis_arb_tready => '1',
      m_axis_arb_tvalid => NLW_inst_m_axis_arb_tvalid_UNCONNECTED,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(0) => NLW_inst_m_sc_info_UNCONNECTED(0),
      m_sc_payld(6 downto 5) => M_SC_B_payld(1 downto 0),
      m_sc_payld(4 downto 0) => NLW_inst_m_sc_payld_UNCONNECTED(4 downto 0),
      m_sc_recv(0) => M_SC_B_recv(0),
      m_sc_req(0) => NLW_inst_m_sc_req_UNCONNECTED(0),
      m_sc_send(0) => M_SC_B_send(0),
      s_axis_arb_tdata(15 downto 0) => B"0000000000000000",
      s_axis_arb_tready => NLW_inst_s_axis_arb_tready_UNCONNECTED,
      s_axis_arb_tvalid => '0',
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(0) => '0',
      s_sc_payld(6 downto 1) => M01_SC_B_payld(5 downto 0),
      s_sc_payld(0) => '0',
      s_sc_recv(0) => S_SC_B_recv(0),
      s_sc_req(0) => '0',
      s_sc_send(0) => M01_SC_B_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_srn_0 is
  port (
    S_SC_R_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_payld : out STD_LOGIC_VECTOR ( 34 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_R_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_R_payld : in STD_LOGIC_VECTOR ( 138 downto 0 );
    M_SC_R_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_srn_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_srn_0 is
  signal NLW_inst_m_axis_arb_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_arb_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 148 downto 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 0;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 4;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 0;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 16;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 1;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 149;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "1'b0";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 2;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 1;
  attribute C_S_NUM_BYTES_ARRAY : integer;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 512;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 1;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 2;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 1;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 4;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 4;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 4;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 2;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 1;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 0;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 4;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 1;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 1;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 1;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_node_v1_0_17_top__parameterized5\
     port map (
      m_axis_arb_tdata(15 downto 0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 0),
      m_axis_arb_tready => '1',
      m_axis_arb_tvalid => NLW_inst_m_axis_arb_tvalid_UNCONNECTED,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(0) => NLW_inst_m_sc_info_UNCONNECTED(0),
      m_sc_payld(148 downto 53) => NLW_inst_m_sc_payld_UNCONNECTED(148 downto 53),
      m_sc_payld(52 downto 18) => M_SC_R_payld(34 downto 0),
      m_sc_payld(17 downto 0) => NLW_inst_m_sc_payld_UNCONNECTED(17 downto 0),
      m_sc_recv(0) => M_SC_R_recv(0),
      m_sc_req(0) => NLW_inst_m_sc_req_UNCONNECTED(0),
      m_sc_send(0) => M_SC_R_send(0),
      s_axis_arb_tdata(15 downto 0) => B"0000000000000000",
      s_axis_arb_tready => NLW_inst_s_axis_arb_tready_UNCONNECTED,
      s_axis_arb_tvalid => '0',
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(0) => '0',
      s_sc_payld(148 downto 14) => M00_SC_R_payld(138 downto 4),
      s_sc_payld(13) => '0',
      s_sc_payld(12 downto 11) => M00_SC_R_payld(3 downto 2),
      s_sc_payld(10 downto 6) => B"00000",
      s_sc_payld(5 downto 4) => M00_SC_R_payld(1 downto 0),
      s_sc_payld(3 downto 0) => B"0000",
      s_sc_recv(0) => S_SC_R_recv(0),
      s_sc_req(0) => '0',
      s_sc_send(0) => M00_SC_R_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_srn_1 is
  port (
    S_SC_R_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_payld : out STD_LOGIC_VECTOR ( 34 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_R_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_R_payld : in STD_LOGIC_VECTOR ( 138 downto 0 );
    M_SC_R_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_srn_1;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_srn_1 is
  signal NLW_inst_m_axis_arb_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_arb_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_info_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 148 downto 0 );
  signal NLW_inst_m_sc_req_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 0;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 4;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 0;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 2;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 1;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 149;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "1'b0";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 2;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 1;
  attribute C_S_NUM_BYTES_ARRAY : integer;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 512;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 1;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 2;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 1;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 4;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 1;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 4;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 4;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 2;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 1;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 0;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 1;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 1;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 1;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 1;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 2;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_node_v1_0_17_top__parameterized9\
     port map (
      m_axis_arb_tdata(15 downto 0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 0),
      m_axis_arb_tready => '1',
      m_axis_arb_tvalid => NLW_inst_m_axis_arb_tvalid_UNCONNECTED,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(0) => NLW_inst_m_sc_info_UNCONNECTED(0),
      m_sc_payld(148 downto 53) => NLW_inst_m_sc_payld_UNCONNECTED(148 downto 53),
      m_sc_payld(52 downto 18) => M_SC_R_payld(34 downto 0),
      m_sc_payld(17 downto 0) => NLW_inst_m_sc_payld_UNCONNECTED(17 downto 0),
      m_sc_recv(0) => M_SC_R_recv(0),
      m_sc_req(0) => NLW_inst_m_sc_req_UNCONNECTED(0),
      m_sc_send(0) => M_SC_R_send(0),
      s_axis_arb_tdata(15 downto 0) => B"0000000000000000",
      s_axis_arb_tready => NLW_inst_s_axis_arb_tready_UNCONNECTED,
      s_axis_arb_tvalid => '0',
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(0) => '0',
      s_sc_payld(148 downto 14) => M01_SC_R_payld(138 downto 4),
      s_sc_payld(13) => '0',
      s_sc_payld(12 downto 11) => M01_SC_R_payld(3 downto 2),
      s_sc_payld(10 downto 6) => B"00000",
      s_sc_payld(5 downto 4) => M01_SC_R_payld(1 downto 0),
      s_sc_payld(3 downto 0) => B"0000",
      s_sc_recv(0) => S_SC_R_recv(0),
      s_sc_req(0) => '0',
      s_sc_send(0) => M01_SC_R_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c_swn_0 is
  port (
    S_SC_W_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_info : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_payld : out STD_LOGIC_VECTOR ( 147 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_W_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_W_payld : in STD_LOGIC_VECTOR ( 50 downto 0 );
    S01_SC_W_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_bd_e34c_swn_0;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c_swn_0 is
  signal NLW_inst_m_axis_arb_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_arb_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_arb_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_m_sc_payld_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  attribute C_ACLKEN_CONVERSION : integer;
  attribute C_ACLKEN_CONVERSION of inst : label is 0;
  attribute C_ACLK_RELATIONSHIP : integer;
  attribute C_ACLK_RELATIONSHIP of inst : label is 1;
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of inst : label is 32;
  attribute C_ARBITER_MODE : integer;
  attribute C_ARBITER_MODE of inst : label is 1;
  attribute C_CHANNEL : integer;
  attribute C_CHANNEL of inst : label is 1;
  attribute C_DISABLE_IP : integer;
  attribute C_DISABLE_IP of inst : label is 0;
  attribute C_ENABLE_PIPELINING : string;
  attribute C_ENABLE_PIPELINING of inst : label is "8'b00000001";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "zynquplus";
  attribute C_FIFO_IP : integer;
  attribute C_FIFO_IP of inst : label is 0;
  attribute C_FIFO_OUTPUT_REG : integer;
  attribute C_FIFO_OUTPUT_REG of inst : label is 1;
  attribute C_FIFO_SIZE : integer;
  attribute C_FIFO_SIZE of inst : label is 5;
  attribute C_FIFO_TYPE : integer;
  attribute C_FIFO_TYPE of inst : label is 0;
  attribute C_ID_WIDTH : integer;
  attribute C_ID_WIDTH of inst : label is 2;
  attribute C_MAX_PAYLD_BYTES : integer;
  attribute C_MAX_PAYLD_BYTES of inst : label is 16;
  attribute C_M_NUM_BYTES_ARRAY : integer;
  attribute C_M_NUM_BYTES_ARRAY of inst : label is 16;
  attribute C_M_PIPELINE : integer;
  attribute C_M_PIPELINE of inst : label is 0;
  attribute C_M_SEND_PIPELINE : integer;
  attribute C_M_SEND_PIPELINE of inst : label is 1;
  attribute C_NUM_MI : integer;
  attribute C_NUM_MI of inst : label is 1;
  attribute C_NUM_OUTSTANDING : integer;
  attribute C_NUM_OUTSTANDING of inst : label is 2;
  attribute C_NUM_SI : integer;
  attribute C_NUM_SI of inst : label is 1;
  attribute C_PAYLD_WIDTH : integer;
  attribute C_PAYLD_WIDTH of inst : label is 160;
  attribute C_PRIORITY_ARB_ARRAY : string;
  attribute C_PRIORITY_ARB_ARRAY of inst : label is "1'b0";
  attribute C_SC_ROUTE_WIDTH : integer;
  attribute C_SC_ROUTE_WIDTH of inst : label is 1;
  attribute C_SYNCHRONIZATION_STAGES : integer;
  attribute C_SYNCHRONIZATION_STAGES of inst : label is 3;
  attribute C_S_LATENCY : integer;
  attribute C_S_LATENCY of inst : label is 0;
  attribute C_S_NUM_BYTES_ARRAY : integer;
  attribute C_S_NUM_BYTES_ARRAY of inst : label is 4;
  attribute C_S_PIPELINE : integer;
  attribute C_S_PIPELINE of inst : label is 0;
  attribute C_USER_BITS_PER_BYTE : integer;
  attribute C_USER_BITS_PER_BYTE of inst : label is 0;
  attribute C_USER_WIDTH : integer;
  attribute C_USER_WIDTH of inst : label is 512;
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of inst : label is "soft";
  attribute LP_ACLK_RELATIONSHIP : integer;
  attribute LP_ACLK_RELATIONSHIP of inst : label is 1;
  attribute LP_ARBITER_MODE : integer;
  attribute LP_ARBITER_MODE of inst : label is 2;
  attribute LP_DT_REG : string;
  attribute LP_DT_REG of inst : label is "true";
  attribute LP_FIFO_OUTPUT_REG : integer;
  attribute LP_FIFO_OUTPUT_REG of inst : label is 1;
  attribute LP_FIFO_TYPE : integer;
  attribute LP_FIFO_TYPE of inst : label is 0;
  attribute LP_LIGHTWT_MI : integer;
  attribute LP_LIGHTWT_MI of inst : label is 0;
  attribute LP_LIGHTWT_PASS : integer;
  attribute LP_LIGHTWT_PASS of inst : label is 0;
  attribute LP_LIGHTWT_SI : integer;
  attribute LP_LIGHTWT_SI of inst : label is 0;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_LOG_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_LOG_MAX_UPSIZER_RATIO : integer;
  attribute LP_LOG_MAX_UPSIZER_RATIO of inst : label is 2;
  attribute LP_LOG_NUM_MI : integer;
  attribute LP_LOG_NUM_MI of inst : label is 1;
  attribute LP_LOG_NUM_SI : integer;
  attribute LP_LOG_NUM_SI of inst : label is 1;
  attribute LP_LTWT_REG_TYPE : integer;
  attribute LP_LTWT_REG_TYPE of inst : label is 1;
  attribute LP_MAX_DOWNSIZER_RATIO : integer;
  attribute LP_MAX_DOWNSIZER_RATIO of inst : label is 1;
  attribute LP_MAX_NUM_BYTES : integer;
  attribute LP_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_MAX_UPSIZER_RATIO : integer;
  attribute LP_MAX_UPSIZER_RATIO of inst : label is 4;
  attribute LP_M_MAX_NUM_BYTES : integer;
  attribute LP_M_MAX_NUM_BYTES of inst : label is 16;
  attribute LP_M_MIN_NUM_BYTES : integer;
  attribute LP_M_MIN_NUM_BYTES of inst : label is 16;
  attribute LP_M_STATIC_DWIDTH : integer;
  attribute LP_M_STATIC_DWIDTH of inst : label is 1;
  attribute LP_NODE_ADDR_WIDTH : integer;
  attribute LP_NODE_ADDR_WIDTH of inst : label is 32;
  attribute LP_NODE_ID_WIDTH : integer;
  attribute LP_NODE_ID_WIDTH of inst : label is 2;
  attribute LP_NODE_ROUTE_WIDTH : integer;
  attribute LP_NODE_ROUTE_WIDTH of inst : label is 1;
  attribute LP_NODE_USER_WIDTH : integer;
  attribute LP_NODE_USER_WIDTH of inst : label is 1;
  attribute LP_SYNCHRONIZATION_STAGES : integer;
  attribute LP_SYNCHRONIZATION_STAGES of inst : label is 2;
  attribute LP_S_AXIS_REG_SLICE_CONFIG : integer;
  attribute LP_S_AXIS_REG_SLICE_CONFIG of inst : label is 0;
  attribute LP_S_MAX_NUM_BYTES : integer;
  attribute LP_S_MAX_NUM_BYTES of inst : label is 4;
  attribute LP_S_MIN_NUM_BYTES : integer;
  attribute LP_S_MIN_NUM_BYTES of inst : label is 4;
  attribute LP_S_PIPELINE : integer;
  attribute LP_S_PIPELINE of inst : label is 0;
  attribute LP_S_STATIC_DWIDTH : integer;
  attribute LP_S_STATIC_DWIDTH of inst : label is 1;
  attribute LP_ZERO_ROUTE_WIDTH : integer;
  attribute LP_ZERO_ROUTE_WIDTH of inst : label is 1;
  attribute P_NUM_OUTSTANDING : integer;
  attribute P_NUM_OUTSTANDING of inst : label is 16;
  attribute P_QUEUE_SIZE : integer;
  attribute P_QUEUE_SIZE of inst : label is 1;
  attribute T_SC_ADDR_WIDTH : integer;
  attribute T_SC_ADDR_WIDTH of inst : label is 32;
  attribute T_SC_ARUSER_WIDTH : integer;
  attribute T_SC_ARUSER_WIDTH of inst : label is 1;
  attribute T_SC_AWUSER_WIDTH : integer;
  attribute T_SC_AWUSER_WIDTH of inst : label is 1;
  attribute T_SC_BUSER_WIDTH : integer;
  attribute T_SC_BUSER_WIDTH of inst : label is 1;
  attribute T_SC_ID_WIDTH : integer;
  attribute T_SC_ID_WIDTH of inst : label is 2;
  attribute T_SC_MSC_ROUTE_WIDTH : integer;
  attribute T_SC_MSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_RDATA_WIDTH : integer;
  attribute T_SC_RDATA_WIDTH of inst : label is 128;
  attribute T_SC_RUSER_BITS_PER_BYTE : integer;
  attribute T_SC_RUSER_BITS_PER_BYTE of inst : label is 0;
  attribute T_SC_SSC_ROUTE_WIDTH : integer;
  attribute T_SC_SSC_ROUTE_WIDTH of inst : label is 1;
  attribute T_SC_WDATA_WIDTH : integer;
  attribute T_SC_WDATA_WIDTH of inst : label is 128;
  attribute T_SC_WUSER_BITS_PER_BYTE : integer;
  attribute T_SC_WUSER_BITS_PER_BYTE of inst : label is 0;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of inst : label is "true";
begin
inst: entity work.\Loopback_smartconnect_0_0_sc_node_v1_0_17_top__parameterized10\
     port map (
      m_axis_arb_tdata(15 downto 0) => NLW_inst_m_axis_arb_tdata_UNCONNECTED(15 downto 0),
      m_axis_arb_tready => '1',
      m_axis_arb_tvalid => NLW_inst_m_axis_arb_tvalid_UNCONNECTED,
      m_sc_aclk => aclk,
      m_sc_aclken => '1',
      m_sc_aresetn => interconnect_aresetn(0),
      m_sc_info(0) => M_SC_W_info(0),
      m_sc_payld(159 downto 14) => M_SC_W_payld(147 downto 2),
      m_sc_payld(13 downto 9) => NLW_inst_m_sc_payld_UNCONNECTED(13 downto 9),
      m_sc_payld(8) => M_SC_W_payld(1),
      m_sc_payld(7 downto 2) => NLW_inst_m_sc_payld_UNCONNECTED(7 downto 2),
      m_sc_payld(1) => M_SC_W_payld(0),
      m_sc_payld(0) => NLW_inst_m_sc_payld_UNCONNECTED(0),
      m_sc_recv(0) => S01_SC_W_recv(0),
      m_sc_req(0) => M_SC_W_req(0),
      m_sc_send(0) => M_SC_W_send(0),
      s_axis_arb_tdata(15 downto 0) => B"0000000000000000",
      s_axis_arb_tready => NLW_inst_s_axis_arb_tready_UNCONNECTED,
      s_axis_arb_tvalid => '0',
      s_sc_aclk => aclk,
      s_sc_aclken => '1',
      s_sc_aresetn => interconnect_aresetn(0),
      s_sc_info(0) => '0',
      s_sc_payld(159 downto 52) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_sc_payld(51 downto 1) => S_SC_W_payld(50 downto 0),
      s_sc_payld(0) => '0',
      s_sc_recv(0) => S_SC_W_recv(0),
      s_sc_req(0) => '0',
      s_sc_send(0) => S_SC_W_send(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_m00_nodes_imp_1J21SGW is
  port (
    S_SC_AR_recv : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_SC_AR_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_payld : out STD_LOGIC_VECTOR ( 70 downto 0 );
    S_SC_AW_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AW_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AW_payld : out STD_LOGIC_VECTOR ( 63 downto 0 );
    S_SC_B_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_B_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_B_payld : out STD_LOGIC_VECTOR ( 5 downto 0 );
    S_SC_R_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_send : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_SC_R_payld : out STD_LOGIC_VECTOR ( 138 downto 0 );
    S_SC_W_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_payld : out STD_LOGIC_VECTOR ( 144 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AR_req : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_SC_AR_send : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_SC_AR_payld : in STD_LOGIC_VECTOR ( 82 downto 0 );
    M_SC_AR_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_req : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_AW_payld : in STD_LOGIC_VECTOR ( 82 downto 0 );
    M_SC_AW_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_B_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_B_payld : in STD_LOGIC_VECTOR ( 5 downto 0 );
    S00_SC_B_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_R_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_R_payld : in STD_LOGIC_VECTOR ( 148 downto 0 );
    S00_SC_R_recv : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_SC_W_req : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_info : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_W_payld : in STD_LOGIC_VECTOR ( 147 downto 0 );
    M_SC_W_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_m00_nodes_imp_1J21SGW;

architecture STRUCTURE of Loopback_smartconnect_0_0_m00_nodes_imp_1J21SGW is
  signal m00_aw_node_M_AXIS_ARB_TDATA : STD_LOGIC_VECTOR ( 1 to 1 );
  signal m00_aw_node_M_AXIS_ARB_TREADY : STD_LOGIC;
  signal m00_aw_node_M_AXIS_ARB_TVALID : STD_LOGIC;
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of m00_ar_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
  attribute X_CORE_INFO of m00_aw_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
  attribute X_CORE_INFO of m00_b_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
  attribute X_CORE_INFO of m00_r_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
  attribute X_CORE_INFO of m00_w_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
begin
m00_ar_node: entity work.Loopback_smartconnect_0_0_bd_e34c_m00arn_0
     port map (
      M00_SC_AR_payld(82 downto 0) => M00_SC_AR_payld(82 downto 0),
      M00_SC_AR_req(1 downto 0) => M00_SC_AR_req(1 downto 0),
      M00_SC_AR_send(1 downto 0) => M00_SC_AR_send(1 downto 0),
      M_SC_AR_payld(70 downto 0) => M_SC_AR_payld(70 downto 0),
      M_SC_AR_recv(0) => M_SC_AR_recv(0),
      M_SC_AR_send(0) => M_SC_AR_send(0),
      S_SC_AR_recv(1 downto 0) => S_SC_AR_recv(1 downto 0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
m00_aw_node: entity work.Loopback_smartconnect_0_0_bd_e34c_m00awn_0
     port map (
      M00_SC_AW_payld(82 downto 0) => M00_SC_AW_payld(82 downto 0),
      M00_SC_AW_req(0) => M00_SC_AW_req(0),
      M00_SC_AW_send(0) => M00_SC_AW_send(0),
      M_SC_AW_payld(63 downto 0) => M_SC_AW_payld(63 downto 0),
      M_SC_AW_recv(0) => M_SC_AW_recv(0),
      M_SC_AW_send(0) => M_SC_AW_send(0),
      S_SC_AW_recv(0) => S_SC_AW_recv(0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0),
      m_axis_arb_tdata(0) => m00_aw_node_M_AXIS_ARB_TDATA(1),
      m_axis_arb_tvalid => m00_aw_node_M_AXIS_ARB_TVALID,
      s_axis_arb_tready => m00_aw_node_M_AXIS_ARB_TREADY
    );
m00_b_node: entity work.Loopback_smartconnect_0_0_bd_e34c_m00bn_0
     port map (
      M_SC_B_payld(5 downto 0) => M_SC_B_payld(5 downto 0),
      M_SC_B_send(0) => M_SC_B_send(0),
      S00_SC_B_recv(0) => S00_SC_B_recv(0),
      S_SC_B_payld(5 downto 0) => S_SC_B_payld(5 downto 0),
      S_SC_B_recv(0) => S_SC_B_recv(0),
      S_SC_B_send(0) => S_SC_B_send(0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
m00_r_node: entity work.Loopback_smartconnect_0_0_bd_e34c_m00rn_0
     port map (
      M_SC_R_payld(138 downto 0) => M_SC_R_payld(138 downto 0),
      M_SC_R_send(1 downto 0) => M_SC_R_send(1 downto 0),
      S00_SC_R_recv(1 downto 0) => S00_SC_R_recv(1 downto 0),
      S_SC_R_payld(148 downto 0) => S_SC_R_payld(148 downto 0),
      S_SC_R_recv(0) => S_SC_R_recv(0),
      S_SC_R_send(0) => S_SC_R_send(0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
m00_w_node: entity work.Loopback_smartconnect_0_0_bd_e34c_m00wn_0
     port map (
      M00_SC_W_info(0) => M00_SC_W_info(0),
      M00_SC_W_payld(147 downto 0) => M00_SC_W_payld(147 downto 0),
      M00_SC_W_req(0) => M00_SC_W_req(0),
      M00_SC_W_send(0) => M00_SC_W_send(0),
      M_SC_W_payld(144 downto 0) => M_SC_W_payld(144 downto 0),
      M_SC_W_recv(0) => M_SC_W_recv(0),
      M_SC_W_send(0) => M_SC_W_send(0),
      S_SC_W_recv(0) => S_SC_W_recv(0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0),
      m_axis_arb_tdata(0) => m00_aw_node_M_AXIS_ARB_TDATA(1),
      m_axis_arb_tvalid => m00_aw_node_M_AXIS_ARB_TVALID,
      s_axis_arb_tready => m00_aw_node_M_AXIS_ARB_TREADY
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_s00_nodes_imp_7T00L is
  port (
    S_SC_AR_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_payld : out STD_LOGIC_VECTOR ( 82 downto 0 );
    S_SC_R_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_payld : out STD_LOGIC_VECTOR ( 34 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_payld : in STD_LOGIC_VECTOR ( 68 downto 0 );
    S00_SC_AR_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_R_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_SC_R_payld : in STD_LOGIC_VECTOR ( 138 downto 0 );
    M_SC_R_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_s00_nodes_imp_7T00L;

architecture STRUCTURE of Loopback_smartconnect_0_0_s00_nodes_imp_7T00L is
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of s00_ar_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
  attribute X_CORE_INFO of s00_r_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
begin
s00_ar_node: entity work.Loopback_smartconnect_0_0_bd_e34c_sarn_0
     port map (
      M_SC_AR_payld(82 downto 0) => M_SC_AR_payld(82 downto 0),
      M_SC_AR_req(0) => M_SC_AR_req(0),
      M_SC_AR_send(0) => M_SC_AR_send(0),
      S00_SC_AR_recv(0) => S00_SC_AR_recv(0),
      S_SC_AR_payld(68 downto 0) => S_SC_AR_payld(68 downto 0),
      S_SC_AR_recv(0) => S_SC_AR_recv(0),
      S_SC_AR_send(0) => S_SC_AR_send(0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
s00_r_node: entity work.Loopback_smartconnect_0_0_bd_e34c_srn_0
     port map (
      M00_SC_R_payld(138 downto 0) => M00_SC_R_payld(138 downto 0),
      M00_SC_R_send(0) => M00_SC_R_send(0),
      M_SC_R_payld(34 downto 0) => M_SC_R_payld(34 downto 0),
      M_SC_R_recv(0) => M_SC_R_recv(0),
      M_SC_R_send(0) => M_SC_R_send(0),
      S_SC_R_recv(0) => S_SC_R_recv(0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_s01_nodes_imp_17S12XV is
  port (
    S_SC_AR_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AR_payld : out STD_LOGIC_VECTOR ( 82 downto 0 );
    S_SC_AW_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AW_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AW_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_AW_payld : out STD_LOGIC_VECTOR ( 82 downto 0 );
    S_SC_B_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_B_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_B_payld : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S_SC_R_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_R_payld : out STD_LOGIC_VECTOR ( 34 downto 0 );
    S_SC_W_recv : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_send : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_req : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_info : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_SC_W_payld : out STD_LOGIC_VECTOR ( 147 downto 0 );
    aclk : in STD_LOGIC;
    interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AR_payld : in STD_LOGIC_VECTOR ( 68 downto 0 );
    S01_SC_AR_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AW_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_AW_payld : in STD_LOGIC_VECTOR ( 68 downto 0 );
    S01_SC_AW_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_B_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_B_payld : in STD_LOGIC_VECTOR ( 5 downto 0 );
    M_SC_B_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_R_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_SC_R_payld : in STD_LOGIC_VECTOR ( 138 downto 0 );
    M_SC_R_recv : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_W_send : in STD_LOGIC_VECTOR ( 0 to 0 );
    S_SC_W_payld : in STD_LOGIC_VECTOR ( 50 downto 0 );
    S01_SC_W_recv : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end Loopback_smartconnect_0_0_s01_nodes_imp_17S12XV;

architecture STRUCTURE of Loopback_smartconnect_0_0_s01_nodes_imp_17S12XV is
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of s01_ar_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
  attribute X_CORE_INFO of s01_aw_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
  attribute X_CORE_INFO of s01_b_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
  attribute X_CORE_INFO of s01_r_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
  attribute X_CORE_INFO of s01_w_node : label is "sc_node_v1_0_17_top,Vivado 2024.2";
begin
s01_ar_node: entity work.Loopback_smartconnect_0_0_bd_e34c_sarn_1
     port map (
      M_SC_AR_payld(82 downto 0) => M_SC_AR_payld(82 downto 0),
      M_SC_AR_req(0) => M_SC_AR_req(0),
      M_SC_AR_send(0) => M_SC_AR_send(0),
      S01_SC_AR_recv(0) => S01_SC_AR_recv(0),
      S_SC_AR_payld(68 downto 0) => S_SC_AR_payld(68 downto 0),
      S_SC_AR_recv(0) => S_SC_AR_recv(0),
      S_SC_AR_send(0) => S_SC_AR_send(0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
s01_aw_node: entity work.Loopback_smartconnect_0_0_bd_e34c_sawn_0
     port map (
      M_SC_AW_payld(82 downto 0) => M_SC_AW_payld(82 downto 0),
      M_SC_AW_req(0) => M_SC_AW_req(0),
      M_SC_AW_send(0) => M_SC_AW_send(0),
      S01_SC_AW_recv(0) => S01_SC_AW_recv(0),
      S_SC_AW_payld(68 downto 0) => S_SC_AW_payld(68 downto 0),
      S_SC_AW_recv(0) => S_SC_AW_recv(0),
      S_SC_AW_send(0) => S_SC_AW_send(0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
s01_b_node: entity work.Loopback_smartconnect_0_0_bd_e34c_sbn_0
     port map (
      M01_SC_B_payld(5 downto 0) => M01_SC_B_payld(5 downto 0),
      M01_SC_B_send(0) => M01_SC_B_send(0),
      M_SC_B_payld(1 downto 0) => M_SC_B_payld(1 downto 0),
      M_SC_B_recv(0) => M_SC_B_recv(0),
      M_SC_B_send(0) => M_SC_B_send(0),
      S_SC_B_recv(0) => S_SC_B_recv(0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
s01_r_node: entity work.Loopback_smartconnect_0_0_bd_e34c_srn_1
     port map (
      M01_SC_R_payld(138 downto 0) => M01_SC_R_payld(138 downto 0),
      M01_SC_R_send(0) => M01_SC_R_send(0),
      M_SC_R_payld(34 downto 0) => M_SC_R_payld(34 downto 0),
      M_SC_R_recv(0) => M_SC_R_recv(0),
      M_SC_R_send(0) => M_SC_R_send(0),
      S_SC_R_recv(0) => S_SC_R_recv(0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
s01_w_node: entity work.Loopback_smartconnect_0_0_bd_e34c_swn_0
     port map (
      M_SC_W_info(0) => M_SC_W_info(0),
      M_SC_W_payld(147 downto 0) => M_SC_W_payld(147 downto 0),
      M_SC_W_req(0) => M_SC_W_req(0),
      M_SC_W_send(0) => M_SC_W_send(0),
      S01_SC_W_recv(0) => S01_SC_W_recv(0),
      S_SC_W_payld(50 downto 0) => S_SC_W_payld(50 downto 0),
      S_SC_W_recv(0) => S_SC_W_recv(0),
      S_SC_W_send(0) => S_SC_W_send(0),
      aclk => aclk,
      interconnect_aresetn(0) => interconnect_aresetn(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0_bd_e34c is
  port (
    M00_AXI_araddr : out STD_LOGIC_VECTOR ( 48 downto 0 );
    M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arready : in STD_LOGIC;
    M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arvalid : out STD_LOGIC;
    M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 48 downto 0 );
    M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awready : in STD_LOGIC;
    M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awvalid : out STD_LOGIC;
    M00_AXI_bready : out STD_LOGIC;
    M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_bvalid : in STD_LOGIC;
    M00_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    M00_AXI_rlast : in STD_LOGIC;
    M00_AXI_rready : out STD_LOGIC;
    M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_rvalid : in STD_LOGIC;
    M00_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    M00_AXI_wlast : out STD_LOGIC;
    M00_AXI_wready : in STD_LOGIC;
    M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
    M00_AXI_wvalid : out STD_LOGIC;
    S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arready : out STD_LOGIC;
    S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arvalid : in STD_LOGIC;
    S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_rlast : out STD_LOGIC;
    S00_AXI_rready : in STD_LOGIC;
    S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_rvalid : out STD_LOGIC;
    S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arready : out STD_LOGIC;
    S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arvalid : in STD_LOGIC;
    S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awready : out STD_LOGIC;
    S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awvalid : in STD_LOGIC;
    S01_AXI_bready : in STD_LOGIC;
    S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_bvalid : out STD_LOGIC;
    S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_rlast : out STD_LOGIC;
    S01_AXI_rready : in STD_LOGIC;
    S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_rvalid : out STD_LOGIC;
    S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_wlast : in STD_LOGIC;
    S01_AXI_wready : out STD_LOGIC;
    S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_wvalid : in STD_LOGIC;
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC
  );
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of Loopback_smartconnect_0_0_bd_e34c : entity is "Loopback_smartconnect_0_0.hwdef";
end Loopback_smartconnect_0_0_bd_e34c;

architecture STRUCTURE of Loopback_smartconnect_0_0_bd_e34c is
  signal \<const0>\ : STD_LOGIC;
  signal \^m00_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \^m00_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal S_SC_AR_1_PAYLD : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal S_SC_AR_1_RECV : STD_LOGIC;
  signal S_SC_AR_1_SEND : STD_LOGIC;
  signal S_SC_AR_2_PAYLD : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal S_SC_AR_2_RECV : STD_LOGIC;
  signal S_SC_AR_2_SEND : STD_LOGIC;
  signal S_SC_AR_3_PAYLD : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal S_SC_AR_3_RECV : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal S_SC_AR_3_REQ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal S_SC_AR_3_SEND : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal S_SC_AW_1_PAYLD : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal S_SC_AW_1_RECV : STD_LOGIC;
  signal S_SC_AW_1_SEND : STD_LOGIC;
  signal S_SC_AW_2_PAYLD : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal S_SC_AW_2_RECV : STD_LOGIC_VECTOR ( 1 to 1 );
  signal S_SC_AW_2_REQ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal S_SC_AW_2_SEND : STD_LOGIC_VECTOR ( 1 to 1 );
  signal S_SC_B_1_PAYLD : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal S_SC_B_1_RECV : STD_LOGIC;
  signal S_SC_B_1_SEND : STD_LOGIC;
  signal S_SC_B_2_PAYLD : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal S_SC_B_2_RECV : STD_LOGIC;
  signal S_SC_B_2_SEND : STD_LOGIC;
  signal S_SC_R_1_PAYLD : STD_LOGIC_VECTOR ( 148 downto 4 );
  signal S_SC_R_1_RECV : STD_LOGIC;
  signal S_SC_R_1_SEND : STD_LOGIC;
  signal S_SC_R_2_PAYLD : STD_LOGIC_VECTOR ( 148 downto 4 );
  signal S_SC_R_2_RECV : STD_LOGIC;
  signal S_SC_R_2_SEND : STD_LOGIC;
  signal S_SC_R_3_PAYLD : STD_LOGIC_VECTOR ( 148 downto 0 );
  signal S_SC_R_3_RECV : STD_LOGIC;
  signal S_SC_R_3_SEND : STD_LOGIC;
  signal S_SC_W_1_PAYLD : STD_LOGIC_VECTOR ( 51 downto 1 );
  signal S_SC_W_1_RECV : STD_LOGIC;
  signal S_SC_W_1_SEND : STD_LOGIC;
  signal S_SC_W_2_INFO : STD_LOGIC_VECTOR ( 1 to 1 );
  signal S_SC_W_2_PAYLD : STD_LOGIC_VECTOR ( 159 downto 1 );
  signal S_SC_W_2_RECV : STD_LOGIC_VECTOR ( 1 to 1 );
  signal S_SC_W_2_REQ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal S_SC_W_2_SEND : STD_LOGIC_VECTOR ( 1 to 1 );
  signal m00_nodes_M_SC_AR_PAYLD : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal m00_nodes_M_SC_AR_RECV : STD_LOGIC;
  signal m00_nodes_M_SC_AR_SEND : STD_LOGIC;
  signal m00_nodes_M_SC_AW_PAYLD : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal m00_nodes_M_SC_AW_RECV : STD_LOGIC;
  signal m00_nodes_M_SC_AW_SEND : STD_LOGIC;
  signal m00_nodes_M_SC_B_PAYLD : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal m00_nodes_M_SC_B_RECV : STD_LOGIC_VECTOR ( 1 to 1 );
  signal m00_nodes_M_SC_B_SEND : STD_LOGIC_VECTOR ( 1 to 1 );
  signal m00_nodes_M_SC_R_PAYLD : STD_LOGIC_VECTOR ( 148 downto 4 );
  signal m00_nodes_M_SC_R_RECV : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m00_nodes_M_SC_R_SEND : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m00_nodes_M_SC_W_PAYLD : STD_LOGIC_VECTOR ( 159 downto 15 );
  signal m00_nodes_M_SC_W_RECV : STD_LOGIC;
  signal m00_nodes_M_SC_W_SEND : STD_LOGIC;
  signal m00_sc2axi_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal m00_sc2axi_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal m00_sc2axi_M_AXI_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m00_sc2axi_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal m00_sc2axi_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal m00_sc2axi_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal m00_sc2axi_M_AXI_ARREADY : STD_LOGIC;
  signal m00_sc2axi_M_AXI_ARUSER : STD_LOGIC_VECTOR ( 185 downto 136 );
  signal m00_sc2axi_M_AXI_ARVALID : STD_LOGIC;
  signal m00_sc2axi_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal m00_sc2axi_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal m00_sc2axi_M_AXI_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m00_sc2axi_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal m00_sc2axi_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal m00_sc2axi_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal m00_sc2axi_M_AXI_AWREADY : STD_LOGIC;
  signal m00_sc2axi_M_AXI_AWUSER : STD_LOGIC_VECTOR ( 146 downto 136 );
  signal m00_sc2axi_M_AXI_AWVALID : STD_LOGIC;
  signal m00_sc2axi_M_AXI_BID : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m00_sc2axi_M_AXI_BREADY : STD_LOGIC;
  signal m00_sc2axi_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m00_sc2axi_M_AXI_BUSER : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m00_sc2axi_M_AXI_BVALID : STD_LOGIC;
  signal m00_sc2axi_M_AXI_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal m00_sc2axi_M_AXI_RID : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m00_sc2axi_M_AXI_RLAST : STD_LOGIC;
  signal m00_sc2axi_M_AXI_RREADY : STD_LOGIC;
  signal m00_sc2axi_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m00_sc2axi_M_AXI_RUSER : STD_LOGIC_VECTOR ( 77 downto 0 );
  signal m00_sc2axi_M_AXI_RVALID : STD_LOGIC;
  signal m00_sc2axi_M_AXI_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal m00_sc2axi_M_AXI_WLAST : STD_LOGIC;
  signal m00_sc2axi_M_AXI_WREADY : STD_LOGIC;
  signal m00_sc2axi_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal m00_sc2axi_M_AXI_WVALID : STD_LOGIC;
  signal m_axi_aresetn_1 : STD_LOGIC;
  signal s00_entry_pipeline_m_axi_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s00_entry_pipeline_m_axi_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s00_entry_pipeline_m_axi_ARLOCK : STD_LOGIC;
  signal s00_entry_pipeline_m_axi_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal s00_entry_pipeline_m_axi_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s00_entry_pipeline_m_axi_ARREADY : STD_LOGIC;
  signal s00_entry_pipeline_m_axi_ARUSER : STD_LOGIC_VECTOR ( 185 downto 64 );
  signal s00_entry_pipeline_m_axi_ARVALID : STD_LOGIC;
  signal s00_entry_pipeline_m_axi_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s00_entry_pipeline_m_axi_RLAST : STD_LOGIC;
  signal s00_entry_pipeline_m_axi_RREADY : STD_LOGIC;
  signal s00_entry_pipeline_m_axi_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s00_entry_pipeline_m_axi_RVALID : STD_LOGIC;
  signal s00_nodes_M_SC_AR_PAYLD : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal s00_nodes_M_SC_AR_RECV : STD_LOGIC;
  signal s00_nodes_M_SC_AR_REQ : STD_LOGIC;
  signal s00_nodes_M_SC_AR_SEND : STD_LOGIC;
  signal s00_nodes_M_SC_R_PAYLD : STD_LOGIC_VECTOR ( 52 downto 18 );
  signal s00_nodes_M_SC_R_RECV : STD_LOGIC;
  signal s00_nodes_M_SC_R_SEND : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_entry_pipeline_m_axi_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_entry_pipeline_m_axi_ARLOCK : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal s01_entry_pipeline_m_axi_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_entry_pipeline_m_axi_ARREADY : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_ARUSER : STD_LOGIC_VECTOR ( 185 downto 64 );
  signal s01_entry_pipeline_m_axi_ARVALID : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_entry_pipeline_m_axi_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_entry_pipeline_m_axi_AWLOCK : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal s01_entry_pipeline_m_axi_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_entry_pipeline_m_axi_AWREADY : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_AWUSER : STD_LOGIC_VECTOR ( 185 downto 64 );
  signal s01_entry_pipeline_m_axi_AWVALID : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_BREADY : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s01_entry_pipeline_m_axi_BVALID : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_entry_pipeline_m_axi_RLAST : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_RREADY : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal s01_entry_pipeline_m_axi_RVALID : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal s01_entry_pipeline_m_axi_WLAST : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_WREADY : STD_LOGIC;
  signal s01_entry_pipeline_m_axi_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s01_entry_pipeline_m_axi_WUSER : STD_LOGIC_VECTOR ( 77 downto 64 );
  signal s01_entry_pipeline_m_axi_WVALID : STD_LOGIC;
  signal s01_nodes_M_SC_AR_PAYLD : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal s01_nodes_M_SC_AR_RECV : STD_LOGIC;
  signal s01_nodes_M_SC_AR_REQ : STD_LOGIC;
  signal s01_nodes_M_SC_AR_SEND : STD_LOGIC;
  signal s01_nodes_M_SC_AW_PAYLD : STD_LOGIC_VECTOR ( 139 downto 1 );
  signal s01_nodes_M_SC_AW_RECV : STD_LOGIC;
  signal s01_nodes_M_SC_AW_REQ : STD_LOGIC;
  signal s01_nodes_M_SC_AW_SEND : STD_LOGIC;
  signal s01_nodes_M_SC_B_PAYLD : STD_LOGIC_VECTOR ( 6 downto 5 );
  signal s01_nodes_M_SC_B_RECV : STD_LOGIC;
  signal s01_nodes_M_SC_B_SEND : STD_LOGIC;
  signal s01_nodes_M_SC_R_PAYLD : STD_LOGIC_VECTOR ( 52 downto 18 );
  signal s01_nodes_M_SC_R_RECV : STD_LOGIC;
  signal s01_nodes_M_SC_R_SEND : STD_LOGIC;
  signal s01_nodes_M_SC_W_INFO : STD_LOGIC;
  signal s01_nodes_M_SC_W_PAYLD : STD_LOGIC_VECTOR ( 159 downto 1 );
  signal s01_nodes_M_SC_W_RECV : STD_LOGIC;
  signal s01_nodes_M_SC_W_REQ : STD_LOGIC;
  signal s01_nodes_M_SC_W_SEND : STD_LOGIC;
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of m00_sc2axi : label is "sc_sc2axi_v1_0_10_top,Vivado 2024.2";
  attribute X_CORE_INFO of s00_axi2sc : label is "sc_axi2sc_v1_0_10_top,Vivado 2024.2";
  attribute X_CORE_INFO of s01_axi2sc : label is "sc_axi2sc_v1_0_10_top,Vivado 2024.2";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of M00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
  attribute X_INTERFACE_INFO of M00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
  attribute X_INTERFACE_INFO of M00_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
  attribute X_INTERFACE_INFO of M00_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
  attribute X_INTERFACE_INFO of M00_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
  attribute X_INTERFACE_INFO of M00_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
  attribute X_INTERFACE_INFO of M00_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RLAST";
  attribute X_INTERFACE_INFO of M00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
  attribute X_INTERFACE_INFO of M00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
  attribute X_INTERFACE_INFO of M00_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WLAST";
  attribute X_INTERFACE_INFO of M00_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
  attribute X_INTERFACE_INFO of M00_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
  attribute X_INTERFACE_INFO of S00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
  attribute X_INTERFACE_INFO of S00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
  attribute X_INTERFACE_INFO of S00_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RLAST";
  attribute X_INTERFACE_INFO of S00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
  attribute X_INTERFACE_INFO of S00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
  attribute X_INTERFACE_INFO of S01_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARREADY";
  attribute X_INTERFACE_INFO of S01_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARVALID";
  attribute X_INTERFACE_INFO of S01_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWREADY";
  attribute X_INTERFACE_INFO of S01_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWVALID";
  attribute X_INTERFACE_INFO of S01_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BREADY";
  attribute X_INTERFACE_INFO of S01_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BVALID";
  attribute X_INTERFACE_INFO of S01_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RLAST";
  attribute X_INTERFACE_INFO of S01_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RREADY";
  attribute X_INTERFACE_INFO of S01_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RVALID";
  attribute X_INTERFACE_INFO of S01_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WLAST";
  attribute X_INTERFACE_INFO of S01_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WREADY";
  attribute X_INTERFACE_INFO of S01_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WVALID";
  attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
  attribute X_INTERFACE_MODE : string;
  attribute X_INTERFACE_MODE of aclk : signal is "slave";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 249999954, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
  attribute X_INTERFACE_MODE of aresetn : signal is "slave aux_reset";
  attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
  attribute X_INTERFACE_MODE of M00_AXI_araddr : signal is "Master";
  attribute X_INTERFACE_PARAMETER of M00_AXI_araddr : signal is "XIL_INTERFACENAME M00_AXI, ADDR_WIDTH 49, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, DATA_WIDTH 128, FREQ_HZ 249999954, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 4, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
  attribute X_INTERFACE_INFO of M00_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST";
  attribute X_INTERFACE_INFO of M00_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE";
  attribute X_INTERFACE_INFO of M00_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN";
  attribute X_INTERFACE_INFO of M00_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK";
  attribute X_INTERFACE_INFO of M00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
  attribute X_INTERFACE_INFO of M00_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS";
  attribute X_INTERFACE_INFO of M00_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE";
  attribute X_INTERFACE_INFO of M00_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
  attribute X_INTERFACE_INFO of M00_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST";
  attribute X_INTERFACE_INFO of M00_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE";
  attribute X_INTERFACE_INFO of M00_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN";
  attribute X_INTERFACE_INFO of M00_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK";
  attribute X_INTERFACE_INFO of M00_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
  attribute X_INTERFACE_INFO of M00_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS";
  attribute X_INTERFACE_INFO of M00_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE";
  attribute X_INTERFACE_INFO of M00_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
  attribute X_INTERFACE_INFO of M00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
  attribute X_INTERFACE_INFO of M00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
  attribute X_INTERFACE_INFO of M00_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
  attribute X_INTERFACE_INFO of M00_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
  attribute X_INTERFACE_INFO of S00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
  attribute X_INTERFACE_MODE of S00_AXI_araddr : signal is "Slave";
  attribute X_INTERFACE_PARAMETER of S00_AXI_araddr : signal is "XIL_INTERFACENAME S00_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, DATA_WIDTH 32, FREQ_HZ 249999954, HAS_BRESP 0, HAS_BURST 0, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 0, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4, READ_WRITE_MODE READ_ONLY, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
  attribute X_INTERFACE_INFO of S00_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST";
  attribute X_INTERFACE_INFO of S00_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE";
  attribute X_INTERFACE_INFO of S00_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN";
  attribute X_INTERFACE_INFO of S00_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK";
  attribute X_INTERFACE_INFO of S00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
  attribute X_INTERFACE_INFO of S00_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS";
  attribute X_INTERFACE_INFO of S00_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE";
  attribute X_INTERFACE_INFO of S00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
  attribute X_INTERFACE_INFO of S00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
  attribute X_INTERFACE_INFO of S01_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARADDR";
  attribute X_INTERFACE_MODE of S01_AXI_araddr : signal is "Slave";
  attribute X_INTERFACE_PARAMETER of S01_AXI_araddr : signal is "XIL_INTERFACENAME S01_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, DATA_WIDTH 32, FREQ_HZ 249999954, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
  attribute X_INTERFACE_INFO of S01_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARBURST";
  attribute X_INTERFACE_INFO of S01_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE";
  attribute X_INTERFACE_INFO of S01_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARLEN";
  attribute X_INTERFACE_INFO of S01_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK";
  attribute X_INTERFACE_INFO of S01_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARPROT";
  attribute X_INTERFACE_INFO of S01_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARQOS";
  attribute X_INTERFACE_INFO of S01_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE";
  attribute X_INTERFACE_INFO of S01_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWADDR";
  attribute X_INTERFACE_MODE of S01_AXI_awaddr : signal is "slave";
  attribute X_INTERFACE_PARAMETER of S01_AXI_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 249999954, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of S01_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWBURST";
  attribute X_INTERFACE_INFO of S01_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE";
  attribute X_INTERFACE_INFO of S01_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWLEN";
  attribute X_INTERFACE_INFO of S01_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK";
  attribute X_INTERFACE_INFO of S01_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWPROT";
  attribute X_INTERFACE_INFO of S01_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWQOS";
  attribute X_INTERFACE_INFO of S01_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE";
  attribute X_INTERFACE_INFO of S01_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BRESP";
  attribute X_INTERFACE_INFO of S01_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RDATA";
  attribute X_INTERFACE_INFO of S01_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RRESP";
  attribute X_INTERFACE_INFO of S01_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WDATA";
  attribute X_INTERFACE_INFO of S01_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WSTRB";
begin
  M00_AXI_araddr(48) <= \<const0>\;
  M00_AXI_araddr(47) <= \<const0>\;
  M00_AXI_araddr(46) <= \<const0>\;
  M00_AXI_araddr(45) <= \<const0>\;
  M00_AXI_araddr(44) <= \<const0>\;
  M00_AXI_araddr(43) <= \<const0>\;
  M00_AXI_araddr(42) <= \<const0>\;
  M00_AXI_araddr(41) <= \<const0>\;
  M00_AXI_araddr(40) <= \<const0>\;
  M00_AXI_araddr(39) <= \<const0>\;
  M00_AXI_araddr(38) <= \<const0>\;
  M00_AXI_araddr(37) <= \<const0>\;
  M00_AXI_araddr(36) <= \<const0>\;
  M00_AXI_araddr(35) <= \<const0>\;
  M00_AXI_araddr(34) <= \<const0>\;
  M00_AXI_araddr(33) <= \<const0>\;
  M00_AXI_araddr(32) <= \<const0>\;
  M00_AXI_araddr(31 downto 0) <= \^m00_axi_araddr\(31 downto 0);
  M00_AXI_arburst(1) <= \<const0>\;
  M00_AXI_arburst(0) <= \<const0>\;
  M00_AXI_arlock(0) <= \<const0>\;
  M00_AXI_awaddr(48) <= \<const0>\;
  M00_AXI_awaddr(47) <= \<const0>\;
  M00_AXI_awaddr(46) <= \<const0>\;
  M00_AXI_awaddr(45) <= \<const0>\;
  M00_AXI_awaddr(44) <= \<const0>\;
  M00_AXI_awaddr(43) <= \<const0>\;
  M00_AXI_awaddr(42) <= \<const0>\;
  M00_AXI_awaddr(41) <= \<const0>\;
  M00_AXI_awaddr(40) <= \<const0>\;
  M00_AXI_awaddr(39) <= \<const0>\;
  M00_AXI_awaddr(38) <= \<const0>\;
  M00_AXI_awaddr(37) <= \<const0>\;
  M00_AXI_awaddr(36) <= \<const0>\;
  M00_AXI_awaddr(35) <= \<const0>\;
  M00_AXI_awaddr(34) <= \<const0>\;
  M00_AXI_awaddr(33) <= \<const0>\;
  M00_AXI_awaddr(32) <= \<const0>\;
  M00_AXI_awaddr(31 downto 0) <= \^m00_axi_awaddr\(31 downto 0);
  M00_AXI_awburst(1) <= \<const0>\;
  M00_AXI_awburst(0) <= \<const0>\;
  M00_AXI_awlock(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
clk_map: entity work.Loopback_smartconnect_0_0_clk_map_imp_USF1QV
     port map (
      aclk => aclk,
      aresetn => aresetn,
      interconnect_aresetn(0) => m_axi_aresetn_1
    );
m00_exit_pipeline: entity work.Loopback_smartconnect_0_0_m00_exit_pipeline_imp_15PRL8S
     port map (
      M00_AXI_araddr(31 downto 0) => \^m00_axi_araddr\(31 downto 0),
      M00_AXI_arcache(3 downto 0) => M00_AXI_arcache(3 downto 0),
      M00_AXI_arlen(7 downto 0) => M00_AXI_arlen(7 downto 0),
      M00_AXI_arprot(2 downto 0) => M00_AXI_arprot(2 downto 0),
      M00_AXI_arqos(3 downto 0) => M00_AXI_arqos(3 downto 0),
      M00_AXI_arready => M00_AXI_arready,
      M00_AXI_arsize(2 downto 0) => M00_AXI_arsize(2 downto 0),
      M00_AXI_arvalid => M00_AXI_arvalid,
      M00_AXI_awaddr(31 downto 0) => \^m00_axi_awaddr\(31 downto 0),
      M00_AXI_awcache(3 downto 0) => M00_AXI_awcache(3 downto 0),
      M00_AXI_awlen(7 downto 0) => M00_AXI_awlen(7 downto 0),
      M00_AXI_awprot(2 downto 0) => M00_AXI_awprot(2 downto 0),
      M00_AXI_awqos(3 downto 0) => M00_AXI_awqos(3 downto 0),
      M00_AXI_awready => M00_AXI_awready,
      M00_AXI_awsize(2 downto 0) => M00_AXI_awsize(2 downto 0),
      M00_AXI_awvalid => M00_AXI_awvalid,
      M00_AXI_bready => M00_AXI_bready,
      M00_AXI_bresp(1 downto 0) => M00_AXI_bresp(1 downto 0),
      M00_AXI_bvalid => M00_AXI_bvalid,
      M00_AXI_rdata(127 downto 0) => M00_AXI_rdata(127 downto 0),
      M00_AXI_rlast => M00_AXI_rlast,
      M00_AXI_rready => M00_AXI_rready,
      M00_AXI_rresp(1 downto 0) => M00_AXI_rresp(1 downto 0),
      M00_AXI_rvalid => M00_AXI_rvalid,
      M00_AXI_wdata(127 downto 0) => M00_AXI_wdata(127 downto 0),
      M00_AXI_wlast => M00_AXI_wlast,
      M00_AXI_wready => M00_AXI_wready,
      M00_AXI_wstrb(15 downto 0) => M00_AXI_wstrb(15 downto 0),
      M00_AXI_wvalid => M00_AXI_wvalid,
      aclk => aclk,
      interconnect_aresetn(0) => m_axi_aresetn_1,
      m_axi_araddr(31 downto 0) => m00_sc2axi_M_AXI_ARADDR(31 downto 0),
      m_axi_arcache(3 downto 0) => m00_sc2axi_M_AXI_ARCACHE(3 downto 0),
      m_axi_arid(1 downto 0) => m00_sc2axi_M_AXI_ARID(1 downto 0),
      m_axi_arlen(7 downto 0) => m00_sc2axi_M_AXI_ARLEN(7 downto 0),
      m_axi_arprot(2 downto 0) => m00_sc2axi_M_AXI_ARPROT(2 downto 0),
      m_axi_arqos(3 downto 0) => m00_sc2axi_M_AXI_ARQOS(3 downto 0),
      m_axi_aruser(17 downto 11) => m00_sc2axi_M_AXI_ARUSER(185 downto 179),
      m_axi_aruser(10 downto 0) => m00_sc2axi_M_AXI_ARUSER(146 downto 136),
      m_axi_arvalid => m00_sc2axi_M_AXI_ARVALID,
      m_axi_awaddr(31 downto 0) => m00_sc2axi_M_AXI_AWADDR(31 downto 0),
      m_axi_awcache(3 downto 0) => m00_sc2axi_M_AXI_AWCACHE(3 downto 0),
      m_axi_awid(1 downto 0) => m00_sc2axi_M_AXI_AWID(1 downto 0),
      m_axi_awlen(7 downto 0) => m00_sc2axi_M_AXI_AWLEN(7 downto 0),
      m_axi_awprot(2 downto 0) => m00_sc2axi_M_AXI_AWPROT(2 downto 0),
      m_axi_awqos(3 downto 0) => m00_sc2axi_M_AXI_AWQOS(3 downto 0),
      m_axi_awuser(10 downto 0) => m00_sc2axi_M_AXI_AWUSER(146 downto 136),
      m_axi_awvalid => m00_sc2axi_M_AXI_AWVALID,
      m_axi_bready => m00_sc2axi_M_AXI_BREADY,
      m_axi_rready => m00_sc2axi_M_AXI_RREADY,
      m_axi_wdata(127 downto 0) => m00_sc2axi_M_AXI_WDATA(127 downto 0),
      m_axi_wlast => m00_sc2axi_M_AXI_WLAST,
      m_axi_wstrb(15 downto 0) => m00_sc2axi_M_AXI_WSTRB(15 downto 0),
      m_axi_wvalid => m00_sc2axi_M_AXI_WVALID,
      s_axi_arready => m00_sc2axi_M_AXI_ARREADY,
      s_axi_awready => m00_sc2axi_M_AXI_AWREADY,
      s_axi_bid(1 downto 0) => m00_sc2axi_M_AXI_BID(1 downto 0),
      s_axi_bresp(1 downto 0) => m00_sc2axi_M_AXI_BRESP(1 downto 0),
      s_axi_buser(1 downto 0) => m00_sc2axi_M_AXI_BUSER(1 downto 0),
      s_axi_bvalid => m00_sc2axi_M_AXI_BVALID,
      s_axi_rdata(127 downto 0) => m00_sc2axi_M_AXI_RDATA(127 downto 0),
      s_axi_rid(1 downto 0) => m00_sc2axi_M_AXI_RID(1 downto 0),
      s_axi_rlast => m00_sc2axi_M_AXI_RLAST,
      s_axi_rresp(1 downto 0) => m00_sc2axi_M_AXI_RRESP(1 downto 0),
      s_axi_ruser(15 downto 2) => m00_sc2axi_M_AXI_RUSER(77 downto 64),
      s_axi_ruser(1 downto 0) => m00_sc2axi_M_AXI_RUSER(1 downto 0),
      s_axi_rvalid => m00_sc2axi_M_AXI_RVALID,
      s_axi_wready => m00_sc2axi_M_AXI_WREADY
    );
m00_nodes: entity work.Loopback_smartconnect_0_0_m00_nodes_imp_1J21SGW
     port map (
      M00_SC_AR_payld(82 downto 13) => S_SC_AR_3_PAYLD(139 downto 70),
      M00_SC_AR_payld(12 downto 0) => S_SC_AR_3_PAYLD(13 downto 1),
      M00_SC_AR_req(1 downto 0) => S_SC_AR_3_REQ(1 downto 0),
      M00_SC_AR_send(1 downto 0) => S_SC_AR_3_SEND(1 downto 0),
      M00_SC_AW_payld(82 downto 13) => S_SC_AW_2_PAYLD(139 downto 70),
      M00_SC_AW_payld(12 downto 0) => S_SC_AW_2_PAYLD(13 downto 1),
      M00_SC_AW_req(0) => S_SC_AW_2_REQ(1),
      M00_SC_AW_send(0) => S_SC_AW_2_SEND(1),
      M00_SC_W_info(0) => S_SC_W_2_INFO(1),
      M00_SC_W_payld(147 downto 2) => S_SC_W_2_PAYLD(159 downto 14),
      M00_SC_W_payld(1) => S_SC_W_2_PAYLD(8),
      M00_SC_W_payld(0) => S_SC_W_2_PAYLD(1),
      M00_SC_W_req(0) => S_SC_W_2_REQ(1),
      M00_SC_W_send(0) => S_SC_W_2_SEND(1),
      M_SC_AR_payld(70 downto 60) => m00_nodes_M_SC_AR_PAYLD(139 downto 129),
      M_SC_AR_payld(59 downto 26) => m00_nodes_M_SC_AR_PAYLD(127 downto 94),
      M_SC_AR_payld(25 downto 19) => m00_nodes_M_SC_AR_PAYLD(92 downto 86),
      M_SC_AR_payld(18 downto 8) => m00_nodes_M_SC_AR_PAYLD(83 downto 73),
      M_SC_AR_payld(7 downto 0) => m00_nodes_M_SC_AR_PAYLD(8 downto 1),
      M_SC_AR_recv(0) => m00_nodes_M_SC_AR_RECV,
      M_SC_AR_send(0) => m00_nodes_M_SC_AR_SEND,
      M_SC_AW_payld(63 downto 53) => m00_nodes_M_SC_AW_PAYLD(139 downto 129),
      M_SC_AW_payld(52 downto 19) => m00_nodes_M_SC_AW_PAYLD(127 downto 94),
      M_SC_AW_payld(18 downto 8) => m00_nodes_M_SC_AW_PAYLD(83 downto 73),
      M_SC_AW_payld(7 downto 0) => m00_nodes_M_SC_AW_PAYLD(8 downto 1),
      M_SC_AW_recv(0) => m00_nodes_M_SC_AW_RECV,
      M_SC_AW_send(0) => m00_nodes_M_SC_AW_SEND,
      M_SC_B_payld(5 downto 0) => m00_nodes_M_SC_B_PAYLD(6 downto 1),
      M_SC_B_send(0) => m00_nodes_M_SC_B_SEND(1),
      M_SC_R_payld(138 downto 4) => m00_nodes_M_SC_R_PAYLD(148 downto 14),
      M_SC_R_payld(3 downto 2) => m00_nodes_M_SC_R_PAYLD(12 downto 11),
      M_SC_R_payld(1 downto 0) => m00_nodes_M_SC_R_PAYLD(5 downto 4),
      M_SC_R_send(1 downto 0) => m00_nodes_M_SC_R_SEND(1 downto 0),
      M_SC_W_payld(144 downto 0) => m00_nodes_M_SC_W_PAYLD(159 downto 15),
      M_SC_W_recv(0) => m00_nodes_M_SC_W_RECV,
      M_SC_W_send(0) => m00_nodes_M_SC_W_SEND,
      S00_SC_B_recv(0) => m00_nodes_M_SC_B_RECV(1),
      S00_SC_R_recv(1 downto 0) => m00_nodes_M_SC_R_RECV(1 downto 0),
      S_SC_AR_recv(1 downto 0) => S_SC_AR_3_RECV(1 downto 0),
      S_SC_AW_recv(0) => S_SC_AW_2_RECV(1),
      S_SC_B_payld(5 downto 2) => S_SC_B_2_PAYLD(6 downto 3),
      S_SC_B_payld(1 downto 0) => S_SC_B_2_PAYLD(1 downto 0),
      S_SC_B_recv(0) => S_SC_B_2_RECV,
      S_SC_B_send(0) => S_SC_B_2_SEND,
      S_SC_R_payld(148 downto 0) => S_SC_R_3_PAYLD(148 downto 0),
      S_SC_R_recv(0) => S_SC_R_3_RECV,
      S_SC_R_send(0) => S_SC_R_3_SEND,
      S_SC_W_recv(0) => S_SC_W_2_RECV(1),
      aclk => aclk,
      interconnect_aresetn(0) => m_axi_aresetn_1
    );
m00_sc2axi: entity work.Loopback_smartconnect_0_0_bd_e34c_m00s2a_0
     port map (
      M_SC_AR_payld(70 downto 60) => m00_nodes_M_SC_AR_PAYLD(139 downto 129),
      M_SC_AR_payld(59 downto 26) => m00_nodes_M_SC_AR_PAYLD(127 downto 94),
      M_SC_AR_payld(25 downto 19) => m00_nodes_M_SC_AR_PAYLD(92 downto 86),
      M_SC_AR_payld(18 downto 8) => m00_nodes_M_SC_AR_PAYLD(83 downto 73),
      M_SC_AR_payld(7 downto 0) => m00_nodes_M_SC_AR_PAYLD(8 downto 1),
      M_SC_AR_send(0) => m00_nodes_M_SC_AR_SEND,
      M_SC_AW_payld(63 downto 53) => m00_nodes_M_SC_AW_PAYLD(139 downto 129),
      M_SC_AW_payld(52 downto 19) => m00_nodes_M_SC_AW_PAYLD(127 downto 94),
      M_SC_AW_payld(18 downto 8) => m00_nodes_M_SC_AW_PAYLD(83 downto 73),
      M_SC_AW_payld(7 downto 0) => m00_nodes_M_SC_AW_PAYLD(8 downto 1),
      M_SC_AW_send(0) => m00_nodes_M_SC_AW_SEND,
      M_SC_W_payld(144 downto 0) => m00_nodes_M_SC_W_PAYLD(159 downto 15),
      M_SC_W_send(0) => m00_nodes_M_SC_W_SEND,
      S_SC_B_recv(0) => S_SC_B_2_RECV,
      S_SC_R_recv(0) => S_SC_R_3_RECV,
      m_axi_araddr(31 downto 0) => m00_sc2axi_M_AXI_ARADDR(31 downto 0),
      m_axi_arcache(3 downto 0) => m00_sc2axi_M_AXI_ARCACHE(3 downto 0),
      m_axi_arid(1 downto 0) => m00_sc2axi_M_AXI_ARID(1 downto 0),
      m_axi_arlen(7 downto 0) => m00_sc2axi_M_AXI_ARLEN(7 downto 0),
      m_axi_arprot(2 downto 0) => m00_sc2axi_M_AXI_ARPROT(2 downto 0),
      m_axi_arqos(3 downto 0) => m00_sc2axi_M_AXI_ARQOS(3 downto 0),
      m_axi_aruser(17 downto 11) => m00_sc2axi_M_AXI_ARUSER(185 downto 179),
      m_axi_aruser(10 downto 0) => m00_sc2axi_M_AXI_ARUSER(146 downto 136),
      m_axi_arvalid => m00_sc2axi_M_AXI_ARVALID,
      m_axi_awaddr(31 downto 0) => m00_sc2axi_M_AXI_AWADDR(31 downto 0),
      m_axi_awcache(3 downto 0) => m00_sc2axi_M_AXI_AWCACHE(3 downto 0),
      m_axi_awid(1 downto 0) => m00_sc2axi_M_AXI_AWID(1 downto 0),
      m_axi_awlen(7 downto 0) => m00_sc2axi_M_AXI_AWLEN(7 downto 0),
      m_axi_awprot(2 downto 0) => m00_sc2axi_M_AXI_AWPROT(2 downto 0),
      m_axi_awqos(3 downto 0) => m00_sc2axi_M_AXI_AWQOS(3 downto 0),
      m_axi_awuser(10 downto 0) => m00_sc2axi_M_AXI_AWUSER(146 downto 136),
      m_axi_awvalid => m00_sc2axi_M_AXI_AWVALID,
      m_axi_bready => m00_sc2axi_M_AXI_BREADY,
      m_axi_rready => m00_sc2axi_M_AXI_RREADY,
      m_axi_wdata(127 downto 0) => m00_sc2axi_M_AXI_WDATA(127 downto 0),
      m_axi_wlast => m00_sc2axi_M_AXI_WLAST,
      m_axi_wstrb(15 downto 0) => m00_sc2axi_M_AXI_WSTRB(15 downto 0),
      m_axi_wvalid => m00_sc2axi_M_AXI_WVALID,
      m_sc_b_payld(5 downto 2) => S_SC_B_2_PAYLD(6 downto 3),
      m_sc_b_payld(1 downto 0) => S_SC_B_2_PAYLD(1 downto 0),
      m_sc_b_send => S_SC_B_2_SEND,
      m_sc_r_payld(148 downto 0) => S_SC_R_3_PAYLD(148 downto 0),
      m_sc_r_send => S_SC_R_3_SEND,
      s_axi_arready => m00_sc2axi_M_AXI_ARREADY,
      s_axi_awready => m00_sc2axi_M_AXI_AWREADY,
      s_axi_bid(1 downto 0) => m00_sc2axi_M_AXI_BID(1 downto 0),
      s_axi_bresp(1 downto 0) => m00_sc2axi_M_AXI_BRESP(1 downto 0),
      s_axi_buser(1 downto 0) => m00_sc2axi_M_AXI_BUSER(1 downto 0),
      s_axi_bvalid => m00_sc2axi_M_AXI_BVALID,
      s_axi_rdata(127 downto 0) => m00_sc2axi_M_AXI_RDATA(127 downto 0),
      s_axi_rid(1 downto 0) => m00_sc2axi_M_AXI_RID(1 downto 0),
      s_axi_rlast => m00_sc2axi_M_AXI_RLAST,
      s_axi_rresp(1 downto 0) => m00_sc2axi_M_AXI_RRESP(1 downto 0),
      s_axi_ruser(15 downto 2) => m00_sc2axi_M_AXI_RUSER(77 downto 64),
      s_axi_ruser(1 downto 0) => m00_sc2axi_M_AXI_RUSER(1 downto 0),
      s_axi_rvalid => m00_sc2axi_M_AXI_RVALID,
      s_axi_wready => m00_sc2axi_M_AXI_WREADY,
      s_sc_ar_recv => m00_nodes_M_SC_AR_RECV,
      s_sc_aw_recv => m00_nodes_M_SC_AW_RECV,
      s_sc_w_recv => m00_nodes_M_SC_W_RECV
    );
s00_axi2sc: entity work.Loopback_smartconnect_0_0_bd_e34c_s00a2s_0
     port map (
      M_SC_R_payld(34 downto 0) => s00_nodes_M_SC_R_PAYLD(52 downto 18),
      M_SC_R_recv(0) => s00_nodes_M_SC_R_RECV,
      M_SC_R_send(0) => s00_nodes_M_SC_R_SEND,
      S_SC_AR_payld(68 downto 25) => S_SC_AR_1_PAYLD(139 downto 96),
      S_SC_AR_payld(24 downto 18) => S_SC_AR_1_PAYLD(92 downto 86),
      S_SC_AR_payld(17 downto 7) => S_SC_AR_1_PAYLD(83 downto 73),
      S_SC_AR_payld(6 downto 0) => S_SC_AR_1_PAYLD(7 downto 1),
      S_SC_AR_recv(0) => S_SC_AR_1_RECV,
      S_SC_AR_send(0) => S_SC_AR_1_SEND,
      m_axi_araddr(31 downto 0) => s00_entry_pipeline_m_axi_ARADDR(31 downto 0),
      m_axi_arcache(3 downto 0) => s00_entry_pipeline_m_axi_ARCACHE(3 downto 0),
      m_axi_arlock(0) => s00_entry_pipeline_m_axi_ARLOCK,
      m_axi_arprot(2 downto 0) => s00_entry_pipeline_m_axi_ARPROT(2 downto 0),
      m_axi_arqos(3 downto 0) => s00_entry_pipeline_m_axi_ARQOS(3 downto 0),
      m_axi_aruser(24 downto 18) => s00_entry_pipeline_m_axi_ARUSER(185 downto 179),
      m_axi_aruser(17 downto 7) => s00_entry_pipeline_m_axi_ARUSER(146 downto 136),
      m_axi_aruser(6 downto 0) => s00_entry_pipeline_m_axi_ARUSER(70 downto 64),
      m_axi_arvalid => s00_entry_pipeline_m_axi_ARVALID,
      m_axi_rready => s00_entry_pipeline_m_axi_RREADY,
      s_axi_arready => s00_entry_pipeline_m_axi_ARREADY,
      s_axi_rdata(31 downto 0) => s00_entry_pipeline_m_axi_RDATA(31 downto 0),
      s_axi_rlast => s00_entry_pipeline_m_axi_RLAST,
      s_axi_rresp(1 downto 0) => s00_entry_pipeline_m_axi_RRESP(1 downto 0),
      s_axi_rvalid => s00_entry_pipeline_m_axi_RVALID
    );
s00_entry_pipeline: entity work.Loopback_smartconnect_0_0_s00_entry_pipeline_imp_5Y6K3Z
     port map (
      S00_AXI_araddr(31 downto 0) => S00_AXI_araddr(31 downto 0),
      S00_AXI_arburst(1 downto 0) => S00_AXI_arburst(1 downto 0),
      S00_AXI_arcache(3 downto 0) => S00_AXI_arcache(3 downto 0),
      S00_AXI_arlen(7 downto 0) => S00_AXI_arlen(7 downto 0),
      S00_AXI_arlock(0) => S00_AXI_arlock(0),
      S00_AXI_arprot(2 downto 0) => S00_AXI_arprot(2 downto 0),
      S00_AXI_arqos(3 downto 0) => S00_AXI_arqos(3 downto 0),
      S00_AXI_arready => S00_AXI_arready,
      S00_AXI_arsize(2 downto 0) => S00_AXI_arsize(2 downto 0),
      S00_AXI_arvalid => S00_AXI_arvalid,
      S00_AXI_rdata(31 downto 0) => S00_AXI_rdata(31 downto 0),
      S00_AXI_rlast => S00_AXI_rlast,
      S00_AXI_rready => S00_AXI_rready,
      S00_AXI_rresp(1 downto 0) => S00_AXI_rresp(1 downto 0),
      S00_AXI_rvalid => S00_AXI_rvalid,
      aclk => aclk,
      interconnect_aresetn(0) => m_axi_aresetn_1,
      m_axi_araddr(31 downto 0) => s00_entry_pipeline_m_axi_ARADDR(31 downto 0),
      m_axi_arcache(3 downto 0) => s00_entry_pipeline_m_axi_ARCACHE(3 downto 0),
      m_axi_arlock(0) => s00_entry_pipeline_m_axi_ARLOCK,
      m_axi_arprot(2 downto 0) => s00_entry_pipeline_m_axi_ARPROT(2 downto 0),
      m_axi_arqos(3 downto 0) => s00_entry_pipeline_m_axi_ARQOS(3 downto 0),
      m_axi_aruser(24 downto 18) => s00_entry_pipeline_m_axi_ARUSER(185 downto 179),
      m_axi_aruser(17 downto 7) => s00_entry_pipeline_m_axi_ARUSER(146 downto 136),
      m_axi_aruser(6 downto 0) => s00_entry_pipeline_m_axi_ARUSER(70 downto 64),
      m_axi_arvalid => s00_entry_pipeline_m_axi_ARVALID,
      m_axi_rready => s00_entry_pipeline_m_axi_RREADY,
      s_axi_arready => s00_entry_pipeline_m_axi_ARREADY,
      s_axi_rdata(31 downto 0) => s00_entry_pipeline_m_axi_RDATA(31 downto 0),
      s_axi_rlast => s00_entry_pipeline_m_axi_RLAST,
      s_axi_rresp(1 downto 0) => s00_entry_pipeline_m_axi_RRESP(1 downto 0),
      s_axi_rvalid => s00_entry_pipeline_m_axi_RVALID
    );
s00_nodes: entity work.Loopback_smartconnect_0_0_s00_nodes_imp_7T00L
     port map (
      M00_SC_R_payld(138 downto 4) => S_SC_R_1_PAYLD(148 downto 14),
      M00_SC_R_payld(3 downto 2) => S_SC_R_1_PAYLD(12 downto 11),
      M00_SC_R_payld(1 downto 0) => S_SC_R_1_PAYLD(5 downto 4),
      M00_SC_R_send(0) => S_SC_R_1_SEND,
      M_SC_AR_payld(82 downto 13) => s00_nodes_M_SC_AR_PAYLD(139 downto 70),
      M_SC_AR_payld(12 downto 0) => s00_nodes_M_SC_AR_PAYLD(13 downto 1),
      M_SC_AR_req(0) => s00_nodes_M_SC_AR_REQ,
      M_SC_AR_send(0) => s00_nodes_M_SC_AR_SEND,
      M_SC_R_payld(34 downto 0) => s00_nodes_M_SC_R_PAYLD(52 downto 18),
      M_SC_R_recv(0) => s00_nodes_M_SC_R_RECV,
      M_SC_R_send(0) => s00_nodes_M_SC_R_SEND,
      S00_SC_AR_recv(0) => s00_nodes_M_SC_AR_RECV,
      S_SC_AR_payld(68 downto 25) => S_SC_AR_1_PAYLD(139 downto 96),
      S_SC_AR_payld(24 downto 18) => S_SC_AR_1_PAYLD(92 downto 86),
      S_SC_AR_payld(17 downto 7) => S_SC_AR_1_PAYLD(83 downto 73),
      S_SC_AR_payld(6 downto 0) => S_SC_AR_1_PAYLD(7 downto 1),
      S_SC_AR_recv(0) => S_SC_AR_1_RECV,
      S_SC_AR_send(0) => S_SC_AR_1_SEND,
      S_SC_R_recv(0) => S_SC_R_1_RECV,
      aclk => aclk,
      interconnect_aresetn(0) => m_axi_aresetn_1
    );
s01_axi2sc: entity work.Loopback_smartconnect_0_0_bd_e34c_s01a2s_0
     port map (
      M_SC_B_payld(1 downto 0) => s01_nodes_M_SC_B_PAYLD(6 downto 5),
      M_SC_B_recv(0) => s01_nodes_M_SC_B_RECV,
      M_SC_B_send(0) => s01_nodes_M_SC_B_SEND,
      M_SC_R_payld(34 downto 0) => s01_nodes_M_SC_R_PAYLD(52 downto 18),
      M_SC_R_recv(0) => s01_nodes_M_SC_R_RECV,
      M_SC_R_send(0) => s01_nodes_M_SC_R_SEND,
      S_SC_AR_payld(68 downto 25) => S_SC_AR_2_PAYLD(139 downto 96),
      S_SC_AR_payld(24 downto 18) => S_SC_AR_2_PAYLD(92 downto 86),
      S_SC_AR_payld(17 downto 7) => S_SC_AR_2_PAYLD(83 downto 73),
      S_SC_AR_payld(6 downto 0) => S_SC_AR_2_PAYLD(7 downto 1),
      S_SC_AR_recv(0) => S_SC_AR_2_RECV,
      S_SC_AR_send(0) => S_SC_AR_2_SEND,
      S_SC_AW_payld(68 downto 25) => S_SC_AW_1_PAYLD(139 downto 96),
      S_SC_AW_payld(24 downto 18) => S_SC_AW_1_PAYLD(92 downto 86),
      S_SC_AW_payld(17 downto 7) => S_SC_AW_1_PAYLD(83 downto 73),
      S_SC_AW_payld(6 downto 0) => S_SC_AW_1_PAYLD(7 downto 1),
      S_SC_AW_recv(0) => S_SC_AW_1_RECV,
      S_SC_AW_send(0) => S_SC_AW_1_SEND,
      S_SC_W_payld(50 downto 0) => S_SC_W_1_PAYLD(51 downto 1),
      S_SC_W_recv(0) => S_SC_W_1_RECV,
      S_SC_W_send(0) => S_SC_W_1_SEND,
      m_axi_araddr(31 downto 0) => s01_entry_pipeline_m_axi_ARADDR(31 downto 0),
      m_axi_arcache(3 downto 0) => s01_entry_pipeline_m_axi_ARCACHE(3 downto 0),
      m_axi_arlock(0) => s01_entry_pipeline_m_axi_ARLOCK,
      m_axi_arprot(2 downto 0) => s01_entry_pipeline_m_axi_ARPROT(2 downto 0),
      m_axi_arqos(3 downto 0) => s01_entry_pipeline_m_axi_ARQOS(3 downto 0),
      m_axi_aruser(24 downto 18) => s01_entry_pipeline_m_axi_ARUSER(185 downto 179),
      m_axi_aruser(17 downto 7) => s01_entry_pipeline_m_axi_ARUSER(146 downto 136),
      m_axi_aruser(6 downto 0) => s01_entry_pipeline_m_axi_ARUSER(70 downto 64),
      m_axi_arvalid => s01_entry_pipeline_m_axi_ARVALID,
      m_axi_awaddr(31 downto 0) => s01_entry_pipeline_m_axi_AWADDR(31 downto 0),
      m_axi_awcache(3 downto 0) => s01_entry_pipeline_m_axi_AWCACHE(3 downto 0),
      m_axi_awlock(0) => s01_entry_pipeline_m_axi_AWLOCK,
      m_axi_awprot(2 downto 0) => s01_entry_pipeline_m_axi_AWPROT(2 downto 0),
      m_axi_awqos(3 downto 0) => s01_entry_pipeline_m_axi_AWQOS(3 downto 0),
      m_axi_awuser(24 downto 18) => s01_entry_pipeline_m_axi_AWUSER(185 downto 179),
      m_axi_awuser(17 downto 7) => s01_entry_pipeline_m_axi_AWUSER(146 downto 136),
      m_axi_awuser(6 downto 0) => s01_entry_pipeline_m_axi_AWUSER(70 downto 64),
      m_axi_awvalid => s01_entry_pipeline_m_axi_AWVALID,
      m_axi_bready => s01_entry_pipeline_m_axi_BREADY,
      m_axi_rready => s01_entry_pipeline_m_axi_RREADY,
      m_axi_wdata(31 downto 0) => s01_entry_pipeline_m_axi_WDATA(31 downto 0),
      m_axi_wlast => s01_entry_pipeline_m_axi_WLAST,
      m_axi_wstrb(3 downto 0) => s01_entry_pipeline_m_axi_WSTRB(3 downto 0),
      m_axi_wuser(13 downto 0) => s01_entry_pipeline_m_axi_WUSER(77 downto 64),
      m_axi_wvalid => s01_entry_pipeline_m_axi_WVALID,
      s_axi_arready => s01_entry_pipeline_m_axi_ARREADY,
      s_axi_awready => s01_entry_pipeline_m_axi_AWREADY,
      s_axi_bresp(1 downto 0) => s01_entry_pipeline_m_axi_BRESP(1 downto 0),
      s_axi_bvalid => s01_entry_pipeline_m_axi_BVALID,
      s_axi_rdata(31 downto 0) => s01_entry_pipeline_m_axi_RDATA(31 downto 0),
      s_axi_rlast => s01_entry_pipeline_m_axi_RLAST,
      s_axi_rresp(1 downto 0) => s01_entry_pipeline_m_axi_RRESP(1 downto 0),
      s_axi_rvalid => s01_entry_pipeline_m_axi_RVALID,
      s_axi_wready => s01_entry_pipeline_m_axi_WREADY
    );
s01_entry_pipeline: entity work.Loopback_smartconnect_0_0_s01_entry_pipeline_imp_13EI3DN
     port map (
      S01_AXI_araddr(31 downto 0) => S01_AXI_araddr(31 downto 0),
      S01_AXI_arburst(1 downto 0) => S01_AXI_arburst(1 downto 0),
      S01_AXI_arcache(3 downto 0) => S01_AXI_arcache(3 downto 0),
      S01_AXI_arlen(7 downto 0) => S01_AXI_arlen(7 downto 0),
      S01_AXI_arlock(0) => S01_AXI_arlock(0),
      S01_AXI_arprot(2 downto 0) => S01_AXI_arprot(2 downto 0),
      S01_AXI_arqos(3 downto 0) => S01_AXI_arqos(3 downto 0),
      S01_AXI_arready => S01_AXI_arready,
      S01_AXI_arsize(2 downto 0) => S01_AXI_arsize(2 downto 0),
      S01_AXI_arvalid => S01_AXI_arvalid,
      S01_AXI_awaddr(31 downto 0) => S01_AXI_awaddr(31 downto 0),
      S01_AXI_awburst(1 downto 0) => S01_AXI_awburst(1 downto 0),
      S01_AXI_awcache(3 downto 0) => S01_AXI_awcache(3 downto 0),
      S01_AXI_awlen(7 downto 0) => S01_AXI_awlen(7 downto 0),
      S01_AXI_awlock(0) => S01_AXI_awlock(0),
      S01_AXI_awprot(2 downto 0) => S01_AXI_awprot(2 downto 0),
      S01_AXI_awqos(3 downto 0) => S01_AXI_awqos(3 downto 0),
      S01_AXI_awready => S01_AXI_awready,
      S01_AXI_awsize(2 downto 0) => S01_AXI_awsize(2 downto 0),
      S01_AXI_awvalid => S01_AXI_awvalid,
      S01_AXI_bready => S01_AXI_bready,
      S01_AXI_bresp(1 downto 0) => S01_AXI_bresp(1 downto 0),
      S01_AXI_bvalid => S01_AXI_bvalid,
      S01_AXI_rdata(31 downto 0) => S01_AXI_rdata(31 downto 0),
      S01_AXI_rlast => S01_AXI_rlast,
      S01_AXI_rready => S01_AXI_rready,
      S01_AXI_rresp(1 downto 0) => S01_AXI_rresp(1 downto 0),
      S01_AXI_rvalid => S01_AXI_rvalid,
      S01_AXI_wdata(31 downto 0) => S01_AXI_wdata(31 downto 0),
      S01_AXI_wlast => S01_AXI_wlast,
      S01_AXI_wready => S01_AXI_wready,
      S01_AXI_wstrb(3 downto 0) => S01_AXI_wstrb(3 downto 0),
      S01_AXI_wvalid => S01_AXI_wvalid,
      aclk => aclk,
      interconnect_aresetn(0) => m_axi_aresetn_1,
      m_axi_araddr(31 downto 0) => s01_entry_pipeline_m_axi_ARADDR(31 downto 0),
      m_axi_arcache(3 downto 0) => s01_entry_pipeline_m_axi_ARCACHE(3 downto 0),
      m_axi_arlock(0) => s01_entry_pipeline_m_axi_ARLOCK,
      m_axi_arprot(2 downto 0) => s01_entry_pipeline_m_axi_ARPROT(2 downto 0),
      m_axi_arqos(3 downto 0) => s01_entry_pipeline_m_axi_ARQOS(3 downto 0),
      m_axi_aruser(24 downto 18) => s01_entry_pipeline_m_axi_ARUSER(185 downto 179),
      m_axi_aruser(17 downto 7) => s01_entry_pipeline_m_axi_ARUSER(146 downto 136),
      m_axi_aruser(6 downto 0) => s01_entry_pipeline_m_axi_ARUSER(70 downto 64),
      m_axi_arvalid => s01_entry_pipeline_m_axi_ARVALID,
      m_axi_awaddr(31 downto 0) => s01_entry_pipeline_m_axi_AWADDR(31 downto 0),
      m_axi_awcache(3 downto 0) => s01_entry_pipeline_m_axi_AWCACHE(3 downto 0),
      m_axi_awlock(0) => s01_entry_pipeline_m_axi_AWLOCK,
      m_axi_awprot(2 downto 0) => s01_entry_pipeline_m_axi_AWPROT(2 downto 0),
      m_axi_awqos(3 downto 0) => s01_entry_pipeline_m_axi_AWQOS(3 downto 0),
      m_axi_awuser(24 downto 18) => s01_entry_pipeline_m_axi_AWUSER(185 downto 179),
      m_axi_awuser(17 downto 7) => s01_entry_pipeline_m_axi_AWUSER(146 downto 136),
      m_axi_awuser(6 downto 0) => s01_entry_pipeline_m_axi_AWUSER(70 downto 64),
      m_axi_awvalid => s01_entry_pipeline_m_axi_AWVALID,
      m_axi_bready => s01_entry_pipeline_m_axi_BREADY,
      m_axi_rready => s01_entry_pipeline_m_axi_RREADY,
      m_axi_wdata(31 downto 0) => s01_entry_pipeline_m_axi_WDATA(31 downto 0),
      m_axi_wlast => s01_entry_pipeline_m_axi_WLAST,
      m_axi_wstrb(3 downto 0) => s01_entry_pipeline_m_axi_WSTRB(3 downto 0),
      m_axi_wuser(13 downto 0) => s01_entry_pipeline_m_axi_WUSER(77 downto 64),
      m_axi_wvalid => s01_entry_pipeline_m_axi_WVALID,
      s_axi_arready => s01_entry_pipeline_m_axi_ARREADY,
      s_axi_awready => s01_entry_pipeline_m_axi_AWREADY,
      s_axi_bresp(1 downto 0) => s01_entry_pipeline_m_axi_BRESP(1 downto 0),
      s_axi_bvalid => s01_entry_pipeline_m_axi_BVALID,
      s_axi_rdata(31 downto 0) => s01_entry_pipeline_m_axi_RDATA(31 downto 0),
      s_axi_rlast => s01_entry_pipeline_m_axi_RLAST,
      s_axi_rresp(1 downto 0) => s01_entry_pipeline_m_axi_RRESP(1 downto 0),
      s_axi_rvalid => s01_entry_pipeline_m_axi_RVALID,
      s_axi_wready => s01_entry_pipeline_m_axi_WREADY
    );
s01_nodes: entity work.Loopback_smartconnect_0_0_s01_nodes_imp_17S12XV
     port map (
      M01_SC_B_payld(5 downto 0) => S_SC_B_1_PAYLD(6 downto 1),
      M01_SC_B_send(0) => S_SC_B_1_SEND,
      M01_SC_R_payld(138 downto 4) => S_SC_R_2_PAYLD(148 downto 14),
      M01_SC_R_payld(3 downto 2) => S_SC_R_2_PAYLD(12 downto 11),
      M01_SC_R_payld(1 downto 0) => S_SC_R_2_PAYLD(5 downto 4),
      M01_SC_R_send(0) => S_SC_R_2_SEND,
      M_SC_AR_payld(82 downto 13) => s01_nodes_M_SC_AR_PAYLD(139 downto 70),
      M_SC_AR_payld(12 downto 0) => s01_nodes_M_SC_AR_PAYLD(13 downto 1),
      M_SC_AR_req(0) => s01_nodes_M_SC_AR_REQ,
      M_SC_AR_send(0) => s01_nodes_M_SC_AR_SEND,
      M_SC_AW_payld(82 downto 13) => s01_nodes_M_SC_AW_PAYLD(139 downto 70),
      M_SC_AW_payld(12 downto 0) => s01_nodes_M_SC_AW_PAYLD(13 downto 1),
      M_SC_AW_req(0) => s01_nodes_M_SC_AW_REQ,
      M_SC_AW_send(0) => s01_nodes_M_SC_AW_SEND,
      M_SC_B_payld(1 downto 0) => s01_nodes_M_SC_B_PAYLD(6 downto 5),
      M_SC_B_recv(0) => s01_nodes_M_SC_B_RECV,
      M_SC_B_send(0) => s01_nodes_M_SC_B_SEND,
      M_SC_R_payld(34 downto 0) => s01_nodes_M_SC_R_PAYLD(52 downto 18),
      M_SC_R_recv(0) => s01_nodes_M_SC_R_RECV,
      M_SC_R_send(0) => s01_nodes_M_SC_R_SEND,
      M_SC_W_info(0) => s01_nodes_M_SC_W_INFO,
      M_SC_W_payld(147 downto 2) => s01_nodes_M_SC_W_PAYLD(159 downto 14),
      M_SC_W_payld(1) => s01_nodes_M_SC_W_PAYLD(8),
      M_SC_W_payld(0) => s01_nodes_M_SC_W_PAYLD(1),
      M_SC_W_req(0) => s01_nodes_M_SC_W_REQ,
      M_SC_W_send(0) => s01_nodes_M_SC_W_SEND,
      S01_SC_AR_recv(0) => s01_nodes_M_SC_AR_RECV,
      S01_SC_AW_recv(0) => s01_nodes_M_SC_AW_RECV,
      S01_SC_W_recv(0) => s01_nodes_M_SC_W_RECV,
      S_SC_AR_payld(68 downto 25) => S_SC_AR_2_PAYLD(139 downto 96),
      S_SC_AR_payld(24 downto 18) => S_SC_AR_2_PAYLD(92 downto 86),
      S_SC_AR_payld(17 downto 7) => S_SC_AR_2_PAYLD(83 downto 73),
      S_SC_AR_payld(6 downto 0) => S_SC_AR_2_PAYLD(7 downto 1),
      S_SC_AR_recv(0) => S_SC_AR_2_RECV,
      S_SC_AR_send(0) => S_SC_AR_2_SEND,
      S_SC_AW_payld(68 downto 25) => S_SC_AW_1_PAYLD(139 downto 96),
      S_SC_AW_payld(24 downto 18) => S_SC_AW_1_PAYLD(92 downto 86),
      S_SC_AW_payld(17 downto 7) => S_SC_AW_1_PAYLD(83 downto 73),
      S_SC_AW_payld(6 downto 0) => S_SC_AW_1_PAYLD(7 downto 1),
      S_SC_AW_recv(0) => S_SC_AW_1_RECV,
      S_SC_AW_send(0) => S_SC_AW_1_SEND,
      S_SC_B_recv(0) => S_SC_B_1_RECV,
      S_SC_R_recv(0) => S_SC_R_2_RECV,
      S_SC_W_payld(50 downto 0) => S_SC_W_1_PAYLD(51 downto 1),
      S_SC_W_recv(0) => S_SC_W_1_RECV,
      S_SC_W_send(0) => S_SC_W_1_SEND,
      aclk => aclk,
      interconnect_aresetn(0) => m_axi_aresetn_1
    );
switchboards: entity work.Loopback_smartconnect_0_0_switchboards_imp_TR9R9D
     port map (
      M00_SC_AR_payld(82 downto 13) => S_SC_AR_3_PAYLD(139 downto 70),
      M00_SC_AR_payld(12 downto 0) => S_SC_AR_3_PAYLD(13 downto 1),
      M00_SC_AR_recv(1 downto 0) => S_SC_AR_3_RECV(1 downto 0),
      M00_SC_AR_req(1 downto 0) => S_SC_AR_3_REQ(1 downto 0),
      M00_SC_AR_send(1 downto 0) => S_SC_AR_3_SEND(1 downto 0),
      M00_SC_AW_payld(82 downto 13) => S_SC_AW_2_PAYLD(139 downto 70),
      M00_SC_AW_payld(12 downto 0) => S_SC_AW_2_PAYLD(13 downto 1),
      M00_SC_AW_recv(0) => S_SC_AW_2_RECV(1),
      M00_SC_AW_req(0) => S_SC_AW_2_REQ(1),
      M00_SC_AW_send(0) => S_SC_AW_2_SEND(1),
      M00_SC_W_info(0) => S_SC_W_2_INFO(1),
      M00_SC_W_payld(147 downto 2) => S_SC_W_2_PAYLD(159 downto 14),
      M00_SC_W_payld(1) => S_SC_W_2_PAYLD(8),
      M00_SC_W_payld(0) => S_SC_W_2_PAYLD(1),
      M00_SC_W_recv(0) => S_SC_W_2_RECV(1),
      M00_SC_W_req(0) => S_SC_W_2_REQ(1),
      M00_SC_W_send(0) => S_SC_W_2_SEND(1),
      M01_SC_B_payld(5 downto 0) => S_SC_B_1_PAYLD(6 downto 1),
      M01_SC_B_recv(0) => S_SC_B_1_RECV,
      M01_SC_B_send(0) => S_SC_B_1_SEND,
      S00_SC_B_payld(5 downto 0) => m00_nodes_M_SC_B_PAYLD(6 downto 1),
      S00_SC_B_recv(0) => m00_nodes_M_SC_B_RECV(1),
      S00_SC_B_send(0) => m00_nodes_M_SC_B_SEND(1),
      S00_SC_R_payld(138 downto 4) => m00_nodes_M_SC_R_PAYLD(148 downto 14),
      S00_SC_R_payld(3 downto 2) => m00_nodes_M_SC_R_PAYLD(12 downto 11),
      S00_SC_R_payld(1 downto 0) => m00_nodes_M_SC_R_PAYLD(5 downto 4),
      S00_SC_R_recv(1 downto 0) => m00_nodes_M_SC_R_RECV(1 downto 0),
      S00_SC_R_send(1 downto 0) => m00_nodes_M_SC_R_SEND(1 downto 0),
      S01_SC_AW_payld(82 downto 13) => s01_nodes_M_SC_AW_PAYLD(139 downto 70),
      S01_SC_AW_payld(12 downto 0) => s01_nodes_M_SC_AW_PAYLD(13 downto 1),
      S01_SC_AW_recv(0) => s01_nodes_M_SC_AW_RECV,
      S01_SC_AW_req(0) => s01_nodes_M_SC_AW_REQ,
      S01_SC_AW_send(0) => s01_nodes_M_SC_AW_SEND,
      S01_SC_W_info(0) => s01_nodes_M_SC_W_INFO,
      S01_SC_W_payld(147 downto 2) => s01_nodes_M_SC_W_PAYLD(159 downto 14),
      S01_SC_W_payld(1) => s01_nodes_M_SC_W_PAYLD(8),
      S01_SC_W_payld(0) => s01_nodes_M_SC_W_PAYLD(1),
      S01_SC_W_recv(0) => s01_nodes_M_SC_W_RECV,
      S01_SC_W_req(0) => s01_nodes_M_SC_W_REQ,
      S01_SC_W_send(0) => s01_nodes_M_SC_W_SEND,
      aclk => aclk,
      m_sc_payld(277 downto 143) => S_SC_R_2_PAYLD(148 downto 14),
      m_sc_payld(142 downto 141) => S_SC_R_2_PAYLD(12 downto 11),
      m_sc_payld(140 downto 139) => S_SC_R_2_PAYLD(5 downto 4),
      m_sc_payld(138 downto 4) => S_SC_R_1_PAYLD(148 downto 14),
      m_sc_payld(3 downto 2) => S_SC_R_1_PAYLD(12 downto 11),
      m_sc_payld(1 downto 0) => S_SC_R_1_PAYLD(5 downto 4),
      m_sc_recv(1) => S_SC_R_2_RECV,
      m_sc_recv(0) => S_SC_R_1_RECV,
      m_sc_send(1) => S_SC_R_2_SEND,
      m_sc_send(0) => S_SC_R_1_SEND,
      s_sc_payld(165 downto 96) => s01_nodes_M_SC_AR_PAYLD(139 downto 70),
      s_sc_payld(95 downto 83) => s01_nodes_M_SC_AR_PAYLD(13 downto 1),
      s_sc_payld(82 downto 13) => s00_nodes_M_SC_AR_PAYLD(139 downto 70),
      s_sc_payld(12 downto 0) => s00_nodes_M_SC_AR_PAYLD(13 downto 1),
      s_sc_recv(1) => s01_nodes_M_SC_AR_RECV,
      s_sc_recv(0) => s00_nodes_M_SC_AR_RECV,
      s_sc_req(1) => s01_nodes_M_SC_AR_REQ,
      s_sc_req(0) => s00_nodes_M_SC_AR_REQ,
      s_sc_send(1) => s01_nodes_M_SC_AR_SEND,
      s_sc_send(0) => s00_nodes_M_SC_AR_SEND
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Loopback_smartconnect_0_0 is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arvalid : in STD_LOGIC;
    S00_AXI_arready : out STD_LOGIC;
    S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_rlast : out STD_LOGIC;
    S00_AXI_rvalid : out STD_LOGIC;
    S00_AXI_rready : in STD_LOGIC;
    S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awvalid : in STD_LOGIC;
    S01_AXI_awready : out STD_LOGIC;
    S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_wlast : in STD_LOGIC;
    S01_AXI_wvalid : in STD_LOGIC;
    S01_AXI_wready : out STD_LOGIC;
    S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_bvalid : out STD_LOGIC;
    S01_AXI_bready : in STD_LOGIC;
    S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arvalid : in STD_LOGIC;
    S01_AXI_arready : out STD_LOGIC;
    S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_rlast : out STD_LOGIC;
    S01_AXI_rvalid : out STD_LOGIC;
    S01_AXI_rready : in STD_LOGIC;
    M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 48 downto 0 );
    M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awvalid : out STD_LOGIC;
    M00_AXI_awready : in STD_LOGIC;
    M00_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
    M00_AXI_wlast : out STD_LOGIC;
    M00_AXI_wvalid : out STD_LOGIC;
    M00_AXI_wready : in STD_LOGIC;
    M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_bvalid : in STD_LOGIC;
    M00_AXI_bready : out STD_LOGIC;
    M00_AXI_araddr : out STD_LOGIC_VECTOR ( 48 downto 0 );
    M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arvalid : out STD_LOGIC;
    M00_AXI_arready : in STD_LOGIC;
    M00_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_rlast : in STD_LOGIC;
    M00_AXI_rvalid : in STD_LOGIC;
    M00_AXI_rready : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of Loopback_smartconnect_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of Loopback_smartconnect_0_0 : entity is "Loopback_smartconnect_0_0,bd_e34c,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of Loopback_smartconnect_0_0 : entity is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of Loopback_smartconnect_0_0 : entity is "bd_e34c,Vivado 2024.2";
end Loopback_smartconnect_0_0;

architecture STRUCTURE of Loopback_smartconnect_0_0 is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^m00_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \^m00_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_M00_AXI_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 48 downto 32 );
  signal NLW_inst_M00_AXI_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_M00_AXI_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_M00_AXI_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 48 downto 32 );
  signal NLW_inst_M00_AXI_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_M00_AXI_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of inst : label is "Loopback_smartconnect_0_0.hwdef";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of M00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
  attribute X_INTERFACE_INFO of M00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
  attribute X_INTERFACE_INFO of M00_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
  attribute X_INTERFACE_INFO of M00_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
  attribute X_INTERFACE_INFO of M00_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
  attribute X_INTERFACE_INFO of M00_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
  attribute X_INTERFACE_INFO of M00_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RLAST";
  attribute X_INTERFACE_INFO of M00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
  attribute X_INTERFACE_INFO of M00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
  attribute X_INTERFACE_INFO of M00_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WLAST";
  attribute X_INTERFACE_INFO of M00_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
  attribute X_INTERFACE_INFO of M00_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
  attribute X_INTERFACE_INFO of S00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
  attribute X_INTERFACE_INFO of S00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
  attribute X_INTERFACE_INFO of S00_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RLAST";
  attribute X_INTERFACE_INFO of S00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
  attribute X_INTERFACE_INFO of S00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
  attribute X_INTERFACE_INFO of S01_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARREADY";
  attribute X_INTERFACE_INFO of S01_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARVALID";
  attribute X_INTERFACE_INFO of S01_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWREADY";
  attribute X_INTERFACE_INFO of S01_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWVALID";
  attribute X_INTERFACE_INFO of S01_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BREADY";
  attribute X_INTERFACE_INFO of S01_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BVALID";
  attribute X_INTERFACE_INFO of S01_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RLAST";
  attribute X_INTERFACE_INFO of S01_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RREADY";
  attribute X_INTERFACE_INFO of S01_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RVALID";
  attribute X_INTERFACE_INFO of S01_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WLAST";
  attribute X_INTERFACE_INFO of S01_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WREADY";
  attribute X_INTERFACE_INFO of S01_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WVALID";
  attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.aclk CLK";
  attribute X_INTERFACE_MODE : string;
  attribute X_INTERFACE_MODE of aclk : signal is "slave";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.aclk, FREQ_HZ 249999954, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF M00_AXI:S00_AXI:S01_AXI, INSERT_VIP 0, ASSOCIATED_CLKEN m_sc_aclken";
  attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.aresetn RST";
  attribute X_INTERFACE_MODE of aresetn : signal is "slave";
  attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
  attribute X_INTERFACE_INFO of M00_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST";
  attribute X_INTERFACE_INFO of M00_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE";
  attribute X_INTERFACE_INFO of M00_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN";
  attribute X_INTERFACE_INFO of M00_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK";
  attribute X_INTERFACE_INFO of M00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
  attribute X_INTERFACE_INFO of M00_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS";
  attribute X_INTERFACE_INFO of M00_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE";
  attribute X_INTERFACE_INFO of M00_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
  attribute X_INTERFACE_MODE of M00_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M00_AXI_awaddr : signal is "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 249999954, ID_WIDTH 0, ADDR_WIDTH 49, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 4, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M00_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST";
  attribute X_INTERFACE_INFO of M00_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE";
  attribute X_INTERFACE_INFO of M00_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN";
  attribute X_INTERFACE_INFO of M00_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK";
  attribute X_INTERFACE_INFO of M00_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
  attribute X_INTERFACE_INFO of M00_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS";
  attribute X_INTERFACE_INFO of M00_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE";
  attribute X_INTERFACE_INFO of M00_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
  attribute X_INTERFACE_INFO of M00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
  attribute X_INTERFACE_INFO of M00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
  attribute X_INTERFACE_INFO of M00_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
  attribute X_INTERFACE_INFO of M00_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
  attribute X_INTERFACE_INFO of S00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
  attribute X_INTERFACE_MODE of S00_AXI_araddr : signal is "slave";
  attribute X_INTERFACE_PARAMETER of S00_AXI_araddr : signal is "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 249999954, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of S00_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST";
  attribute X_INTERFACE_INFO of S00_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE";
  attribute X_INTERFACE_INFO of S00_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN";
  attribute X_INTERFACE_INFO of S00_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK";
  attribute X_INTERFACE_INFO of S00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
  attribute X_INTERFACE_INFO of S00_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS";
  attribute X_INTERFACE_INFO of S00_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE";
  attribute X_INTERFACE_INFO of S00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
  attribute X_INTERFACE_INFO of S00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
  attribute X_INTERFACE_INFO of S01_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARADDR";
  attribute X_INTERFACE_INFO of S01_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARBURST";
  attribute X_INTERFACE_INFO of S01_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE";
  attribute X_INTERFACE_INFO of S01_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARLEN";
  attribute X_INTERFACE_INFO of S01_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK";
  attribute X_INTERFACE_INFO of S01_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARPROT";
  attribute X_INTERFACE_INFO of S01_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARQOS";
  attribute X_INTERFACE_INFO of S01_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE";
  attribute X_INTERFACE_INFO of S01_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWADDR";
  attribute X_INTERFACE_MODE of S01_AXI_awaddr : signal is "slave";
  attribute X_INTERFACE_PARAMETER of S01_AXI_awaddr : signal is "XIL_INTERFACENAME S01_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 249999954, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of S01_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWBURST";
  attribute X_INTERFACE_INFO of S01_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE";
  attribute X_INTERFACE_INFO of S01_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWLEN";
  attribute X_INTERFACE_INFO of S01_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK";
  attribute X_INTERFACE_INFO of S01_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWPROT";
  attribute X_INTERFACE_INFO of S01_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWQOS";
  attribute X_INTERFACE_INFO of S01_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE";
  attribute X_INTERFACE_INFO of S01_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BRESP";
  attribute X_INTERFACE_INFO of S01_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RDATA";
  attribute X_INTERFACE_INFO of S01_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RRESP";
  attribute X_INTERFACE_INFO of S01_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WDATA";
  attribute X_INTERFACE_INFO of S01_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WSTRB";
begin
  M00_AXI_araddr(48) <= \<const0>\;
  M00_AXI_araddr(47) <= \<const0>\;
  M00_AXI_araddr(46) <= \<const0>\;
  M00_AXI_araddr(45) <= \<const0>\;
  M00_AXI_araddr(44) <= \<const0>\;
  M00_AXI_araddr(43) <= \<const0>\;
  M00_AXI_araddr(42) <= \<const0>\;
  M00_AXI_araddr(41) <= \<const0>\;
  M00_AXI_araddr(40) <= \<const0>\;
  M00_AXI_araddr(39) <= \<const0>\;
  M00_AXI_araddr(38) <= \<const0>\;
  M00_AXI_araddr(37) <= \<const0>\;
  M00_AXI_araddr(36) <= \<const0>\;
  M00_AXI_araddr(35) <= \<const0>\;
  M00_AXI_araddr(34) <= \<const0>\;
  M00_AXI_araddr(33) <= \<const0>\;
  M00_AXI_araddr(32) <= \<const0>\;
  M00_AXI_araddr(31 downto 0) <= \^m00_axi_araddr\(31 downto 0);
  M00_AXI_arburst(1) <= \<const0>\;
  M00_AXI_arburst(0) <= \<const1>\;
  M00_AXI_arlock(0) <= \<const0>\;
  M00_AXI_awaddr(48) <= \<const0>\;
  M00_AXI_awaddr(47) <= \<const0>\;
  M00_AXI_awaddr(46) <= \<const0>\;
  M00_AXI_awaddr(45) <= \<const0>\;
  M00_AXI_awaddr(44) <= \<const0>\;
  M00_AXI_awaddr(43) <= \<const0>\;
  M00_AXI_awaddr(42) <= \<const0>\;
  M00_AXI_awaddr(41) <= \<const0>\;
  M00_AXI_awaddr(40) <= \<const0>\;
  M00_AXI_awaddr(39) <= \<const0>\;
  M00_AXI_awaddr(38) <= \<const0>\;
  M00_AXI_awaddr(37) <= \<const0>\;
  M00_AXI_awaddr(36) <= \<const0>\;
  M00_AXI_awaddr(35) <= \<const0>\;
  M00_AXI_awaddr(34) <= \<const0>\;
  M00_AXI_awaddr(33) <= \<const0>\;
  M00_AXI_awaddr(32) <= \<const0>\;
  M00_AXI_awaddr(31 downto 0) <= \^m00_axi_awaddr\(31 downto 0);
  M00_AXI_awburst(1) <= \<const0>\;
  M00_AXI_awburst(0) <= \<const1>\;
  M00_AXI_awlock(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
inst: entity work.Loopback_smartconnect_0_0_bd_e34c
     port map (
      M00_AXI_araddr(48 downto 32) => NLW_inst_M00_AXI_araddr_UNCONNECTED(48 downto 32),
      M00_AXI_araddr(31 downto 0) => \^m00_axi_araddr\(31 downto 0),
      M00_AXI_arburst(1 downto 0) => NLW_inst_M00_AXI_arburst_UNCONNECTED(1 downto 0),
      M00_AXI_arcache(3 downto 0) => M00_AXI_arcache(3 downto 0),
      M00_AXI_arlen(7 downto 0) => M00_AXI_arlen(7 downto 0),
      M00_AXI_arlock(0) => NLW_inst_M00_AXI_arlock_UNCONNECTED(0),
      M00_AXI_arprot(2 downto 0) => M00_AXI_arprot(2 downto 0),
      M00_AXI_arqos(3 downto 0) => M00_AXI_arqos(3 downto 0),
      M00_AXI_arready => M00_AXI_arready,
      M00_AXI_arsize(2 downto 0) => M00_AXI_arsize(2 downto 0),
      M00_AXI_arvalid => M00_AXI_arvalid,
      M00_AXI_awaddr(48 downto 32) => NLW_inst_M00_AXI_awaddr_UNCONNECTED(48 downto 32),
      M00_AXI_awaddr(31 downto 0) => \^m00_axi_awaddr\(31 downto 0),
      M00_AXI_awburst(1 downto 0) => NLW_inst_M00_AXI_awburst_UNCONNECTED(1 downto 0),
      M00_AXI_awcache(3 downto 0) => M00_AXI_awcache(3 downto 0),
      M00_AXI_awlen(7 downto 0) => M00_AXI_awlen(7 downto 0),
      M00_AXI_awlock(0) => NLW_inst_M00_AXI_awlock_UNCONNECTED(0),
      M00_AXI_awprot(2 downto 0) => M00_AXI_awprot(2 downto 0),
      M00_AXI_awqos(3 downto 0) => M00_AXI_awqos(3 downto 0),
      M00_AXI_awready => M00_AXI_awready,
      M00_AXI_awsize(2 downto 0) => M00_AXI_awsize(2 downto 0),
      M00_AXI_awvalid => M00_AXI_awvalid,
      M00_AXI_bready => M00_AXI_bready,
      M00_AXI_bresp(1 downto 0) => M00_AXI_bresp(1 downto 0),
      M00_AXI_bvalid => M00_AXI_bvalid,
      M00_AXI_rdata(127 downto 0) => M00_AXI_rdata(127 downto 0),
      M00_AXI_rlast => M00_AXI_rlast,
      M00_AXI_rready => M00_AXI_rready,
      M00_AXI_rresp(1 downto 0) => M00_AXI_rresp(1 downto 0),
      M00_AXI_rvalid => M00_AXI_rvalid,
      M00_AXI_wdata(127 downto 0) => M00_AXI_wdata(127 downto 0),
      M00_AXI_wlast => M00_AXI_wlast,
      M00_AXI_wready => M00_AXI_wready,
      M00_AXI_wstrb(15 downto 0) => M00_AXI_wstrb(15 downto 0),
      M00_AXI_wvalid => M00_AXI_wvalid,
      S00_AXI_araddr(31 downto 0) => S00_AXI_araddr(31 downto 0),
      S00_AXI_arburst(1 downto 0) => S00_AXI_arburst(1 downto 0),
      S00_AXI_arcache(3 downto 0) => S00_AXI_arcache(3 downto 0),
      S00_AXI_arlen(7 downto 0) => S00_AXI_arlen(7 downto 0),
      S00_AXI_arlock(0) => S00_AXI_arlock(0),
      S00_AXI_arprot(2 downto 0) => S00_AXI_arprot(2 downto 0),
      S00_AXI_arqos(3 downto 0) => S00_AXI_arqos(3 downto 0),
      S00_AXI_arready => S00_AXI_arready,
      S00_AXI_arsize(2 downto 0) => S00_AXI_arsize(2 downto 0),
      S00_AXI_arvalid => S00_AXI_arvalid,
      S00_AXI_rdata(31 downto 0) => S00_AXI_rdata(31 downto 0),
      S00_AXI_rlast => S00_AXI_rlast,
      S00_AXI_rready => S00_AXI_rready,
      S00_AXI_rresp(1 downto 0) => S00_AXI_rresp(1 downto 0),
      S00_AXI_rvalid => S00_AXI_rvalid,
      S01_AXI_araddr(31 downto 0) => S01_AXI_araddr(31 downto 0),
      S01_AXI_arburst(1 downto 0) => S01_AXI_arburst(1 downto 0),
      S01_AXI_arcache(3 downto 0) => S01_AXI_arcache(3 downto 0),
      S01_AXI_arlen(7 downto 0) => S01_AXI_arlen(7 downto 0),
      S01_AXI_arlock(0) => S01_AXI_arlock(0),
      S01_AXI_arprot(2 downto 0) => S01_AXI_arprot(2 downto 0),
      S01_AXI_arqos(3 downto 0) => S01_AXI_arqos(3 downto 0),
      S01_AXI_arready => S01_AXI_arready,
      S01_AXI_arsize(2 downto 0) => S01_AXI_arsize(2 downto 0),
      S01_AXI_arvalid => S01_AXI_arvalid,
      S01_AXI_awaddr(31 downto 0) => S01_AXI_awaddr(31 downto 0),
      S01_AXI_awburst(1 downto 0) => S01_AXI_awburst(1 downto 0),
      S01_AXI_awcache(3 downto 0) => S01_AXI_awcache(3 downto 0),
      S01_AXI_awlen(7 downto 0) => S01_AXI_awlen(7 downto 0),
      S01_AXI_awlock(0) => S01_AXI_awlock(0),
      S01_AXI_awprot(2 downto 0) => S01_AXI_awprot(2 downto 0),
      S01_AXI_awqos(3 downto 0) => S01_AXI_awqos(3 downto 0),
      S01_AXI_awready => S01_AXI_awready,
      S01_AXI_awsize(2 downto 0) => S01_AXI_awsize(2 downto 0),
      S01_AXI_awvalid => S01_AXI_awvalid,
      S01_AXI_bready => S01_AXI_bready,
      S01_AXI_bresp(1 downto 0) => S01_AXI_bresp(1 downto 0),
      S01_AXI_bvalid => S01_AXI_bvalid,
      S01_AXI_rdata(31 downto 0) => S01_AXI_rdata(31 downto 0),
      S01_AXI_rlast => S01_AXI_rlast,
      S01_AXI_rready => S01_AXI_rready,
      S01_AXI_rresp(1 downto 0) => S01_AXI_rresp(1 downto 0),
      S01_AXI_rvalid => S01_AXI_rvalid,
      S01_AXI_wdata(31 downto 0) => S01_AXI_wdata(31 downto 0),
      S01_AXI_wlast => S01_AXI_wlast,
      S01_AXI_wready => S01_AXI_wready,
      S01_AXI_wstrb(3 downto 0) => S01_AXI_wstrb(3 downto 0),
      S01_AXI_wvalid => S01_AXI_wvalid,
      aclk => aclk,
      aresetn => aresetn
    );
end STRUCTURE;
