//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
//Date        : Tue Jul 28 17:11:10 2026
//Host        : DrewPC2025 running 64-bit major release  (build 9200)
//Command     : generate_target Loopback.bd
//Design      : Loopback
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "Loopback,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Loopback,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=22,numReposBlks=22,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=7,da_clkrst_cnt=5,da_rf_converter_usp_cnt=1,da_zynq_ultra_ps_e_cnt=1,synth_mode=Hierarchical}" *) (* HW_HANDOFF = "Loopback.hwdef" *) 
module Loopback
   (LED0,
    adc2_clk_clk_n,
    adc2_clk_clk_p,
    dac0_clk_clk_n,
    dac0_clk_clk_p,
    sysref_in_diff_n,
    sysref_in_diff_p,
    vin2_23_v_n,
    vin2_23_v_p,
    vout00_v_n,
    vout00_v_p);
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.LED0 DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.LED0, LAYERED_METADATA undef" *) output [0:0]LED0;
  (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 adc2_clk CLK_N" *) (* X_INTERFACE_MODE = "Slave" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME adc2_clk, CAN_DEBUG false, FREQ_HZ 491520000.0" *) input adc2_clk_clk_n;
  (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 adc2_clk CLK_P" *) input adc2_clk_clk_p;
  (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 dac0_clk CLK_N" *) (* X_INTERFACE_MODE = "Slave" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME dac0_clk, CAN_DEBUG false, FREQ_HZ 491520000.0" *) input dac0_clk_clk_n;
  (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 dac0_clk CLK_P" *) input dac0_clk_clk_p;
  (* X_INTERFACE_INFO = "xilinx.com:display_usp_rf_data_converter:diff_pins:1.0 sysref_in diff_n" *) (* X_INTERFACE_MODE = "Slave" *) input sysref_in_diff_n;
  (* X_INTERFACE_INFO = "xilinx.com:display_usp_rf_data_converter:diff_pins:1.0 sysref_in diff_p" *) input sysref_in_diff_p;
  (* X_INTERFACE_INFO = "xilinx.com:interface:diff_analog_io:1.0 vin2_23 V_N" *) (* X_INTERFACE_MODE = "Slave" *) input vin2_23_v_n;
  (* X_INTERFACE_INFO = "xilinx.com:interface:diff_analog_io:1.0 vin2_23 V_P" *) input vin2_23_v_p;
  (* X_INTERFACE_INFO = "xilinx.com:interface:diff_analog_io:1.0 vout00 V_N" *) (* X_INTERFACE_MODE = "Master" *) output vout00_v_n;
  (* X_INTERFACE_INFO = "xilinx.com:interface:diff_analog_io:1.0 vout00 V_P" *) output vout00_v_p;

  wire [31:0]AXI_DMA_NOSG_M_AXI_S2MM_AWADDR;
  wire [1:0]AXI_DMA_NOSG_M_AXI_S2MM_AWBURST;
  wire [3:0]AXI_DMA_NOSG_M_AXI_S2MM_AWCACHE;
  wire [7:0]AXI_DMA_NOSG_M_AXI_S2MM_AWLEN;
  wire [2:0]AXI_DMA_NOSG_M_AXI_S2MM_AWPROT;
  wire AXI_DMA_NOSG_M_AXI_S2MM_AWREADY;
  wire [2:0]AXI_DMA_NOSG_M_AXI_S2MM_AWSIZE;
  wire AXI_DMA_NOSG_M_AXI_S2MM_AWVALID;
  wire AXI_DMA_NOSG_M_AXI_S2MM_BREADY;
  wire [1:0]AXI_DMA_NOSG_M_AXI_S2MM_BRESP;
  wire AXI_DMA_NOSG_M_AXI_S2MM_BVALID;
  wire [31:0]AXI_DMA_NOSG_M_AXI_S2MM_WDATA;
  wire AXI_DMA_NOSG_M_AXI_S2MM_WLAST;
  wire AXI_DMA_NOSG_M_AXI_S2MM_WREADY;
  wire [3:0]AXI_DMA_NOSG_M_AXI_S2MM_WSTRB;
  wire AXI_DMA_NOSG_M_AXI_S2MM_WVALID;
  wire [31:0]AXI_DMA_SG_M_AXIS_MM2S_TDATA;
  wire [3:0]AXI_DMA_SG_M_AXIS_MM2S_TKEEP;
  wire AXI_DMA_SG_M_AXIS_MM2S_TLAST;
  wire AXI_DMA_SG_M_AXIS_MM2S_TREADY;
  wire AXI_DMA_SG_M_AXIS_MM2S_TVALID;
  wire [31:0]AXI_DMA_SG_M_AXI_MM2S_ARADDR;
  wire [1:0]AXI_DMA_SG_M_AXI_MM2S_ARBURST;
  wire [3:0]AXI_DMA_SG_M_AXI_MM2S_ARCACHE;
  wire [7:0]AXI_DMA_SG_M_AXI_MM2S_ARLEN;
  wire [2:0]AXI_DMA_SG_M_AXI_MM2S_ARPROT;
  wire AXI_DMA_SG_M_AXI_MM2S_ARREADY;
  wire [2:0]AXI_DMA_SG_M_AXI_MM2S_ARSIZE;
  wire AXI_DMA_SG_M_AXI_MM2S_ARVALID;
  wire [31:0]AXI_DMA_SG_M_AXI_MM2S_RDATA;
  wire AXI_DMA_SG_M_AXI_MM2S_RLAST;
  wire AXI_DMA_SG_M_AXI_MM2S_RREADY;
  wire [1:0]AXI_DMA_SG_M_AXI_MM2S_RRESP;
  wire AXI_DMA_SG_M_AXI_MM2S_RVALID;
  wire [31:0]AXI_DMA_SG_M_AXI_SG_ARADDR;
  wire [1:0]AXI_DMA_SG_M_AXI_SG_ARBURST;
  wire [3:0]AXI_DMA_SG_M_AXI_SG_ARCACHE;
  wire [7:0]AXI_DMA_SG_M_AXI_SG_ARLEN;
  wire [2:0]AXI_DMA_SG_M_AXI_SG_ARPROT;
  wire AXI_DMA_SG_M_AXI_SG_ARREADY;
  wire [2:0]AXI_DMA_SG_M_AXI_SG_ARSIZE;
  wire AXI_DMA_SG_M_AXI_SG_ARVALID;
  wire [31:0]AXI_DMA_SG_M_AXI_SG_AWADDR;
  wire [1:0]AXI_DMA_SG_M_AXI_SG_AWBURST;
  wire [3:0]AXI_DMA_SG_M_AXI_SG_AWCACHE;
  wire [7:0]AXI_DMA_SG_M_AXI_SG_AWLEN;
  wire [2:0]AXI_DMA_SG_M_AXI_SG_AWPROT;
  wire AXI_DMA_SG_M_AXI_SG_AWREADY;
  wire [2:0]AXI_DMA_SG_M_AXI_SG_AWSIZE;
  wire AXI_DMA_SG_M_AXI_SG_AWVALID;
  wire AXI_DMA_SG_M_AXI_SG_BREADY;
  wire [1:0]AXI_DMA_SG_M_AXI_SG_BRESP;
  wire AXI_DMA_SG_M_AXI_SG_BVALID;
  wire [31:0]AXI_DMA_SG_M_AXI_SG_RDATA;
  wire AXI_DMA_SG_M_AXI_SG_RLAST;
  wire AXI_DMA_SG_M_AXI_SG_RREADY;
  wire [1:0]AXI_DMA_SG_M_AXI_SG_RRESP;
  wire AXI_DMA_SG_M_AXI_SG_RVALID;
  wire [31:0]AXI_DMA_SG_M_AXI_SG_WDATA;
  wire AXI_DMA_SG_M_AXI_SG_WLAST;
  wire AXI_DMA_SG_M_AXI_SG_WREADY;
  wire [3:0]AXI_DMA_SG_M_AXI_SG_WSTRB;
  wire AXI_DMA_SG_M_AXI_SG_WVALID;
  wire [0:0]LED0;
  wire Net;
  wire [0:0]ONE_dout;
  wire RFDC_clk_adc2;
  wire RFDC_clk_dac0;
  wire [15:0]RFDC_m22_axis_TDATA;
  wire RFDC_m22_axis_TREADY;
  wire RFDC_m22_axis_TVALID;
  wire [15:0]RFDC_m23_axis_TDATA;
  wire RFDC_m23_axis_TREADY;
  wire RFDC_m23_axis_TVALID;
  wire [31:0]RX_FIFO_M_AXIS_TDATA;
  wire RX_FIFO_M_AXIS_TREADY;
  wire RX_FIFO_M_AXIS_TVALID;
  wire [0:0]RX_FIFO_RESET_SYNC_peripheral_aresetn;
  wire [23:0]RX_FIFO_TLAST_gpio_io_o;
  wire [48:0]SMART_NOSG_M00_AXI_AWADDR;
  wire [1:0]SMART_NOSG_M00_AXI_AWBURST;
  wire [3:0]SMART_NOSG_M00_AXI_AWCACHE;
  wire [7:0]SMART_NOSG_M00_AXI_AWLEN;
  wire [0:0]SMART_NOSG_M00_AXI_AWLOCK;
  wire [2:0]SMART_NOSG_M00_AXI_AWPROT;
  wire [3:0]SMART_NOSG_M00_AXI_AWQOS;
  wire SMART_NOSG_M00_AXI_AWREADY;
  wire [2:0]SMART_NOSG_M00_AXI_AWSIZE;
  wire SMART_NOSG_M00_AXI_AWVALID;
  wire SMART_NOSG_M00_AXI_BREADY;
  wire [1:0]SMART_NOSG_M00_AXI_BRESP;
  wire SMART_NOSG_M00_AXI_BVALID;
  wire [127:0]SMART_NOSG_M00_AXI_WDATA;
  wire SMART_NOSG_M00_AXI_WLAST;
  wire SMART_NOSG_M00_AXI_WREADY;
  wire [15:0]SMART_NOSG_M00_AXI_WSTRB;
  wire SMART_NOSG_M00_AXI_WVALID;
  wire [48:0]SMART_SG_M00_AXI_ARADDR;
  wire [1:0]SMART_SG_M00_AXI_ARBURST;
  wire [3:0]SMART_SG_M00_AXI_ARCACHE;
  wire [7:0]SMART_SG_M00_AXI_ARLEN;
  wire [0:0]SMART_SG_M00_AXI_ARLOCK;
  wire [2:0]SMART_SG_M00_AXI_ARPROT;
  wire [3:0]SMART_SG_M00_AXI_ARQOS;
  wire SMART_SG_M00_AXI_ARREADY;
  wire [2:0]SMART_SG_M00_AXI_ARSIZE;
  wire SMART_SG_M00_AXI_ARVALID;
  wire [48:0]SMART_SG_M00_AXI_AWADDR;
  wire [1:0]SMART_SG_M00_AXI_AWBURST;
  wire [3:0]SMART_SG_M00_AXI_AWCACHE;
  wire [7:0]SMART_SG_M00_AXI_AWLEN;
  wire [0:0]SMART_SG_M00_AXI_AWLOCK;
  wire [2:0]SMART_SG_M00_AXI_AWPROT;
  wire [3:0]SMART_SG_M00_AXI_AWQOS;
  wire SMART_SG_M00_AXI_AWREADY;
  wire [2:0]SMART_SG_M00_AXI_AWSIZE;
  wire SMART_SG_M00_AXI_AWVALID;
  wire SMART_SG_M00_AXI_BREADY;
  wire [1:0]SMART_SG_M00_AXI_BRESP;
  wire SMART_SG_M00_AXI_BVALID;
  wire [127:0]SMART_SG_M00_AXI_RDATA;
  wire SMART_SG_M00_AXI_RLAST;
  wire SMART_SG_M00_AXI_RREADY;
  wire [1:0]SMART_SG_M00_AXI_RRESP;
  wire SMART_SG_M00_AXI_RVALID;
  wire [127:0]SMART_SG_M00_AXI_WDATA;
  wire SMART_SG_M00_AXI_WLAST;
  wire SMART_SG_M00_AXI_WREADY;
  wire [15:0]SMART_SG_M00_AXI_WSTRB;
  wire SMART_SG_M00_AXI_WVALID;
  wire TX_FIFO_CLK_clk_out1;
  wire [31:0]TX_FIFO_M_AXIS_TDATA;
  wire TX_FIFO_M_AXIS_TREADY;
  wire TX_FIFO_M_AXIS_TVALID;
  wire [0:0]ZERO_dout;
  wire [39:0]ZYNQ_M_AXI_HPM0_FPD_ARADDR;
  wire [1:0]ZYNQ_M_AXI_HPM0_FPD_ARBURST;
  wire [3:0]ZYNQ_M_AXI_HPM0_FPD_ARCACHE;
  wire [15:0]ZYNQ_M_AXI_HPM0_FPD_ARID;
  wire [7:0]ZYNQ_M_AXI_HPM0_FPD_ARLEN;
  wire ZYNQ_M_AXI_HPM0_FPD_ARLOCK;
  wire [2:0]ZYNQ_M_AXI_HPM0_FPD_ARPROT;
  wire [3:0]ZYNQ_M_AXI_HPM0_FPD_ARQOS;
  wire ZYNQ_M_AXI_HPM0_FPD_ARREADY;
  wire [2:0]ZYNQ_M_AXI_HPM0_FPD_ARSIZE;
  wire [15:0]ZYNQ_M_AXI_HPM0_FPD_ARUSER;
  wire ZYNQ_M_AXI_HPM0_FPD_ARVALID;
  wire [39:0]ZYNQ_M_AXI_HPM0_FPD_AWADDR;
  wire [1:0]ZYNQ_M_AXI_HPM0_FPD_AWBURST;
  wire [3:0]ZYNQ_M_AXI_HPM0_FPD_AWCACHE;
  wire [15:0]ZYNQ_M_AXI_HPM0_FPD_AWID;
  wire [7:0]ZYNQ_M_AXI_HPM0_FPD_AWLEN;
  wire ZYNQ_M_AXI_HPM0_FPD_AWLOCK;
  wire [2:0]ZYNQ_M_AXI_HPM0_FPD_AWPROT;
  wire [3:0]ZYNQ_M_AXI_HPM0_FPD_AWQOS;
  wire ZYNQ_M_AXI_HPM0_FPD_AWREADY;
  wire [2:0]ZYNQ_M_AXI_HPM0_FPD_AWSIZE;
  wire [15:0]ZYNQ_M_AXI_HPM0_FPD_AWUSER;
  wire ZYNQ_M_AXI_HPM0_FPD_AWVALID;
  wire [15:0]ZYNQ_M_AXI_HPM0_FPD_BID;
  wire ZYNQ_M_AXI_HPM0_FPD_BREADY;
  wire [1:0]ZYNQ_M_AXI_HPM0_FPD_BRESP;
  wire ZYNQ_M_AXI_HPM0_FPD_BVALID;
  wire [127:0]ZYNQ_M_AXI_HPM0_FPD_RDATA;
  wire [15:0]ZYNQ_M_AXI_HPM0_FPD_RID;
  wire ZYNQ_M_AXI_HPM0_FPD_RLAST;
  wire ZYNQ_M_AXI_HPM0_FPD_RREADY;
  wire [1:0]ZYNQ_M_AXI_HPM0_FPD_RRESP;
  wire ZYNQ_M_AXI_HPM0_FPD_RVALID;
  wire [127:0]ZYNQ_M_AXI_HPM0_FPD_WDATA;
  wire ZYNQ_M_AXI_HPM0_FPD_WLAST;
  wire ZYNQ_M_AXI_HPM0_FPD_WREADY;
  wire [15:0]ZYNQ_M_AXI_HPM0_FPD_WSTRB;
  wire ZYNQ_M_AXI_HPM0_FPD_WVALID;
  wire [39:0]ZYNQ_M_AXI_HPM1_FPD_ARADDR;
  wire [1:0]ZYNQ_M_AXI_HPM1_FPD_ARBURST;
  wire [3:0]ZYNQ_M_AXI_HPM1_FPD_ARCACHE;
  wire [15:0]ZYNQ_M_AXI_HPM1_FPD_ARID;
  wire [7:0]ZYNQ_M_AXI_HPM1_FPD_ARLEN;
  wire ZYNQ_M_AXI_HPM1_FPD_ARLOCK;
  wire [2:0]ZYNQ_M_AXI_HPM1_FPD_ARPROT;
  wire [3:0]ZYNQ_M_AXI_HPM1_FPD_ARQOS;
  wire ZYNQ_M_AXI_HPM1_FPD_ARREADY;
  wire [2:0]ZYNQ_M_AXI_HPM1_FPD_ARSIZE;
  wire [15:0]ZYNQ_M_AXI_HPM1_FPD_ARUSER;
  wire ZYNQ_M_AXI_HPM1_FPD_ARVALID;
  wire [39:0]ZYNQ_M_AXI_HPM1_FPD_AWADDR;
  wire [1:0]ZYNQ_M_AXI_HPM1_FPD_AWBURST;
  wire [3:0]ZYNQ_M_AXI_HPM1_FPD_AWCACHE;
  wire [15:0]ZYNQ_M_AXI_HPM1_FPD_AWID;
  wire [7:0]ZYNQ_M_AXI_HPM1_FPD_AWLEN;
  wire ZYNQ_M_AXI_HPM1_FPD_AWLOCK;
  wire [2:0]ZYNQ_M_AXI_HPM1_FPD_AWPROT;
  wire [3:0]ZYNQ_M_AXI_HPM1_FPD_AWQOS;
  wire ZYNQ_M_AXI_HPM1_FPD_AWREADY;
  wire [2:0]ZYNQ_M_AXI_HPM1_FPD_AWSIZE;
  wire [15:0]ZYNQ_M_AXI_HPM1_FPD_AWUSER;
  wire ZYNQ_M_AXI_HPM1_FPD_AWVALID;
  wire [15:0]ZYNQ_M_AXI_HPM1_FPD_BID;
  wire ZYNQ_M_AXI_HPM1_FPD_BREADY;
  wire [1:0]ZYNQ_M_AXI_HPM1_FPD_BRESP;
  wire ZYNQ_M_AXI_HPM1_FPD_BVALID;
  wire [127:0]ZYNQ_M_AXI_HPM1_FPD_RDATA;
  wire [15:0]ZYNQ_M_AXI_HPM1_FPD_RID;
  wire ZYNQ_M_AXI_HPM1_FPD_RLAST;
  wire ZYNQ_M_AXI_HPM1_FPD_RREADY;
  wire [1:0]ZYNQ_M_AXI_HPM1_FPD_RRESP;
  wire ZYNQ_M_AXI_HPM1_FPD_RVALID;
  wire [127:0]ZYNQ_M_AXI_HPM1_FPD_WDATA;
  wire ZYNQ_M_AXI_HPM1_FPD_WLAST;
  wire ZYNQ_M_AXI_HPM1_FPD_WREADY;
  wire [15:0]ZYNQ_M_AXI_HPM1_FPD_WSTRB;
  wire ZYNQ_M_AXI_HPM1_FPD_WVALID;
  wire ZYNQ_pl_clk0;
  wire ZYNQ_pl_resetn0;
  wire adc2_clk_clk_n;
  wire adc2_clk_clk_p;
  wire [9:0]axi_smc_M00_AXI_ARADDR;
  wire axi_smc_M00_AXI_ARREADY;
  wire axi_smc_M00_AXI_ARVALID;
  wire [9:0]axi_smc_M00_AXI_AWADDR;
  wire axi_smc_M00_AXI_AWREADY;
  wire axi_smc_M00_AXI_AWVALID;
  wire axi_smc_M00_AXI_BREADY;
  wire [1:0]axi_smc_M00_AXI_BRESP;
  wire axi_smc_M00_AXI_BVALID;
  wire [31:0]axi_smc_M00_AXI_RDATA;
  wire axi_smc_M00_AXI_RREADY;
  wire [1:0]axi_smc_M00_AXI_RRESP;
  wire axi_smc_M00_AXI_RVALID;
  wire [31:0]axi_smc_M00_AXI_WDATA;
  wire axi_smc_M00_AXI_WREADY;
  wire axi_smc_M00_AXI_WVALID;
  wire [9:0]axi_smc_M01_AXI_ARADDR;
  wire axi_smc_M01_AXI_ARREADY;
  wire axi_smc_M01_AXI_ARVALID;
  wire [9:0]axi_smc_M01_AXI_AWADDR;
  wire axi_smc_M01_AXI_AWREADY;
  wire axi_smc_M01_AXI_AWVALID;
  wire axi_smc_M01_AXI_BREADY;
  wire [1:0]axi_smc_M01_AXI_BRESP;
  wire axi_smc_M01_AXI_BVALID;
  wire [31:0]axi_smc_M01_AXI_RDATA;
  wire axi_smc_M01_AXI_RREADY;
  wire [1:0]axi_smc_M01_AXI_RRESP;
  wire axi_smc_M01_AXI_RVALID;
  wire [31:0]axi_smc_M01_AXI_WDATA;
  wire axi_smc_M01_AXI_WREADY;
  wire axi_smc_M01_AXI_WVALID;
  wire [8:0]axi_smc_M02_AXI_ARADDR;
  wire axi_smc_M02_AXI_ARREADY;
  wire axi_smc_M02_AXI_ARVALID;
  wire [8:0]axi_smc_M02_AXI_AWADDR;
  wire axi_smc_M02_AXI_AWREADY;
  wire axi_smc_M02_AXI_AWVALID;
  wire axi_smc_M02_AXI_BREADY;
  wire [1:0]axi_smc_M02_AXI_BRESP;
  wire axi_smc_M02_AXI_BVALID;
  wire [31:0]axi_smc_M02_AXI_RDATA;
  wire axi_smc_M02_AXI_RREADY;
  wire [1:0]axi_smc_M02_AXI_RRESP;
  wire axi_smc_M02_AXI_RVALID;
  wire [31:0]axi_smc_M02_AXI_WDATA;
  wire axi_smc_M02_AXI_WREADY;
  wire [3:0]axi_smc_M02_AXI_WSTRB;
  wire axi_smc_M02_AXI_WVALID;
  wire [8:0]axi_smc_M03_AXI_ARADDR;
  wire axi_smc_M03_AXI_ARREADY;
  wire axi_smc_M03_AXI_ARVALID;
  wire [8:0]axi_smc_M03_AXI_AWADDR;
  wire axi_smc_M03_AXI_AWREADY;
  wire axi_smc_M03_AXI_AWVALID;
  wire axi_smc_M03_AXI_BREADY;
  wire [1:0]axi_smc_M03_AXI_BRESP;
  wire axi_smc_M03_AXI_BVALID;
  wire [31:0]axi_smc_M03_AXI_RDATA;
  wire axi_smc_M03_AXI_RREADY;
  wire [1:0]axi_smc_M03_AXI_RRESP;
  wire axi_smc_M03_AXI_RVALID;
  wire [31:0]axi_smc_M03_AXI_WDATA;
  wire axi_smc_M03_AXI_WREADY;
  wire [3:0]axi_smc_M03_AXI_WSTRB;
  wire axi_smc_M03_AXI_WVALID;
  wire [8:0]axi_smc_M04_AXI_ARADDR;
  wire axi_smc_M04_AXI_ARREADY;
  wire axi_smc_M04_AXI_ARVALID;
  wire [8:0]axi_smc_M04_AXI_AWADDR;
  wire axi_smc_M04_AXI_AWREADY;
  wire axi_smc_M04_AXI_AWVALID;
  wire axi_smc_M04_AXI_BREADY;
  wire [1:0]axi_smc_M04_AXI_BRESP;
  wire axi_smc_M04_AXI_BVALID;
  wire [31:0]axi_smc_M04_AXI_RDATA;
  wire axi_smc_M04_AXI_RREADY;
  wire [1:0]axi_smc_M04_AXI_RRESP;
  wire axi_smc_M04_AXI_RVALID;
  wire [31:0]axi_smc_M04_AXI_WDATA;
  wire axi_smc_M04_AXI_WREADY;
  wire [3:0]axi_smc_M04_AXI_WSTRB;
  wire axi_smc_M04_AXI_WVALID;
  wire [17:0]axi_smc_M05_AXI_ARADDR;
  wire axi_smc_M05_AXI_ARREADY;
  wire axi_smc_M05_AXI_ARVALID;
  wire [17:0]axi_smc_M05_AXI_AWADDR;
  wire axi_smc_M05_AXI_AWREADY;
  wire axi_smc_M05_AXI_AWVALID;
  wire axi_smc_M05_AXI_BREADY;
  wire [1:0]axi_smc_M05_AXI_BRESP;
  wire axi_smc_M05_AXI_BVALID;
  wire [31:0]axi_smc_M05_AXI_RDATA;
  wire axi_smc_M05_AXI_RREADY;
  wire [1:0]axi_smc_M05_AXI_RRESP;
  wire axi_smc_M05_AXI_RVALID;
  wire [31:0]axi_smc_M05_AXI_WDATA;
  wire axi_smc_M05_AXI_WREADY;
  wire [3:0]axi_smc_M05_AXI_WSTRB;
  wire axi_smc_M05_AXI_WVALID;
  wire [31:0]axis_iq_packer_0_m_axis_TDATA;
  wire axis_iq_packer_0_m_axis_TREADY;
  wire axis_iq_packer_0_m_axis_TVALID;
  wire [31:0]axis_tlast_gen_0_m_axis_TDATA;
  wire axis_tlast_gen_0_m_axis_TLAST;
  wire axis_tlast_gen_0_m_axis_TREADY;
  wire axis_tlast_gen_0_m_axis_TVALID;
  wire dac0_clk_clk_n;
  wire dac0_clk_clk_p;
  wire [0:0]proc_sys_reset_0_peripheral_aresetn;
  wire [0:0]rst_ZYNQ_99M_peripheral_aresetn;
  wire sysref_in_diff_n;
  wire sysref_in_diff_p;
  wire vin2_23_v_n;
  wire vin2_23_v_p;
  wire vout00_v_n;
  wire vout00_v_p;
  wire [31:0]xlconstant_0_dout;

  Loopback_axi_dma_0_0 AXI_DMA_NOSG
       (.axi_resetn(rst_ZYNQ_99M_peripheral_aresetn),
        .m_axi_s2mm_aclk(ZYNQ_pl_clk0),
        .m_axi_s2mm_awaddr(AXI_DMA_NOSG_M_AXI_S2MM_AWADDR),
        .m_axi_s2mm_awburst(AXI_DMA_NOSG_M_AXI_S2MM_AWBURST),
        .m_axi_s2mm_awcache(AXI_DMA_NOSG_M_AXI_S2MM_AWCACHE),
        .m_axi_s2mm_awlen(AXI_DMA_NOSG_M_AXI_S2MM_AWLEN),
        .m_axi_s2mm_awprot(AXI_DMA_NOSG_M_AXI_S2MM_AWPROT),
        .m_axi_s2mm_awready(AXI_DMA_NOSG_M_AXI_S2MM_AWREADY),
        .m_axi_s2mm_awsize(AXI_DMA_NOSG_M_AXI_S2MM_AWSIZE),
        .m_axi_s2mm_awvalid(AXI_DMA_NOSG_M_AXI_S2MM_AWVALID),
        .m_axi_s2mm_bready(AXI_DMA_NOSG_M_AXI_S2MM_BREADY),
        .m_axi_s2mm_bresp(AXI_DMA_NOSG_M_AXI_S2MM_BRESP),
        .m_axi_s2mm_bvalid(AXI_DMA_NOSG_M_AXI_S2MM_BVALID),
        .m_axi_s2mm_wdata(AXI_DMA_NOSG_M_AXI_S2MM_WDATA),
        .m_axi_s2mm_wlast(AXI_DMA_NOSG_M_AXI_S2MM_WLAST),
        .m_axi_s2mm_wready(AXI_DMA_NOSG_M_AXI_S2MM_WREADY),
        .m_axi_s2mm_wstrb(AXI_DMA_NOSG_M_AXI_S2MM_WSTRB),
        .m_axi_s2mm_wvalid(AXI_DMA_NOSG_M_AXI_S2MM_WVALID),
        .s_axi_lite_aclk(ZYNQ_pl_clk0),
        .s_axi_lite_araddr(axi_smc_M00_AXI_ARADDR),
        .s_axi_lite_arready(axi_smc_M00_AXI_ARREADY),
        .s_axi_lite_arvalid(axi_smc_M00_AXI_ARVALID),
        .s_axi_lite_awaddr(axi_smc_M00_AXI_AWADDR),
        .s_axi_lite_awready(axi_smc_M00_AXI_AWREADY),
        .s_axi_lite_awvalid(axi_smc_M00_AXI_AWVALID),
        .s_axi_lite_bready(axi_smc_M00_AXI_BREADY),
        .s_axi_lite_bresp(axi_smc_M00_AXI_BRESP),
        .s_axi_lite_bvalid(axi_smc_M00_AXI_BVALID),
        .s_axi_lite_rdata(axi_smc_M00_AXI_RDATA),
        .s_axi_lite_rready(axi_smc_M00_AXI_RREADY),
        .s_axi_lite_rresp(axi_smc_M00_AXI_RRESP),
        .s_axi_lite_rvalid(axi_smc_M00_AXI_RVALID),
        .s_axi_lite_wdata(axi_smc_M00_AXI_WDATA),
        .s_axi_lite_wready(axi_smc_M00_AXI_WREADY),
        .s_axi_lite_wvalid(axi_smc_M00_AXI_WVALID),
        .s_axis_s2mm_tdata(axis_tlast_gen_0_m_axis_TDATA),
        .s_axis_s2mm_tkeep({1'b1,1'b1,1'b1,1'b1}),
        .s_axis_s2mm_tlast(axis_tlast_gen_0_m_axis_TLAST),
        .s_axis_s2mm_tready(axis_tlast_gen_0_m_axis_TREADY),
        .s_axis_s2mm_tvalid(axis_tlast_gen_0_m_axis_TVALID));
  Loopback_axi_dma_1_0 AXI_DMA_SG
       (.axi_resetn(rst_ZYNQ_99M_peripheral_aresetn),
        .m_axi_mm2s_aclk(ZYNQ_pl_clk0),
        .m_axi_mm2s_araddr(AXI_DMA_SG_M_AXI_MM2S_ARADDR),
        .m_axi_mm2s_arburst(AXI_DMA_SG_M_AXI_MM2S_ARBURST),
        .m_axi_mm2s_arcache(AXI_DMA_SG_M_AXI_MM2S_ARCACHE),
        .m_axi_mm2s_arlen(AXI_DMA_SG_M_AXI_MM2S_ARLEN),
        .m_axi_mm2s_arprot(AXI_DMA_SG_M_AXI_MM2S_ARPROT),
        .m_axi_mm2s_arready(AXI_DMA_SG_M_AXI_MM2S_ARREADY),
        .m_axi_mm2s_arsize(AXI_DMA_SG_M_AXI_MM2S_ARSIZE),
        .m_axi_mm2s_arvalid(AXI_DMA_SG_M_AXI_MM2S_ARVALID),
        .m_axi_mm2s_rdata(AXI_DMA_SG_M_AXI_MM2S_RDATA),
        .m_axi_mm2s_rlast(AXI_DMA_SG_M_AXI_MM2S_RLAST),
        .m_axi_mm2s_rready(AXI_DMA_SG_M_AXI_MM2S_RREADY),
        .m_axi_mm2s_rresp(AXI_DMA_SG_M_AXI_MM2S_RRESP),
        .m_axi_mm2s_rvalid(AXI_DMA_SG_M_AXI_MM2S_RVALID),
        .m_axi_sg_aclk(ZYNQ_pl_clk0),
        .m_axi_sg_araddr(AXI_DMA_SG_M_AXI_SG_ARADDR),
        .m_axi_sg_arburst(AXI_DMA_SG_M_AXI_SG_ARBURST),
        .m_axi_sg_arcache(AXI_DMA_SG_M_AXI_SG_ARCACHE),
        .m_axi_sg_arlen(AXI_DMA_SG_M_AXI_SG_ARLEN),
        .m_axi_sg_arprot(AXI_DMA_SG_M_AXI_SG_ARPROT),
        .m_axi_sg_arready(AXI_DMA_SG_M_AXI_SG_ARREADY),
        .m_axi_sg_arsize(AXI_DMA_SG_M_AXI_SG_ARSIZE),
        .m_axi_sg_arvalid(AXI_DMA_SG_M_AXI_SG_ARVALID),
        .m_axi_sg_awaddr(AXI_DMA_SG_M_AXI_SG_AWADDR),
        .m_axi_sg_awburst(AXI_DMA_SG_M_AXI_SG_AWBURST),
        .m_axi_sg_awcache(AXI_DMA_SG_M_AXI_SG_AWCACHE),
        .m_axi_sg_awlen(AXI_DMA_SG_M_AXI_SG_AWLEN),
        .m_axi_sg_awprot(AXI_DMA_SG_M_AXI_SG_AWPROT),
        .m_axi_sg_awready(AXI_DMA_SG_M_AXI_SG_AWREADY),
        .m_axi_sg_awsize(AXI_DMA_SG_M_AXI_SG_AWSIZE),
        .m_axi_sg_awvalid(AXI_DMA_SG_M_AXI_SG_AWVALID),
        .m_axi_sg_bready(AXI_DMA_SG_M_AXI_SG_BREADY),
        .m_axi_sg_bresp(AXI_DMA_SG_M_AXI_SG_BRESP),
        .m_axi_sg_bvalid(AXI_DMA_SG_M_AXI_SG_BVALID),
        .m_axi_sg_rdata(AXI_DMA_SG_M_AXI_SG_RDATA),
        .m_axi_sg_rlast(AXI_DMA_SG_M_AXI_SG_RLAST),
        .m_axi_sg_rready(AXI_DMA_SG_M_AXI_SG_RREADY),
        .m_axi_sg_rresp(AXI_DMA_SG_M_AXI_SG_RRESP),
        .m_axi_sg_rvalid(AXI_DMA_SG_M_AXI_SG_RVALID),
        .m_axi_sg_wdata(AXI_DMA_SG_M_AXI_SG_WDATA),
        .m_axi_sg_wlast(AXI_DMA_SG_M_AXI_SG_WLAST),
        .m_axi_sg_wready(AXI_DMA_SG_M_AXI_SG_WREADY),
        .m_axi_sg_wstrb(AXI_DMA_SG_M_AXI_SG_WSTRB),
        .m_axi_sg_wvalid(AXI_DMA_SG_M_AXI_SG_WVALID),
        .m_axis_mm2s_cntrl_tready(1'b1),
        .m_axis_mm2s_tdata(AXI_DMA_SG_M_AXIS_MM2S_TDATA),
        .m_axis_mm2s_tkeep(AXI_DMA_SG_M_AXIS_MM2S_TKEEP),
        .m_axis_mm2s_tlast(AXI_DMA_SG_M_AXIS_MM2S_TLAST),
        .m_axis_mm2s_tready(AXI_DMA_SG_M_AXIS_MM2S_TREADY),
        .m_axis_mm2s_tvalid(AXI_DMA_SG_M_AXIS_MM2S_TVALID),
        .s_axi_lite_aclk(ZYNQ_pl_clk0),
        .s_axi_lite_araddr(axi_smc_M01_AXI_ARADDR),
        .s_axi_lite_arready(axi_smc_M01_AXI_ARREADY),
        .s_axi_lite_arvalid(axi_smc_M01_AXI_ARVALID),
        .s_axi_lite_awaddr(axi_smc_M01_AXI_AWADDR),
        .s_axi_lite_awready(axi_smc_M01_AXI_AWREADY),
        .s_axi_lite_awvalid(axi_smc_M01_AXI_AWVALID),
        .s_axi_lite_bready(axi_smc_M01_AXI_BREADY),
        .s_axi_lite_bresp(axi_smc_M01_AXI_BRESP),
        .s_axi_lite_bvalid(axi_smc_M01_AXI_BVALID),
        .s_axi_lite_rdata(axi_smc_M01_AXI_RDATA),
        .s_axi_lite_rready(axi_smc_M01_AXI_RREADY),
        .s_axi_lite_rresp(axi_smc_M01_AXI_RRESP),
        .s_axi_lite_rvalid(axi_smc_M01_AXI_RVALID),
        .s_axi_lite_wdata(axi_smc_M01_AXI_WDATA),
        .s_axi_lite_wready(axi_smc_M01_AXI_WREADY),
        .s_axi_lite_wvalid(axi_smc_M01_AXI_WVALID));
  Loopback_xlconstant_1_1 ONE
       (.dout(ONE_dout));
  Loopback_usp_rf_data_converter_0_0 RFDC
       (.adc2_clk_n(adc2_clk_clk_n),
        .adc2_clk_p(adc2_clk_clk_p),
        .clk_adc2(RFDC_clk_adc2),
        .clk_dac0(RFDC_clk_dac0),
        .dac0_clk_n(dac0_clk_clk_n),
        .dac0_clk_p(dac0_clk_clk_p),
        .m22_axis_tdata(RFDC_m22_axis_TDATA),
        .m22_axis_tready(RFDC_m22_axis_TREADY),
        .m22_axis_tvalid(RFDC_m22_axis_TVALID),
        .m23_axis_tdata(RFDC_m23_axis_TDATA),
        .m23_axis_tready(RFDC_m23_axis_TREADY),
        .m23_axis_tvalid(RFDC_m23_axis_TVALID),
        .m2_axis_aclk(Net),
        .m2_axis_aresetn(RX_FIFO_RESET_SYNC_peripheral_aresetn),
        .s00_axis_tdata(TX_FIFO_M_AXIS_TDATA),
        .s00_axis_tready(TX_FIFO_M_AXIS_TREADY),
        .s00_axis_tvalid(TX_FIFO_M_AXIS_TVALID),
        .s0_axis_aclk(TX_FIFO_CLK_clk_out1),
        .s0_axis_aresetn(proc_sys_reset_0_peripheral_aresetn),
        .s_axi_aclk(ZYNQ_pl_clk0),
        .s_axi_araddr(axi_smc_M05_AXI_ARADDR),
        .s_axi_aresetn(rst_ZYNQ_99M_peripheral_aresetn),
        .s_axi_arready(axi_smc_M05_AXI_ARREADY),
        .s_axi_arvalid(axi_smc_M05_AXI_ARVALID),
        .s_axi_awaddr(axi_smc_M05_AXI_AWADDR),
        .s_axi_awready(axi_smc_M05_AXI_AWREADY),
        .s_axi_awvalid(axi_smc_M05_AXI_AWVALID),
        .s_axi_bready(axi_smc_M05_AXI_BREADY),
        .s_axi_bresp(axi_smc_M05_AXI_BRESP),
        .s_axi_bvalid(axi_smc_M05_AXI_BVALID),
        .s_axi_rdata(axi_smc_M05_AXI_RDATA),
        .s_axi_rready(axi_smc_M05_AXI_RREADY),
        .s_axi_rresp(axi_smc_M05_AXI_RRESP),
        .s_axi_rvalid(axi_smc_M05_AXI_RVALID),
        .s_axi_wdata(axi_smc_M05_AXI_WDATA),
        .s_axi_wready(axi_smc_M05_AXI_WREADY),
        .s_axi_wstrb(axi_smc_M05_AXI_WSTRB),
        .s_axi_wvalid(axi_smc_M05_AXI_WVALID),
        .sysref_in_n(sysref_in_diff_n),
        .sysref_in_p(sysref_in_diff_p),
        .vin2_23_n(vin2_23_v_n),
        .vin2_23_p(vin2_23_v_p),
        .vout00_n(vout00_v_n),
        .vout00_p(vout00_v_p));
  Loopback_axis_data_fifo_0_0 RX_FIFO
       (.m_axis_aclk(ZYNQ_pl_clk0),
        .m_axis_tdata(RX_FIFO_M_AXIS_TDATA),
        .m_axis_tready(RX_FIFO_M_AXIS_TREADY),
        .m_axis_tvalid(RX_FIFO_M_AXIS_TVALID),
        .s_axis_aclk(Net),
        .s_axis_aresetn(RX_FIFO_RESET_SYNC_peripheral_aresetn),
        .s_axis_tdata(axis_iq_packer_0_m_axis_TDATA),
        .s_axis_tready(axis_iq_packer_0_m_axis_TREADY),
        .s_axis_tvalid(axis_iq_packer_0_m_axis_TVALID));
  Loopback_clk_wiz_1_0 RX_FIFO_CLK
       (.clk_in1(RFDC_clk_adc2),
        .clk_out1(Net));
  Loopback_axi_gpio_0_1 RX_FIFO_RESET
       (.gpio_io_o(LED0),
        .s_axi_aclk(ZYNQ_pl_clk0),
        .s_axi_araddr(axi_smc_M02_AXI_ARADDR),
        .s_axi_aresetn(rst_ZYNQ_99M_peripheral_aresetn),
        .s_axi_arready(axi_smc_M02_AXI_ARREADY),
        .s_axi_arvalid(axi_smc_M02_AXI_ARVALID),
        .s_axi_awaddr(axi_smc_M02_AXI_AWADDR),
        .s_axi_awready(axi_smc_M02_AXI_AWREADY),
        .s_axi_awvalid(axi_smc_M02_AXI_AWVALID),
        .s_axi_bready(axi_smc_M02_AXI_BREADY),
        .s_axi_bresp(axi_smc_M02_AXI_BRESP),
        .s_axi_bvalid(axi_smc_M02_AXI_BVALID),
        .s_axi_rdata(axi_smc_M02_AXI_RDATA),
        .s_axi_rready(axi_smc_M02_AXI_RREADY),
        .s_axi_rresp(axi_smc_M02_AXI_RRESP),
        .s_axi_rvalid(axi_smc_M02_AXI_RVALID),
        .s_axi_wdata(axi_smc_M02_AXI_WDATA),
        .s_axi_wready(axi_smc_M02_AXI_WREADY),
        .s_axi_wstrb(axi_smc_M02_AXI_WSTRB),
        .s_axi_wvalid(axi_smc_M02_AXI_WVALID));
  Loopback_proc_sys_reset_0_0 RX_FIFO_RESET_SYNC
       (.aux_reset_in(LED0),
        .dcm_locked(ONE_dout),
        .ext_reset_in(ZYNQ_pl_resetn0),
        .mb_debug_sys_rst(ZERO_dout),
        .peripheral_aresetn(RX_FIFO_RESET_SYNC_peripheral_aresetn),
        .slowest_sync_clk(Net));
  Loopback_axi_gpio_0_2 RX_FIFO_TLAST
       (.gpio_io_o(RX_FIFO_TLAST_gpio_io_o),
        .s_axi_aclk(ZYNQ_pl_clk0),
        .s_axi_araddr(axi_smc_M03_AXI_ARADDR),
        .s_axi_aresetn(rst_ZYNQ_99M_peripheral_aresetn),
        .s_axi_arready(axi_smc_M03_AXI_ARREADY),
        .s_axi_arvalid(axi_smc_M03_AXI_ARVALID),
        .s_axi_awaddr(axi_smc_M03_AXI_AWADDR),
        .s_axi_awready(axi_smc_M03_AXI_AWREADY),
        .s_axi_awvalid(axi_smc_M03_AXI_AWVALID),
        .s_axi_bready(axi_smc_M03_AXI_BREADY),
        .s_axi_bresp(axi_smc_M03_AXI_BRESP),
        .s_axi_bvalid(axi_smc_M03_AXI_BVALID),
        .s_axi_rdata(axi_smc_M03_AXI_RDATA),
        .s_axi_rready(axi_smc_M03_AXI_RREADY),
        .s_axi_rresp(axi_smc_M03_AXI_RRESP),
        .s_axi_rvalid(axi_smc_M03_AXI_RVALID),
        .s_axi_wdata(axi_smc_M03_AXI_WDATA),
        .s_axi_wready(axi_smc_M03_AXI_WREADY),
        .s_axi_wstrb(axi_smc_M03_AXI_WSTRB),
        .s_axi_wvalid(axi_smc_M03_AXI_WVALID));
  Loopback_smartconnect_0_1 SMART_NOSG
       (.M00_AXI_awaddr(SMART_NOSG_M00_AXI_AWADDR),
        .M00_AXI_awburst(SMART_NOSG_M00_AXI_AWBURST),
        .M00_AXI_awcache(SMART_NOSG_M00_AXI_AWCACHE),
        .M00_AXI_awlen(SMART_NOSG_M00_AXI_AWLEN),
        .M00_AXI_awlock(SMART_NOSG_M00_AXI_AWLOCK),
        .M00_AXI_awprot(SMART_NOSG_M00_AXI_AWPROT),
        .M00_AXI_awqos(SMART_NOSG_M00_AXI_AWQOS),
        .M00_AXI_awready(SMART_NOSG_M00_AXI_AWREADY),
        .M00_AXI_awsize(SMART_NOSG_M00_AXI_AWSIZE),
        .M00_AXI_awvalid(SMART_NOSG_M00_AXI_AWVALID),
        .M00_AXI_bready(SMART_NOSG_M00_AXI_BREADY),
        .M00_AXI_bresp(SMART_NOSG_M00_AXI_BRESP),
        .M00_AXI_bvalid(SMART_NOSG_M00_AXI_BVALID),
        .M00_AXI_wdata(SMART_NOSG_M00_AXI_WDATA),
        .M00_AXI_wlast(SMART_NOSG_M00_AXI_WLAST),
        .M00_AXI_wready(SMART_NOSG_M00_AXI_WREADY),
        .M00_AXI_wstrb(SMART_NOSG_M00_AXI_WSTRB),
        .M00_AXI_wvalid(SMART_NOSG_M00_AXI_WVALID),
        .S00_AXI_awaddr(AXI_DMA_NOSG_M_AXI_S2MM_AWADDR),
        .S00_AXI_awburst(AXI_DMA_NOSG_M_AXI_S2MM_AWBURST),
        .S00_AXI_awcache(AXI_DMA_NOSG_M_AXI_S2MM_AWCACHE),
        .S00_AXI_awlen(AXI_DMA_NOSG_M_AXI_S2MM_AWLEN),
        .S00_AXI_awlock(1'b0),
        .S00_AXI_awprot(AXI_DMA_NOSG_M_AXI_S2MM_AWPROT),
        .S00_AXI_awqos({1'b0,1'b0,1'b0,1'b0}),
        .S00_AXI_awready(AXI_DMA_NOSG_M_AXI_S2MM_AWREADY),
        .S00_AXI_awsize(AXI_DMA_NOSG_M_AXI_S2MM_AWSIZE),
        .S00_AXI_awvalid(AXI_DMA_NOSG_M_AXI_S2MM_AWVALID),
        .S00_AXI_bready(AXI_DMA_NOSG_M_AXI_S2MM_BREADY),
        .S00_AXI_bresp(AXI_DMA_NOSG_M_AXI_S2MM_BRESP),
        .S00_AXI_bvalid(AXI_DMA_NOSG_M_AXI_S2MM_BVALID),
        .S00_AXI_wdata(AXI_DMA_NOSG_M_AXI_S2MM_WDATA),
        .S00_AXI_wlast(AXI_DMA_NOSG_M_AXI_S2MM_WLAST),
        .S00_AXI_wready(AXI_DMA_NOSG_M_AXI_S2MM_WREADY),
        .S00_AXI_wstrb(AXI_DMA_NOSG_M_AXI_S2MM_WSTRB),
        .S00_AXI_wvalid(AXI_DMA_NOSG_M_AXI_S2MM_WVALID),
        .aclk(ZYNQ_pl_clk0),
        .aresetn(1'b1));
  Loopback_smartconnect_0_0 SMART_SG
       (.M00_AXI_araddr(SMART_SG_M00_AXI_ARADDR),
        .M00_AXI_arburst(SMART_SG_M00_AXI_ARBURST),
        .M00_AXI_arcache(SMART_SG_M00_AXI_ARCACHE),
        .M00_AXI_arlen(SMART_SG_M00_AXI_ARLEN),
        .M00_AXI_arlock(SMART_SG_M00_AXI_ARLOCK),
        .M00_AXI_arprot(SMART_SG_M00_AXI_ARPROT),
        .M00_AXI_arqos(SMART_SG_M00_AXI_ARQOS),
        .M00_AXI_arready(SMART_SG_M00_AXI_ARREADY),
        .M00_AXI_arsize(SMART_SG_M00_AXI_ARSIZE),
        .M00_AXI_arvalid(SMART_SG_M00_AXI_ARVALID),
        .M00_AXI_awaddr(SMART_SG_M00_AXI_AWADDR),
        .M00_AXI_awburst(SMART_SG_M00_AXI_AWBURST),
        .M00_AXI_awcache(SMART_SG_M00_AXI_AWCACHE),
        .M00_AXI_awlen(SMART_SG_M00_AXI_AWLEN),
        .M00_AXI_awlock(SMART_SG_M00_AXI_AWLOCK),
        .M00_AXI_awprot(SMART_SG_M00_AXI_AWPROT),
        .M00_AXI_awqos(SMART_SG_M00_AXI_AWQOS),
        .M00_AXI_awready(SMART_SG_M00_AXI_AWREADY),
        .M00_AXI_awsize(SMART_SG_M00_AXI_AWSIZE),
        .M00_AXI_awvalid(SMART_SG_M00_AXI_AWVALID),
        .M00_AXI_bready(SMART_SG_M00_AXI_BREADY),
        .M00_AXI_bresp(SMART_SG_M00_AXI_BRESP),
        .M00_AXI_bvalid(SMART_SG_M00_AXI_BVALID),
        .M00_AXI_rdata(SMART_SG_M00_AXI_RDATA),
        .M00_AXI_rlast(SMART_SG_M00_AXI_RLAST),
        .M00_AXI_rready(SMART_SG_M00_AXI_RREADY),
        .M00_AXI_rresp(SMART_SG_M00_AXI_RRESP),
        .M00_AXI_rvalid(SMART_SG_M00_AXI_RVALID),
        .M00_AXI_wdata(SMART_SG_M00_AXI_WDATA),
        .M00_AXI_wlast(SMART_SG_M00_AXI_WLAST),
        .M00_AXI_wready(SMART_SG_M00_AXI_WREADY),
        .M00_AXI_wstrb(SMART_SG_M00_AXI_WSTRB),
        .M00_AXI_wvalid(SMART_SG_M00_AXI_WVALID),
        .S00_AXI_araddr(AXI_DMA_SG_M_AXI_MM2S_ARADDR),
        .S00_AXI_arburst(AXI_DMA_SG_M_AXI_MM2S_ARBURST),
        .S00_AXI_arcache(AXI_DMA_SG_M_AXI_MM2S_ARCACHE),
        .S00_AXI_arlen(AXI_DMA_SG_M_AXI_MM2S_ARLEN),
        .S00_AXI_arlock(1'b0),
        .S00_AXI_arprot(AXI_DMA_SG_M_AXI_MM2S_ARPROT),
        .S00_AXI_arqos({1'b0,1'b0,1'b0,1'b0}),
        .S00_AXI_arready(AXI_DMA_SG_M_AXI_MM2S_ARREADY),
        .S00_AXI_arsize(AXI_DMA_SG_M_AXI_MM2S_ARSIZE),
        .S00_AXI_arvalid(AXI_DMA_SG_M_AXI_MM2S_ARVALID),
        .S00_AXI_rdata(AXI_DMA_SG_M_AXI_MM2S_RDATA),
        .S00_AXI_rlast(AXI_DMA_SG_M_AXI_MM2S_RLAST),
        .S00_AXI_rready(AXI_DMA_SG_M_AXI_MM2S_RREADY),
        .S00_AXI_rresp(AXI_DMA_SG_M_AXI_MM2S_RRESP),
        .S00_AXI_rvalid(AXI_DMA_SG_M_AXI_MM2S_RVALID),
        .S01_AXI_araddr(AXI_DMA_SG_M_AXI_SG_ARADDR),
        .S01_AXI_arburst(AXI_DMA_SG_M_AXI_SG_ARBURST),
        .S01_AXI_arcache(AXI_DMA_SG_M_AXI_SG_ARCACHE),
        .S01_AXI_arlen(AXI_DMA_SG_M_AXI_SG_ARLEN),
        .S01_AXI_arlock(1'b0),
        .S01_AXI_arprot(AXI_DMA_SG_M_AXI_SG_ARPROT),
        .S01_AXI_arqos({1'b0,1'b0,1'b0,1'b0}),
        .S01_AXI_arready(AXI_DMA_SG_M_AXI_SG_ARREADY),
        .S01_AXI_arsize(AXI_DMA_SG_M_AXI_SG_ARSIZE),
        .S01_AXI_arvalid(AXI_DMA_SG_M_AXI_SG_ARVALID),
        .S01_AXI_awaddr(AXI_DMA_SG_M_AXI_SG_AWADDR),
        .S01_AXI_awburst(AXI_DMA_SG_M_AXI_SG_AWBURST),
        .S01_AXI_awcache(AXI_DMA_SG_M_AXI_SG_AWCACHE),
        .S01_AXI_awlen(AXI_DMA_SG_M_AXI_SG_AWLEN),
        .S01_AXI_awlock(1'b0),
        .S01_AXI_awprot(AXI_DMA_SG_M_AXI_SG_AWPROT),
        .S01_AXI_awqos({1'b0,1'b0,1'b0,1'b0}),
        .S01_AXI_awready(AXI_DMA_SG_M_AXI_SG_AWREADY),
        .S01_AXI_awsize(AXI_DMA_SG_M_AXI_SG_AWSIZE),
        .S01_AXI_awvalid(AXI_DMA_SG_M_AXI_SG_AWVALID),
        .S01_AXI_bready(AXI_DMA_SG_M_AXI_SG_BREADY),
        .S01_AXI_bresp(AXI_DMA_SG_M_AXI_SG_BRESP),
        .S01_AXI_bvalid(AXI_DMA_SG_M_AXI_SG_BVALID),
        .S01_AXI_rdata(AXI_DMA_SG_M_AXI_SG_RDATA),
        .S01_AXI_rlast(AXI_DMA_SG_M_AXI_SG_RLAST),
        .S01_AXI_rready(AXI_DMA_SG_M_AXI_SG_RREADY),
        .S01_AXI_rresp(AXI_DMA_SG_M_AXI_SG_RRESP),
        .S01_AXI_rvalid(AXI_DMA_SG_M_AXI_SG_RVALID),
        .S01_AXI_wdata(AXI_DMA_SG_M_AXI_SG_WDATA),
        .S01_AXI_wlast(AXI_DMA_SG_M_AXI_SG_WLAST),
        .S01_AXI_wready(AXI_DMA_SG_M_AXI_SG_WREADY),
        .S01_AXI_wstrb(AXI_DMA_SG_M_AXI_SG_WSTRB),
        .S01_AXI_wvalid(AXI_DMA_SG_M_AXI_SG_WVALID),
        .aclk(ZYNQ_pl_clk0),
        .aresetn(1'b1));
  Loopback_axis_data_fifo_0_1 TX_FIFO
       (.m_axis_aclk(TX_FIFO_CLK_clk_out1),
        .m_axis_tdata(TX_FIFO_M_AXIS_TDATA),
        .m_axis_tready(TX_FIFO_M_AXIS_TREADY),
        .m_axis_tvalid(TX_FIFO_M_AXIS_TVALID),
        .s_axis_aclk(ZYNQ_pl_clk0),
        .s_axis_aresetn(rst_ZYNQ_99M_peripheral_aresetn),
        .s_axis_tdata(AXI_DMA_SG_M_AXIS_MM2S_TDATA),
        .s_axis_tkeep(AXI_DMA_SG_M_AXIS_MM2S_TKEEP),
        .s_axis_tlast(AXI_DMA_SG_M_AXIS_MM2S_TLAST),
        .s_axis_tready(AXI_DMA_SG_M_AXIS_MM2S_TREADY),
        .s_axis_tvalid(AXI_DMA_SG_M_AXIS_MM2S_TVALID));
  Loopback_clk_wiz_0_0 TX_FIFO_CLK
       (.clk_in1(RFDC_clk_dac0),
        .clk_out1(TX_FIFO_CLK_clk_out1));
  Loopback_axi_gpio_0_0 VESION
       (.gpio_io_i(xlconstant_0_dout),
        .s_axi_aclk(ZYNQ_pl_clk0),
        .s_axi_araddr(axi_smc_M04_AXI_ARADDR),
        .s_axi_aresetn(rst_ZYNQ_99M_peripheral_aresetn),
        .s_axi_arready(axi_smc_M04_AXI_ARREADY),
        .s_axi_arvalid(axi_smc_M04_AXI_ARVALID),
        .s_axi_awaddr(axi_smc_M04_AXI_AWADDR),
        .s_axi_awready(axi_smc_M04_AXI_AWREADY),
        .s_axi_awvalid(axi_smc_M04_AXI_AWVALID),
        .s_axi_bready(axi_smc_M04_AXI_BREADY),
        .s_axi_bresp(axi_smc_M04_AXI_BRESP),
        .s_axi_bvalid(axi_smc_M04_AXI_BVALID),
        .s_axi_rdata(axi_smc_M04_AXI_RDATA),
        .s_axi_rready(axi_smc_M04_AXI_RREADY),
        .s_axi_rresp(axi_smc_M04_AXI_RRESP),
        .s_axi_rvalid(axi_smc_M04_AXI_RVALID),
        .s_axi_wdata(axi_smc_M04_AXI_WDATA),
        .s_axi_wready(axi_smc_M04_AXI_WREADY),
        .s_axi_wstrb(axi_smc_M04_AXI_WSTRB),
        .s_axi_wvalid(axi_smc_M04_AXI_WVALID));
  Loopback_xlconstant_1_0 ZERO
       (.dout(ZERO_dout));
  Loopback_zynq_ultra_ps_e_0_0 ZYNQ
       (.emio_gpio_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .maxigp0_araddr(ZYNQ_M_AXI_HPM0_FPD_ARADDR),
        .maxigp0_arburst(ZYNQ_M_AXI_HPM0_FPD_ARBURST),
        .maxigp0_arcache(ZYNQ_M_AXI_HPM0_FPD_ARCACHE),
        .maxigp0_arid(ZYNQ_M_AXI_HPM0_FPD_ARID),
        .maxigp0_arlen(ZYNQ_M_AXI_HPM0_FPD_ARLEN),
        .maxigp0_arlock(ZYNQ_M_AXI_HPM0_FPD_ARLOCK),
        .maxigp0_arprot(ZYNQ_M_AXI_HPM0_FPD_ARPROT),
        .maxigp0_arqos(ZYNQ_M_AXI_HPM0_FPD_ARQOS),
        .maxigp0_arready(ZYNQ_M_AXI_HPM0_FPD_ARREADY),
        .maxigp0_arsize(ZYNQ_M_AXI_HPM0_FPD_ARSIZE),
        .maxigp0_aruser(ZYNQ_M_AXI_HPM0_FPD_ARUSER),
        .maxigp0_arvalid(ZYNQ_M_AXI_HPM0_FPD_ARVALID),
        .maxigp0_awaddr(ZYNQ_M_AXI_HPM0_FPD_AWADDR),
        .maxigp0_awburst(ZYNQ_M_AXI_HPM0_FPD_AWBURST),
        .maxigp0_awcache(ZYNQ_M_AXI_HPM0_FPD_AWCACHE),
        .maxigp0_awid(ZYNQ_M_AXI_HPM0_FPD_AWID),
        .maxigp0_awlen(ZYNQ_M_AXI_HPM0_FPD_AWLEN),
        .maxigp0_awlock(ZYNQ_M_AXI_HPM0_FPD_AWLOCK),
        .maxigp0_awprot(ZYNQ_M_AXI_HPM0_FPD_AWPROT),
        .maxigp0_awqos(ZYNQ_M_AXI_HPM0_FPD_AWQOS),
        .maxigp0_awready(ZYNQ_M_AXI_HPM0_FPD_AWREADY),
        .maxigp0_awsize(ZYNQ_M_AXI_HPM0_FPD_AWSIZE),
        .maxigp0_awuser(ZYNQ_M_AXI_HPM0_FPD_AWUSER),
        .maxigp0_awvalid(ZYNQ_M_AXI_HPM0_FPD_AWVALID),
        .maxigp0_bid(ZYNQ_M_AXI_HPM0_FPD_BID),
        .maxigp0_bready(ZYNQ_M_AXI_HPM0_FPD_BREADY),
        .maxigp0_bresp(ZYNQ_M_AXI_HPM0_FPD_BRESP),
        .maxigp0_bvalid(ZYNQ_M_AXI_HPM0_FPD_BVALID),
        .maxigp0_rdata(ZYNQ_M_AXI_HPM0_FPD_RDATA),
        .maxigp0_rid(ZYNQ_M_AXI_HPM0_FPD_RID),
        .maxigp0_rlast(ZYNQ_M_AXI_HPM0_FPD_RLAST),
        .maxigp0_rready(ZYNQ_M_AXI_HPM0_FPD_RREADY),
        .maxigp0_rresp(ZYNQ_M_AXI_HPM0_FPD_RRESP),
        .maxigp0_rvalid(ZYNQ_M_AXI_HPM0_FPD_RVALID),
        .maxigp0_wdata(ZYNQ_M_AXI_HPM0_FPD_WDATA),
        .maxigp0_wlast(ZYNQ_M_AXI_HPM0_FPD_WLAST),
        .maxigp0_wready(ZYNQ_M_AXI_HPM0_FPD_WREADY),
        .maxigp0_wstrb(ZYNQ_M_AXI_HPM0_FPD_WSTRB),
        .maxigp0_wvalid(ZYNQ_M_AXI_HPM0_FPD_WVALID),
        .maxigp1_araddr(ZYNQ_M_AXI_HPM1_FPD_ARADDR),
        .maxigp1_arburst(ZYNQ_M_AXI_HPM1_FPD_ARBURST),
        .maxigp1_arcache(ZYNQ_M_AXI_HPM1_FPD_ARCACHE),
        .maxigp1_arid(ZYNQ_M_AXI_HPM1_FPD_ARID),
        .maxigp1_arlen(ZYNQ_M_AXI_HPM1_FPD_ARLEN),
        .maxigp1_arlock(ZYNQ_M_AXI_HPM1_FPD_ARLOCK),
        .maxigp1_arprot(ZYNQ_M_AXI_HPM1_FPD_ARPROT),
        .maxigp1_arqos(ZYNQ_M_AXI_HPM1_FPD_ARQOS),
        .maxigp1_arready(ZYNQ_M_AXI_HPM1_FPD_ARREADY),
        .maxigp1_arsize(ZYNQ_M_AXI_HPM1_FPD_ARSIZE),
        .maxigp1_aruser(ZYNQ_M_AXI_HPM1_FPD_ARUSER),
        .maxigp1_arvalid(ZYNQ_M_AXI_HPM1_FPD_ARVALID),
        .maxigp1_awaddr(ZYNQ_M_AXI_HPM1_FPD_AWADDR),
        .maxigp1_awburst(ZYNQ_M_AXI_HPM1_FPD_AWBURST),
        .maxigp1_awcache(ZYNQ_M_AXI_HPM1_FPD_AWCACHE),
        .maxigp1_awid(ZYNQ_M_AXI_HPM1_FPD_AWID),
        .maxigp1_awlen(ZYNQ_M_AXI_HPM1_FPD_AWLEN),
        .maxigp1_awlock(ZYNQ_M_AXI_HPM1_FPD_AWLOCK),
        .maxigp1_awprot(ZYNQ_M_AXI_HPM1_FPD_AWPROT),
        .maxigp1_awqos(ZYNQ_M_AXI_HPM1_FPD_AWQOS),
        .maxigp1_awready(ZYNQ_M_AXI_HPM1_FPD_AWREADY),
        .maxigp1_awsize(ZYNQ_M_AXI_HPM1_FPD_AWSIZE),
        .maxigp1_awuser(ZYNQ_M_AXI_HPM1_FPD_AWUSER),
        .maxigp1_awvalid(ZYNQ_M_AXI_HPM1_FPD_AWVALID),
        .maxigp1_bid(ZYNQ_M_AXI_HPM1_FPD_BID),
        .maxigp1_bready(ZYNQ_M_AXI_HPM1_FPD_BREADY),
        .maxigp1_bresp(ZYNQ_M_AXI_HPM1_FPD_BRESP),
        .maxigp1_bvalid(ZYNQ_M_AXI_HPM1_FPD_BVALID),
        .maxigp1_rdata(ZYNQ_M_AXI_HPM1_FPD_RDATA),
        .maxigp1_rid(ZYNQ_M_AXI_HPM1_FPD_RID),
        .maxigp1_rlast(ZYNQ_M_AXI_HPM1_FPD_RLAST),
        .maxigp1_rready(ZYNQ_M_AXI_HPM1_FPD_RREADY),
        .maxigp1_rresp(ZYNQ_M_AXI_HPM1_FPD_RRESP),
        .maxigp1_rvalid(ZYNQ_M_AXI_HPM1_FPD_RVALID),
        .maxigp1_wdata(ZYNQ_M_AXI_HPM1_FPD_WDATA),
        .maxigp1_wlast(ZYNQ_M_AXI_HPM1_FPD_WLAST),
        .maxigp1_wready(ZYNQ_M_AXI_HPM1_FPD_WREADY),
        .maxigp1_wstrb(ZYNQ_M_AXI_HPM1_FPD_WSTRB),
        .maxigp1_wvalid(ZYNQ_M_AXI_HPM1_FPD_WVALID),
        .maxihpm0_fpd_aclk(ZYNQ_pl_clk0),
        .maxihpm1_fpd_aclk(ZYNQ_pl_clk0),
        .pl_clk0(ZYNQ_pl_clk0),
        .pl_ps_irq0(1'b0),
        .pl_ps_irq1(1'b0),
        .pl_resetn0(ZYNQ_pl_resetn0),
        .saxigp2_araddr(SMART_SG_M00_AXI_ARADDR),
        .saxigp2_arburst(SMART_SG_M00_AXI_ARBURST),
        .saxigp2_arcache(SMART_SG_M00_AXI_ARCACHE),
        .saxigp2_arid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .saxigp2_arlen(SMART_SG_M00_AXI_ARLEN),
        .saxigp2_arlock(SMART_SG_M00_AXI_ARLOCK),
        .saxigp2_arprot(SMART_SG_M00_AXI_ARPROT),
        .saxigp2_arqos(SMART_SG_M00_AXI_ARQOS),
        .saxigp2_arready(SMART_SG_M00_AXI_ARREADY),
        .saxigp2_arsize(SMART_SG_M00_AXI_ARSIZE),
        .saxigp2_aruser(1'b0),
        .saxigp2_arvalid(SMART_SG_M00_AXI_ARVALID),
        .saxigp2_awaddr(SMART_SG_M00_AXI_AWADDR),
        .saxigp2_awburst(SMART_SG_M00_AXI_AWBURST),
        .saxigp2_awcache(SMART_SG_M00_AXI_AWCACHE),
        .saxigp2_awid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .saxigp2_awlen(SMART_SG_M00_AXI_AWLEN),
        .saxigp2_awlock(SMART_SG_M00_AXI_AWLOCK),
        .saxigp2_awprot(SMART_SG_M00_AXI_AWPROT),
        .saxigp2_awqos(SMART_SG_M00_AXI_AWQOS),
        .saxigp2_awready(SMART_SG_M00_AXI_AWREADY),
        .saxigp2_awsize(SMART_SG_M00_AXI_AWSIZE),
        .saxigp2_awuser(1'b0),
        .saxigp2_awvalid(SMART_SG_M00_AXI_AWVALID),
        .saxigp2_bready(SMART_SG_M00_AXI_BREADY),
        .saxigp2_bresp(SMART_SG_M00_AXI_BRESP),
        .saxigp2_bvalid(SMART_SG_M00_AXI_BVALID),
        .saxigp2_rdata(SMART_SG_M00_AXI_RDATA),
        .saxigp2_rlast(SMART_SG_M00_AXI_RLAST),
        .saxigp2_rready(SMART_SG_M00_AXI_RREADY),
        .saxigp2_rresp(SMART_SG_M00_AXI_RRESP),
        .saxigp2_rvalid(SMART_SG_M00_AXI_RVALID),
        .saxigp2_wdata(SMART_SG_M00_AXI_WDATA),
        .saxigp2_wlast(SMART_SG_M00_AXI_WLAST),
        .saxigp2_wready(SMART_SG_M00_AXI_WREADY),
        .saxigp2_wstrb(SMART_SG_M00_AXI_WSTRB),
        .saxigp2_wvalid(SMART_SG_M00_AXI_WVALID),
        .saxigp3_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .saxigp3_arburst({1'b0,1'b1}),
        .saxigp3_arcache({1'b0,1'b0,1'b1,1'b1}),
        .saxigp3_arid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .saxigp3_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .saxigp3_arlock(1'b0),
        .saxigp3_arprot({1'b0,1'b0,1'b0}),
        .saxigp3_arqos({1'b0,1'b0,1'b0,1'b0}),
        .saxigp3_arsize({1'b1,1'b0,1'b0}),
        .saxigp3_aruser(1'b0),
        .saxigp3_arvalid(1'b0),
        .saxigp3_awaddr(SMART_NOSG_M00_AXI_AWADDR),
        .saxigp3_awburst(SMART_NOSG_M00_AXI_AWBURST),
        .saxigp3_awcache(SMART_NOSG_M00_AXI_AWCACHE),
        .saxigp3_awid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .saxigp3_awlen(SMART_NOSG_M00_AXI_AWLEN),
        .saxigp3_awlock(SMART_NOSG_M00_AXI_AWLOCK),
        .saxigp3_awprot(SMART_NOSG_M00_AXI_AWPROT),
        .saxigp3_awqos(SMART_NOSG_M00_AXI_AWQOS),
        .saxigp3_awready(SMART_NOSG_M00_AXI_AWREADY),
        .saxigp3_awsize(SMART_NOSG_M00_AXI_AWSIZE),
        .saxigp3_awuser(1'b0),
        .saxigp3_awvalid(SMART_NOSG_M00_AXI_AWVALID),
        .saxigp3_bready(SMART_NOSG_M00_AXI_BREADY),
        .saxigp3_bresp(SMART_NOSG_M00_AXI_BRESP),
        .saxigp3_bvalid(SMART_NOSG_M00_AXI_BVALID),
        .saxigp3_rready(1'b0),
        .saxigp3_wdata(SMART_NOSG_M00_AXI_WDATA),
        .saxigp3_wlast(SMART_NOSG_M00_AXI_WLAST),
        .saxigp3_wready(SMART_NOSG_M00_AXI_WREADY),
        .saxigp3_wstrb(SMART_NOSG_M00_AXI_WSTRB),
        .saxigp3_wvalid(SMART_NOSG_M00_AXI_WVALID),
        .saxihp0_fpd_aclk(ZYNQ_pl_clk0),
        .saxihp1_fpd_aclk(ZYNQ_pl_clk0));
  Loopback_axi_smc_0 axi_smc
       (.M00_AXI_araddr(axi_smc_M00_AXI_ARADDR),
        .M00_AXI_arready(axi_smc_M00_AXI_ARREADY),
        .M00_AXI_arvalid(axi_smc_M00_AXI_ARVALID),
        .M00_AXI_awaddr(axi_smc_M00_AXI_AWADDR),
        .M00_AXI_awready(axi_smc_M00_AXI_AWREADY),
        .M00_AXI_awvalid(axi_smc_M00_AXI_AWVALID),
        .M00_AXI_bready(axi_smc_M00_AXI_BREADY),
        .M00_AXI_bresp(axi_smc_M00_AXI_BRESP),
        .M00_AXI_bvalid(axi_smc_M00_AXI_BVALID),
        .M00_AXI_rdata(axi_smc_M00_AXI_RDATA),
        .M00_AXI_rready(axi_smc_M00_AXI_RREADY),
        .M00_AXI_rresp(axi_smc_M00_AXI_RRESP),
        .M00_AXI_rvalid(axi_smc_M00_AXI_RVALID),
        .M00_AXI_wdata(axi_smc_M00_AXI_WDATA),
        .M00_AXI_wready(axi_smc_M00_AXI_WREADY),
        .M00_AXI_wvalid(axi_smc_M00_AXI_WVALID),
        .M01_AXI_araddr(axi_smc_M01_AXI_ARADDR),
        .M01_AXI_arready(axi_smc_M01_AXI_ARREADY),
        .M01_AXI_arvalid(axi_smc_M01_AXI_ARVALID),
        .M01_AXI_awaddr(axi_smc_M01_AXI_AWADDR),
        .M01_AXI_awready(axi_smc_M01_AXI_AWREADY),
        .M01_AXI_awvalid(axi_smc_M01_AXI_AWVALID),
        .M01_AXI_bready(axi_smc_M01_AXI_BREADY),
        .M01_AXI_bresp(axi_smc_M01_AXI_BRESP),
        .M01_AXI_bvalid(axi_smc_M01_AXI_BVALID),
        .M01_AXI_rdata(axi_smc_M01_AXI_RDATA),
        .M01_AXI_rready(axi_smc_M01_AXI_RREADY),
        .M01_AXI_rresp(axi_smc_M01_AXI_RRESP),
        .M01_AXI_rvalid(axi_smc_M01_AXI_RVALID),
        .M01_AXI_wdata(axi_smc_M01_AXI_WDATA),
        .M01_AXI_wready(axi_smc_M01_AXI_WREADY),
        .M01_AXI_wvalid(axi_smc_M01_AXI_WVALID),
        .M02_AXI_araddr(axi_smc_M02_AXI_ARADDR),
        .M02_AXI_arready(axi_smc_M02_AXI_ARREADY),
        .M02_AXI_arvalid(axi_smc_M02_AXI_ARVALID),
        .M02_AXI_awaddr(axi_smc_M02_AXI_AWADDR),
        .M02_AXI_awready(axi_smc_M02_AXI_AWREADY),
        .M02_AXI_awvalid(axi_smc_M02_AXI_AWVALID),
        .M02_AXI_bready(axi_smc_M02_AXI_BREADY),
        .M02_AXI_bresp(axi_smc_M02_AXI_BRESP),
        .M02_AXI_bvalid(axi_smc_M02_AXI_BVALID),
        .M02_AXI_rdata(axi_smc_M02_AXI_RDATA),
        .M02_AXI_rready(axi_smc_M02_AXI_RREADY),
        .M02_AXI_rresp(axi_smc_M02_AXI_RRESP),
        .M02_AXI_rvalid(axi_smc_M02_AXI_RVALID),
        .M02_AXI_wdata(axi_smc_M02_AXI_WDATA),
        .M02_AXI_wready(axi_smc_M02_AXI_WREADY),
        .M02_AXI_wstrb(axi_smc_M02_AXI_WSTRB),
        .M02_AXI_wvalid(axi_smc_M02_AXI_WVALID),
        .M03_AXI_araddr(axi_smc_M03_AXI_ARADDR),
        .M03_AXI_arready(axi_smc_M03_AXI_ARREADY),
        .M03_AXI_arvalid(axi_smc_M03_AXI_ARVALID),
        .M03_AXI_awaddr(axi_smc_M03_AXI_AWADDR),
        .M03_AXI_awready(axi_smc_M03_AXI_AWREADY),
        .M03_AXI_awvalid(axi_smc_M03_AXI_AWVALID),
        .M03_AXI_bready(axi_smc_M03_AXI_BREADY),
        .M03_AXI_bresp(axi_smc_M03_AXI_BRESP),
        .M03_AXI_bvalid(axi_smc_M03_AXI_BVALID),
        .M03_AXI_rdata(axi_smc_M03_AXI_RDATA),
        .M03_AXI_rready(axi_smc_M03_AXI_RREADY),
        .M03_AXI_rresp(axi_smc_M03_AXI_RRESP),
        .M03_AXI_rvalid(axi_smc_M03_AXI_RVALID),
        .M03_AXI_wdata(axi_smc_M03_AXI_WDATA),
        .M03_AXI_wready(axi_smc_M03_AXI_WREADY),
        .M03_AXI_wstrb(axi_smc_M03_AXI_WSTRB),
        .M03_AXI_wvalid(axi_smc_M03_AXI_WVALID),
        .M04_AXI_araddr(axi_smc_M04_AXI_ARADDR),
        .M04_AXI_arready(axi_smc_M04_AXI_ARREADY),
        .M04_AXI_arvalid(axi_smc_M04_AXI_ARVALID),
        .M04_AXI_awaddr(axi_smc_M04_AXI_AWADDR),
        .M04_AXI_awready(axi_smc_M04_AXI_AWREADY),
        .M04_AXI_awvalid(axi_smc_M04_AXI_AWVALID),
        .M04_AXI_bready(axi_smc_M04_AXI_BREADY),
        .M04_AXI_bresp(axi_smc_M04_AXI_BRESP),
        .M04_AXI_bvalid(axi_smc_M04_AXI_BVALID),
        .M04_AXI_rdata(axi_smc_M04_AXI_RDATA),
        .M04_AXI_rready(axi_smc_M04_AXI_RREADY),
        .M04_AXI_rresp(axi_smc_M04_AXI_RRESP),
        .M04_AXI_rvalid(axi_smc_M04_AXI_RVALID),
        .M04_AXI_wdata(axi_smc_M04_AXI_WDATA),
        .M04_AXI_wready(axi_smc_M04_AXI_WREADY),
        .M04_AXI_wstrb(axi_smc_M04_AXI_WSTRB),
        .M04_AXI_wvalid(axi_smc_M04_AXI_WVALID),
        .M05_AXI_araddr(axi_smc_M05_AXI_ARADDR),
        .M05_AXI_arready(axi_smc_M05_AXI_ARREADY),
        .M05_AXI_arvalid(axi_smc_M05_AXI_ARVALID),
        .M05_AXI_awaddr(axi_smc_M05_AXI_AWADDR),
        .M05_AXI_awready(axi_smc_M05_AXI_AWREADY),
        .M05_AXI_awvalid(axi_smc_M05_AXI_AWVALID),
        .M05_AXI_bready(axi_smc_M05_AXI_BREADY),
        .M05_AXI_bresp(axi_smc_M05_AXI_BRESP),
        .M05_AXI_bvalid(axi_smc_M05_AXI_BVALID),
        .M05_AXI_rdata(axi_smc_M05_AXI_RDATA),
        .M05_AXI_rready(axi_smc_M05_AXI_RREADY),
        .M05_AXI_rresp(axi_smc_M05_AXI_RRESP),
        .M05_AXI_rvalid(axi_smc_M05_AXI_RVALID),
        .M05_AXI_wdata(axi_smc_M05_AXI_WDATA),
        .M05_AXI_wready(axi_smc_M05_AXI_WREADY),
        .M05_AXI_wstrb(axi_smc_M05_AXI_WSTRB),
        .M05_AXI_wvalid(axi_smc_M05_AXI_WVALID),
        .S00_AXI_araddr(ZYNQ_M_AXI_HPM0_FPD_ARADDR),
        .S00_AXI_arburst(ZYNQ_M_AXI_HPM0_FPD_ARBURST),
        .S00_AXI_arcache(ZYNQ_M_AXI_HPM0_FPD_ARCACHE),
        .S00_AXI_arid(ZYNQ_M_AXI_HPM0_FPD_ARID),
        .S00_AXI_arlen(ZYNQ_M_AXI_HPM0_FPD_ARLEN),
        .S00_AXI_arlock(ZYNQ_M_AXI_HPM0_FPD_ARLOCK),
        .S00_AXI_arprot(ZYNQ_M_AXI_HPM0_FPD_ARPROT),
        .S00_AXI_arqos(ZYNQ_M_AXI_HPM0_FPD_ARQOS),
        .S00_AXI_arready(ZYNQ_M_AXI_HPM0_FPD_ARREADY),
        .S00_AXI_arsize(ZYNQ_M_AXI_HPM0_FPD_ARSIZE),
        .S00_AXI_aruser(ZYNQ_M_AXI_HPM0_FPD_ARUSER),
        .S00_AXI_arvalid(ZYNQ_M_AXI_HPM0_FPD_ARVALID),
        .S00_AXI_awaddr(ZYNQ_M_AXI_HPM0_FPD_AWADDR),
        .S00_AXI_awburst(ZYNQ_M_AXI_HPM0_FPD_AWBURST),
        .S00_AXI_awcache(ZYNQ_M_AXI_HPM0_FPD_AWCACHE),
        .S00_AXI_awid(ZYNQ_M_AXI_HPM0_FPD_AWID),
        .S00_AXI_awlen(ZYNQ_M_AXI_HPM0_FPD_AWLEN),
        .S00_AXI_awlock(ZYNQ_M_AXI_HPM0_FPD_AWLOCK),
        .S00_AXI_awprot(ZYNQ_M_AXI_HPM0_FPD_AWPROT),
        .S00_AXI_awqos(ZYNQ_M_AXI_HPM0_FPD_AWQOS),
        .S00_AXI_awready(ZYNQ_M_AXI_HPM0_FPD_AWREADY),
        .S00_AXI_awsize(ZYNQ_M_AXI_HPM0_FPD_AWSIZE),
        .S00_AXI_awuser(ZYNQ_M_AXI_HPM0_FPD_AWUSER),
        .S00_AXI_awvalid(ZYNQ_M_AXI_HPM0_FPD_AWVALID),
        .S00_AXI_bid(ZYNQ_M_AXI_HPM0_FPD_BID),
        .S00_AXI_bready(ZYNQ_M_AXI_HPM0_FPD_BREADY),
        .S00_AXI_bresp(ZYNQ_M_AXI_HPM0_FPD_BRESP),
        .S00_AXI_bvalid(ZYNQ_M_AXI_HPM0_FPD_BVALID),
        .S00_AXI_rdata(ZYNQ_M_AXI_HPM0_FPD_RDATA),
        .S00_AXI_rid(ZYNQ_M_AXI_HPM0_FPD_RID),
        .S00_AXI_rlast(ZYNQ_M_AXI_HPM0_FPD_RLAST),
        .S00_AXI_rready(ZYNQ_M_AXI_HPM0_FPD_RREADY),
        .S00_AXI_rresp(ZYNQ_M_AXI_HPM0_FPD_RRESP),
        .S00_AXI_rvalid(ZYNQ_M_AXI_HPM0_FPD_RVALID),
        .S00_AXI_wdata(ZYNQ_M_AXI_HPM0_FPD_WDATA),
        .S00_AXI_wlast(ZYNQ_M_AXI_HPM0_FPD_WLAST),
        .S00_AXI_wready(ZYNQ_M_AXI_HPM0_FPD_WREADY),
        .S00_AXI_wstrb(ZYNQ_M_AXI_HPM0_FPD_WSTRB),
        .S00_AXI_wvalid(ZYNQ_M_AXI_HPM0_FPD_WVALID),
        .S01_AXI_araddr(ZYNQ_M_AXI_HPM1_FPD_ARADDR),
        .S01_AXI_arburst(ZYNQ_M_AXI_HPM1_FPD_ARBURST),
        .S01_AXI_arcache(ZYNQ_M_AXI_HPM1_FPD_ARCACHE),
        .S01_AXI_arid(ZYNQ_M_AXI_HPM1_FPD_ARID),
        .S01_AXI_arlen(ZYNQ_M_AXI_HPM1_FPD_ARLEN),
        .S01_AXI_arlock(ZYNQ_M_AXI_HPM1_FPD_ARLOCK),
        .S01_AXI_arprot(ZYNQ_M_AXI_HPM1_FPD_ARPROT),
        .S01_AXI_arqos(ZYNQ_M_AXI_HPM1_FPD_ARQOS),
        .S01_AXI_arready(ZYNQ_M_AXI_HPM1_FPD_ARREADY),
        .S01_AXI_arsize(ZYNQ_M_AXI_HPM1_FPD_ARSIZE),
        .S01_AXI_aruser(ZYNQ_M_AXI_HPM1_FPD_ARUSER),
        .S01_AXI_arvalid(ZYNQ_M_AXI_HPM1_FPD_ARVALID),
        .S01_AXI_awaddr(ZYNQ_M_AXI_HPM1_FPD_AWADDR),
        .S01_AXI_awburst(ZYNQ_M_AXI_HPM1_FPD_AWBURST),
        .S01_AXI_awcache(ZYNQ_M_AXI_HPM1_FPD_AWCACHE),
        .S01_AXI_awid(ZYNQ_M_AXI_HPM1_FPD_AWID),
        .S01_AXI_awlen(ZYNQ_M_AXI_HPM1_FPD_AWLEN),
        .S01_AXI_awlock(ZYNQ_M_AXI_HPM1_FPD_AWLOCK),
        .S01_AXI_awprot(ZYNQ_M_AXI_HPM1_FPD_AWPROT),
        .S01_AXI_awqos(ZYNQ_M_AXI_HPM1_FPD_AWQOS),
        .S01_AXI_awready(ZYNQ_M_AXI_HPM1_FPD_AWREADY),
        .S01_AXI_awsize(ZYNQ_M_AXI_HPM1_FPD_AWSIZE),
        .S01_AXI_awuser(ZYNQ_M_AXI_HPM1_FPD_AWUSER),
        .S01_AXI_awvalid(ZYNQ_M_AXI_HPM1_FPD_AWVALID),
        .S01_AXI_bid(ZYNQ_M_AXI_HPM1_FPD_BID),
        .S01_AXI_bready(ZYNQ_M_AXI_HPM1_FPD_BREADY),
        .S01_AXI_bresp(ZYNQ_M_AXI_HPM1_FPD_BRESP),
        .S01_AXI_bvalid(ZYNQ_M_AXI_HPM1_FPD_BVALID),
        .S01_AXI_rdata(ZYNQ_M_AXI_HPM1_FPD_RDATA),
        .S01_AXI_rid(ZYNQ_M_AXI_HPM1_FPD_RID),
        .S01_AXI_rlast(ZYNQ_M_AXI_HPM1_FPD_RLAST),
        .S01_AXI_rready(ZYNQ_M_AXI_HPM1_FPD_RREADY),
        .S01_AXI_rresp(ZYNQ_M_AXI_HPM1_FPD_RRESP),
        .S01_AXI_rvalid(ZYNQ_M_AXI_HPM1_FPD_RVALID),
        .S01_AXI_wdata(ZYNQ_M_AXI_HPM1_FPD_WDATA),
        .S01_AXI_wlast(ZYNQ_M_AXI_HPM1_FPD_WLAST),
        .S01_AXI_wready(ZYNQ_M_AXI_HPM1_FPD_WREADY),
        .S01_AXI_wstrb(ZYNQ_M_AXI_HPM1_FPD_WSTRB),
        .S01_AXI_wvalid(ZYNQ_M_AXI_HPM1_FPD_WVALID),
        .aclk(ZYNQ_pl_clk0),
        .aresetn(rst_ZYNQ_99M_peripheral_aresetn));
  Loopback_axis_iq_packer_0_0 axis_iq_packer_0
       (.aclk(Net),
        .aresetn(RX_FIFO_RESET_SYNC_peripheral_aresetn),
        .m_axis_tdata(axis_iq_packer_0_m_axis_TDATA),
        .m_axis_tready(axis_iq_packer_0_m_axis_TREADY),
        .m_axis_tvalid(axis_iq_packer_0_m_axis_TVALID),
        .s_axis_i_tdata(RFDC_m22_axis_TDATA),
        .s_axis_i_tready(RFDC_m22_axis_TREADY),
        .s_axis_i_tvalid(RFDC_m22_axis_TVALID),
        .s_axis_q_tdata(RFDC_m23_axis_TDATA),
        .s_axis_q_tready(RFDC_m23_axis_TREADY),
        .s_axis_q_tvalid(RFDC_m23_axis_TVALID));
  Loopback_axis_tlast_gen_0_0 axis_tlast_gen_0
       (.aclk(ZYNQ_pl_clk0),
        .aresetn(rst_ZYNQ_99M_peripheral_aresetn),
        .m_axis_tdata(axis_tlast_gen_0_m_axis_TDATA),
        .m_axis_tlast(axis_tlast_gen_0_m_axis_TLAST),
        .m_axis_tready(axis_tlast_gen_0_m_axis_TREADY),
        .m_axis_tvalid(axis_tlast_gen_0_m_axis_TVALID),
        .s_axis_tdata(RX_FIFO_M_AXIS_TDATA),
        .s_axis_tready(RX_FIFO_M_AXIS_TREADY),
        .s_axis_tvalid(RX_FIFO_M_AXIS_TVALID),
        .word_count(RX_FIFO_TLAST_gpio_io_o));
  Loopback_proc_sys_reset_0_1 proc_sys_reset_0
       (.aux_reset_in(1'b1),
        .dcm_locked(1'b1),
        .ext_reset_in(ZYNQ_pl_resetn0),
        .mb_debug_sys_rst(1'b0),
        .peripheral_aresetn(proc_sys_reset_0_peripheral_aresetn),
        .slowest_sync_clk(TX_FIFO_CLK_clk_out1));
  Loopback_rst_ZYNQ_99M_0 rst_ZYNQ_99M
       (.aux_reset_in(1'b1),
        .dcm_locked(1'b1),
        .ext_reset_in(ZYNQ_pl_resetn0),
        .mb_debug_sys_rst(1'b0),
        .peripheral_aresetn(rst_ZYNQ_99M_peripheral_aresetn),
        .slowest_sync_clk(ZYNQ_pl_clk0));
  Loopback_xlconstant_0_0 xlconstant_0
       (.dout(xlconstant_0_dout));
endmodule
