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// IP VLNV: xilinx.com:module_ref:axis_iq_packer:1.0
// IP Revision: 1

`timescale 1ns/1ps

(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module Loopback_axis_iq_packer_0_0 (
  aclk,
  aresetn,
  s_axis_i_tdata,
  s_axis_i_tvalid,
  s_axis_i_tready,
  s_axis_q_tdata,
  s_axis_q_tvalid,
  s_axis_q_tready,
  m_axis_tdata,
  m_axis_tvalid,
  m_axis_tready
);

(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
(* X_INTERFACE_MODE = "slave" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF m_axis:s_axis_i:s_axis_q, ASSOCIATED_RESET aresetn, FREQ_HZ 122880000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN Loopback_clk_wiz_1_0_clk_out1, INSERT_VIP 0" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
(* X_INTERFACE_MODE = "slave" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_i TDATA" *)
(* X_INTERFACE_MODE = "slave" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axis_i, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 122880000, PHASE 0.0, CLK_DOMAIN Loopback_clk_wiz_1_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0" *)
input wire [15 : 0] s_axis_i_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_i TVALID" *)
input wire s_axis_i_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_i TREADY" *)
output wire s_axis_i_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_q TDATA" *)
(* X_INTERFACE_MODE = "slave" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axis_q, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 122880000, PHASE 0.0, CLK_DOMAIN Loopback_clk_wiz_1_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0" *)
input wire [15 : 0] s_axis_q_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_q TVALID" *)
input wire s_axis_q_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_q TREADY" *)
output wire s_axis_q_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
(* X_INTERFACE_MODE = "master" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 122880000, PHASE 0.0, CLK_DOMAIN Loopback_clk_wiz_1_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
input wire m_axis_tready;

  axis_iq_packer inst (
    .aclk(aclk),
    .aresetn(aresetn),
    .s_axis_i_tdata(s_axis_i_tdata),
    .s_axis_i_tvalid(s_axis_i_tvalid),
    .s_axis_i_tready(s_axis_i_tready),
    .s_axis_q_tdata(s_axis_q_tdata),
    .s_axis_q_tvalid(s_axis_q_tvalid),
    .s_axis_q_tready(s_axis_q_tready),
    .m_axis_tdata(m_axis_tdata),
    .m_axis_tvalid(m_axis_tvalid),
    .m_axis_tready(m_axis_tready)
  );
endmodule
