module axis_iq_packer (
    input  wire        aclk,
    input  wire        aresetn,
    
    // Slave 0: I stream (16-bit)
    input  wire [15:0] s_axis_i_tdata,
    input  wire        s_axis_i_tvalid,
    output wire        s_axis_i_tready,
    
    // Slave 1: Q stream (16-bit)
    input  wire [15:0] s_axis_q_tdata,
    input  wire        s_axis_q_tvalid,
    output wire        s_axis_q_tready,
    
    // Master: Packed IQ stream (32-bit)
    output wire [31:0] m_axis_tdata,
    output wire        m_axis_tvalid,
    input  wire        m_axis_tready
);

    // Join I and Q into a single 32-bit word [Q | I]
    assign m_axis_tdata  = {s_axis_q_tdata, s_axis_i_tdata};
    
    // Synchronize handshakes (both must be valid)
    assign m_axis_tvalid   = s_axis_i_tvalid && s_axis_q_tvalid;
    assign s_axis_i_tready = m_axis_tready && s_axis_q_tvalid;
    assign s_axis_q_tready = m_axis_tready && s_axis_i_tvalid;

endmodule