//----------------------------------------------------------------------------
// Title : Reset Counter Module
// Project : Ultrascale+ RF Data Converter Subsystem
//----------------------------------------------------------------------------
// File : Loopback_usp_rf_data_converter_0_0"_reset_cnt.v
//----------------------------------------------------------------------------
//
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`timescale 1ns / 1ps

module Loopback_usp_rf_data_converter_0_0_reset_count
(
  input            clk,
  input            reset,
  input            sm_reset,
  input            axi_read_req,
  output           read_ack,
  output reg [7:0] count
);

  reg     sm_reset_r;
  reg     sm_reset_pulse;

  reg     axi_read_req_r;
  reg     axi_read_req_tog;
  reg     read_ack_tog;
  reg     read_ack_tog_r;

  // Register unexpected reset
  always @(posedge clk)
    if (reset) begin
      sm_reset_r     <= 1'b0;
      sm_reset_pulse <= 1'b0;
    end
    else begin
      sm_reset_r     <= sm_reset;
      sm_reset_pulse <= sm_reset & ~sm_reset_r;
    end

  // Register read request
  always @(posedge clk)
    if (reset)
      axi_read_req_r <= 1'b0;
    else
      axi_read_req_r <= axi_read_req;

  // Flip toggle on rising edge of read request
  always @(posedge clk)
    if (reset)
      axi_read_req_tog <= 1'b0;
    else if (axi_read_req & ~axi_read_req_r)
      axi_read_req_tog <= ~axi_read_req_tog;

  // Ack immediately
  always @(posedge clk)
    if (reset)
      read_ack_tog <= 1'b0;
    else
      read_ack_tog <= axi_read_req_tog;

  // Register ack
  always @(posedge clk)
    if (reset)
      read_ack_tog_r <= 1'b0;
    else
      read_ack_tog_r <= read_ack_tog;

  // Detect rising and falling edge
  assign read_ack = (read_ack_tog_r != read_ack_tog);

  always @(posedge clk)
  begin
    if (reset) begin
      count <= 8'h00;
    end
    else if (read_ack == 1'b1) begin
      // clear on read of register
      count <= 8'h00;
    end
    else begin
      if (sm_reset_pulse == 1'b1 && count != 8'hFF) begin
        count <= count + 1;
      end
    end
  end

endmodule
