// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
// Date        : Tue Jul 28 13:51:57 2026
// Host        : DrewPC2025 running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim -rename_top Loopback_axi_dma_1_0 -prefix
//               Loopback_axi_dma_1_0_ Loopback_axi_dma_1_0_sim_netlist.v
// Design      : Loopback_axi_dma_1_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xczu48dr-ffvg1517-2-e
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "Loopback_axi_dma_1_0,axi_dma,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_dma,Vivado 2024.2" *) 
(* NotValidForBitStream *)
module Loopback_axi_dma_1_0
   (s_axi_lite_aclk,
    m_axi_sg_aclk,
    m_axi_mm2s_aclk,
    axi_resetn,
    s_axi_lite_awvalid,
    s_axi_lite_awready,
    s_axi_lite_awaddr,
    s_axi_lite_wvalid,
    s_axi_lite_wready,
    s_axi_lite_wdata,
    s_axi_lite_bresp,
    s_axi_lite_bvalid,
    s_axi_lite_bready,
    s_axi_lite_arvalid,
    s_axi_lite_arready,
    s_axi_lite_araddr,
    s_axi_lite_rvalid,
    s_axi_lite_rready,
    s_axi_lite_rdata,
    s_axi_lite_rresp,
    m_axi_sg_awaddr,
    m_axi_sg_awlen,
    m_axi_sg_awsize,
    m_axi_sg_awburst,
    m_axi_sg_awprot,
    m_axi_sg_awcache,
    m_axi_sg_awvalid,
    m_axi_sg_awready,
    m_axi_sg_wdata,
    m_axi_sg_wstrb,
    m_axi_sg_wlast,
    m_axi_sg_wvalid,
    m_axi_sg_wready,
    m_axi_sg_bresp,
    m_axi_sg_bvalid,
    m_axi_sg_bready,
    m_axi_sg_araddr,
    m_axi_sg_arlen,
    m_axi_sg_arsize,
    m_axi_sg_arburst,
    m_axi_sg_arprot,
    m_axi_sg_arcache,
    m_axi_sg_arvalid,
    m_axi_sg_arready,
    m_axi_sg_rdata,
    m_axi_sg_rresp,
    m_axi_sg_rlast,
    m_axi_sg_rvalid,
    m_axi_sg_rready,
    m_axi_mm2s_araddr,
    m_axi_mm2s_arlen,
    m_axi_mm2s_arsize,
    m_axi_mm2s_arburst,
    m_axi_mm2s_arprot,
    m_axi_mm2s_arcache,
    m_axi_mm2s_arvalid,
    m_axi_mm2s_arready,
    m_axi_mm2s_rdata,
    m_axi_mm2s_rresp,
    m_axi_mm2s_rlast,
    m_axi_mm2s_rvalid,
    m_axi_mm2s_rready,
    mm2s_prmry_reset_out_n,
    m_axis_mm2s_tdata,
    m_axis_mm2s_tkeep,
    m_axis_mm2s_tvalid,
    m_axis_mm2s_tready,
    m_axis_mm2s_tlast,
    mm2s_cntrl_reset_out_n,
    m_axis_mm2s_cntrl_tdata,
    m_axis_mm2s_cntrl_tkeep,
    m_axis_mm2s_cntrl_tvalid,
    m_axis_mm2s_cntrl_tready,
    m_axis_mm2s_cntrl_tlast,
    mm2s_introut,
    axi_dma_tstvec);
  (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK" *) (* x_interface_mode = "slave S_AXI_LITE_ACLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 249999954, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, INSERT_VIP 0" *) input s_axi_lite_aclk;
  (* x_interface_info = "xilinx.com:signal:clock:1.0 M_AXI_SG_CLK CLK" *) (* x_interface_mode = "slave M_AXI_SG_CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXI_SG_CLK, ASSOCIATED_BUSIF M_AXI_SG, FREQ_HZ 249999954, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, INSERT_VIP 0" *) input m_axi_sg_aclk;
  (* x_interface_info = "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK" *) (* x_interface_mode = "slave M_AXI_MM2S_CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXI_MM2S_CLK, ASSOCIATED_BUSIF M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL, ASSOCIATED_RESET mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n, FREQ_HZ 249999954, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, INSERT_VIP 0" *) input m_axi_mm2s_aclk;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 AXI_RESETN RST" *) (* x_interface_mode = "slave AXI_RESETN" *) (* x_interface_parameter = "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input axi_resetn;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) (* x_interface_mode = "slave S_AXI_LITE" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 249999954, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_lite_awvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) output s_axi_lite_awready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *) input [9:0]s_axi_lite_awaddr;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *) input s_axi_lite_wvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *) output s_axi_lite_wready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *) input [31:0]s_axi_lite_wdata;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *) output [1:0]s_axi_lite_bresp;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *) output s_axi_lite_bvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *) input s_axi_lite_bready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *) input s_axi_lite_arvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *) output s_axi_lite_arready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *) input [9:0]s_axi_lite_araddr;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *) output s_axi_lite_rvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *) input s_axi_lite_rready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) output [31:0]s_axi_lite_rdata;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) output [1:0]s_axi_lite_rresp;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG AWADDR" *) (* x_interface_mode = "master M_AXI_SG" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXI_SG, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 249999954, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [31:0]m_axi_sg_awaddr;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG AWLEN" *) output [7:0]m_axi_sg_awlen;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG AWSIZE" *) output [2:0]m_axi_sg_awsize;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG AWBURST" *) output [1:0]m_axi_sg_awburst;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG AWPROT" *) output [2:0]m_axi_sg_awprot;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG AWCACHE" *) output [3:0]m_axi_sg_awcache;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG AWVALID" *) output m_axi_sg_awvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG AWREADY" *) input m_axi_sg_awready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG WDATA" *) output [31:0]m_axi_sg_wdata;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG WSTRB" *) output [3:0]m_axi_sg_wstrb;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG WLAST" *) output m_axi_sg_wlast;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG WVALID" *) output m_axi_sg_wvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG WREADY" *) input m_axi_sg_wready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG BRESP" *) input [1:0]m_axi_sg_bresp;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG BVALID" *) input m_axi_sg_bvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG BREADY" *) output m_axi_sg_bready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG ARADDR" *) output [31:0]m_axi_sg_araddr;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG ARLEN" *) output [7:0]m_axi_sg_arlen;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG ARSIZE" *) output [2:0]m_axi_sg_arsize;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG ARBURST" *) output [1:0]m_axi_sg_arburst;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG ARPROT" *) output [2:0]m_axi_sg_arprot;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG ARCACHE" *) output [3:0]m_axi_sg_arcache;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG ARVALID" *) output m_axi_sg_arvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG ARREADY" *) input m_axi_sg_arready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG RDATA" *) input [31:0]m_axi_sg_rdata;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG RRESP" *) input [1:0]m_axi_sg_rresp;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG RLAST" *) input m_axi_sg_rlast;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG RVALID" *) input m_axi_sg_rvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_SG RREADY" *) output m_axi_sg_rready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR" *) (* x_interface_mode = "master M_AXI_MM2S" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXI_MM2S, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 249999954, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [31:0]m_axi_mm2s_araddr;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN" *) output [7:0]m_axi_mm2s_arlen;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE" *) output [2:0]m_axi_mm2s_arsize;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST" *) output [1:0]m_axi_mm2s_arburst;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT" *) output [2:0]m_axi_mm2s_arprot;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE" *) output [3:0]m_axi_mm2s_arcache;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID" *) output m_axi_mm2s_arvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY" *) input m_axi_mm2s_arready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA" *) input [31:0]m_axi_mm2s_rdata;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP" *) input [1:0]m_axi_mm2s_rresp;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST" *) input m_axi_mm2s_rlast;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID" *) input m_axi_mm2s_rvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY" *) output m_axi_mm2s_rready;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST" *) (* x_interface_mode = "master MM2S_PRMRY_RESET_OUT_N" *) (* x_interface_parameter = "XIL_INTERFACENAME MM2S_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output mm2s_prmry_reset_out_n;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA" *) (* x_interface_mode = "master M_AXIS_MM2S" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS_MM2S, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 249999954, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, LAYERED_METADATA undef, INSERT_VIP 0" *) output [31:0]m_axis_mm2s_tdata;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP" *) output [3:0]m_axis_mm2s_tkeep;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID" *) output m_axis_mm2s_tvalid;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY" *) input m_axis_mm2s_tready;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST" *) output m_axis_mm2s_tlast;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 MM2S_CNTRL_RESET_OUT_N RST" *) (* x_interface_mode = "master MM2S_CNTRL_RESET_OUT_N" *) (* x_interface_parameter = "XIL_INTERFACENAME MM2S_CNTRL_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output mm2s_cntrl_reset_out_n;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_CNTRL TDATA" *) (* x_interface_mode = "master M_AXIS_CNTRL" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS_CNTRL, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 249999954, PHASE 0.0, CLK_DOMAIN Loopback_zynq_ultra_ps_e_0_0_pl_clk0, LAYERED_METADATA undef, INSERT_VIP 0" *) output [31:0]m_axis_mm2s_cntrl_tdata;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_CNTRL TKEEP" *) output [3:0]m_axis_mm2s_cntrl_tkeep;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_CNTRL TVALID" *) output m_axis_mm2s_cntrl_tvalid;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_CNTRL TREADY" *) input m_axis_mm2s_cntrl_tready;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_CNTRL TLAST" *) output m_axis_mm2s_cntrl_tlast;
  (* x_interface_info = "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT" *) (* x_interface_mode = "master MM2S_INTROUT" *) (* x_interface_parameter = "XIL_INTERFACENAME MM2S_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) output mm2s_introut;
  output [31:0]axi_dma_tstvec;

  wire \<const0> ;
  wire \<const1> ;
  wire [4:0]\^axi_dma_tstvec ;
  wire axi_resetn;
  wire m_axi_mm2s_aclk;
  wire [31:0]m_axi_mm2s_araddr;
  wire [0:0]\^m_axi_mm2s_arburst ;
  wire [3:0]\^m_axi_mm2s_arlen ;
  wire m_axi_mm2s_arready;
  wire [1:1]\^m_axi_mm2s_arsize ;
  wire m_axi_mm2s_arvalid;
  wire [31:0]m_axi_mm2s_rdata;
  wire m_axi_mm2s_rlast;
  wire m_axi_mm2s_rready;
  wire [1:0]m_axi_mm2s_rresp;
  wire m_axi_mm2s_rvalid;
  wire m_axi_sg_aclk;
  wire [31:6]\^m_axi_sg_araddr ;
  wire [0:0]\^m_axi_sg_arburst ;
  wire [3:0]\^m_axi_sg_arlen ;
  wire m_axi_sg_arready;
  wire [1:1]\^m_axi_sg_arsize ;
  wire m_axi_sg_arvalid;
  wire [31:2]\^m_axi_sg_awaddr ;
  wire [0:0]\^m_axi_sg_awburst ;
  wire [2:0]\^m_axi_sg_awlen ;
  wire m_axi_sg_awready;
  wire [1:1]\^m_axi_sg_awsize ;
  wire m_axi_sg_awvalid;
  wire m_axi_sg_bready;
  wire [1:0]m_axi_sg_bresp;
  wire m_axi_sg_bvalid;
  wire [31:0]m_axi_sg_rdata;
  wire m_axi_sg_rlast;
  wire m_axi_sg_rready;
  wire [1:0]m_axi_sg_rresp;
  wire m_axi_sg_rvalid;
  wire [31:0]\^m_axi_sg_wdata ;
  wire m_axi_sg_wlast;
  wire m_axi_sg_wready;
  wire [3:0]m_axi_sg_wstrb;
  wire m_axi_sg_wvalid;
  wire [31:0]m_axis_mm2s_cntrl_tdata;
  wire m_axis_mm2s_cntrl_tlast;
  wire m_axis_mm2s_cntrl_tready;
  wire m_axis_mm2s_cntrl_tvalid;
  wire [31:0]m_axis_mm2s_tdata;
  wire [3:0]m_axis_mm2s_tkeep;
  wire m_axis_mm2s_tlast;
  wire m_axis_mm2s_tready;
  wire m_axis_mm2s_tvalid;
  wire mm2s_cntrl_reset_out_n;
  wire mm2s_introut;
  wire mm2s_prmry_reset_out_n;
  wire s_axi_lite_aclk;
  wire [9:0]s_axi_lite_araddr;
  wire s_axi_lite_arready;
  wire s_axi_lite_arvalid;
  wire [9:0]s_axi_lite_awaddr;
  wire s_axi_lite_awready;
  wire s_axi_lite_awvalid;
  wire s_axi_lite_bready;
  wire s_axi_lite_bvalid;
  wire [31:0]s_axi_lite_rdata;
  wire s_axi_lite_rready;
  wire s_axi_lite_rvalid;
  wire [31:0]s_axi_lite_wdata;
  wire s_axi_lite_wready;
  wire s_axi_lite_wvalid;
  wire NLW_U0_m_axi_s2mm_awvalid_UNCONNECTED;
  wire NLW_U0_m_axi_s2mm_bready_UNCONNECTED;
  wire NLW_U0_m_axi_s2mm_wlast_UNCONNECTED;
  wire NLW_U0_m_axi_s2mm_wvalid_UNCONNECTED;
  wire NLW_U0_s2mm_introut_UNCONNECTED;
  wire NLW_U0_s2mm_prmry_reset_out_n_UNCONNECTED;
  wire NLW_U0_s2mm_sts_reset_out_n_UNCONNECTED;
  wire NLW_U0_s_axis_s2mm_sts_tready_UNCONNECTED;
  wire NLW_U0_s_axis_s2mm_tready_UNCONNECTED;
  wire [31:2]NLW_U0_axi_dma_tstvec_UNCONNECTED;
  wire [1:1]NLW_U0_m_axi_mm2s_arburst_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_mm2s_arcache_UNCONNECTED;
  wire [7:4]NLW_U0_m_axi_mm2s_arlen_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_mm2s_arprot_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_mm2s_arsize_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_mm2s_aruser_UNCONNECTED;
  wire [31:0]NLW_U0_m_axi_s2mm_awaddr_UNCONNECTED;
  wire [1:0]NLW_U0_m_axi_s2mm_awburst_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_s2mm_awcache_UNCONNECTED;
  wire [7:0]NLW_U0_m_axi_s2mm_awlen_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_s2mm_awprot_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_s2mm_awsize_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_s2mm_awuser_UNCONNECTED;
  wire [31:0]NLW_U0_m_axi_s2mm_wdata_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_s2mm_wstrb_UNCONNECTED;
  wire [5:0]NLW_U0_m_axi_sg_araddr_UNCONNECTED;
  wire [1:1]NLW_U0_m_axi_sg_arburst_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_sg_arcache_UNCONNECTED;
  wire [7:4]NLW_U0_m_axi_sg_arlen_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_sg_arprot_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_sg_arsize_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_sg_aruser_UNCONNECTED;
  wire [5:0]NLW_U0_m_axi_sg_awaddr_UNCONNECTED;
  wire [1:1]NLW_U0_m_axi_sg_awburst_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_sg_awcache_UNCONNECTED;
  wire [7:1]NLW_U0_m_axi_sg_awlen_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_sg_awprot_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_sg_awsize_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_sg_awuser_UNCONNECTED;
  wire [27:26]NLW_U0_m_axi_sg_wdata_UNCONNECTED;
  wire [3:0]NLW_U0_m_axis_mm2s_cntrl_tkeep_UNCONNECTED;
  wire [4:0]NLW_U0_m_axis_mm2s_tdest_UNCONNECTED;
  wire [4:0]NLW_U0_m_axis_mm2s_tid_UNCONNECTED;
  wire [3:0]NLW_U0_m_axis_mm2s_tuser_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_lite_bresp_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_lite_rresp_UNCONNECTED;

  assign axi_dma_tstvec[31] = \<const0> ;
  assign axi_dma_tstvec[30] = \<const0> ;
  assign axi_dma_tstvec[29] = \<const0> ;
  assign axi_dma_tstvec[28] = \<const0> ;
  assign axi_dma_tstvec[27] = \<const0> ;
  assign axi_dma_tstvec[26] = \<const0> ;
  assign axi_dma_tstvec[25] = \<const0> ;
  assign axi_dma_tstvec[24] = \<const0> ;
  assign axi_dma_tstvec[23] = \<const0> ;
  assign axi_dma_tstvec[22] = \<const0> ;
  assign axi_dma_tstvec[21] = \<const0> ;
  assign axi_dma_tstvec[20] = \<const0> ;
  assign axi_dma_tstvec[19] = \<const0> ;
  assign axi_dma_tstvec[18] = \<const0> ;
  assign axi_dma_tstvec[17] = \<const0> ;
  assign axi_dma_tstvec[16] = \<const0> ;
  assign axi_dma_tstvec[15] = \<const0> ;
  assign axi_dma_tstvec[14] = \<const0> ;
  assign axi_dma_tstvec[13] = \<const0> ;
  assign axi_dma_tstvec[12] = \<const0> ;
  assign axi_dma_tstvec[11] = \<const0> ;
  assign axi_dma_tstvec[10] = \<const0> ;
  assign axi_dma_tstvec[9] = \<const0> ;
  assign axi_dma_tstvec[8] = \<const0> ;
  assign axi_dma_tstvec[7] = \<const0> ;
  assign axi_dma_tstvec[6] = \<const0> ;
  assign axi_dma_tstvec[5] = \<const0> ;
  assign axi_dma_tstvec[4] = \^axi_dma_tstvec [4];
  assign axi_dma_tstvec[3] = \<const0> ;
  assign axi_dma_tstvec[2] = \<const0> ;
  assign axi_dma_tstvec[1:0] = \^axi_dma_tstvec [1:0];
  assign m_axi_mm2s_arburst[1] = \<const0> ;
  assign m_axi_mm2s_arburst[0] = \^m_axi_mm2s_arburst [0];
  assign m_axi_mm2s_arcache[3] = \<const0> ;
  assign m_axi_mm2s_arcache[2] = \<const0> ;
  assign m_axi_mm2s_arcache[1] = \<const1> ;
  assign m_axi_mm2s_arcache[0] = \<const1> ;
  assign m_axi_mm2s_arlen[7] = \<const0> ;
  assign m_axi_mm2s_arlen[6] = \<const0> ;
  assign m_axi_mm2s_arlen[5] = \<const0> ;
  assign m_axi_mm2s_arlen[4] = \<const0> ;
  assign m_axi_mm2s_arlen[3:0] = \^m_axi_mm2s_arlen [3:0];
  assign m_axi_mm2s_arprot[2] = \<const0> ;
  assign m_axi_mm2s_arprot[1] = \<const0> ;
  assign m_axi_mm2s_arprot[0] = \<const0> ;
  assign m_axi_mm2s_arsize[2] = \<const0> ;
  assign m_axi_mm2s_arsize[1] = \^m_axi_mm2s_arsize [1];
  assign m_axi_mm2s_arsize[0] = \<const0> ;
  assign m_axi_sg_araddr[31:6] = \^m_axi_sg_araddr [31:6];
  assign m_axi_sg_araddr[5] = \<const0> ;
  assign m_axi_sg_araddr[4] = \<const0> ;
  assign m_axi_sg_araddr[3] = \<const0> ;
  assign m_axi_sg_araddr[2] = \<const0> ;
  assign m_axi_sg_araddr[1] = \<const0> ;
  assign m_axi_sg_araddr[0] = \<const0> ;
  assign m_axi_sg_arburst[1] = \<const0> ;
  assign m_axi_sg_arburst[0] = \^m_axi_sg_arburst [0];
  assign m_axi_sg_arcache[3] = \<const0> ;
  assign m_axi_sg_arcache[2] = \<const0> ;
  assign m_axi_sg_arcache[1] = \<const1> ;
  assign m_axi_sg_arcache[0] = \<const1> ;
  assign m_axi_sg_arlen[7] = \<const0> ;
  assign m_axi_sg_arlen[6] = \<const0> ;
  assign m_axi_sg_arlen[5] = \<const0> ;
  assign m_axi_sg_arlen[4] = \<const0> ;
  assign m_axi_sg_arlen[3:0] = \^m_axi_sg_arlen [3:0];
  assign m_axi_sg_arprot[2] = \<const0> ;
  assign m_axi_sg_arprot[1] = \<const0> ;
  assign m_axi_sg_arprot[0] = \<const0> ;
  assign m_axi_sg_arsize[2] = \<const0> ;
  assign m_axi_sg_arsize[1] = \^m_axi_sg_arsize [1];
  assign m_axi_sg_arsize[0] = \<const0> ;
  assign m_axi_sg_awaddr[31:6] = \^m_axi_sg_awaddr [31:6];
  assign m_axi_sg_awaddr[5] = \<const0> ;
  assign m_axi_sg_awaddr[4:2] = \^m_axi_sg_awaddr [4:2];
  assign m_axi_sg_awaddr[1] = \<const0> ;
  assign m_axi_sg_awaddr[0] = \<const0> ;
  assign m_axi_sg_awburst[1] = \<const0> ;
  assign m_axi_sg_awburst[0] = \^m_axi_sg_awburst [0];
  assign m_axi_sg_awcache[3] = \<const0> ;
  assign m_axi_sg_awcache[2] = \<const0> ;
  assign m_axi_sg_awcache[1] = \<const1> ;
  assign m_axi_sg_awcache[0] = \<const1> ;
  assign m_axi_sg_awlen[7] = \<const0> ;
  assign m_axi_sg_awlen[6] = \<const0> ;
  assign m_axi_sg_awlen[5] = \<const0> ;
  assign m_axi_sg_awlen[4] = \<const0> ;
  assign m_axi_sg_awlen[3] = \<const0> ;
  assign m_axi_sg_awlen[2] = \^m_axi_sg_awlen [2];
  assign m_axi_sg_awlen[1] = \<const0> ;
  assign m_axi_sg_awlen[0] = \^m_axi_sg_awlen [0];
  assign m_axi_sg_awprot[2] = \<const0> ;
  assign m_axi_sg_awprot[1] = \<const0> ;
  assign m_axi_sg_awprot[0] = \<const0> ;
  assign m_axi_sg_awsize[2] = \<const0> ;
  assign m_axi_sg_awsize[1] = \^m_axi_sg_awsize [1];
  assign m_axi_sg_awsize[0] = \<const0> ;
  assign m_axi_sg_wdata[31:28] = \^m_axi_sg_wdata [31:28];
  assign m_axi_sg_wdata[27] = \<const0> ;
  assign m_axi_sg_wdata[26] = \<const0> ;
  assign m_axi_sg_wdata[25:0] = \^m_axi_sg_wdata [25:0];
  assign m_axis_mm2s_cntrl_tkeep[3] = \<const1> ;
  assign m_axis_mm2s_cntrl_tkeep[2] = \<const1> ;
  assign m_axis_mm2s_cntrl_tkeep[1] = \<const1> ;
  assign m_axis_mm2s_cntrl_tkeep[0] = \<const1> ;
  assign s_axi_lite_bresp[1] = \<const0> ;
  assign s_axi_lite_bresp[0] = \<const0> ;
  assign s_axi_lite_rresp[1] = \<const0> ;
  assign s_axi_lite_rresp[0] = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_DLYTMR_RESOLUTION = "125" *) 
  (* C_ENABLE_MULTI_CHANNEL = "0" *) 
  (* C_FAMILY = "zynquplus" *) 
  (* C_INCLUDE_MM2S = "1" *) 
  (* C_INCLUDE_MM2S_DRE = "0" *) 
  (* C_INCLUDE_MM2S_SF = "1" *) 
  (* C_INCLUDE_S2MM = "0" *) 
  (* C_INCLUDE_S2MM_DRE = "0" *) 
  (* C_INCLUDE_S2MM_SF = "1" *) 
  (* C_INCLUDE_SG = "1" *) 
  (* C_INCREASE_THROUGHPUT = "0" *) 
  (* C_INSTANCE = "axi_dma" *) 
  (* C_MICRO_DMA = "0" *) 
  (* C_MM2S_BURST_SIZE = "16" *) 
  (* C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH = "32" *) 
  (* C_M_AXIS_MM2S_TDATA_WIDTH = "32" *) 
  (* C_M_AXI_MM2S_ADDR_WIDTH = "32" *) 
  (* C_M_AXI_MM2S_DATA_WIDTH = "32" *) 
  (* C_M_AXI_S2MM_ADDR_WIDTH = "32" *) 
  (* C_M_AXI_S2MM_DATA_WIDTH = "32" *) 
  (* C_M_AXI_SG_ADDR_WIDTH = "32" *) 
  (* C_M_AXI_SG_DATA_WIDTH = "32" *) 
  (* C_NUM_MM2S_CHANNELS = "1" *) 
  (* C_NUM_S2MM_CHANNELS = "1" *) 
  (* C_PRMRY_IS_ACLK_ASYNC = "0" *) 
  (* C_S2MM_BURST_SIZE = "16" *) 
  (* C_SG_INCLUDE_STSCNTRL_STRM = "1" *) 
  (* C_SG_LENGTH_WIDTH = "26" *) 
  (* C_SG_USE_STSAPP_LENGTH = "0" *) 
  (* C_S_AXIS_S2MM_STS_TDATA_WIDTH = "32" *) 
  (* C_S_AXIS_S2MM_TDATA_WIDTH = "32" *) 
  (* C_S_AXI_LITE_ADDR_WIDTH = "10" *) 
  (* C_S_AXI_LITE_DATA_WIDTH = "32" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  Loopback_axi_dma_1_0_axi_dma U0
       (.axi_dma_tstvec({NLW_U0_axi_dma_tstvec_UNCONNECTED[31:5],\^axi_dma_tstvec }),
        .axi_resetn(axi_resetn),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axi_mm2s_araddr(m_axi_mm2s_araddr),
        .m_axi_mm2s_arburst({NLW_U0_m_axi_mm2s_arburst_UNCONNECTED[1],\^m_axi_mm2s_arburst }),
        .m_axi_mm2s_arcache(NLW_U0_m_axi_mm2s_arcache_UNCONNECTED[3:0]),
        .m_axi_mm2s_arlen({NLW_U0_m_axi_mm2s_arlen_UNCONNECTED[7:4],\^m_axi_mm2s_arlen }),
        .m_axi_mm2s_arprot(NLW_U0_m_axi_mm2s_arprot_UNCONNECTED[2:0]),
        .m_axi_mm2s_arready(m_axi_mm2s_arready),
        .m_axi_mm2s_arsize({NLW_U0_m_axi_mm2s_arsize_UNCONNECTED[2],\^m_axi_mm2s_arsize ,NLW_U0_m_axi_mm2s_arsize_UNCONNECTED[0]}),
        .m_axi_mm2s_aruser(NLW_U0_m_axi_mm2s_aruser_UNCONNECTED[3:0]),
        .m_axi_mm2s_arvalid(m_axi_mm2s_arvalid),
        .m_axi_mm2s_rdata(m_axi_mm2s_rdata),
        .m_axi_mm2s_rlast(m_axi_mm2s_rlast),
        .m_axi_mm2s_rready(m_axi_mm2s_rready),
        .m_axi_mm2s_rresp(m_axi_mm2s_rresp),
        .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid),
        .m_axi_s2mm_aclk(1'b0),
        .m_axi_s2mm_awaddr(NLW_U0_m_axi_s2mm_awaddr_UNCONNECTED[31:0]),
        .m_axi_s2mm_awburst(NLW_U0_m_axi_s2mm_awburst_UNCONNECTED[1:0]),
        .m_axi_s2mm_awcache(NLW_U0_m_axi_s2mm_awcache_UNCONNECTED[3:0]),
        .m_axi_s2mm_awlen(NLW_U0_m_axi_s2mm_awlen_UNCONNECTED[7:0]),
        .m_axi_s2mm_awprot(NLW_U0_m_axi_s2mm_awprot_UNCONNECTED[2:0]),
        .m_axi_s2mm_awready(1'b0),
        .m_axi_s2mm_awsize(NLW_U0_m_axi_s2mm_awsize_UNCONNECTED[2:0]),
        .m_axi_s2mm_awuser(NLW_U0_m_axi_s2mm_awuser_UNCONNECTED[3:0]),
        .m_axi_s2mm_awvalid(NLW_U0_m_axi_s2mm_awvalid_UNCONNECTED),
        .m_axi_s2mm_bready(NLW_U0_m_axi_s2mm_bready_UNCONNECTED),
        .m_axi_s2mm_bresp({1'b0,1'b0}),
        .m_axi_s2mm_bvalid(1'b0),
        .m_axi_s2mm_wdata(NLW_U0_m_axi_s2mm_wdata_UNCONNECTED[31:0]),
        .m_axi_s2mm_wlast(NLW_U0_m_axi_s2mm_wlast_UNCONNECTED),
        .m_axi_s2mm_wready(1'b0),
        .m_axi_s2mm_wstrb(NLW_U0_m_axi_s2mm_wstrb_UNCONNECTED[3:0]),
        .m_axi_s2mm_wvalid(NLW_U0_m_axi_s2mm_wvalid_UNCONNECTED),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_araddr({\^m_axi_sg_araddr ,NLW_U0_m_axi_sg_araddr_UNCONNECTED[5:0]}),
        .m_axi_sg_arburst({NLW_U0_m_axi_sg_arburst_UNCONNECTED[1],\^m_axi_sg_arburst }),
        .m_axi_sg_arcache(NLW_U0_m_axi_sg_arcache_UNCONNECTED[3:0]),
        .m_axi_sg_arlen({NLW_U0_m_axi_sg_arlen_UNCONNECTED[7:4],\^m_axi_sg_arlen }),
        .m_axi_sg_arprot(NLW_U0_m_axi_sg_arprot_UNCONNECTED[2:0]),
        .m_axi_sg_arready(m_axi_sg_arready),
        .m_axi_sg_arsize({NLW_U0_m_axi_sg_arsize_UNCONNECTED[2],\^m_axi_sg_arsize ,NLW_U0_m_axi_sg_arsize_UNCONNECTED[0]}),
        .m_axi_sg_aruser(NLW_U0_m_axi_sg_aruser_UNCONNECTED[3:0]),
        .m_axi_sg_arvalid(m_axi_sg_arvalid),
        .m_axi_sg_awaddr({\^m_axi_sg_awaddr ,NLW_U0_m_axi_sg_awaddr_UNCONNECTED[1:0]}),
        .m_axi_sg_awburst({NLW_U0_m_axi_sg_awburst_UNCONNECTED[1],\^m_axi_sg_awburst }),
        .m_axi_sg_awcache(NLW_U0_m_axi_sg_awcache_UNCONNECTED[3:0]),
        .m_axi_sg_awlen({NLW_U0_m_axi_sg_awlen_UNCONNECTED[7:3],\^m_axi_sg_awlen }),
        .m_axi_sg_awprot(NLW_U0_m_axi_sg_awprot_UNCONNECTED[2:0]),
        .m_axi_sg_awready(m_axi_sg_awready),
        .m_axi_sg_awsize({NLW_U0_m_axi_sg_awsize_UNCONNECTED[2],\^m_axi_sg_awsize ,NLW_U0_m_axi_sg_awsize_UNCONNECTED[0]}),
        .m_axi_sg_awuser(NLW_U0_m_axi_sg_awuser_UNCONNECTED[3:0]),
        .m_axi_sg_awvalid(m_axi_sg_awvalid),
        .m_axi_sg_bready(m_axi_sg_bready),
        .m_axi_sg_bresp(m_axi_sg_bresp),
        .m_axi_sg_bvalid(m_axi_sg_bvalid),
        .m_axi_sg_rdata(m_axi_sg_rdata),
        .m_axi_sg_rlast(m_axi_sg_rlast),
        .m_axi_sg_rready(m_axi_sg_rready),
        .m_axi_sg_rresp(m_axi_sg_rresp),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .m_axi_sg_wdata(\^m_axi_sg_wdata ),
        .m_axi_sg_wlast(m_axi_sg_wlast),
        .m_axi_sg_wready(m_axi_sg_wready),
        .m_axi_sg_wstrb(m_axi_sg_wstrb),
        .m_axi_sg_wvalid(m_axi_sg_wvalid),
        .m_axis_mm2s_cntrl_tdata(m_axis_mm2s_cntrl_tdata),
        .m_axis_mm2s_cntrl_tkeep(NLW_U0_m_axis_mm2s_cntrl_tkeep_UNCONNECTED[3:0]),
        .m_axis_mm2s_cntrl_tlast(m_axis_mm2s_cntrl_tlast),
        .m_axis_mm2s_cntrl_tready(m_axis_mm2s_cntrl_tready),
        .m_axis_mm2s_cntrl_tvalid(m_axis_mm2s_cntrl_tvalid),
        .m_axis_mm2s_tdata(m_axis_mm2s_tdata),
        .m_axis_mm2s_tdest(NLW_U0_m_axis_mm2s_tdest_UNCONNECTED[4:0]),
        .m_axis_mm2s_tid(NLW_U0_m_axis_mm2s_tid_UNCONNECTED[4:0]),
        .m_axis_mm2s_tkeep(m_axis_mm2s_tkeep),
        .m_axis_mm2s_tlast(m_axis_mm2s_tlast),
        .m_axis_mm2s_tready(m_axis_mm2s_tready),
        .m_axis_mm2s_tuser(NLW_U0_m_axis_mm2s_tuser_UNCONNECTED[3:0]),
        .m_axis_mm2s_tvalid(m_axis_mm2s_tvalid),
        .mm2s_cntrl_reset_out_n(mm2s_cntrl_reset_out_n),
        .mm2s_introut(mm2s_introut),
        .mm2s_prmry_reset_out_n(mm2s_prmry_reset_out_n),
        .s2mm_introut(NLW_U0_s2mm_introut_UNCONNECTED),
        .s2mm_prmry_reset_out_n(NLW_U0_s2mm_prmry_reset_out_n_UNCONNECTED),
        .s2mm_sts_reset_out_n(NLW_U0_s2mm_sts_reset_out_n_UNCONNECTED),
        .s_axi_lite_aclk(s_axi_lite_aclk),
        .s_axi_lite_araddr(s_axi_lite_araddr),
        .s_axi_lite_arready(s_axi_lite_arready),
        .s_axi_lite_arvalid(s_axi_lite_arvalid),
        .s_axi_lite_awaddr({1'b0,1'b0,1'b0,s_axi_lite_awaddr[6:2],1'b0,1'b0}),
        .s_axi_lite_awready(s_axi_lite_awready),
        .s_axi_lite_awvalid(s_axi_lite_awvalid),
        .s_axi_lite_bready(s_axi_lite_bready),
        .s_axi_lite_bresp(NLW_U0_s_axi_lite_bresp_UNCONNECTED[1:0]),
        .s_axi_lite_bvalid(s_axi_lite_bvalid),
        .s_axi_lite_rdata(s_axi_lite_rdata),
        .s_axi_lite_rready(s_axi_lite_rready),
        .s_axi_lite_rresp(NLW_U0_s_axi_lite_rresp_UNCONNECTED[1:0]),
        .s_axi_lite_rvalid(s_axi_lite_rvalid),
        .s_axi_lite_wdata({s_axi_lite_wdata[31:6],1'b0,s_axi_lite_wdata[4:2],1'b0,s_axi_lite_wdata[0]}),
        .s_axi_lite_wready(s_axi_lite_wready),
        .s_axi_lite_wvalid(s_axi_lite_wvalid),
        .s_axis_s2mm_sts_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_s2mm_sts_tkeep({1'b1,1'b1,1'b1,1'b1}),
        .s_axis_s2mm_sts_tlast(1'b0),
        .s_axis_s2mm_sts_tready(NLW_U0_s_axis_s2mm_sts_tready_UNCONNECTED),
        .s_axis_s2mm_sts_tvalid(1'b0),
        .s_axis_s2mm_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_s2mm_tdest({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_s2mm_tid({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_s2mm_tkeep({1'b1,1'b1,1'b1,1'b1}),
        .s_axis_s2mm_tlast(1'b0),
        .s_axis_s2mm_tready(NLW_U0_s_axis_s2mm_tready_UNCONNECTED),
        .s_axis_s2mm_tuser({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_s2mm_tvalid(1'b0));
  VCC VCC
       (.P(\<const1> ));
endmodule

module Loopback_axi_dma_1_0_axi_datamover
   (m_axis_mm2s_tvalid,
    sig_rst2all_stop_request,
    m_axi_mm2s_arsize,
    m_axi_mm2s_arburst,
    m_axi_mm2s_arvalid,
    m_axis_mm2s_tlast,
    s_axis_mm2s_cmd_tready,
    m_axis_mm2s_sts_tvalid_int,
    mm2s_decerr_i,
    mm2s_interr_i,
    mm2s_slverr_i,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ,
    m_axi_mm2s_rready,
    mm2s_halt_cmplt,
    m_axi_mm2s_araddr,
    m_axi_mm2s_arlen,
    m_axis_mm2s_tdata,
    m_axis_mm2s_tkeep,
    m_axi_mm2s_aclk,
    m_axi_mm2s_rdata,
    out,
    sig_s_h_halt_reg_reg,
    m_axi_sg_aclk,
    mm2s_sts_received,
    m_axis_mm2s_sts_tready,
    s_axis_mm2s_cmd_tvalid_split,
    m_axi_mm2s_rlast,
    m_axi_mm2s_rvalid,
    m_axis_mm2s_tready,
    m_axi_mm2s_rresp,
    m_axi_mm2s_arready,
    D);
  output m_axis_mm2s_tvalid;
  output sig_rst2all_stop_request;
  output [0:0]m_axi_mm2s_arsize;
  output [0:0]m_axi_mm2s_arburst;
  output m_axi_mm2s_arvalid;
  output m_axis_mm2s_tlast;
  output s_axis_mm2s_cmd_tready;
  output m_axis_mm2s_sts_tvalid_int;
  output mm2s_decerr_i;
  output mm2s_interr_i;
  output mm2s_slverr_i;
  output \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ;
  output m_axi_mm2s_rready;
  output mm2s_halt_cmplt;
  output [31:0]m_axi_mm2s_araddr;
  output [3:0]m_axi_mm2s_arlen;
  output [31:0]m_axis_mm2s_tdata;
  output [3:0]m_axis_mm2s_tkeep;
  input m_axi_mm2s_aclk;
  input [31:0]m_axi_mm2s_rdata;
  input out;
  input sig_s_h_halt_reg_reg;
  input m_axi_sg_aclk;
  input mm2s_sts_received;
  input m_axis_mm2s_sts_tready;
  input s_axis_mm2s_cmd_tvalid_split;
  input m_axi_mm2s_rlast;
  input m_axi_mm2s_rvalid;
  input m_axis_mm2s_tready;
  input [1:0]m_axi_mm2s_rresp;
  input m_axi_mm2s_arready;
  input [59:0]D;

  wire [59:0]D;
  wire \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ;
  wire m_axi_mm2s_aclk;
  wire [31:0]m_axi_mm2s_araddr;
  wire [0:0]m_axi_mm2s_arburst;
  wire [3:0]m_axi_mm2s_arlen;
  wire m_axi_mm2s_arready;
  wire [0:0]m_axi_mm2s_arsize;
  wire m_axi_mm2s_arvalid;
  wire [31:0]m_axi_mm2s_rdata;
  wire m_axi_mm2s_rlast;
  wire m_axi_mm2s_rready;
  wire [1:0]m_axi_mm2s_rresp;
  wire m_axi_mm2s_rvalid;
  (* DONT_TOUCH *) wire m_axi_sg_aclk;
  wire m_axis_mm2s_sts_tready;
  wire m_axis_mm2s_sts_tvalid_int;
  wire [31:0]m_axis_mm2s_tdata;
  wire [3:0]m_axis_mm2s_tkeep;
  wire m_axis_mm2s_tlast;
  wire m_axis_mm2s_tready;
  wire m_axis_mm2s_tvalid;
  wire mm2s_decerr_i;
  wire mm2s_halt_cmplt;
  wire mm2s_interr_i;
  wire mm2s_slverr_i;
  wire mm2s_sts_received;
  wire out;
  wire s_axis_mm2s_cmd_tready;
  wire s_axis_mm2s_cmd_tvalid_split;
  wire sig_rst2all_stop_request;
  wire sig_s_h_halt_reg_reg;

  Loopback_axi_dma_1_0_axi_datamover_mm2s_full_wrap \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER 
       (.D(D),
        .\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] (\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ),
        .\USE_SINGLE_REG.sig_regfifo_full_reg_reg (m_axis_mm2s_sts_tvalid_int),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axi_mm2s_araddr(m_axi_mm2s_araddr),
        .m_axi_mm2s_arburst(m_axi_mm2s_arburst),
        .m_axi_mm2s_arlen(m_axi_mm2s_arlen),
        .m_axi_mm2s_arready(m_axi_mm2s_arready),
        .m_axi_mm2s_arsize(m_axi_mm2s_arsize),
        .m_axi_mm2s_arvalid(m_axi_mm2s_arvalid),
        .m_axi_mm2s_rdata(m_axi_mm2s_rdata),
        .m_axi_mm2s_rlast(m_axi_mm2s_rlast),
        .m_axi_mm2s_rready(m_axi_mm2s_rready),
        .m_axi_mm2s_rresp(m_axi_mm2s_rresp),
        .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid),
        .m_axis_mm2s_sts_tready(m_axis_mm2s_sts_tready),
        .m_axis_mm2s_tdata(m_axis_mm2s_tdata),
        .m_axis_mm2s_tkeep(m_axis_mm2s_tkeep),
        .m_axis_mm2s_tlast(m_axis_mm2s_tlast),
        .m_axis_mm2s_tready(m_axis_mm2s_tready),
        .m_axis_mm2s_tvalid(m_axis_mm2s_tvalid),
        .mm2s_decerr_i(mm2s_decerr_i),
        .mm2s_halt_cmplt(mm2s_halt_cmplt),
        .mm2s_interr_i(mm2s_interr_i),
        .mm2s_slverr_i(mm2s_slverr_i),
        .mm2s_sts_received(mm2s_sts_received),
        .out(out),
        .s_axis_mm2s_cmd_tready(s_axis_mm2s_cmd_tready),
        .s_axis_mm2s_cmd_tvalid_split(s_axis_mm2s_cmd_tvalid_split),
        .sig_rst2all_stop_request(sig_rst2all_stop_request),
        .sig_s_h_halt_reg_reg(sig_s_h_halt_reg_reg));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_addr_cntl
   (out,
    sig_posted_to_axi_reg_0,
    FIFO_Full_reg,
    sig_init_reg2,
    sig_addr_reg_empty,
    sig_addr2rsc_calc_error,
    m_axi_mm2s_arsize,
    m_axi_mm2s_arburst,
    m_axi_mm2s_arvalid,
    sig_inhibit_rdy_n,
    FIFO_Full_reg_0,
    m_axi_mm2s_araddr,
    m_axi_mm2s_arlen,
    SS,
    m_axi_mm2s_aclk,
    sig_init_reg,
    sig_mstr2addr_cmd_valid,
    sig_mmap_rst_reg_n,
    sig_sf_allow_addr_req,
    sig_data2addr_stop_req,
    m_axi_mm2s_arready,
    in);
  output out;
  output sig_posted_to_axi_reg_0;
  output FIFO_Full_reg;
  output sig_init_reg2;
  output sig_addr_reg_empty;
  output sig_addr2rsc_calc_error;
  output [0:0]m_axi_mm2s_arsize;
  output [0:0]m_axi_mm2s_arburst;
  output m_axi_mm2s_arvalid;
  output sig_inhibit_rdy_n;
  output FIFO_Full_reg_0;
  output [31:0]m_axi_mm2s_araddr;
  output [3:0]m_axi_mm2s_arlen;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input sig_init_reg;
  input sig_mstr2addr_cmd_valid;
  input sig_mmap_rst_reg_n;
  input sig_sf_allow_addr_req;
  input sig_data2addr_stop_req;
  input m_axi_mm2s_arready;
  input [37:0]in;

  wire FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_5 ;
  wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_6 ;
  wire [0:0]SS;
  wire [37:0]in;
  wire m_axi_mm2s_aclk;
  wire [31:0]m_axi_mm2s_araddr;
  wire [0:0]m_axi_mm2s_arburst;
  wire [3:0]m_axi_mm2s_arlen;
  wire m_axi_mm2s_arready;
  wire [0:0]m_axi_mm2s_arsize;
  wire m_axi_mm2s_arvalid;
  wire sig_addr2rsc_calc_error;
  wire sig_addr_reg_empty;
  wire sig_addr_reg_full;
  wire [50:4]sig_aq_fifo_data_out;
  wire sig_data2addr_stop_req;
  wire sig_inhibit_rdy_n;
  wire sig_init_reg;
  wire sig_init_reg2;
  wire sig_mmap_rst_reg_n;
  wire sig_mstr2addr_cmd_valid;
  wire sig_next_addr_reg0;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_posted_to_axi;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_posted_to_axi_2;
  wire sig_push_addr_reg1_out;
  wire sig_sf_allow_addr_req;

  assign out = sig_posted_to_axi_2;
  assign sig_posted_to_axi_reg_0 = sig_posted_to_axi;
  Loopback_axi_dma_1_0_axi_datamover_fifo__parameterized1 \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO 
       (.FIFO_Full_reg(FIFO_Full_reg),
        .FIFO_Full_reg_0(FIFO_Full_reg_0),
        .SS(SS),
        .in(in),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .out({sig_aq_fifo_data_out[50],sig_aq_fifo_data_out[47],sig_aq_fifo_data_out[45],sig_aq_fifo_data_out[39:4]}),
        .sig_addr_reg_empty(sig_addr_reg_empty),
        .sig_addr_reg_empty_reg(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_5 ),
        .sig_calc_error_reg_reg(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_6 ),
        .sig_data2addr_stop_req(sig_data2addr_stop_req),
        .sig_inhibit_rdy_n_reg_0(sig_inhibit_rdy_n),
        .sig_init_reg(sig_init_reg),
        .sig_init_reg2(sig_init_reg2),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid),
        .sig_push_addr_reg1_out(sig_push_addr_reg1_out),
        .sig_sf_allow_addr_req(sig_sf_allow_addr_req));
  FDSE #(
    .INIT(1'b0)) 
    sig_addr_reg_empty_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(1'b0),
        .Q(sig_addr_reg_empty),
        .S(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_addr_reg_full_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(1'b1),
        .Q(sig_addr_reg_full),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_addr_valid_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_6 ),
        .Q(m_axi_mm2s_arvalid),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_calc_error_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[50]),
        .Q(sig_addr2rsc_calc_error),
        .R(sig_next_addr_reg0));
  LUT4 #(
    .INIT(16'h08FF)) 
    \sig_next_addr_reg[31]_i_1__1 
       (.I0(sig_addr_reg_full),
        .I1(m_axi_mm2s_arready),
        .I2(sig_addr2rsc_calc_error),
        .I3(sig_mmap_rst_reg_n),
        .O(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[4]),
        .Q(m_axi_mm2s_araddr[0]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[10] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[14]),
        .Q(m_axi_mm2s_araddr[10]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[11] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[15]),
        .Q(m_axi_mm2s_araddr[11]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[12] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[16]),
        .Q(m_axi_mm2s_araddr[12]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[13] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[17]),
        .Q(m_axi_mm2s_araddr[13]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[14] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[18]),
        .Q(m_axi_mm2s_araddr[14]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[15] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[19]),
        .Q(m_axi_mm2s_araddr[15]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[16] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[20]),
        .Q(m_axi_mm2s_araddr[16]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[17] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[21]),
        .Q(m_axi_mm2s_araddr[17]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[18] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[22]),
        .Q(m_axi_mm2s_araddr[18]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[19] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[23]),
        .Q(m_axi_mm2s_araddr[19]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[5]),
        .Q(m_axi_mm2s_araddr[1]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[20] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[24]),
        .Q(m_axi_mm2s_araddr[20]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[21] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[25]),
        .Q(m_axi_mm2s_araddr[21]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[22] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[26]),
        .Q(m_axi_mm2s_araddr[22]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[23] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[27]),
        .Q(m_axi_mm2s_araddr[23]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[24] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[28]),
        .Q(m_axi_mm2s_araddr[24]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[25] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[29]),
        .Q(m_axi_mm2s_araddr[25]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[26] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[30]),
        .Q(m_axi_mm2s_araddr[26]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[27] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[31]),
        .Q(m_axi_mm2s_araddr[27]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[28] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[32]),
        .Q(m_axi_mm2s_araddr[28]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[29] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[33]),
        .Q(m_axi_mm2s_araddr[29]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[6]),
        .Q(m_axi_mm2s_araddr[2]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[30] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[34]),
        .Q(m_axi_mm2s_araddr[30]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[31] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[35]),
        .Q(m_axi_mm2s_araddr[31]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[7]),
        .Q(m_axi_mm2s_araddr[3]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[8]),
        .Q(m_axi_mm2s_araddr[4]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[9]),
        .Q(m_axi_mm2s_araddr[5]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[10]),
        .Q(m_axi_mm2s_araddr[6]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[7] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[11]),
        .Q(m_axi_mm2s_araddr[7]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[8] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[12]),
        .Q(m_axi_mm2s_araddr[8]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[9] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[13]),
        .Q(m_axi_mm2s_araddr[9]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_burst_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[47]),
        .Q(m_axi_mm2s_arburst),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_len_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[36]),
        .Q(m_axi_mm2s_arlen[0]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_len_reg_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[37]),
        .Q(m_axi_mm2s_arlen[1]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_len_reg_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[38]),
        .Q(m_axi_mm2s_arlen[2]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_len_reg_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[39]),
        .Q(m_axi_mm2s_arlen[3]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_size_reg_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_aq_fifo_data_out[45]),
        .Q(m_axi_mm2s_arsize),
        .R(sig_next_addr_reg0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_posted_to_axi_2_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_5 ),
        .Q(sig_posted_to_axi_2),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_posted_to_axi_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_5 ),
        .Q(sig_posted_to_axi),
        .R(1'b0));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_cmd_status
   (sig_init_done,
    sig_cmd2mstr_cmd_valid,
    s_axis_mm2s_cmd_tready,
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg ,
    sig_stat2rsc_status_ready,
    mm2s_decerr_i,
    mm2s_interr_i,
    mm2s_slverr_i,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ,
    E,
    Q,
    SR,
    m_axi_mm2s_aclk,
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ,
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ,
    mm2s_sts_received,
    sig_cmd_stat_rst_int_reg_n,
    sig_rsc2stat_status_valid,
    m_axis_mm2s_sts_tready,
    s_axis_mm2s_cmd_tvalid_split,
    D,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6] );
  output sig_init_done;
  output sig_cmd2mstr_cmd_valid;
  output s_axis_mm2s_cmd_tready;
  output \USE_SINGLE_REG.sig_regfifo_full_reg_reg ;
  output sig_stat2rsc_status_ready;
  output mm2s_decerr_i;
  output mm2s_interr_i;
  output mm2s_slverr_i;
  output \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ;
  output [0:0]E;
  output [59:0]Q;
  input [0:0]SR;
  input m_axi_mm2s_aclk;
  input \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  input \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ;
  input mm2s_sts_received;
  input sig_cmd_stat_rst_int_reg_n;
  input sig_rsc2stat_status_valid;
  input m_axis_mm2s_sts_tready;
  input s_axis_mm2s_cmd_tvalid_split;
  input [59:0]D;
  input [3:0]\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6] ;

  wire [59:0]D;
  wire [0:0]E;
  wire I_CMD_FIFO_n_4;
  wire [59:0]Q;
  wire [0:0]SR;
  wire \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ;
  wire [3:0]\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6] ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_reg ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  wire m_axi_mm2s_aclk;
  wire m_axis_mm2s_sts_tready;
  wire mm2s_decerr_i;
  wire mm2s_interr_i;
  wire mm2s_slverr_i;
  wire mm2s_sts_received;
  wire s_axis_mm2s_cmd_tready;
  wire s_axis_mm2s_cmd_tvalid_split;
  wire sig_cmd2mstr_cmd_valid;
  wire sig_cmd_stat_rst_int_reg_n;
  wire sig_init_done;
  wire sig_init_done_0;
  wire sig_rsc2stat_status_valid;
  wire sig_stat2rsc_status_ready;

  Loopback_axi_dma_1_0_axi_datamover_fifo__parameterized0 \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO 
       (.SR(SR),
        .\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0]_0 (\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ),
        .\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6]_0 (\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6] ),
        .\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 (sig_stat2rsc_status_ready),
        .\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 (\USE_SINGLE_REG.sig_regfifo_full_reg_reg ),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axis_mm2s_sts_tready(m_axis_mm2s_sts_tready),
        .mm2s_decerr_i(mm2s_decerr_i),
        .mm2s_interr_i(mm2s_interr_i),
        .mm2s_slverr_i(mm2s_slverr_i),
        .mm2s_sts_received(mm2s_sts_received),
        .sig_cmd_stat_rst_int_reg_n(sig_cmd_stat_rst_int_reg_n),
        .sig_init_done(sig_init_done_0),
        .sig_init_done_reg_0(I_CMD_FIFO_n_4),
        .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid));
  Loopback_axi_dma_1_0_axi_datamover_fifo I_CMD_FIFO
       (.D(D),
        .E(E),
        .Q(Q),
        .SR(SR),
        .\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 (\USE_SINGLE_REG.sig_regfifo_empty_reg_reg ),
        .\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 (\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .s_axis_mm2s_cmd_tready(s_axis_mm2s_cmd_tready),
        .s_axis_mm2s_cmd_tvalid_split(s_axis_mm2s_cmd_tvalid_split),
        .sig_cmd2mstr_cmd_valid(sig_cmd2mstr_cmd_valid),
        .sig_cmd_stat_rst_int_reg_n(sig_cmd_stat_rst_int_reg_n),
        .sig_cmd_stat_rst_int_reg_n_reg(I_CMD_FIFO_n_4),
        .sig_init_done(sig_init_done),
        .sig_init_done_0(sig_init_done_0));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_fifo
   (sig_init_done,
    sig_cmd2mstr_cmd_valid,
    s_axis_mm2s_cmd_tready,
    E,
    sig_cmd_stat_rst_int_reg_n_reg,
    Q,
    SR,
    m_axi_mm2s_aclk,
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ,
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ,
    s_axis_mm2s_cmd_tvalid_split,
    sig_cmd_stat_rst_int_reg_n,
    sig_init_done_0,
    D);
  output sig_init_done;
  output sig_cmd2mstr_cmd_valid;
  output s_axis_mm2s_cmd_tready;
  output [0:0]E;
  output sig_cmd_stat_rst_int_reg_n_reg;
  output [59:0]Q;
  input [0:0]SR;
  input m_axi_mm2s_aclk;
  input \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  input \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ;
  input s_axis_mm2s_cmd_tvalid_split;
  input sig_cmd_stat_rst_int_reg_n;
  input sig_init_done_0;
  input [59:0]D;

  wire [59:0]D;
  wire [0:0]E;
  wire \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_reg ;
  wire \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_reg2 ;
  wire [59:0]Q;
  wire [0:0]SR;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  wire m_axi_mm2s_aclk;
  wire s_axis_mm2s_cmd_tready;
  wire s_axis_mm2s_cmd_tvalid_split;
  wire sig_cmd2mstr_cmd_valid;
  wire sig_cmd_stat_rst_int_reg_n;
  wire sig_cmd_stat_rst_int_reg_n_reg;
  wire sig_init_done;
  wire sig_init_done_0;
  wire sig_init_done_i_1__8_n_0;

  LUT2 #(
    .INIT(4'h8)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg[66]_i_1 
       (.I0(s_axis_mm2s_cmd_tready),
        .I1(s_axis_mm2s_cmd_tvalid_split),
        .O(E));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[10] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[10]),
        .Q(Q[10]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[11] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[11]),
        .Q(Q[11]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[12] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[12]),
        .Q(Q[12]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[13] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[13]),
        .Q(Q[13]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[14] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[14]),
        .Q(Q[14]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[15] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[15]),
        .Q(Q[15]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[16] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[16]),
        .Q(Q[16]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[17] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[17]),
        .Q(Q[17]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[18] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[18]),
        .Q(Q[18]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[19] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[19]),
        .Q(Q[19]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[20] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[20]),
        .Q(Q[20]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[21] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[21]),
        .Q(Q[21]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[22] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[22]),
        .Q(Q[22]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[23] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[23]),
        .Q(Q[23]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[24] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[24]),
        .Q(Q[24]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[25] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[25]),
        .Q(Q[25]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[26] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[26]),
        .Q(Q[26]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[33] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[27]),
        .Q(Q[27]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[35] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[28]),
        .Q(Q[28]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[36] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[29]),
        .Q(Q[29]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[37] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[30]),
        .Q(Q[30]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[38] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[31]),
        .Q(Q[31]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[39] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[32]),
        .Q(Q[32]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[40] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[33]),
        .Q(Q[33]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[41] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[34]),
        .Q(Q[34]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[42] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[35]),
        .Q(Q[35]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[43] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[36]),
        .Q(Q[36]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[44] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[37]),
        .Q(Q[37]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[45] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[38]),
        .Q(Q[38]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[46] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[39]),
        .Q(Q[39]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[47] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[40]),
        .Q(Q[40]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[48] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[41]),
        .Q(Q[41]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[49] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[42]),
        .Q(Q[42]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[4]),
        .Q(Q[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[50] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[43]),
        .Q(Q[43]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[51] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[44]),
        .Q(Q[44]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[52] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[45]),
        .Q(Q[45]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[53] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[46]),
        .Q(Q[46]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[54] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[47]),
        .Q(Q[47]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[55] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[48]),
        .Q(Q[48]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[56] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[49]),
        .Q(Q[49]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[57] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[50]),
        .Q(Q[50]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[58] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[51]),
        .Q(Q[51]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[59] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[52]),
        .Q(Q[52]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[5]),
        .Q(Q[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[60] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[53]),
        .Q(Q[53]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[61] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[54]),
        .Q(Q[54]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[62] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[55]),
        .Q(Q[55]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[56]),
        .Q(Q[56]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[64] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[57]),
        .Q(Q[57]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[65] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[58]),
        .Q(Q[58]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[66] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[59]),
        .Q(Q[59]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[6]),
        .Q(Q[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[7]),
        .Q(Q[7]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[8] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[8]),
        .Q(Q[8]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[9] 
       (.C(m_axi_mm2s_aclk),
        .CE(E),
        .D(D[9]),
        .Q(Q[9]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .Q(s_axis_mm2s_cmd_tready),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .Q(sig_cmd2mstr_cmd_valid),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    sig_init_done_i_1__8
       (.I0(sig_cmd_stat_rst_int_reg_n),
        .I1(sig_init_done),
        .I2(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_reg ),
        .I3(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_reg2 ),
        .O(sig_init_done_i_1__8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    sig_init_done_i_1__9
       (.I0(sig_cmd_stat_rst_int_reg_n),
        .I1(sig_init_done_0),
        .I2(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_reg ),
        .I3(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_reg2 ),
        .O(sig_cmd_stat_rst_int_reg_n_reg));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_done_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_init_done_i_1__8_n_0),
        .Q(sig_init_done),
        .R(1'b0));
  FDSE #(
    .INIT(1'b0)) 
    sig_init_reg2_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_reg ),
        .Q(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_reg2 ),
        .S(SR));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(SR),
        .Q(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_reg ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "axi_datamover_fifo" *) 
module Loopback_axi_dma_1_0_axi_datamover_fifo__parameterized0
   (sig_init_done,
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ,
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ,
    mm2s_decerr_i,
    mm2s_interr_i,
    mm2s_slverr_i,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0]_0 ,
    sig_init_done_reg_0,
    m_axi_mm2s_aclk,
    SR,
    mm2s_sts_received,
    sig_cmd_stat_rst_int_reg_n,
    sig_rsc2stat_status_valid,
    m_axis_mm2s_sts_tready,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6]_0 );
  output sig_init_done;
  output \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  output \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ;
  output mm2s_decerr_i;
  output mm2s_interr_i;
  output mm2s_slverr_i;
  output \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0]_0 ;
  input sig_init_done_reg_0;
  input m_axi_mm2s_aclk;
  input [0:0]SR;
  input mm2s_sts_received;
  input sig_cmd_stat_rst_int_reg_n;
  input sig_rsc2stat_status_valid;
  input m_axis_mm2s_sts_tready;
  input [3:0]\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6]_0 ;

  wire [0:0]SR;
  wire \USE_SINGLE_REG.sig_push_regfifo ;
  wire \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0]_0 ;
  wire [3:0]\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6]_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__4_n_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_i_1__3_n_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  wire m_axi_mm2s_aclk;
  wire [6:0]m_axis_mm2s_sts_tdata_int;
  wire m_axis_mm2s_sts_tready;
  wire mm2s_decerr_i;
  wire mm2s_interr_i;
  wire mm2s_slverr_i;
  wire mm2s_sts_received;
  wire sig_cmd_stat_rst_int_reg_n;
  wire sig_init_done;
  wire sig_init_done_reg_0;
  wire sig_rsc2stat_status_valid;

  LUT2 #(
    .INIT(4'h8)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg[6]_i_1 
       (.I0(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .I1(sig_rsc2stat_status_valid),
        .O(\USE_SINGLE_REG.sig_push_regfifo ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6]_0 [0]),
        .Q(m_axis_mm2s_sts_tdata_int[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6]_0 [1]),
        .Q(m_axis_mm2s_sts_tdata_int[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6]_0 [2]),
        .Q(m_axis_mm2s_sts_tdata_int[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6]_0 [3]),
        .Q(m_axis_mm2s_sts_tdata_int[6]),
        .R(SR));
  LUT5 #(
    .INIT(32'hF8FFF8F8)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__4 
       (.I0(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .I1(m_axis_mm2s_sts_tready),
        .I2(sig_init_done),
        .I3(sig_rsc2stat_status_valid),
        .I4(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .O(\USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__4_n_0 ),
        .Q(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .R(SR));
  LUT5 #(
    .INIT(32'h00AA8080)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_i_1__3 
       (.I0(sig_cmd_stat_rst_int_reg_n),
        .I1(sig_rsc2stat_status_valid),
        .I2(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .I3(m_axis_mm2s_sts_tready),
        .I4(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .O(\USE_SINGLE_REG.sig_regfifo_full_reg_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_full_reg_i_1__3_n_0 ),
        .Q(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT3 #(
    .INIT(8'h20)) 
    mm2s_decerr_i_i_1
       (.I0(m_axis_mm2s_sts_tdata_int[5]),
        .I1(mm2s_sts_received),
        .I2(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .O(mm2s_decerr_i));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT3 #(
    .INIT(8'h20)) 
    mm2s_interr_i_i_1
       (.I0(m_axis_mm2s_sts_tdata_int[4]),
        .I1(mm2s_sts_received),
        .I2(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .O(mm2s_interr_i));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT3 #(
    .INIT(8'h20)) 
    mm2s_slverr_i_i_1
       (.I0(m_axis_mm2s_sts_tdata_int[6]),
        .I1(mm2s_sts_received),
        .I2(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .O(mm2s_slverr_i));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \mm2s_tag[0]_i_1 
       (.I0(m_axis_mm2s_sts_tdata_int[0]),
        .I1(mm2s_sts_received),
        .I2(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .O(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_done_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_init_done_reg_0),
        .Q(sig_init_done),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "axi_datamover_fifo" *) 
module Loopback_axi_dma_1_0_axi_datamover_fifo__parameterized1
   (FIFO_Full_reg,
    sig_init_reg2,
    sig_push_addr_reg1_out,
    sig_inhibit_rdy_n_reg_0,
    FIFO_Full_reg_0,
    sig_addr_reg_empty_reg,
    sig_calc_error_reg_reg,
    out,
    SS,
    m_axi_mm2s_aclk,
    sig_init_reg,
    sig_mstr2addr_cmd_valid,
    sig_mmap_rst_reg_n,
    sig_addr_reg_empty,
    sig_sf_allow_addr_req,
    sig_data2addr_stop_req,
    in);
  output FIFO_Full_reg;
  output sig_init_reg2;
  output sig_push_addr_reg1_out;
  output sig_inhibit_rdy_n_reg_0;
  output FIFO_Full_reg_0;
  output sig_addr_reg_empty_reg;
  output sig_calc_error_reg_reg;
  output [38:0]out;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input sig_init_reg;
  input sig_mstr2addr_cmd_valid;
  input sig_mmap_rst_reg_n;
  input sig_addr_reg_empty;
  input sig_sf_allow_addr_req;
  input sig_data2addr_stop_req;
  input [37:0]in;

  wire FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire [0:0]SS;
  wire [37:0]in;
  wire m_axi_mm2s_aclk;
  wire [38:0]out;
  wire sig_addr_reg_empty;
  wire sig_addr_reg_empty_reg;
  wire sig_calc_error_reg_reg;
  wire sig_data2addr_stop_req;
  wire sig_inhibit_rdy_n_i_1_n_0;
  wire sig_inhibit_rdy_n_reg_0;
  wire sig_init_done;
  wire sig_init_done_i_1__7_n_0;
  wire sig_init_reg;
  wire sig_init_reg2;
  wire sig_mmap_rst_reg_n;
  wire sig_mstr2addr_cmd_valid;
  wire sig_push_addr_reg1_out;
  wire sig_sf_allow_addr_req;

  Loopback_axi_dma_1_0_srl_fifo_f__parameterized2 \USE_SRL_FIFO.I_SYNC_FIFO 
       (.FIFO_Full_reg(FIFO_Full_reg),
        .FIFO_Full_reg_0(FIFO_Full_reg_0),
        .\INFERRED_GEN.cnt_i_reg[1] (sig_inhibit_rdy_n_reg_0),
        .SS(SS),
        .in(in),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .out(out),
        .sig_addr_reg_empty(sig_addr_reg_empty),
        .sig_addr_reg_empty_reg(sig_addr_reg_empty_reg),
        .sig_calc_error_reg_reg(sig_calc_error_reg_reg),
        .sig_data2addr_stop_req(sig_data2addr_stop_req),
        .sig_halt_reg_reg(sig_push_addr_reg1_out),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid),
        .sig_sf_allow_addr_req(sig_sf_allow_addr_req));
  LUT2 #(
    .INIT(4'hE)) 
    sig_inhibit_rdy_n_i_1
       (.I0(sig_init_done),
        .I1(sig_inhibit_rdy_n_reg_0),
        .O(sig_inhibit_rdy_n_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_inhibit_rdy_n_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_inhibit_rdy_n_i_1_n_0),
        .Q(sig_inhibit_rdy_n_reg_0),
        .R(SS));
  LUT4 #(
    .INIT(16'h2000)) 
    sig_init_done_i_1__7
       (.I0(sig_mmap_rst_reg_n),
        .I1(sig_init_done),
        .I2(sig_init_reg),
        .I3(sig_init_reg2),
        .O(sig_init_done_i_1__7_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_done_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_init_done_i_1__7_n_0),
        .Q(sig_init_done),
        .R(1'b0));
  FDSE #(
    .INIT(1'b0)) 
    sig_init_reg2_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_init_reg),
        .Q(sig_init_reg2),
        .S(SS));
endmodule

(* ORIG_REF_NAME = "axi_datamover_fifo" *) 
module Loopback_axi_dma_1_0_axi_datamover_fifo__parameterized2
   (FIFO_Full_reg,
    sig_init_done,
    sig_mmap_rst_reg_n_reg,
    sig_push_dqual_reg,
    sig_inhibit_rdy_n_reg_0,
    FIFO_Full_reg_0,
    E,
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ,
    SR,
    D,
    out,
    sig_mmap_rst_reg_n_reg_0,
    sig_next_calc_error_reg_reg,
    sig_mmap_rst_reg_n_reg_1,
    SS,
    m_axi_mm2s_aclk,
    sig_init_done_reg_0,
    sig_mmap_rst_reg_n,
    sig_first_dbeat_reg,
    sig_first_dbeat_reg_0,
    sig_mstr2data_cmd_valid,
    sig_dqual_reg_empty,
    sig_dqual_reg_empty_reg,
    sig_next_sequential_reg,
    m_axi_mm2s_rlast,
    Q,
    \sig_dbeat_cntr_reg[6] ,
    \sig_dbeat_cntr_reg[5] ,
    sig_ld_new_cmd_reg,
    sig_rsc2stat_status_valid,
    sig_stat2rsc_status_ready,
    sig_next_calc_error_reg,
    m_axi_mm2s_rready,
    full,
    sig_dqual_reg_empty_reg_0,
    m_axi_mm2s_rvalid,
    sig_dqual_reg_empty_reg_1,
    sig_dqual_reg_full,
    sig_last_dbeat_reg,
    in);
  output FIFO_Full_reg;
  output sig_init_done;
  output sig_mmap_rst_reg_n_reg;
  output sig_push_dqual_reg;
  output sig_inhibit_rdy_n_reg_0;
  output FIFO_Full_reg_0;
  output [0:0]E;
  output \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  output [0:0]SR;
  output [7:0]D;
  output [12:0]out;
  output sig_mmap_rst_reg_n_reg_0;
  output sig_next_calc_error_reg_reg;
  output sig_mmap_rst_reg_n_reg_1;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input sig_init_done_reg_0;
  input sig_mmap_rst_reg_n;
  input sig_first_dbeat_reg;
  input sig_first_dbeat_reg_0;
  input sig_mstr2data_cmd_valid;
  input sig_dqual_reg_empty;
  input sig_dqual_reg_empty_reg;
  input sig_next_sequential_reg;
  input m_axi_mm2s_rlast;
  input [7:0]Q;
  input \sig_dbeat_cntr_reg[6] ;
  input \sig_dbeat_cntr_reg[5] ;
  input sig_ld_new_cmd_reg;
  input sig_rsc2stat_status_valid;
  input sig_stat2rsc_status_ready;
  input sig_next_calc_error_reg;
  input [2:0]m_axi_mm2s_rready;
  input full;
  input sig_dqual_reg_empty_reg_0;
  input m_axi_mm2s_rvalid;
  input sig_dqual_reg_empty_reg_1;
  input sig_dqual_reg_full;
  input sig_last_dbeat_reg;
  input [16:0]in;

  wire [7:0]D;
  wire [0:0]E;
  wire FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire [7:0]Q;
  wire [0:0]SR;
  wire [0:0]SS;
  wire full;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  wire [16:0]in;
  wire m_axi_mm2s_aclk;
  wire m_axi_mm2s_rlast;
  wire [2:0]m_axi_mm2s_rready;
  wire m_axi_mm2s_rvalid;
  wire [12:0]out;
  wire \sig_dbeat_cntr_reg[5] ;
  wire \sig_dbeat_cntr_reg[6] ;
  wire sig_dqual_reg_empty;
  wire sig_dqual_reg_empty_reg;
  wire sig_dqual_reg_empty_reg_0;
  wire sig_dqual_reg_empty_reg_1;
  wire sig_dqual_reg_full;
  wire sig_first_dbeat_reg;
  wire sig_first_dbeat_reg_0;
  wire sig_inhibit_rdy_n_i_1_n_0;
  wire sig_inhibit_rdy_n_reg_0;
  wire sig_init_done;
  wire sig_init_done_reg_0;
  wire sig_last_dbeat_reg;
  wire sig_ld_new_cmd_reg;
  wire sig_mmap_rst_reg_n;
  wire sig_mmap_rst_reg_n_reg;
  wire sig_mmap_rst_reg_n_reg_0;
  wire sig_mmap_rst_reg_n_reg_1;
  wire sig_mstr2data_cmd_valid;
  wire sig_next_calc_error_reg;
  wire sig_next_calc_error_reg_reg;
  wire sig_next_sequential_reg;
  wire sig_push_dqual_reg;
  wire sig_rsc2stat_status_valid;
  wire sig_stat2rsc_status_ready;

  Loopback_axi_dma_1_0_srl_fifo_f__parameterized3 \USE_SRL_FIFO.I_SYNC_FIFO 
       (.D(D),
        .E(E),
        .FIFO_Full_reg(FIFO_Full_reg),
        .FIFO_Full_reg_0(FIFO_Full_reg_0),
        .\INFERRED_GEN.cnt_i_reg[1] (sig_inhibit_rdy_n_reg_0),
        .Q(Q),
        .SR(SR),
        .SS(SS),
        .full(full),
        .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg (\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ),
        .in(in),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axi_mm2s_rlast(m_axi_mm2s_rlast),
        .m_axi_mm2s_rready(m_axi_mm2s_rready),
        .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid),
        .out(out),
        .\sig_dbeat_cntr_reg[5] (\sig_dbeat_cntr_reg[5] ),
        .\sig_dbeat_cntr_reg[6] (\sig_dbeat_cntr_reg[6] ),
        .sig_dqual_reg_empty(sig_dqual_reg_empty),
        .sig_dqual_reg_empty_reg(sig_dqual_reg_empty_reg),
        .sig_dqual_reg_empty_reg_0(sig_dqual_reg_empty_reg_0),
        .sig_dqual_reg_empty_reg_1(sig_dqual_reg_empty_reg_1),
        .sig_dqual_reg_full(sig_dqual_reg_full),
        .sig_first_dbeat_reg(sig_first_dbeat_reg),
        .sig_first_dbeat_reg_0(sig_first_dbeat_reg_0),
        .sig_last_dbeat_reg(sig_last_dbeat_reg),
        .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mmap_rst_reg_n_reg(sig_mmap_rst_reg_n_reg),
        .sig_mmap_rst_reg_n_reg_0(sig_mmap_rst_reg_n_reg_0),
        .sig_mmap_rst_reg_n_reg_1(sig_mmap_rst_reg_n_reg_1),
        .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid),
        .sig_next_calc_error_reg(sig_next_calc_error_reg),
        .sig_next_calc_error_reg_reg(sig_next_calc_error_reg_reg),
        .sig_next_sequential_reg(sig_next_sequential_reg),
        .sig_next_sequential_reg_reg(sig_push_dqual_reg),
        .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid),
        .sig_stat2rsc_status_ready(sig_stat2rsc_status_ready));
  LUT2 #(
    .INIT(4'hE)) 
    sig_inhibit_rdy_n_i_1
       (.I0(sig_init_done),
        .I1(sig_inhibit_rdy_n_reg_0),
        .O(sig_inhibit_rdy_n_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_inhibit_rdy_n_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_inhibit_rdy_n_i_1_n_0),
        .Q(sig_inhibit_rdy_n_reg_0),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_done_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_init_done_reg_0),
        .Q(sig_init_done),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "axi_datamover_fifo" *) 
module Loopback_axi_dma_1_0_axi_datamover_fifo__parameterized3
   (FIFO_Full_reg,
    sig_init_done,
    Q,
    sig_inhibit_rdy_n_reg_0,
    sig_inhibit_rdy_n_reg_1,
    SS,
    m_axi_mm2s_aclk,
    sig_init_done_reg_0,
    FIFO_Full_reg_0,
    \INFERRED_GEN.cnt_i_reg[2] ,
    \INFERRED_GEN.cnt_i_reg[1] ,
    sig_mstr2sf_cmd_valid);
  output FIFO_Full_reg;
  output sig_init_done;
  output [0:0]Q;
  output sig_inhibit_rdy_n_reg_0;
  output sig_inhibit_rdy_n_reg_1;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input sig_init_done_reg_0;
  input FIFO_Full_reg_0;
  input \INFERRED_GEN.cnt_i_reg[2] ;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input sig_mstr2sf_cmd_valid;

  wire FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire \INFERRED_GEN.cnt_i_reg[2] ;
  wire [0:0]Q;
  wire [0:0]SS;
  wire m_axi_mm2s_aclk;
  wire sig_inhibit_rdy_n_i_1_n_0;
  wire sig_inhibit_rdy_n_reg_0;
  wire sig_inhibit_rdy_n_reg_1;
  wire sig_init_done;
  wire sig_init_done_reg_0;
  wire sig_mstr2sf_cmd_valid;

  Loopback_axi_dma_1_0_srl_fifo_f__parameterized4 \USE_SRL_FIFO.I_SYNC_FIFO 
       (.FIFO_Full_reg(FIFO_Full_reg),
        .FIFO_Full_reg_0(FIFO_Full_reg_0),
        .\INFERRED_GEN.cnt_i_reg[0] (sig_inhibit_rdy_n_reg_1),
        .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ),
        .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ),
        .Q(Q),
        .SS(SS),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg_0),
        .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid));
  LUT2 #(
    .INIT(4'hE)) 
    sig_inhibit_rdy_n_i_1
       (.I0(sig_init_done),
        .I1(sig_inhibit_rdy_n_reg_1),
        .O(sig_inhibit_rdy_n_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_inhibit_rdy_n_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_inhibit_rdy_n_i_1_n_0),
        .Q(sig_inhibit_rdy_n_reg_1),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_done_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_init_done_reg_0),
        .Q(sig_init_done),
        .R(1'b0));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_mm2s_full_wrap
   (m_axis_mm2s_tvalid,
    sig_rst2all_stop_request,
    m_axi_mm2s_arsize,
    m_axi_mm2s_arburst,
    m_axi_mm2s_arvalid,
    m_axis_mm2s_tlast,
    s_axis_mm2s_cmd_tready,
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg ,
    mm2s_decerr_i,
    mm2s_interr_i,
    mm2s_slverr_i,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ,
    m_axi_mm2s_rready,
    mm2s_halt_cmplt,
    m_axi_mm2s_araddr,
    m_axi_mm2s_arlen,
    m_axis_mm2s_tdata,
    m_axis_mm2s_tkeep,
    m_axi_mm2s_aclk,
    m_axi_mm2s_rdata,
    out,
    sig_s_h_halt_reg_reg,
    mm2s_sts_received,
    m_axis_mm2s_sts_tready,
    s_axis_mm2s_cmd_tvalid_split,
    m_axi_mm2s_rlast,
    m_axi_mm2s_rvalid,
    m_axis_mm2s_tready,
    m_axi_mm2s_rresp,
    m_axi_mm2s_arready,
    D);
  output m_axis_mm2s_tvalid;
  output sig_rst2all_stop_request;
  output [0:0]m_axi_mm2s_arsize;
  output [0:0]m_axi_mm2s_arburst;
  output m_axi_mm2s_arvalid;
  output m_axis_mm2s_tlast;
  output s_axis_mm2s_cmd_tready;
  output \USE_SINGLE_REG.sig_regfifo_full_reg_reg ;
  output mm2s_decerr_i;
  output mm2s_interr_i;
  output mm2s_slverr_i;
  output \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ;
  output m_axi_mm2s_rready;
  output mm2s_halt_cmplt;
  output [31:0]m_axi_mm2s_araddr;
  output [3:0]m_axi_mm2s_arlen;
  output [31:0]m_axis_mm2s_tdata;
  output [3:0]m_axis_mm2s_tkeep;
  input m_axi_mm2s_aclk;
  input [31:0]m_axi_mm2s_rdata;
  input out;
  input sig_s_h_halt_reg_reg;
  input mm2s_sts_received;
  input m_axis_mm2s_sts_tready;
  input s_axis_mm2s_cmd_tvalid_split;
  input m_axi_mm2s_rlast;
  input m_axi_mm2s_rvalid;
  input m_axis_mm2s_tready;
  input [1:0]m_axi_mm2s_rresp;
  input m_axi_mm2s_arready;
  input [59:0]D;

  wire [59:0]D;
  wire \ENABLE_AXIS_SKID.I_MM2S_SKID_BUF_n_6 ;
  wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_inhibit_rdy_n ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_inhibit_rdy_n ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done ;
  wire \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_37 ;
  wire \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_38 ;
  wire \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_42 ;
  wire \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_46 ;
  wire I_ADDR_CNTL_n_0;
  wire I_ADDR_CNTL_n_10;
  wire I_ADDR_CNTL_n_2;
  wire \I_CMD_FIFO/USE_SINGLE_REG.sig_push_regfifo ;
  wire \I_CMD_FIFO/sig_init_done ;
  wire I_CMD_STATUS_n_26;
  wire I_CMD_STATUS_n_27;
  wire I_CMD_STATUS_n_28;
  wire I_CMD_STATUS_n_29;
  wire I_CMD_STATUS_n_30;
  wire I_CMD_STATUS_n_31;
  wire I_CMD_STATUS_n_32;
  wire I_CMD_STATUS_n_33;
  wire I_CMD_STATUS_n_34;
  wire I_CMD_STATUS_n_35;
  wire I_CMD_STATUS_n_36;
  wire I_CMD_STATUS_n_37;
  wire I_CMD_STATUS_n_38;
  wire I_CMD_STATUS_n_39;
  wire I_CMD_STATUS_n_40;
  wire I_CMD_STATUS_n_41;
  wire I_MSTR_PCC_n_54;
  wire I_MSTR_PCC_n_55;
  wire I_RD_DATA_CNTL_n_1;
  wire I_RD_DATA_CNTL_n_12;
  wire I_RD_DATA_CNTL_n_21;
  wire I_RD_DATA_CNTL_n_22;
  wire I_RD_DATA_CNTL_n_23;
  wire I_RD_DATA_CNTL_n_3;
  wire I_RESET_n_5;
  wire I_RESET_n_6;
  wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ;
  wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_done ;
  wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ;
  wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2 ;
  wire \OMIT_UNPACKING.lsig_cmd_loaded ;
  wire \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_reg ;
  wire [15:0]data;
  wire m_axi_mm2s_aclk;
  wire [31:0]m_axi_mm2s_araddr;
  wire [0:0]m_axi_mm2s_arburst;
  wire [3:0]m_axi_mm2s_arlen;
  wire m_axi_mm2s_arready;
  wire [0:0]m_axi_mm2s_arsize;
  wire m_axi_mm2s_arvalid;
  wire [31:0]m_axi_mm2s_rdata;
  wire m_axi_mm2s_rlast;
  wire m_axi_mm2s_rready;
  wire [1:0]m_axi_mm2s_rresp;
  wire m_axi_mm2s_rvalid;
  wire m_axis_mm2s_sts_tready;
  wire [31:0]m_axis_mm2s_tdata;
  wire [3:0]m_axis_mm2s_tkeep;
  wire m_axis_mm2s_tlast;
  wire m_axis_mm2s_tready;
  wire m_axis_mm2s_tvalid;
  wire mm2s_decerr_i;
  wire mm2s_halt_cmplt;
  wire mm2s_interr_i;
  wire mm2s_slverr_i;
  wire mm2s_sts_received;
  wire out;
  wire p_0_in5_in;
  wire s_axis_mm2s_cmd_tready;
  wire s_axis_mm2s_cmd_tvalid_split;
  wire sig_addr2data_addr_posted;
  wire sig_addr2rsc_calc_error;
  wire sig_addr_reg_empty;
  wire sig_calc_error_reg;
  wire sig_cmd2mstr_cmd_valid;
  wire [25:0]sig_cmd2mstr_command;
  wire sig_cmd_eof_slice;
  wire sig_cmd_stat_rst_int;
  wire sig_cmd_stat_rst_int_reg_n;
  wire sig_cmd_type_slice;
  wire [0:0]sig_coelsc_tag_reg;
  wire sig_data2addr_stop_req;
  wire sig_data2rsc_decerr;
  wire sig_data2rsc_valid;
  wire sig_data2sf_cmd_cmplt;
  wire sig_data_fifo_full;
  wire sig_good_sin_strm_dbeat;
  wire sig_halt_reg_dly2;
  wire sig_halt_reg_dly3;
  wire sig_last_skid_mux_out;
  wire sig_last_skid_reg;
  wire sig_mmap_rst;
  wire sig_mmap_rst_reg_n;
  wire [31:3]sig_mstr2addr_addr;
  wire [0:0]sig_mstr2addr_burst;
  wire sig_mstr2addr_cmd_valid;
  wire sig_mstr2data_cmd_cmplt;
  wire sig_mstr2data_cmd_valid;
  wire sig_mstr2data_eof;
  wire [3:0]sig_mstr2data_last_strb;
  wire sig_mstr2data_sequential;
  wire [3:0]sig_mstr2data_strt_strb;
  wire sig_mstr2sf_cmd_valid;
  wire sig_mstr2sf_eof;
  wire sig_mstr2sf_strt_offset;
  wire sig_rd_sts_interr_reg0;
  wire sig_rd_sts_slverr_reg0;
  wire sig_rdc2sf_wlast;
  wire [3:0]sig_rdc2sf_wstrb;
  wire sig_rsc2data_ready;
  wire [0:0]sig_rsc2stat_status;
  wire [6:4]sig_rsc2stat_status_0;
  wire sig_rsc2stat_status_valid;
  wire sig_rst2all_stop_request;
  wire sig_s_h_halt_reg_reg;
  wire [31:0]sig_sf2dre_wdata;
  wire [3:0]sig_sf2dre_wstrb;
  wire sig_sf_allow_addr_req;
  wire sig_skid2dre_wready;
  wire sig_slast_with_stop;
  wire [3:3]sig_sstrb_stop_mask;
  wire sig_stat2rsc_status_ready;
  wire sig_stream_rst;
  wire sig_stream_rst_reg_n;
  wire [1:0]sig_xfer_addr_reg;
  wire [3:0]sig_xfer_len_im2;

  Loopback_axi_dma_1_0_axi_datamover_skid_buf \ENABLE_AXIS_SKID.I_MM2S_SKID_BUF 
       (.\OMIT_UNPACKING.lsig_cmd_loaded (\OMIT_UNPACKING.lsig_cmd_loaded ),
        .SR(sig_stream_rst),
        .dout({sig_sf2dre_wstrb,sig_sf2dre_wdata}),
        .empty(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_37 ),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axis_mm2s_tdata(m_axis_mm2s_tdata),
        .m_axis_mm2s_tkeep(m_axis_mm2s_tkeep),
        .m_axis_mm2s_tlast(m_axis_mm2s_tlast),
        .m_axis_mm2s_tready(m_axis_mm2s_tready),
        .m_axis_mm2s_tvalid(m_axis_mm2s_tvalid),
        .out(p_0_in5_in),
        .sig_halt_reg_dly2(sig_halt_reg_dly2),
        .sig_halt_reg_dly3(sig_halt_reg_dly3),
        .sig_last_skid_mux_out(sig_last_skid_mux_out),
        .sig_last_skid_reg(sig_last_skid_reg),
        .sig_m_valid_out_reg_0(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_46 ),
        .sig_s_ready_dup_reg_0(\ENABLE_AXIS_SKID.I_MM2S_SKID_BUF_n_6 ),
        .sig_s_ready_dup_reg_1(I_RD_DATA_CNTL_n_22),
        .sig_s_ready_out_reg_0(sig_skid2dre_wready),
        .sig_slast_with_stop(sig_slast_with_stop),
        .sig_sstrb_stop_mask(sig_sstrb_stop_mask),
        .\sig_sstrb_stop_mask_reg[3]_0 (I_RD_DATA_CNTL_n_23),
        .sig_stream_rst_reg_n(sig_stream_rst_reg_n));
  Loopback_axi_dma_1_0_axi_datamover_rd_sf \GEN_INCLUDE_MM2S_SF.I_RD_SF 
       (.FIFO_Full_reg(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_38 ),
        .\OMIT_UNPACKING.lsig_cmd_loaded (\OMIT_UNPACKING.lsig_cmd_loaded ),
        .\OMIT_UNPACKING.lsig_cmd_loaded_reg_0 (sig_skid2dre_wready),
        .SS(sig_mmap_rst),
        .din({sig_data2sf_cmd_cmplt,sig_rdc2sf_wlast,sig_rdc2sf_wstrb,m_axi_mm2s_rdata}),
        .dout({sig_sf2dre_wstrb,sig_sf2dre_wdata}),
        .empty(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_37 ),
        .full(sig_data_fifo_full),
        .\gen_fwft.empty_fwft_i_reg (\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_46 ),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .out(p_0_in5_in),
        .sig_inhibit_rdy_n(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ),
        .sig_inhibit_rdy_n_reg(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_42 ),
        .sig_init_done(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_done ),
        .sig_init_done_reg(I_RESET_n_5),
        .sig_last_skid_mux_out(sig_last_skid_mux_out),
        .sig_last_skid_reg(sig_last_skid_reg),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid),
        .sig_ok_to_post_rd_addr_reg_0(I_ADDR_CNTL_n_0),
        .sig_sf_allow_addr_req(sig_sf_allow_addr_req),
        .sig_slast_with_stop(sig_slast_with_stop),
        .sig_sstrb_stop_mask(sig_sstrb_stop_mask),
        .\sig_token_cntr_reg[2]_0 (I_RD_DATA_CNTL_n_3),
        .wr_en(sig_good_sin_strm_dbeat));
  Loopback_axi_dma_1_0_axi_datamover_addr_cntl I_ADDR_CNTL
       (.FIFO_Full_reg(I_ADDR_CNTL_n_2),
        .FIFO_Full_reg_0(I_ADDR_CNTL_n_10),
        .SS(sig_mmap_rst),
        .in({sig_calc_error_reg,sig_mstr2addr_burst,sig_xfer_len_im2,sig_mstr2addr_addr,sig_mstr2sf_strt_offset,sig_xfer_addr_reg}),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axi_mm2s_araddr(m_axi_mm2s_araddr),
        .m_axi_mm2s_arburst(m_axi_mm2s_arburst),
        .m_axi_mm2s_arlen(m_axi_mm2s_arlen),
        .m_axi_mm2s_arready(m_axi_mm2s_arready),
        .m_axi_mm2s_arsize(m_axi_mm2s_arsize),
        .m_axi_mm2s_arvalid(m_axi_mm2s_arvalid),
        .out(I_ADDR_CNTL_n_0),
        .sig_addr2rsc_calc_error(sig_addr2rsc_calc_error),
        .sig_addr_reg_empty(sig_addr_reg_empty),
        .sig_data2addr_stop_req(sig_data2addr_stop_req),
        .sig_inhibit_rdy_n(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_inhibit_rdy_n ),
        .sig_init_reg(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ),
        .sig_init_reg2(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2 ),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid),
        .sig_posted_to_axi_reg_0(sig_addr2data_addr_posted),
        .sig_sf_allow_addr_req(sig_sf_allow_addr_req));
  Loopback_axi_dma_1_0_axi_datamover_cmd_status I_CMD_STATUS
       (.D(D),
        .E(\I_CMD_FIFO/USE_SINGLE_REG.sig_push_regfifo ),
        .Q({data,I_CMD_STATUS_n_26,I_CMD_STATUS_n_27,I_CMD_STATUS_n_28,I_CMD_STATUS_n_29,I_CMD_STATUS_n_30,I_CMD_STATUS_n_31,I_CMD_STATUS_n_32,I_CMD_STATUS_n_33,I_CMD_STATUS_n_34,I_CMD_STATUS_n_35,I_CMD_STATUS_n_36,I_CMD_STATUS_n_37,I_CMD_STATUS_n_38,I_CMD_STATUS_n_39,I_CMD_STATUS_n_40,I_CMD_STATUS_n_41,sig_cmd_eof_slice,sig_cmd_type_slice,sig_cmd2mstr_command}),
        .SR(sig_cmd_stat_rst_int),
        .\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] (\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] ),
        .\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6] ({sig_rsc2stat_status_0,sig_rsc2stat_status}),
        .\USE_SINGLE_REG.sig_regfifo_empty_reg_reg (I_MSTR_PCC_n_55),
        .\USE_SINGLE_REG.sig_regfifo_full_reg_reg (\USE_SINGLE_REG.sig_regfifo_full_reg_reg ),
        .\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 (I_MSTR_PCC_n_54),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axis_mm2s_sts_tready(m_axis_mm2s_sts_tready),
        .mm2s_decerr_i(mm2s_decerr_i),
        .mm2s_interr_i(mm2s_interr_i),
        .mm2s_slverr_i(mm2s_slverr_i),
        .mm2s_sts_received(mm2s_sts_received),
        .s_axis_mm2s_cmd_tready(s_axis_mm2s_cmd_tready),
        .s_axis_mm2s_cmd_tvalid_split(s_axis_mm2s_cmd_tvalid_split),
        .sig_cmd2mstr_cmd_valid(sig_cmd2mstr_cmd_valid),
        .sig_cmd_stat_rst_int_reg_n(sig_cmd_stat_rst_int_reg_n),
        .sig_init_done(\I_CMD_FIFO/sig_init_done ),
        .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid),
        .sig_stat2rsc_status_ready(sig_stat2rsc_status_ready));
  Loopback_axi_dma_1_0_axi_datamover_pcc I_MSTR_PCC
       (.E(\I_CMD_FIFO/USE_SINGLE_REG.sig_push_regfifo ),
        .\GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg (I_MSTR_PCC_n_55),
        .Q({data,I_CMD_STATUS_n_26,I_CMD_STATUS_n_27,I_CMD_STATUS_n_28,I_CMD_STATUS_n_29,I_CMD_STATUS_n_30,I_CMD_STATUS_n_31,I_CMD_STATUS_n_32,I_CMD_STATUS_n_33,I_CMD_STATUS_n_34,I_CMD_STATUS_n_35,I_CMD_STATUS_n_36,I_CMD_STATUS_n_37,I_CMD_STATUS_n_38,I_CMD_STATUS_n_39,I_CMD_STATUS_n_40,I_CMD_STATUS_n_41,sig_cmd_eof_slice,sig_cmd_type_slice,sig_cmd2mstr_command}),
        .SS(sig_mmap_rst),
        .in({sig_calc_error_reg,sig_mstr2addr_burst,sig_xfer_len_im2,sig_mstr2addr_addr,sig_mstr2sf_strt_offset,sig_xfer_addr_reg}),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .s_axis_mm2s_cmd_tready(s_axis_mm2s_cmd_tready),
        .s_axis_mm2s_cmd_tvalid_split(s_axis_mm2s_cmd_tvalid_split),
        .sig_calc_error_reg_reg_0({sig_mstr2data_cmd_cmplt,sig_mstr2data_sequential,sig_mstr2data_eof,sig_mstr2data_last_strb,sig_mstr2data_strt_strb,sig_mstr2sf_eof}),
        .sig_cmd2addr_valid_reg_0(I_ADDR_CNTL_n_2),
        .sig_cmd2data_valid_reg_0(I_RD_DATA_CNTL_n_1),
        .sig_cmd2dre_valid_reg_0(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_38 ),
        .sig_cmd2mstr_cmd_valid(sig_cmd2mstr_cmd_valid),
        .sig_cmd_stat_rst_int_reg_n(sig_cmd_stat_rst_int_reg_n),
        .sig_cmd_stat_rst_int_reg_n_reg(I_MSTR_PCC_n_54),
        .sig_inhibit_rdy_n(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_inhibit_rdy_n ),
        .sig_inhibit_rdy_n_0(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ),
        .sig_inhibit_rdy_n_1(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_inhibit_rdy_n ),
        .sig_init_done(\I_CMD_FIFO/sig_init_done ),
        .sig_init_reg(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ),
        .sig_ld_xfer_reg_tmp_reg_0(I_ADDR_CNTL_n_10),
        .sig_ld_xfer_reg_tmp_reg_1(I_RD_DATA_CNTL_n_12),
        .sig_ld_xfer_reg_tmp_reg_2(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_42 ),
        .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid),
        .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid),
        .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid));
  Loopback_axi_dma_1_0_axi_datamover_rddata_cntl I_RD_DATA_CNTL
       (.FIFO_Full_reg(I_RD_DATA_CNTL_n_1),
        .FIFO_Full_reg_0(I_RD_DATA_CNTL_n_12),
        .SS(sig_mmap_rst),
        .din({sig_data2sf_cmd_cmplt,sig_rdc2sf_wlast,sig_rdc2sf_wstrb}),
        .full(sig_data_fifo_full),
        .in({sig_calc_error_reg,sig_mstr2data_cmd_cmplt,sig_mstr2data_sequential,sig_mstr2data_eof,sig_mstr2data_last_strb,sig_mstr2data_strt_strb,sig_xfer_len_im2,sig_mstr2sf_eof}),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axi_mm2s_rlast(m_axi_mm2s_rlast),
        .m_axi_mm2s_rready(m_axi_mm2s_rready),
        .m_axi_mm2s_rresp(m_axi_mm2s_rresp),
        .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid),
        .\sig_addr_posted_cntr_reg[1]_0 (sig_addr2data_addr_posted),
        .\sig_addr_posted_cntr_reg[2]_0 (I_RD_DATA_CNTL_n_21),
        .sig_coelsc_tag_reg(sig_coelsc_tag_reg),
        .sig_data2addr_stop_req(sig_data2addr_stop_req),
        .sig_data2rsc_decerr(sig_data2rsc_decerr),
        .sig_data2rsc_valid(sig_data2rsc_valid),
        .sig_halt_reg_dly2(sig_halt_reg_dly2),
        .sig_halt_reg_dly2_reg_0(I_RD_DATA_CNTL_n_22),
        .sig_halt_reg_dly3(sig_halt_reg_dly3),
        .sig_halt_reg_dly3_reg_0(I_RD_DATA_CNTL_n_23),
        .sig_inhibit_rdy_n(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_inhibit_rdy_n ),
        .sig_init_done(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done ),
        .sig_init_done_reg(I_RESET_n_6),
        .sig_last_mmap_dbeat_reg_reg_0(I_RD_DATA_CNTL_n_3),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid),
        .sig_rd_sts_interr_reg0(sig_rd_sts_interr_reg0),
        .sig_rd_sts_slverr_reg0(sig_rd_sts_slverr_reg0),
        .sig_rd_sts_slverr_reg_reg({sig_rsc2stat_status_0[6],sig_rsc2stat_status_0[4]}),
        .sig_rsc2data_ready(sig_rsc2data_ready),
        .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid),
        .sig_rst2all_stop_request(sig_rst2all_stop_request),
        .sig_s_ready_dup_reg(\ENABLE_AXIS_SKID.I_MM2S_SKID_BUF_n_6 ),
        .sig_sstrb_stop_mask(sig_sstrb_stop_mask),
        .sig_stat2rsc_status_ready(sig_stat2rsc_status_ready),
        .sig_stream_rst_reg_n(sig_stream_rst_reg_n),
        .wr_en(sig_good_sin_strm_dbeat));
  Loopback_axi_dma_1_0_axi_datamover_rd_status_cntl I_RD_STATUS_CNTLR
       (.m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .sig_coelsc_tag_reg(sig_coelsc_tag_reg),
        .sig_data2rsc_decerr(sig_data2rsc_decerr),
        .sig_data2rsc_valid(sig_data2rsc_valid),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_rd_sts_interr_reg0(sig_rd_sts_interr_reg0),
        .sig_rd_sts_slverr_reg0(sig_rd_sts_slverr_reg0),
        .sig_rd_sts_slverr_reg_reg_0({sig_rsc2stat_status_0,sig_rsc2stat_status}),
        .sig_rsc2data_ready(sig_rsc2data_ready),
        .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid),
        .sig_stat2rsc_status_ready(sig_stat2rsc_status_ready));
  Loopback_axi_dma_1_0_axi_datamover_reset I_RESET
       (.SR(sig_cmd_stat_rst_int),
        .SS(sig_mmap_rst),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .mm2s_halt_cmplt(mm2s_halt_cmplt),
        .out(out),
        .sig_addr2rsc_calc_error(sig_addr2rsc_calc_error),
        .sig_addr_reg_empty(sig_addr_reg_empty),
        .sig_cmd_stat_rst_int_reg_n(sig_cmd_stat_rst_int_reg_n),
        .sig_data2addr_stop_req(sig_data2addr_stop_req),
        .sig_halt_cmplt_reg_0(I_RD_DATA_CNTL_n_21),
        .sig_halt_reg_dly3(sig_halt_reg_dly3),
        .sig_init_done(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_done ),
        .sig_init_done_0(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done ),
        .sig_init_reg(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ),
        .sig_init_reg2(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2 ),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mmap_rst_reg_n_reg_0(I_RESET_n_5),
        .sig_mmap_rst_reg_n_reg_1(I_RESET_n_6),
        .sig_rst2all_stop_request(sig_rst2all_stop_request),
        .sig_s_h_halt_reg_reg_0(sig_s_h_halt_reg_reg),
        .sig_stream_rst_reg_n(sig_stream_rst_reg_n),
        .sig_stream_rst_reg_n_reg_0(sig_stream_rst));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_pcc
   (sig_init_reg,
    in,
    sig_calc_error_reg_reg_0,
    sig_mstr2sf_cmd_valid,
    sig_mstr2data_cmd_valid,
    sig_mstr2addr_cmd_valid,
    sig_cmd_stat_rst_int_reg_n_reg,
    \GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg ,
    SS,
    m_axi_mm2s_aclk,
    Q,
    sig_cmd_stat_rst_int_reg_n,
    E,
    sig_cmd2mstr_cmd_valid,
    sig_init_done,
    sig_ld_xfer_reg_tmp_reg_0,
    sig_ld_xfer_reg_tmp_reg_1,
    sig_ld_xfer_reg_tmp_reg_2,
    sig_cmd2data_valid_reg_0,
    sig_inhibit_rdy_n,
    sig_cmd2dre_valid_reg_0,
    sig_inhibit_rdy_n_0,
    sig_cmd2addr_valid_reg_0,
    sig_inhibit_rdy_n_1,
    s_axis_mm2s_cmd_tvalid_split,
    s_axis_mm2s_cmd_tready);
  output sig_init_reg;
  output [37:0]in;
  output [11:0]sig_calc_error_reg_reg_0;
  output sig_mstr2sf_cmd_valid;
  output sig_mstr2data_cmd_valid;
  output sig_mstr2addr_cmd_valid;
  output sig_cmd_stat_rst_int_reg_n_reg;
  output \GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg ;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input [59:0]Q;
  input sig_cmd_stat_rst_int_reg_n;
  input [0:0]E;
  input sig_cmd2mstr_cmd_valid;
  input sig_init_done;
  input sig_ld_xfer_reg_tmp_reg_0;
  input sig_ld_xfer_reg_tmp_reg_1;
  input sig_ld_xfer_reg_tmp_reg_2;
  input sig_cmd2data_valid_reg_0;
  input sig_inhibit_rdy_n;
  input sig_cmd2dre_valid_reg_0;
  input sig_inhibit_rdy_n_0;
  input sig_cmd2addr_valid_reg_0;
  input sig_inhibit_rdy_n_1;
  input s_axis_mm2s_cmd_tvalid_split;
  input s_axis_mm2s_cmd_tready;

  wire [0:0]E;
  wire \FSM_onehot_sig_pcc_sm_state[1]_i_1_n_0 ;
  wire \FSM_onehot_sig_pcc_sm_state[2]_i_1_n_0 ;
  wire \FSM_onehot_sig_pcc_sm_state[5]_i_1_n_0 ;
  wire \FSM_onehot_sig_pcc_sm_state[6]_i_1_n_0 ;
  wire \FSM_onehot_sig_pcc_sm_state[6]_i_2_n_0 ;
  wire \FSM_onehot_sig_pcc_sm_state[7]_i_1_n_0 ;
  wire \FSM_onehot_sig_pcc_sm_state_reg_n_0_[0] ;
  wire \FSM_onehot_sig_pcc_sm_state_reg_n_0_[1] ;
  wire \FSM_onehot_sig_pcc_sm_state_reg_n_0_[5] ;
  wire \FSM_onehot_sig_pcc_sm_state_reg_n_0_[6] ;
  wire \FSM_onehot_sig_pcc_sm_state_reg_n_0_[7] ;
  wire [3:3]\GEN_4BIT_CASE.lsig_end_vect ;
  wire [0:0]\GEN_4BIT_CASE.lsig_start_vect ;
  wire \GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg ;
  wire \I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_empty_reg0 ;
  wire [59:0]Q;
  wire [0:0]SS;
  wire [37:0]in;
  wire m_axi_mm2s_aclk;
  wire [15:0]p_0_in;
  wire [15:0]p_1_in;
  wire p_1_in_0;
  wire s_axis_mm2s_cmd_tready;
  wire s_axis_mm2s_cmd_tvalid_split;
  wire sig_addr_aligned_im0;
  wire sig_addr_aligned_ireg1;
  wire \sig_addr_cntr_im0_msh[10]_i_2_n_0 ;
  wire \sig_addr_cntr_im0_msh[11]_i_2_n_0 ;
  wire \sig_addr_cntr_im0_msh[14]_i_2_n_0 ;
  wire \sig_addr_cntr_im0_msh[15]_i_1_n_0 ;
  wire \sig_addr_cntr_im0_msh[15]_i_3_n_0 ;
  wire \sig_addr_cntr_im0_msh[4]_i_2_n_0 ;
  wire \sig_addr_cntr_im0_msh[5]_i_2_n_0 ;
  wire \sig_addr_cntr_im0_msh[8]_i_2_n_0 ;
  wire \sig_addr_cntr_im0_msh[9]_i_2_n_0 ;
  wire [15:0]sig_addr_cntr_im0_msh_reg;
  wire \sig_addr_cntr_incr_ireg2[0]_i_1_n_0 ;
  wire \sig_addr_cntr_incr_ireg2[1]_i_1_n_0 ;
  wire \sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ;
  wire \sig_addr_cntr_incr_ireg2[3]_i_1_n_0 ;
  wire \sig_addr_cntr_incr_ireg2[4]_i_1_n_0 ;
  wire \sig_addr_cntr_incr_ireg2[5]_i_1_n_0 ;
  wire \sig_addr_cntr_incr_ireg2[6]_i_1_n_0 ;
  wire \sig_addr_cntr_incr_ireg2_reg_n_0_[0] ;
  wire \sig_addr_cntr_incr_ireg2_reg_n_0_[1] ;
  wire \sig_addr_cntr_incr_ireg2_reg_n_0_[2] ;
  wire \sig_addr_cntr_incr_ireg2_reg_n_0_[3] ;
  wire \sig_addr_cntr_incr_ireg2_reg_n_0_[4] ;
  wire \sig_addr_cntr_incr_ireg2_reg_n_0_[5] ;
  wire \sig_addr_cntr_incr_ireg2_reg_n_0_[6] ;
  wire \sig_addr_cntr_lsh_im0[15]_i_1_n_0 ;
  wire \sig_addr_cntr_lsh_im0_reg_n_0_[10] ;
  wire \sig_addr_cntr_lsh_im0_reg_n_0_[11] ;
  wire \sig_addr_cntr_lsh_im0_reg_n_0_[12] ;
  wire \sig_addr_cntr_lsh_im0_reg_n_0_[13] ;
  wire \sig_addr_cntr_lsh_im0_reg_n_0_[14] ;
  wire \sig_addr_cntr_lsh_im0_reg_n_0_[6] ;
  wire \sig_addr_cntr_lsh_im0_reg_n_0_[7] ;
  wire \sig_addr_cntr_lsh_im0_reg_n_0_[8] ;
  wire \sig_addr_cntr_lsh_im0_reg_n_0_[9] ;
  wire [31:0]sig_addr_cntr_lsh_kh;
  wire [5:0]sig_adjusted_addr_incr_im1;
  wire \sig_adjusted_addr_incr_ireg2[1]_i_2_n_0 ;
  wire \sig_adjusted_addr_incr_ireg2[3]_i_2_n_0 ;
  wire \sig_adjusted_addr_incr_ireg2[5]_i_2_n_0 ;
  wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ;
  wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ;
  wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ;
  wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ;
  wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ;
  wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ;
  wire sig_brst_cnt_eq_one_im0;
  wire sig_brst_cnt_eq_one_ireg1;
  wire sig_brst_cnt_eq_zero_im0;
  wire sig_brst_cnt_eq_zero_ireg1;
  wire sig_brst_cnt_eq_zero_ireg1_i_2_n_0;
  wire sig_brst_cnt_eq_zero_ireg1_i_3_n_0;
  wire sig_brst_cnt_eq_zero_ireg1_i_4_n_0;
  wire sig_brst_cnt_eq_zero_ireg1_i_5_n_0;
  wire \sig_btt_cntr_im0[15]_i_2_n_0 ;
  wire \sig_btt_cntr_im0[15]_i_3_n_0 ;
  wire \sig_btt_cntr_im0[15]_i_4_n_0 ;
  wire \sig_btt_cntr_im0[15]_i_5_n_0 ;
  wire \sig_btt_cntr_im0[15]_i_6_n_0 ;
  wire \sig_btt_cntr_im0[15]_i_7_n_0 ;
  wire \sig_btt_cntr_im0[15]_i_8_n_0 ;
  wire \sig_btt_cntr_im0[15]_i_9_n_0 ;
  wire \sig_btt_cntr_im0[23]_i_2_n_0 ;
  wire \sig_btt_cntr_im0[23]_i_3_n_0 ;
  wire \sig_btt_cntr_im0[23]_i_4_n_0 ;
  wire \sig_btt_cntr_im0[23]_i_5_n_0 ;
  wire \sig_btt_cntr_im0[23]_i_6_n_0 ;
  wire \sig_btt_cntr_im0[23]_i_7_n_0 ;
  wire \sig_btt_cntr_im0[23]_i_8_n_0 ;
  wire \sig_btt_cntr_im0[23]_i_9_n_0 ;
  wire \sig_btt_cntr_im0[25]_i_2_n_0 ;
  wire \sig_btt_cntr_im0[25]_i_3_n_0 ;
  wire \sig_btt_cntr_im0[25]_i_4_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_10_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_11_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_12_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_13_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_14_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_15_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_16_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_2_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_3_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_4_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_5_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_6_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_7_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_8_n_0 ;
  wire \sig_btt_cntr_im0[7]_i_9_n_0 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_0 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_1 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_10 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_11 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_12 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_13 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_14 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_15 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_2 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_3 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_4 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_5 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_6 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_7 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_8 ;
  wire \sig_btt_cntr_im0_reg[15]_i_1_n_9 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_0 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_1 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_10 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_11 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_12 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_13 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_14 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_15 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_2 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_3 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_4 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_5 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_6 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_7 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_8 ;
  wire \sig_btt_cntr_im0_reg[23]_i_1_n_9 ;
  wire \sig_btt_cntr_im0_reg[25]_i_1_n_14 ;
  wire \sig_btt_cntr_im0_reg[25]_i_1_n_15 ;
  wire \sig_btt_cntr_im0_reg[25]_i_1_n_7 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_0 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_1 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_10 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_11 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_12 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_13 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_14 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_15 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_2 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_3 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_4 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_5 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_6 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_7 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_8 ;
  wire \sig_btt_cntr_im0_reg[7]_i_1_n_9 ;
  wire \sig_btt_cntr_im0_reg_n_0_[0] ;
  wire \sig_btt_cntr_im0_reg_n_0_[10] ;
  wire \sig_btt_cntr_im0_reg_n_0_[11] ;
  wire \sig_btt_cntr_im0_reg_n_0_[12] ;
  wire \sig_btt_cntr_im0_reg_n_0_[13] ;
  wire \sig_btt_cntr_im0_reg_n_0_[14] ;
  wire \sig_btt_cntr_im0_reg_n_0_[15] ;
  wire \sig_btt_cntr_im0_reg_n_0_[16] ;
  wire \sig_btt_cntr_im0_reg_n_0_[17] ;
  wire \sig_btt_cntr_im0_reg_n_0_[18] ;
  wire \sig_btt_cntr_im0_reg_n_0_[19] ;
  wire \sig_btt_cntr_im0_reg_n_0_[1] ;
  wire \sig_btt_cntr_im0_reg_n_0_[20] ;
  wire \sig_btt_cntr_im0_reg_n_0_[21] ;
  wire \sig_btt_cntr_im0_reg_n_0_[22] ;
  wire \sig_btt_cntr_im0_reg_n_0_[23] ;
  wire \sig_btt_cntr_im0_reg_n_0_[24] ;
  wire \sig_btt_cntr_im0_reg_n_0_[25] ;
  wire \sig_btt_cntr_im0_reg_n_0_[2] ;
  wire \sig_btt_cntr_im0_reg_n_0_[3] ;
  wire \sig_btt_cntr_im0_reg_n_0_[4] ;
  wire \sig_btt_cntr_im0_reg_n_0_[5] ;
  wire \sig_btt_cntr_im0_reg_n_0_[6] ;
  wire \sig_btt_cntr_im0_reg_n_0_[7] ;
  wire \sig_btt_cntr_im0_reg_n_0_[8] ;
  wire \sig_btt_cntr_im0_reg_n_0_[9] ;
  wire sig_btt_eq_b2mbaa_im0;
  wire sig_btt_eq_b2mbaa_ireg1;
  wire sig_btt_eq_b2mbaa_ireg1_i_2_n_0;
  wire sig_btt_eq_b2mbaa_ireg1_i_3_n_0;
  wire sig_btt_eq_b2mbaa_ireg1_i_4_n_0;
  wire sig_btt_is_zero;
  wire sig_btt_lt_b2mbaa_im0;
  wire sig_btt_lt_b2mbaa_im01;
  wire sig_btt_lt_b2mbaa_im01_carry_i_1_n_0;
  wire sig_btt_lt_b2mbaa_im01_carry_i_2_n_0;
  wire sig_btt_lt_b2mbaa_im01_carry_i_3_n_0;
  wire sig_btt_lt_b2mbaa_im01_carry_i_4_n_0;
  wire sig_btt_lt_b2mbaa_im01_carry_i_5_n_0;
  wire sig_btt_lt_b2mbaa_im01_carry_i_6_n_0;
  wire sig_btt_lt_b2mbaa_im01_carry_i_7_n_0;
  wire sig_btt_lt_b2mbaa_im01_carry_i_8_n_0;
  wire sig_btt_lt_b2mbaa_im01_carry_n_5;
  wire sig_btt_lt_b2mbaa_im01_carry_n_6;
  wire sig_btt_lt_b2mbaa_im01_carry_n_7;
  wire sig_btt_lt_b2mbaa_ireg1;
  wire [5:1]sig_bytes_to_mbaa_im0;
  wire [5:0]sig_bytes_to_mbaa_ireg1;
  wire sig_calc_error_pushed;
  wire sig_calc_error_pushed_i_1_n_0;
  wire sig_calc_error_reg_i_2_n_0;
  wire sig_calc_error_reg_i_3_n_0;
  wire sig_calc_error_reg_i_4_n_0;
  wire sig_calc_error_reg_i_5_n_0;
  wire [11:0]sig_calc_error_reg_reg_0;
  wire sig_cmd2addr_valid_i_1_n_0;
  wire sig_cmd2addr_valid_reg_0;
  wire sig_cmd2data_valid_i_1_n_0;
  wire sig_cmd2data_valid_reg_0;
  wire sig_cmd2dre_valid_i_1_n_0;
  wire sig_cmd2dre_valid_reg_0;
  wire sig_cmd2mstr_cmd_valid;
  wire sig_cmd_stat_rst_int_reg_n;
  wire sig_cmd_stat_rst_int_reg_n_reg;
  wire sig_first_xfer_im0;
  wire sig_first_xfer_im0_i_1_n_0;
  wire sig_inhibit_rdy_n;
  wire sig_inhibit_rdy_n_0;
  wire sig_inhibit_rdy_n_1;
  wire sig_init_done;
  wire sig_init_reg;
  wire sig_input_cache_type_reg0;
  wire sig_input_reg_empty;
  wire [1:1]sig_last_addr_offset_im2__0;
  wire sig_ld_xfer_reg;
  wire sig_ld_xfer_reg_i_1_n_0;
  wire sig_ld_xfer_reg_tmp;
  wire sig_ld_xfer_reg_tmp_i_1_n_0;
  wire sig_ld_xfer_reg_tmp_reg_0;
  wire sig_ld_xfer_reg_tmp_reg_1;
  wire sig_ld_xfer_reg_tmp_reg_2;
  wire [5:0]sig_mbaa_addr_cntr_slice_im0;
  wire sig_mstr2addr_cmd_valid;
  wire sig_mstr2data_cmd_valid;
  wire sig_mstr2sf_cmd_valid;
  wire sig_no_btt_residue_im0;
  wire sig_no_btt_residue_ireg1;
  wire sig_parent_done;
  wire sig_parent_done_i_1_n_0;
  wire [15:0]sig_predict_addr_lsh_im2;
  wire [15:15]sig_predict_addr_lsh_ireg3;
  wire \sig_predict_addr_lsh_ireg3[7]_i_2_n_0 ;
  wire \sig_predict_addr_lsh_ireg3[7]_i_3_n_0 ;
  wire \sig_predict_addr_lsh_ireg3[7]_i_4_n_0 ;
  wire \sig_predict_addr_lsh_ireg3[7]_i_5_n_0 ;
  wire \sig_predict_addr_lsh_ireg3[7]_i_6_n_0 ;
  wire \sig_predict_addr_lsh_ireg3[7]_i_7_n_0 ;
  wire \sig_predict_addr_lsh_ireg3[7]_i_8_n_0 ;
  wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_1 ;
  wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_2 ;
  wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_3 ;
  wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_4 ;
  wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_5 ;
  wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_6 ;
  wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_7 ;
  wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0 ;
  wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_1 ;
  wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_2 ;
  wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_3 ;
  wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_4 ;
  wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_5 ;
  wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_6 ;
  wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_7 ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[0] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[10] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[11] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[12] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[13] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[14] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[1] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[2] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[3] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[4] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[5] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[6] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[7] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[8] ;
  wire \sig_predict_addr_lsh_ireg3_reg_n_0_[9] ;
  wire sig_push_input_reg11_out;
  wire sig_sm_halt_ns;
  wire sig_sm_halt_reg;
  wire sig_sm_ld_calc2_reg;
  wire sig_sm_ld_calc2_reg_ns;
  wire sig_sm_ld_calc3_reg;
  wire sig_sm_pop_input_reg;
  wire sig_sm_pop_input_reg_ns;
  wire [1:0]sig_strbgen_addr_ireg2;
  wire [2:2]sig_strbgen_bytes_ireg2;
  wire \sig_strbgen_bytes_ireg2[1]_i_1_n_0 ;
  wire \sig_strbgen_bytes_ireg2[2]_i_1_n_0 ;
  wire \sig_strbgen_bytes_ireg2_reg_n_0_[0] ;
  wire \sig_strbgen_bytes_ireg2_reg_n_0_[1] ;
  wire \sig_strbgen_bytes_ireg2_reg_n_0_[2] ;
  wire [3:0]sig_xfer_end_strb_ireg3;
  wire \sig_xfer_end_strb_ireg3[1]_i_1_n_0 ;
  wire \sig_xfer_end_strb_ireg3[3]_i_1_n_0 ;
  wire sig_xfer_len_eq_0_im2;
  wire sig_xfer_len_eq_0_ireg3;
  wire sig_xfer_reg_empty;
  wire sig_xfer_reg_empty_i_1_n_0;
  wire [2:2]sig_xfer_strt_strb_im2;
  wire [3:0]sig_xfer_strt_strb_ireg3;
  wire \sig_xfer_strt_strb_ireg3[1]_i_1_n_0 ;
  wire [7:1]\NLW_sig_btt_cntr_im0_reg[25]_i_1_CO_UNCONNECTED ;
  wire [7:2]\NLW_sig_btt_cntr_im0_reg[25]_i_1_O_UNCONNECTED ;
  wire [7:4]NLW_sig_btt_lt_b2mbaa_im01_carry_CO_UNCONNECTED;
  wire [7:0]NLW_sig_btt_lt_b2mbaa_im01_carry_O_UNCONNECTED;
  wire [7:7]\NLW_sig_predict_addr_lsh_ireg3_reg[15]_i_1_CO_UNCONNECTED ;

  LUT6 #(
    .INIT(64'hFF40FFFFFF40FF40)) 
    \FSM_onehot_sig_pcc_sm_state[1]_i_1 
       (.I0(sig_calc_error_pushed),
        .I1(sig_parent_done),
        .I2(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[6] ),
        .I3(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[0] ),
        .I4(sig_push_input_reg11_out),
        .I5(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[1] ),
        .O(\FSM_onehot_sig_pcc_sm_state[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT5 #(
    .INIT(32'hFF020202)) 
    \FSM_onehot_sig_pcc_sm_state[2]_i_1 
       (.I0(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[6] ),
        .I1(sig_parent_done),
        .I2(sig_calc_error_pushed),
        .I3(sig_push_input_reg11_out),
        .I4(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[1] ),
        .O(\FSM_onehot_sig_pcc_sm_state[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT3 #(
    .INIT(8'hF4)) 
    \FSM_onehot_sig_pcc_sm_state[5]_i_1 
       (.I0(\FSM_onehot_sig_pcc_sm_state[6]_i_2_n_0 ),
        .I1(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[5] ),
        .I2(sig_sm_ld_calc3_reg),
        .O(\FSM_onehot_sig_pcc_sm_state[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_sig_pcc_sm_state[6]_i_1 
       (.I0(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[5] ),
        .I1(\FSM_onehot_sig_pcc_sm_state[6]_i_2_n_0 ),
        .O(\FSM_onehot_sig_pcc_sm_state[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0777077700000272)) 
    \FSM_onehot_sig_pcc_sm_state[6]_i_2 
       (.I0(sig_mstr2addr_cmd_valid),
        .I1(sig_ld_xfer_reg_tmp_reg_0),
        .I2(sig_mstr2data_cmd_valid),
        .I3(sig_ld_xfer_reg_tmp_reg_1),
        .I4(sig_mstr2sf_cmd_valid),
        .I5(sig_ld_xfer_reg_tmp_reg_2),
        .O(\FSM_onehot_sig_pcc_sm_state[6]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \FSM_onehot_sig_pcc_sm_state[7]_i_1 
       (.I0(sig_calc_error_pushed),
        .I1(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[6] ),
        .I2(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[7] ),
        .O(\FSM_onehot_sig_pcc_sm_state[7]_i_1_n_0 ));
  (* FSM_ENCODED_STATES = "init:00000001,calc_2:00001000,calc_3:00010000,wait_on_xfer_push:00100000,chk_if_done:01000000,error_trap:10000000,calc_1:00000100,wait_for_cmd:00000010" *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_sig_pcc_sm_state_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[0] ),
        .S(sig_init_reg));
  (* FSM_ENCODED_STATES = "init:00000001,calc_2:00001000,calc_3:00010000,wait_on_xfer_push:00100000,chk_if_done:01000000,error_trap:10000000,calc_1:00000100,wait_for_cmd:00000010" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_sig_pcc_sm_state_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\FSM_onehot_sig_pcc_sm_state[1]_i_1_n_0 ),
        .Q(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[1] ),
        .R(sig_init_reg));
  (* FSM_ENCODED_STATES = "init:00000001,calc_2:00001000,calc_3:00010000,wait_on_xfer_push:00100000,chk_if_done:01000000,error_trap:10000000,calc_1:00000100,wait_for_cmd:00000010" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_sig_pcc_sm_state_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\FSM_onehot_sig_pcc_sm_state[2]_i_1_n_0 ),
        .Q(sig_sm_ld_calc2_reg_ns),
        .R(sig_init_reg));
  (* FSM_ENCODED_STATES = "init:00000001,calc_2:00001000,calc_3:00010000,wait_on_xfer_push:00100000,chk_if_done:01000000,error_trap:10000000,calc_1:00000100,wait_for_cmd:00000010" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_sig_pcc_sm_state_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\FSM_onehot_sig_pcc_sm_state[5]_i_1_n_0 ),
        .Q(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[5] ),
        .R(sig_init_reg));
  (* FSM_ENCODED_STATES = "init:00000001,calc_2:00001000,calc_3:00010000,wait_on_xfer_push:00100000,chk_if_done:01000000,error_trap:10000000,calc_1:00000100,wait_for_cmd:00000010" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_sig_pcc_sm_state_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\FSM_onehot_sig_pcc_sm_state[6]_i_1_n_0 ),
        .Q(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[6] ),
        .R(sig_init_reg));
  (* FSM_ENCODED_STATES = "init:00000001,calc_2:00001000,calc_3:00010000,wait_on_xfer_push:00100000,chk_if_done:01000000,error_trap:10000000,calc_1:00000100,wait_for_cmd:00000010" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_sig_pcc_sm_state_reg[7] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\FSM_onehot_sig_pcc_sm_state[7]_i_1_n_0 ),
        .Q(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[7] ),
        .R(sig_init_reg));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT5 #(
    .INIT(32'hCFFFCAAA)) 
    \INFERRED_GEN.data_reg[3][10]_srl4_i_1 
       (.I0(sig_calc_error_reg_reg_0[10]),
        .I1(sig_xfer_strt_strb_ireg3[0]),
        .I2(sig_first_xfer_im0),
        .I3(sig_xfer_len_eq_0_ireg3),
        .I4(sig_xfer_end_strb_ireg3[0]),
        .O(sig_calc_error_reg_reg_0[5]));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \INFERRED_GEN.data_reg[3][11]_srl4_i_1 
       (.I0(sig_xfer_strt_strb_ireg3[3]),
        .I1(sig_first_xfer_im0),
        .O(sig_calc_error_reg_reg_0[4]));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \INFERRED_GEN.data_reg[3][12]_srl4_i_1 
       (.I0(sig_xfer_strt_strb_ireg3[2]),
        .I1(sig_first_xfer_im0),
        .O(sig_calc_error_reg_reg_0[3]));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \INFERRED_GEN.data_reg[3][13]_srl4_i_1 
       (.I0(sig_xfer_strt_strb_ireg3[1]),
        .I1(sig_first_xfer_im0),
        .O(sig_calc_error_reg_reg_0[2]));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \INFERRED_GEN.data_reg[3][14]_srl4_i_1 
       (.I0(sig_xfer_strt_strb_ireg3[0]),
        .I1(sig_first_xfer_im0),
        .O(sig_calc_error_reg_reg_0[1]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \INFERRED_GEN.data_reg[3][19]_srl4_i_1 
       (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ),
        .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ),
        .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ),
        .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ),
        .I4(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ),
        .I5(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ),
        .O(in[35]));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \INFERRED_GEN.data_reg[3][20]_srl4_i_1 
       (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ),
        .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ),
        .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ),
        .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ),
        .I4(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ),
        .O(in[34]));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \INFERRED_GEN.data_reg[3][21]_srl4_i_1 
       (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ),
        .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ),
        .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ),
        .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ),
        .O(in[33]));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \INFERRED_GEN.data_reg[3][22]_srl4_i_1 
       (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ),
        .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ),
        .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ),
        .O(in[32]));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][23]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[15]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[31]),
        .O(in[31]));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][24]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[14]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[30]),
        .O(in[30]));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][25]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[13]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[29]),
        .O(in[29]));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][26]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[12]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[28]),
        .O(in[28]));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][27]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[11]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[27]),
        .O(in[27]));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][28]_srl4_i_1__0 
       (.I0(sig_addr_cntr_im0_msh_reg[10]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[26]),
        .O(in[26]));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][29]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[9]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[25]),
        .O(in[25]));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][30]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[8]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[24]),
        .O(in[24]));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][31]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[7]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[23]),
        .O(in[23]));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][32]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[6]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[22]),
        .O(in[22]));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][33]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[5]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[21]),
        .O(in[21]));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][34]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[4]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[20]),
        .O(in[20]));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][35]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[3]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[19]),
        .O(in[19]));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][36]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[2]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[18]),
        .O(in[18]));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][37]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[1]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[17]),
        .O(in[17]));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][38]_srl4_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[0]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[16]),
        .O(in[16]));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][39]_srl4_i_1 
       (.I0(p_1_in_0),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[15]),
        .O(in[15]));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \INFERRED_GEN.data_reg[3][3]_srl4_i_1 
       (.I0(in[37]),
        .I1(sig_calc_error_reg_reg_0[10]),
        .O(sig_calc_error_reg_reg_0[11]));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][40]_srl4_i_1 
       (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[14] ),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[14]),
        .O(in[14]));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][41]_srl4_i_1 
       (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[13] ),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[13]),
        .O(in[13]));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][42]_srl4_i_1 
       (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[12] ),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[12]),
        .O(in[12]));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][43]_srl4_i_1 
       (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[11] ),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[11]),
        .O(in[11]));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][44]_srl4_i_1 
       (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[10] ),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[10]),
        .O(in[10]));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][45]_srl4_i_1 
       (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[9] ),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[9]),
        .O(in[9]));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][46]_srl4_i_1 
       (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[8] ),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[8]),
        .O(in[8]));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][47]_srl4_i_1 
       (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[7]),
        .O(in[7]));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][48]_srl4_i_1 
       (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[6]),
        .O(in[6]));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][49]_srl4_i_1 
       (.I0(sig_mbaa_addr_cntr_slice_im0[5]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[5]),
        .O(in[5]));
  LUT6 #(
    .INIT(64'h001FFF1FFF1FFF1F)) 
    \INFERRED_GEN.data_reg[3][4]_srl4_i_1 
       (.I0(sig_btt_eq_b2mbaa_ireg1),
        .I1(sig_btt_lt_b2mbaa_ireg1),
        .I2(sig_brst_cnt_eq_zero_ireg1),
        .I3(sig_no_btt_residue_ireg1),
        .I4(sig_brst_cnt_eq_one_ireg1),
        .I5(sig_addr_aligned_ireg1),
        .O(sig_calc_error_reg_reg_0[10]));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][50]_srl4_i_1 
       (.I0(sig_mbaa_addr_cntr_slice_im0[4]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[4]),
        .O(in[4]));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][51]_srl4_i_1 
       (.I0(sig_mbaa_addr_cntr_slice_im0[3]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[3]),
        .O(in[3]));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][52]_srl4_i_1 
       (.I0(sig_mbaa_addr_cntr_slice_im0[2]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[2]),
        .O(in[2]));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][53]_srl4_i_1 
       (.I0(sig_mbaa_addr_cntr_slice_im0[1]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[1]),
        .O(in[1]));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \INFERRED_GEN.data_reg[3][54]_srl4_i_2 
       (.I0(sig_mbaa_addr_cntr_slice_im0[0]),
        .I1(in[36]),
        .I2(sig_addr_cntr_lsh_kh[0]),
        .O(in[0]));
  LUT2 #(
    .INIT(4'h2)) 
    \INFERRED_GEN.data_reg[3][5]_srl4_i_1 
       (.I0(sig_calc_error_reg_reg_0[0]),
        .I1(sig_calc_error_reg_reg_0[10]),
        .O(sig_calc_error_reg_reg_0[9]));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT5 #(
    .INIT(32'hCCFAFAFA)) 
    \INFERRED_GEN.data_reg[3][7]_srl4_i_1 
       (.I0(sig_calc_error_reg_reg_0[10]),
        .I1(sig_xfer_strt_strb_ireg3[3]),
        .I2(sig_xfer_end_strb_ireg3[3]),
        .I3(sig_first_xfer_im0),
        .I4(sig_xfer_len_eq_0_ireg3),
        .O(sig_calc_error_reg_reg_0[8]));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT5 #(
    .INIT(32'hCFFFCAAA)) 
    \INFERRED_GEN.data_reg[3][8]_srl4_i_1 
       (.I0(sig_calc_error_reg_reg_0[10]),
        .I1(sig_xfer_strt_strb_ireg3[2]),
        .I2(sig_first_xfer_im0),
        .I3(sig_xfer_len_eq_0_ireg3),
        .I4(sig_xfer_end_strb_ireg3[2]),
        .O(sig_calc_error_reg_reg_0[7]));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT5 #(
    .INIT(32'hCFFFCAAA)) 
    \INFERRED_GEN.data_reg[3][9]_srl4_i_1 
       (.I0(sig_calc_error_reg_reg_0[10]),
        .I1(sig_xfer_strt_strb_ireg3[1]),
        .I2(sig_first_xfer_im0),
        .I3(sig_xfer_len_eq_0_ireg3),
        .I4(sig_xfer_end_strb_ireg3[1]),
        .O(sig_calc_error_reg_reg_0[6]));
  Loopback_axi_dma_1_0_axi_datamover_strb_gen2 I_STRT_STRB_GEN
       (.D({\GEN_4BIT_CASE.lsig_end_vect ,\GEN_4BIT_CASE.lsig_start_vect }),
        .Q(sig_strbgen_addr_ireg2),
        .\sig_xfer_strt_strb_ireg3_reg[3] ({\sig_strbgen_bytes_ireg2_reg_n_0_[1] ,\sig_strbgen_bytes_ireg2_reg_n_0_[0] }),
        .\sig_xfer_strt_strb_ireg3_reg[3]_0 (\sig_strbgen_bytes_ireg2_reg_n_0_[2] ));
  LUT3 #(
    .INIT(8'hBA)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__3 
       (.I0(\I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_empty_reg0 ),
        .I1(s_axis_mm2s_cmd_tvalid_split),
        .I2(s_axis_mm2s_cmd_tready),
        .O(\GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg ));
  LUT5 #(
    .INIT(32'hAABAAAAA)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_i_2 
       (.I0(sig_init_done),
        .I1(sig_calc_error_pushed),
        .I2(sig_cmd2mstr_cmd_valid),
        .I3(sig_sm_halt_reg),
        .I4(sig_input_reg_empty),
        .O(\I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_empty_reg0 ));
  LUT6 #(
    .INIT(64'hAA88A088AA88AA88)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_i_1__4 
       (.I0(sig_cmd_stat_rst_int_reg_n),
        .I1(E),
        .I2(sig_calc_error_pushed),
        .I3(sig_cmd2mstr_cmd_valid),
        .I4(sig_sm_halt_reg),
        .I5(sig_input_reg_empty),
        .O(sig_cmd_stat_rst_int_reg_n_reg));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    sig_addr_aligned_ireg1_i_1
       (.I0(sig_mbaa_addr_cntr_slice_im0[4]),
        .I1(sig_mbaa_addr_cntr_slice_im0[2]),
        .I2(sig_mbaa_addr_cntr_slice_im0[0]),
        .I3(sig_mbaa_addr_cntr_slice_im0[1]),
        .I4(sig_mbaa_addr_cntr_slice_im0[3]),
        .I5(sig_mbaa_addr_cntr_slice_im0[5]),
        .O(sig_addr_aligned_im0));
  FDRE #(
    .INIT(1'b0)) 
    sig_addr_aligned_ireg1_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_addr_aligned_im0),
        .Q(sig_addr_aligned_ireg1),
        .R(sig_init_reg));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT3 #(
    .INIT(8'h8B)) 
    \sig_addr_cntr_im0_msh[0]_i_1 
       (.I0(Q[44]),
        .I1(sig_push_input_reg11_out),
        .I2(sig_addr_cntr_im0_msh_reg[0]),
        .O(p_0_in[0]));
  LUT4 #(
    .INIT(16'hAAC3)) 
    \sig_addr_cntr_im0_msh[10]_i_1 
       (.I0(Q[54]),
        .I1(sig_addr_cntr_im0_msh_reg[10]),
        .I2(\sig_addr_cntr_im0_msh[10]_i_2_n_0 ),
        .I3(sig_push_input_reg11_out),
        .O(p_0_in[10]));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \sig_addr_cntr_im0_msh[10]_i_2 
       (.I0(sig_addr_cntr_im0_msh_reg[8]),
        .I1(sig_addr_cntr_im0_msh_reg[6]),
        .I2(\sig_addr_cntr_im0_msh[8]_i_2_n_0 ),
        .I3(sig_addr_cntr_im0_msh_reg[7]),
        .I4(sig_addr_cntr_im0_msh_reg[9]),
        .O(\sig_addr_cntr_im0_msh[10]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hAAC3)) 
    \sig_addr_cntr_im0_msh[11]_i_1 
       (.I0(Q[55]),
        .I1(sig_addr_cntr_im0_msh_reg[11]),
        .I2(\sig_addr_cntr_im0_msh[11]_i_2_n_0 ),
        .I3(sig_push_input_reg11_out),
        .O(p_0_in[11]));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \sig_addr_cntr_im0_msh[11]_i_2 
       (.I0(sig_addr_cntr_im0_msh_reg[9]),
        .I1(sig_addr_cntr_im0_msh_reg[7]),
        .I2(\sig_addr_cntr_im0_msh[8]_i_2_n_0 ),
        .I3(sig_addr_cntr_im0_msh_reg[6]),
        .I4(sig_addr_cntr_im0_msh_reg[8]),
        .I5(sig_addr_cntr_im0_msh_reg[10]),
        .O(\sig_addr_cntr_im0_msh[11]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF606)) 
    \sig_addr_cntr_im0_msh[12]_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[12]),
        .I1(\sig_addr_cntr_im0_msh[14]_i_2_n_0 ),
        .I2(sig_push_input_reg11_out),
        .I3(Q[56]),
        .O(p_0_in[12]));
  LUT5 #(
    .INIT(32'hFF6A006A)) 
    \sig_addr_cntr_im0_msh[13]_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[13]),
        .I1(\sig_addr_cntr_im0_msh[14]_i_2_n_0 ),
        .I2(sig_addr_cntr_im0_msh_reg[12]),
        .I3(sig_push_input_reg11_out),
        .I4(Q[57]),
        .O(p_0_in[13]));
  LUT6 #(
    .INIT(64'hFFFF6AAA00006AAA)) 
    \sig_addr_cntr_im0_msh[14]_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[14]),
        .I1(sig_addr_cntr_im0_msh_reg[12]),
        .I2(\sig_addr_cntr_im0_msh[14]_i_2_n_0 ),
        .I3(sig_addr_cntr_im0_msh_reg[13]),
        .I4(sig_push_input_reg11_out),
        .I5(Q[58]),
        .O(p_0_in[14]));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \sig_addr_cntr_im0_msh[14]_i_2 
       (.I0(sig_addr_cntr_im0_msh_reg[11]),
        .I1(\sig_addr_cntr_im0_msh[11]_i_2_n_0 ),
        .O(\sig_addr_cntr_im0_msh[14]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFF08)) 
    \sig_addr_cntr_im0_msh[15]_i_1 
       (.I0(\FSM_onehot_sig_pcc_sm_state[6]_i_2_n_0 ),
        .I1(p_1_in_0),
        .I2(sig_predict_addr_lsh_ireg3),
        .I3(sig_push_input_reg11_out),
        .O(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF6A006A)) 
    \sig_addr_cntr_im0_msh[15]_i_2 
       (.I0(sig_addr_cntr_im0_msh_reg[15]),
        .I1(\sig_addr_cntr_im0_msh[15]_i_3_n_0 ),
        .I2(sig_addr_cntr_im0_msh_reg[14]),
        .I3(sig_push_input_reg11_out),
        .I4(Q[59]),
        .O(p_0_in[15]));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    \sig_addr_cntr_im0_msh[15]_i_3 
       (.I0(sig_addr_cntr_im0_msh_reg[13]),
        .I1(sig_addr_cntr_im0_msh_reg[11]),
        .I2(\sig_addr_cntr_im0_msh[11]_i_2_n_0 ),
        .I3(sig_addr_cntr_im0_msh_reg[12]),
        .O(\sig_addr_cntr_im0_msh[15]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT4 #(
    .INIT(16'hF606)) 
    \sig_addr_cntr_im0_msh[1]_i_1 
       (.I0(sig_addr_cntr_im0_msh_reg[1]),
        .I1(sig_addr_cntr_im0_msh_reg[0]),
        .I2(sig_push_input_reg11_out),
        .I3(Q[45]),
        .O(p_0_in[1]));
  LUT5 #(
    .INIT(32'h8BB8B8B8)) 
    \sig_addr_cntr_im0_msh[2]_i_1 
       (.I0(Q[46]),
        .I1(sig_push_input_reg11_out),
        .I2(sig_addr_cntr_im0_msh_reg[2]),
        .I3(sig_addr_cntr_im0_msh_reg[0]),
        .I4(sig_addr_cntr_im0_msh_reg[1]),
        .O(p_0_in[2]));
  LUT6 #(
    .INIT(64'h8BB8B8B8B8B8B8B8)) 
    \sig_addr_cntr_im0_msh[3]_i_1 
       (.I0(Q[47]),
        .I1(sig_push_input_reg11_out),
        .I2(sig_addr_cntr_im0_msh_reg[3]),
        .I3(sig_addr_cntr_im0_msh_reg[1]),
        .I4(sig_addr_cntr_im0_msh_reg[0]),
        .I5(sig_addr_cntr_im0_msh_reg[2]),
        .O(p_0_in[3]));
  LUT4 #(
    .INIT(16'hAAC3)) 
    \sig_addr_cntr_im0_msh[4]_i_1 
       (.I0(Q[48]),
        .I1(sig_addr_cntr_im0_msh_reg[4]),
        .I2(\sig_addr_cntr_im0_msh[4]_i_2_n_0 ),
        .I3(sig_push_input_reg11_out),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \sig_addr_cntr_im0_msh[4]_i_2 
       (.I0(sig_addr_cntr_im0_msh_reg[2]),
        .I1(sig_addr_cntr_im0_msh_reg[0]),
        .I2(sig_addr_cntr_im0_msh_reg[1]),
        .I3(sig_addr_cntr_im0_msh_reg[3]),
        .O(\sig_addr_cntr_im0_msh[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hAAC3)) 
    \sig_addr_cntr_im0_msh[5]_i_1 
       (.I0(Q[49]),
        .I1(sig_addr_cntr_im0_msh_reg[5]),
        .I2(\sig_addr_cntr_im0_msh[5]_i_2_n_0 ),
        .I3(sig_push_input_reg11_out),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    \sig_addr_cntr_im0_msh[5]_i_2 
       (.I0(sig_addr_cntr_im0_msh_reg[3]),
        .I1(sig_addr_cntr_im0_msh_reg[1]),
        .I2(sig_addr_cntr_im0_msh_reg[0]),
        .I3(sig_addr_cntr_im0_msh_reg[2]),
        .I4(sig_addr_cntr_im0_msh_reg[4]),
        .O(\sig_addr_cntr_im0_msh[5]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hAAC3)) 
    \sig_addr_cntr_im0_msh[6]_i_1 
       (.I0(Q[50]),
        .I1(sig_addr_cntr_im0_msh_reg[6]),
        .I2(\sig_addr_cntr_im0_msh[8]_i_2_n_0 ),
        .I3(sig_push_input_reg11_out),
        .O(p_0_in[6]));
  LUT5 #(
    .INIT(32'hAAAACC3C)) 
    \sig_addr_cntr_im0_msh[7]_i_1 
       (.I0(Q[51]),
        .I1(sig_addr_cntr_im0_msh_reg[7]),
        .I2(sig_addr_cntr_im0_msh_reg[6]),
        .I3(\sig_addr_cntr_im0_msh[8]_i_2_n_0 ),
        .I4(sig_push_input_reg11_out),
        .O(p_0_in[7]));
  LUT6 #(
    .INIT(64'hAAAAAAAACC3CCCCC)) 
    \sig_addr_cntr_im0_msh[8]_i_1 
       (.I0(Q[52]),
        .I1(sig_addr_cntr_im0_msh_reg[8]),
        .I2(sig_addr_cntr_im0_msh_reg[7]),
        .I3(\sig_addr_cntr_im0_msh[8]_i_2_n_0 ),
        .I4(sig_addr_cntr_im0_msh_reg[6]),
        .I5(sig_push_input_reg11_out),
        .O(p_0_in[8]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \sig_addr_cntr_im0_msh[8]_i_2 
       (.I0(sig_addr_cntr_im0_msh_reg[4]),
        .I1(sig_addr_cntr_im0_msh_reg[2]),
        .I2(sig_addr_cntr_im0_msh_reg[0]),
        .I3(sig_addr_cntr_im0_msh_reg[1]),
        .I4(sig_addr_cntr_im0_msh_reg[3]),
        .I5(sig_addr_cntr_im0_msh_reg[5]),
        .O(\sig_addr_cntr_im0_msh[8]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hAAC3)) 
    \sig_addr_cntr_im0_msh[9]_i_1 
       (.I0(Q[53]),
        .I1(sig_addr_cntr_im0_msh_reg[9]),
        .I2(\sig_addr_cntr_im0_msh[9]_i_2_n_0 ),
        .I3(sig_push_input_reg11_out),
        .O(p_0_in[9]));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT4 #(
    .INIT(16'hDFFF)) 
    \sig_addr_cntr_im0_msh[9]_i_2 
       (.I0(sig_addr_cntr_im0_msh_reg[7]),
        .I1(\sig_addr_cntr_im0_msh[8]_i_2_n_0 ),
        .I2(sig_addr_cntr_im0_msh_reg[6]),
        .I3(sig_addr_cntr_im0_msh_reg[8]),
        .O(\sig_addr_cntr_im0_msh[9]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[0]),
        .Q(sig_addr_cntr_im0_msh_reg[0]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[10] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[10]),
        .Q(sig_addr_cntr_im0_msh_reg[10]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[11] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[11]),
        .Q(sig_addr_cntr_im0_msh_reg[11]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[12] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[12]),
        .Q(sig_addr_cntr_im0_msh_reg[12]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[13] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[13]),
        .Q(sig_addr_cntr_im0_msh_reg[13]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[14] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[14]),
        .Q(sig_addr_cntr_im0_msh_reg[14]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[15] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[15]),
        .Q(sig_addr_cntr_im0_msh_reg[15]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[1]),
        .Q(sig_addr_cntr_im0_msh_reg[1]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[2]),
        .Q(sig_addr_cntr_im0_msh_reg[2]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[3]),
        .Q(sig_addr_cntr_im0_msh_reg[3]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[4]),
        .Q(sig_addr_cntr_im0_msh_reg[4]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[5]),
        .Q(sig_addr_cntr_im0_msh_reg[5]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[6]),
        .Q(sig_addr_cntr_im0_msh_reg[6]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[7] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[7]),
        .Q(sig_addr_cntr_im0_msh_reg[7]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[8] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[8]),
        .Q(sig_addr_cntr_im0_msh_reg[8]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_im0_msh_reg[9] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_im0_msh[15]_i_1_n_0 ),
        .D(p_0_in[9]),
        .Q(sig_addr_cntr_im0_msh_reg[9]),
        .R(sig_init_reg));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \sig_addr_cntr_incr_ireg2[0]_i_1 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[0] ),
        .I1(sig_bytes_to_mbaa_ireg1[0]),
        .I2(sig_first_xfer_im0),
        .I3(sig_btt_lt_b2mbaa_ireg1),
        .O(\sig_addr_cntr_incr_ireg2[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \sig_addr_cntr_incr_ireg2[1]_i_1 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[1] ),
        .I1(sig_bytes_to_mbaa_ireg1[1]),
        .I2(sig_first_xfer_im0),
        .I3(sig_btt_lt_b2mbaa_ireg1),
        .O(\sig_addr_cntr_incr_ireg2[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \sig_addr_cntr_incr_ireg2[2]_i_1 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[2] ),
        .I1(sig_bytes_to_mbaa_ireg1[2]),
        .I2(sig_first_xfer_im0),
        .I3(sig_btt_lt_b2mbaa_ireg1),
        .O(\sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT4 #(
    .INIT(16'hAAC0)) 
    \sig_addr_cntr_incr_ireg2[3]_i_1 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[3] ),
        .I1(sig_bytes_to_mbaa_ireg1[3]),
        .I2(sig_first_xfer_im0),
        .I3(sig_btt_lt_b2mbaa_ireg1),
        .O(\sig_addr_cntr_incr_ireg2[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT4 #(
    .INIT(16'hAAC0)) 
    \sig_addr_cntr_incr_ireg2[4]_i_1 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[4] ),
        .I1(sig_bytes_to_mbaa_ireg1[4]),
        .I2(sig_first_xfer_im0),
        .I3(sig_btt_lt_b2mbaa_ireg1),
        .O(\sig_addr_cntr_incr_ireg2[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \sig_addr_cntr_incr_ireg2[5]_i_1 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[5] ),
        .I1(sig_bytes_to_mbaa_ireg1[5]),
        .I2(sig_first_xfer_im0),
        .I3(sig_btt_lt_b2mbaa_ireg1),
        .O(\sig_addr_cntr_incr_ireg2[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT3 #(
    .INIT(8'h31)) 
    \sig_addr_cntr_incr_ireg2[6]_i_1 
       (.I0(sig_first_xfer_im0),
        .I1(sig_btt_lt_b2mbaa_ireg1),
        .I2(sig_addr_aligned_ireg1),
        .O(\sig_addr_cntr_incr_ireg2[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_incr_ireg2_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(\sig_addr_cntr_incr_ireg2[0]_i_1_n_0 ),
        .Q(\sig_addr_cntr_incr_ireg2_reg_n_0_[0] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_incr_ireg2_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(\sig_addr_cntr_incr_ireg2[1]_i_1_n_0 ),
        .Q(\sig_addr_cntr_incr_ireg2_reg_n_0_[1] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_incr_ireg2_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(\sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ),
        .Q(\sig_addr_cntr_incr_ireg2_reg_n_0_[2] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_incr_ireg2_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(\sig_addr_cntr_incr_ireg2[3]_i_1_n_0 ),
        .Q(\sig_addr_cntr_incr_ireg2_reg_n_0_[3] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_incr_ireg2_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(\sig_addr_cntr_incr_ireg2[4]_i_1_n_0 ),
        .Q(\sig_addr_cntr_incr_ireg2_reg_n_0_[4] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_incr_ireg2_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(\sig_addr_cntr_incr_ireg2[5]_i_1_n_0 ),
        .Q(\sig_addr_cntr_incr_ireg2_reg_n_0_[5] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_incr_ireg2_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(\sig_addr_cntr_incr_ireg2[6]_i_1_n_0 ),
        .Q(\sig_addr_cntr_incr_ireg2_reg_n_0_[6] ),
        .R(sig_init_reg));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[0]_i_1 
       (.I0(Q[28]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[0] ),
        .O(p_1_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[10]_i_1 
       (.I0(Q[38]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[10] ),
        .O(p_1_in[10]));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[11]_i_1 
       (.I0(Q[39]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[11] ),
        .O(p_1_in[11]));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[12]_i_1 
       (.I0(Q[40]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[12] ),
        .O(p_1_in[12]));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[13]_i_1 
       (.I0(Q[41]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[13] ),
        .O(p_1_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[14]_i_1 
       (.I0(Q[42]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[14] ),
        .O(p_1_in[14]));
  LUT2 #(
    .INIT(4'hE)) 
    \sig_addr_cntr_lsh_im0[15]_i_1 
       (.I0(sig_push_input_reg11_out),
        .I1(\FSM_onehot_sig_pcc_sm_state[6]_i_2_n_0 ),
        .O(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[15]_i_2 
       (.I0(Q[43]),
        .I1(sig_push_input_reg11_out),
        .I2(sig_predict_addr_lsh_ireg3),
        .O(p_1_in[15]));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[1]_i_1 
       (.I0(Q[29]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[1] ),
        .O(p_1_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[2]_i_1 
       (.I0(Q[30]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[2] ),
        .O(p_1_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[3]_i_1 
       (.I0(Q[31]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[3] ),
        .O(p_1_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[4]_i_1 
       (.I0(Q[32]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[4] ),
        .O(p_1_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[5]_i_1 
       (.I0(Q[33]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[5] ),
        .O(p_1_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[6]_i_1 
       (.I0(Q[34]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[6] ),
        .O(p_1_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[7]_i_1 
       (.I0(Q[35]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[7] ),
        .O(p_1_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[8]_i_1 
       (.I0(Q[36]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[8] ),
        .O(p_1_in[8]));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_addr_cntr_lsh_im0[9]_i_1 
       (.I0(Q[37]),
        .I1(sig_push_input_reg11_out),
        .I2(\sig_predict_addr_lsh_ireg3_reg_n_0_[9] ),
        .O(p_1_in[9]));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[0]),
        .Q(sig_mbaa_addr_cntr_slice_im0[0]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[10] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[10]),
        .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[10] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[11] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[11]),
        .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[11] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[12] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[12]),
        .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[12] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[13] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[13]),
        .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[13] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[14] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[14]),
        .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[14] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[15] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[15]),
        .Q(p_1_in_0),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(sig_mbaa_addr_cntr_slice_im0[1]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(sig_mbaa_addr_cntr_slice_im0[2]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(sig_mbaa_addr_cntr_slice_im0[3]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[4]),
        .Q(sig_mbaa_addr_cntr_slice_im0[4]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[5]),
        .Q(sig_mbaa_addr_cntr_slice_im0[5]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[6]),
        .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[7] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[7]),
        .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[8] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[8]),
        .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[8] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_im0_reg[9] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(p_1_in[9]),
        .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[9] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[28]),
        .Q(sig_addr_cntr_lsh_kh[0]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[10] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[38]),
        .Q(sig_addr_cntr_lsh_kh[10]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[11] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[39]),
        .Q(sig_addr_cntr_lsh_kh[11]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[12] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[40]),
        .Q(sig_addr_cntr_lsh_kh[12]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[13] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[41]),
        .Q(sig_addr_cntr_lsh_kh[13]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[14] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[42]),
        .Q(sig_addr_cntr_lsh_kh[14]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[15] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[43]),
        .Q(sig_addr_cntr_lsh_kh[15]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[16] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[44]),
        .Q(sig_addr_cntr_lsh_kh[16]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[17] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[45]),
        .Q(sig_addr_cntr_lsh_kh[17]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[18] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[46]),
        .Q(sig_addr_cntr_lsh_kh[18]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[19] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[47]),
        .Q(sig_addr_cntr_lsh_kh[19]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[29]),
        .Q(sig_addr_cntr_lsh_kh[1]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[20] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[48]),
        .Q(sig_addr_cntr_lsh_kh[20]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[21] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[49]),
        .Q(sig_addr_cntr_lsh_kh[21]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[22] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[50]),
        .Q(sig_addr_cntr_lsh_kh[22]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[23] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[51]),
        .Q(sig_addr_cntr_lsh_kh[23]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[24] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[52]),
        .Q(sig_addr_cntr_lsh_kh[24]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[25] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[53]),
        .Q(sig_addr_cntr_lsh_kh[25]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[26] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[54]),
        .Q(sig_addr_cntr_lsh_kh[26]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[27] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[55]),
        .Q(sig_addr_cntr_lsh_kh[27]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[28] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[56]),
        .Q(sig_addr_cntr_lsh_kh[28]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[29] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[57]),
        .Q(sig_addr_cntr_lsh_kh[29]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[30]),
        .Q(sig_addr_cntr_lsh_kh[2]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[30] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[58]),
        .Q(sig_addr_cntr_lsh_kh[30]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[31] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[59]),
        .Q(sig_addr_cntr_lsh_kh[31]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[31]),
        .Q(sig_addr_cntr_lsh_kh[3]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[32]),
        .Q(sig_addr_cntr_lsh_kh[4]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[33]),
        .Q(sig_addr_cntr_lsh_kh[5]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[34]),
        .Q(sig_addr_cntr_lsh_kh[6]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[7] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[35]),
        .Q(sig_addr_cntr_lsh_kh[7]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[8] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[36]),
        .Q(sig_addr_cntr_lsh_kh[8]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_cntr_lsh_kh_reg[9] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[37]),
        .Q(sig_addr_cntr_lsh_kh[9]),
        .R(sig_init_reg));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT5 #(
    .INIT(32'h56669AAA)) 
    \sig_adjusted_addr_incr_ireg2[0]_i_1 
       (.I0(sig_mbaa_addr_cntr_slice_im0[0]),
        .I1(sig_btt_lt_b2mbaa_ireg1),
        .I2(sig_first_xfer_im0),
        .I3(sig_bytes_to_mbaa_ireg1[0]),
        .I4(\sig_btt_cntr_im0_reg_n_0_[0] ),
        .O(sig_adjusted_addr_incr_im1[0]));
  LUT6 #(
    .INIT(64'h9999A55566665AAA)) 
    \sig_adjusted_addr_incr_ireg2[1]_i_1 
       (.I0(\sig_adjusted_addr_incr_ireg2[1]_i_2_n_0 ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[1] ),
        .I2(sig_bytes_to_mbaa_ireg1[1]),
        .I3(sig_first_xfer_im0),
        .I4(sig_btt_lt_b2mbaa_ireg1),
        .I5(sig_mbaa_addr_cntr_slice_im0[1]),
        .O(sig_adjusted_addr_incr_im1[1]));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT5 #(
    .INIT(32'hEA400000)) 
    \sig_adjusted_addr_incr_ireg2[1]_i_2 
       (.I0(sig_btt_lt_b2mbaa_ireg1),
        .I1(sig_first_xfer_im0),
        .I2(sig_bytes_to_mbaa_ireg1[0]),
        .I3(\sig_btt_cntr_im0_reg_n_0_[0] ),
        .I4(sig_mbaa_addr_cntr_slice_im0[0]),
        .O(\sig_adjusted_addr_incr_ireg2[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT5 #(
    .INIT(32'h56666AAA)) 
    \sig_adjusted_addr_incr_ireg2[2]_i_1 
       (.I0(\sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ),
        .I1(sig_mbaa_addr_cntr_slice_im0[1]),
        .I2(\sig_addr_cntr_incr_ireg2[0]_i_1_n_0 ),
        .I3(sig_mbaa_addr_cntr_slice_im0[0]),
        .I4(\sig_addr_cntr_incr_ireg2[1]_i_1_n_0 ),
        .O(sig_adjusted_addr_incr_im1[2]));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT5 #(
    .INIT(32'h15BFEA40)) 
    \sig_adjusted_addr_incr_ireg2[3]_i_1 
       (.I0(sig_btt_lt_b2mbaa_ireg1),
        .I1(sig_first_xfer_im0),
        .I2(sig_bytes_to_mbaa_ireg1[3]),
        .I3(\sig_btt_cntr_im0_reg_n_0_[3] ),
        .I4(\sig_adjusted_addr_incr_ireg2[3]_i_2_n_0 ),
        .O(sig_adjusted_addr_incr_im1[3]));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT5 #(
    .INIT(32'hA8888000)) 
    \sig_adjusted_addr_incr_ireg2[3]_i_2 
       (.I0(\sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ),
        .I1(sig_mbaa_addr_cntr_slice_im0[1]),
        .I2(\sig_addr_cntr_incr_ireg2[0]_i_1_n_0 ),
        .I3(sig_mbaa_addr_cntr_slice_im0[0]),
        .I4(\sig_addr_cntr_incr_ireg2[1]_i_1_n_0 ),
        .O(\sig_adjusted_addr_incr_ireg2[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT5 #(
    .INIT(32'h15BFEA40)) 
    \sig_adjusted_addr_incr_ireg2[4]_i_1 
       (.I0(sig_btt_lt_b2mbaa_ireg1),
        .I1(sig_first_xfer_im0),
        .I2(sig_bytes_to_mbaa_ireg1[4]),
        .I3(\sig_btt_cntr_im0_reg_n_0_[4] ),
        .I4(\sig_adjusted_addr_incr_ireg2[5]_i_2_n_0 ),
        .O(sig_adjusted_addr_incr_im1[4]));
  LUT6 #(
    .INIT(64'h15BFEA40EA40EA40)) 
    \sig_adjusted_addr_incr_ireg2[5]_i_1 
       (.I0(sig_btt_lt_b2mbaa_ireg1),
        .I1(sig_first_xfer_im0),
        .I2(sig_bytes_to_mbaa_ireg1[5]),
        .I3(\sig_btt_cntr_im0_reg_n_0_[5] ),
        .I4(\sig_adjusted_addr_incr_ireg2[5]_i_2_n_0 ),
        .I5(\sig_addr_cntr_incr_ireg2[4]_i_1_n_0 ),
        .O(sig_adjusted_addr_incr_im1[5]));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT5 #(
    .INIT(32'hEA400000)) 
    \sig_adjusted_addr_incr_ireg2[5]_i_2 
       (.I0(sig_btt_lt_b2mbaa_ireg1),
        .I1(sig_first_xfer_im0),
        .I2(sig_bytes_to_mbaa_ireg1[3]),
        .I3(\sig_btt_cntr_im0_reg_n_0_[3] ),
        .I4(\sig_adjusted_addr_incr_ireg2[3]_i_2_n_0 ),
        .O(\sig_adjusted_addr_incr_ireg2[5]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_adjusted_addr_incr_ireg2_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(sig_adjusted_addr_incr_im1[0]),
        .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_adjusted_addr_incr_ireg2_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(sig_adjusted_addr_incr_im1[1]),
        .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_adjusted_addr_incr_ireg2_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(sig_adjusted_addr_incr_im1[2]),
        .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_adjusted_addr_incr_ireg2_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(sig_adjusted_addr_incr_im1[3]),
        .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_adjusted_addr_incr_ireg2_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(sig_adjusted_addr_incr_im1[4]),
        .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_adjusted_addr_incr_ireg2_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(sig_adjusted_addr_incr_im1[5]),
        .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ),
        .R(sig_init_reg));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    sig_brst_cnt_eq_one_ireg1_i_1
       (.I0(sig_brst_cnt_eq_zero_ireg1_i_2_n_0),
        .I1(\sig_btt_cntr_im0_reg_n_0_[7] ),
        .I2(\sig_btt_cntr_im0_reg_n_0_[8] ),
        .I3(\sig_btt_cntr_im0_reg_n_0_[24] ),
        .I4(\sig_btt_cntr_im0_reg_n_0_[6] ),
        .I5(sig_brst_cnt_eq_zero_ireg1_i_3_n_0),
        .O(sig_brst_cnt_eq_one_im0));
  FDRE #(
    .INIT(1'b0)) 
    sig_brst_cnt_eq_one_ireg1_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_brst_cnt_eq_one_im0),
        .Q(sig_brst_cnt_eq_one_ireg1),
        .R(sig_init_reg));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    sig_brst_cnt_eq_zero_ireg1_i_1
       (.I0(sig_brst_cnt_eq_zero_ireg1_i_2_n_0),
        .I1(\sig_btt_cntr_im0_reg_n_0_[7] ),
        .I2(\sig_btt_cntr_im0_reg_n_0_[8] ),
        .I3(\sig_btt_cntr_im0_reg_n_0_[24] ),
        .I4(\sig_btt_cntr_im0_reg_n_0_[6] ),
        .I5(sig_brst_cnt_eq_zero_ireg1_i_3_n_0),
        .O(sig_brst_cnt_eq_zero_im0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    sig_brst_cnt_eq_zero_ireg1_i_2
       (.I0(\sig_btt_cntr_im0_reg_n_0_[22] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[23] ),
        .I2(\sig_btt_cntr_im0_reg_n_0_[25] ),
        .I3(\sig_btt_cntr_im0_reg_n_0_[21] ),
        .O(sig_brst_cnt_eq_zero_ireg1_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000200000000)) 
    sig_brst_cnt_eq_zero_ireg1_i_3
       (.I0(sig_brst_cnt_eq_zero_ireg1_i_4_n_0),
        .I1(\sig_btt_cntr_im0_reg_n_0_[20] ),
        .I2(\sig_btt_cntr_im0_reg_n_0_[19] ),
        .I3(\sig_btt_cntr_im0_reg_n_0_[18] ),
        .I4(\sig_btt_cntr_im0_reg_n_0_[17] ),
        .I5(sig_brst_cnt_eq_zero_ireg1_i_5_n_0),
        .O(sig_brst_cnt_eq_zero_ireg1_i_3_n_0));
  LUT4 #(
    .INIT(16'h0001)) 
    sig_brst_cnt_eq_zero_ireg1_i_4
       (.I0(\sig_btt_cntr_im0_reg_n_0_[16] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[15] ),
        .I2(\sig_btt_cntr_im0_reg_n_0_[14] ),
        .I3(\sig_btt_cntr_im0_reg_n_0_[13] ),
        .O(sig_brst_cnt_eq_zero_ireg1_i_4_n_0));
  LUT4 #(
    .INIT(16'h0001)) 
    sig_brst_cnt_eq_zero_ireg1_i_5
       (.I0(\sig_btt_cntr_im0_reg_n_0_[10] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[9] ),
        .I2(\sig_btt_cntr_im0_reg_n_0_[12] ),
        .I3(\sig_btt_cntr_im0_reg_n_0_[11] ),
        .O(sig_brst_cnt_eq_zero_ireg1_i_5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_brst_cnt_eq_zero_ireg1_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_brst_cnt_eq_zero_im0),
        .Q(sig_brst_cnt_eq_zero_ireg1),
        .R(sig_init_reg));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[15]_i_2 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[15] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[15]),
        .O(\sig_btt_cntr_im0[15]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[15]_i_3 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[14] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[14]),
        .O(\sig_btt_cntr_im0[15]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[15]_i_4 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[13] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[13]),
        .O(\sig_btt_cntr_im0[15]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[15]_i_5 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[12] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[12]),
        .O(\sig_btt_cntr_im0[15]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[15]_i_6 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[11] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[11]),
        .O(\sig_btt_cntr_im0[15]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[15]_i_7 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[10] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[10]),
        .O(\sig_btt_cntr_im0[15]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[15]_i_8 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[9] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[9]),
        .O(\sig_btt_cntr_im0[15]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[15]_i_9 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[8] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[8]),
        .O(\sig_btt_cntr_im0[15]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[23]_i_2 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[23] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[23]),
        .O(\sig_btt_cntr_im0[23]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[23]_i_3 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[22] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[22]),
        .O(\sig_btt_cntr_im0[23]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[23]_i_4 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[21] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[21]),
        .O(\sig_btt_cntr_im0[23]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[23]_i_5 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[20] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[20]),
        .O(\sig_btt_cntr_im0[23]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[23]_i_6 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[19] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[19]),
        .O(\sig_btt_cntr_im0[23]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[23]_i_7 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[18] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[18]),
        .O(\sig_btt_cntr_im0[23]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[23]_i_8 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[17] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[17]),
        .O(\sig_btt_cntr_im0[23]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[23]_i_9 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[16] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[16]),
        .O(\sig_btt_cntr_im0[23]_i_9_n_0 ));
  LUT4 #(
    .INIT(16'hFFDF)) 
    \sig_btt_cntr_im0[25]_i_2 
       (.I0(sig_cmd2mstr_cmd_valid),
        .I1(sig_sm_halt_reg),
        .I2(sig_input_reg_empty),
        .I3(in[37]),
        .O(\sig_btt_cntr_im0[25]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[25]_i_3 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[25] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[25]),
        .O(\sig_btt_cntr_im0[25]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[25]_i_4 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[24] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[24]),
        .O(\sig_btt_cntr_im0[25]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hF909)) 
    \sig_btt_cntr_im0[7]_i_10 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[6] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[6] ),
        .I2(sig_push_input_reg11_out),
        .I3(Q[6]),
        .O(\sig_btt_cntr_im0[7]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'hF909)) 
    \sig_btt_cntr_im0[7]_i_11 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[5] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[5] ),
        .I2(sig_push_input_reg11_out),
        .I3(Q[5]),
        .O(\sig_btt_cntr_im0[7]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'hF909)) 
    \sig_btt_cntr_im0[7]_i_12 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[4] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[4] ),
        .I2(sig_push_input_reg11_out),
        .I3(Q[4]),
        .O(\sig_btt_cntr_im0[7]_i_12_n_0 ));
  LUT4 #(
    .INIT(16'hF909)) 
    \sig_btt_cntr_im0[7]_i_13 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[3] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[3] ),
        .I2(sig_push_input_reg11_out),
        .I3(Q[3]),
        .O(\sig_btt_cntr_im0[7]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'hF909)) 
    \sig_btt_cntr_im0[7]_i_14 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[2] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[2] ),
        .I2(sig_push_input_reg11_out),
        .I3(Q[2]),
        .O(\sig_btt_cntr_im0[7]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'hF909)) 
    \sig_btt_cntr_im0[7]_i_15 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[1] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[1] ),
        .I2(sig_push_input_reg11_out),
        .I3(Q[1]),
        .O(\sig_btt_cntr_im0[7]_i_15_n_0 ));
  LUT4 #(
    .INIT(16'hF909)) 
    \sig_btt_cntr_im0[7]_i_16 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[0] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[0] ),
        .I2(sig_push_input_reg11_out),
        .I3(Q[0]),
        .O(\sig_btt_cntr_im0[7]_i_16_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \sig_btt_cntr_im0[7]_i_2 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[6] ),
        .I1(sig_push_input_reg11_out),
        .O(\sig_btt_cntr_im0[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \sig_btt_cntr_im0[7]_i_3 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[5] ),
        .I1(sig_push_input_reg11_out),
        .O(\sig_btt_cntr_im0[7]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \sig_btt_cntr_im0[7]_i_4 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[4] ),
        .I1(sig_push_input_reg11_out),
        .O(\sig_btt_cntr_im0[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \sig_btt_cntr_im0[7]_i_5 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[3] ),
        .I1(sig_push_input_reg11_out),
        .O(\sig_btt_cntr_im0[7]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \sig_btt_cntr_im0[7]_i_6 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[2] ),
        .I1(sig_push_input_reg11_out),
        .O(\sig_btt_cntr_im0[7]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \sig_btt_cntr_im0[7]_i_7 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[1] ),
        .I1(sig_push_input_reg11_out),
        .O(\sig_btt_cntr_im0[7]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \sig_btt_cntr_im0[7]_i_8 
       (.I0(\sig_addr_cntr_incr_ireg2_reg_n_0_[0] ),
        .I1(sig_push_input_reg11_out),
        .O(\sig_btt_cntr_im0[7]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'hD1)) 
    \sig_btt_cntr_im0[7]_i_9 
       (.I0(\sig_btt_cntr_im0_reg_n_0_[7] ),
        .I1(sig_push_input_reg11_out),
        .I2(Q[7]),
        .O(\sig_btt_cntr_im0[7]_i_9_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[7]_i_1_n_15 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[0] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[10] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[15]_i_1_n_13 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[10] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[11] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[15]_i_1_n_12 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[11] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[12] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[15]_i_1_n_11 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[12] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[13] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[15]_i_1_n_10 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[13] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[14] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[15]_i_1_n_9 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[14] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[15] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[15]_i_1_n_8 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[15] ),
        .R(sig_init_reg));
  CARRY8 \sig_btt_cntr_im0_reg[15]_i_1 
       (.CI(\sig_btt_cntr_im0_reg[7]_i_1_n_0 ),
        .CI_TOP(1'b0),
        .CO({\sig_btt_cntr_im0_reg[15]_i_1_n_0 ,\sig_btt_cntr_im0_reg[15]_i_1_n_1 ,\sig_btt_cntr_im0_reg[15]_i_1_n_2 ,\sig_btt_cntr_im0_reg[15]_i_1_n_3 ,\sig_btt_cntr_im0_reg[15]_i_1_n_4 ,\sig_btt_cntr_im0_reg[15]_i_1_n_5 ,\sig_btt_cntr_im0_reg[15]_i_1_n_6 ,\sig_btt_cntr_im0_reg[15]_i_1_n_7 }),
        .DI({\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 }),
        .O({\sig_btt_cntr_im0_reg[15]_i_1_n_8 ,\sig_btt_cntr_im0_reg[15]_i_1_n_9 ,\sig_btt_cntr_im0_reg[15]_i_1_n_10 ,\sig_btt_cntr_im0_reg[15]_i_1_n_11 ,\sig_btt_cntr_im0_reg[15]_i_1_n_12 ,\sig_btt_cntr_im0_reg[15]_i_1_n_13 ,\sig_btt_cntr_im0_reg[15]_i_1_n_14 ,\sig_btt_cntr_im0_reg[15]_i_1_n_15 }),
        .S({\sig_btt_cntr_im0[15]_i_2_n_0 ,\sig_btt_cntr_im0[15]_i_3_n_0 ,\sig_btt_cntr_im0[15]_i_4_n_0 ,\sig_btt_cntr_im0[15]_i_5_n_0 ,\sig_btt_cntr_im0[15]_i_6_n_0 ,\sig_btt_cntr_im0[15]_i_7_n_0 ,\sig_btt_cntr_im0[15]_i_8_n_0 ,\sig_btt_cntr_im0[15]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[16] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[23]_i_1_n_15 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[16] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[17] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[23]_i_1_n_14 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[17] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[18] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[23]_i_1_n_13 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[18] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[19] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[23]_i_1_n_12 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[19] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[7]_i_1_n_14 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[1] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[20] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[23]_i_1_n_11 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[20] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[21] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[23]_i_1_n_10 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[21] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[22] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[23]_i_1_n_9 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[22] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[23] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[23]_i_1_n_8 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[23] ),
        .R(sig_init_reg));
  CARRY8 \sig_btt_cntr_im0_reg[23]_i_1 
       (.CI(\sig_btt_cntr_im0_reg[15]_i_1_n_0 ),
        .CI_TOP(1'b0),
        .CO({\sig_btt_cntr_im0_reg[23]_i_1_n_0 ,\sig_btt_cntr_im0_reg[23]_i_1_n_1 ,\sig_btt_cntr_im0_reg[23]_i_1_n_2 ,\sig_btt_cntr_im0_reg[23]_i_1_n_3 ,\sig_btt_cntr_im0_reg[23]_i_1_n_4 ,\sig_btt_cntr_im0_reg[23]_i_1_n_5 ,\sig_btt_cntr_im0_reg[23]_i_1_n_6 ,\sig_btt_cntr_im0_reg[23]_i_1_n_7 }),
        .DI({\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[25]_i_2_n_0 }),
        .O({\sig_btt_cntr_im0_reg[23]_i_1_n_8 ,\sig_btt_cntr_im0_reg[23]_i_1_n_9 ,\sig_btt_cntr_im0_reg[23]_i_1_n_10 ,\sig_btt_cntr_im0_reg[23]_i_1_n_11 ,\sig_btt_cntr_im0_reg[23]_i_1_n_12 ,\sig_btt_cntr_im0_reg[23]_i_1_n_13 ,\sig_btt_cntr_im0_reg[23]_i_1_n_14 ,\sig_btt_cntr_im0_reg[23]_i_1_n_15 }),
        .S({\sig_btt_cntr_im0[23]_i_2_n_0 ,\sig_btt_cntr_im0[23]_i_3_n_0 ,\sig_btt_cntr_im0[23]_i_4_n_0 ,\sig_btt_cntr_im0[23]_i_5_n_0 ,\sig_btt_cntr_im0[23]_i_6_n_0 ,\sig_btt_cntr_im0[23]_i_7_n_0 ,\sig_btt_cntr_im0[23]_i_8_n_0 ,\sig_btt_cntr_im0[23]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[24] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[25]_i_1_n_15 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[24] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[25] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[25]_i_1_n_14 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[25] ),
        .R(sig_init_reg));
  CARRY8 \sig_btt_cntr_im0_reg[25]_i_1 
       (.CI(\sig_btt_cntr_im0_reg[23]_i_1_n_0 ),
        .CI_TOP(1'b0),
        .CO({\NLW_sig_btt_cntr_im0_reg[25]_i_1_CO_UNCONNECTED [7:1],\sig_btt_cntr_im0_reg[25]_i_1_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\sig_btt_cntr_im0[25]_i_2_n_0 }),
        .O({\NLW_sig_btt_cntr_im0_reg[25]_i_1_O_UNCONNECTED [7:2],\sig_btt_cntr_im0_reg[25]_i_1_n_14 ,\sig_btt_cntr_im0_reg[25]_i_1_n_15 }),
        .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\sig_btt_cntr_im0[25]_i_3_n_0 ,\sig_btt_cntr_im0[25]_i_4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[7]_i_1_n_13 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[2] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[7]_i_1_n_12 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[3] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[7]_i_1_n_11 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[4] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[7]_i_1_n_10 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[5] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[7]_i_1_n_9 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[6] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[7] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[7]_i_1_n_8 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[7] ),
        .R(sig_init_reg));
  CARRY8 \sig_btt_cntr_im0_reg[7]_i_1 
       (.CI(\sig_btt_cntr_im0[25]_i_2_n_0 ),
        .CI_TOP(1'b0),
        .CO({\sig_btt_cntr_im0_reg[7]_i_1_n_0 ,\sig_btt_cntr_im0_reg[7]_i_1_n_1 ,\sig_btt_cntr_im0_reg[7]_i_1_n_2 ,\sig_btt_cntr_im0_reg[7]_i_1_n_3 ,\sig_btt_cntr_im0_reg[7]_i_1_n_4 ,\sig_btt_cntr_im0_reg[7]_i_1_n_5 ,\sig_btt_cntr_im0_reg[7]_i_1_n_6 ,\sig_btt_cntr_im0_reg[7]_i_1_n_7 }),
        .DI({\sig_btt_cntr_im0[25]_i_2_n_0 ,\sig_btt_cntr_im0[7]_i_2_n_0 ,\sig_btt_cntr_im0[7]_i_3_n_0 ,\sig_btt_cntr_im0[7]_i_4_n_0 ,\sig_btt_cntr_im0[7]_i_5_n_0 ,\sig_btt_cntr_im0[7]_i_6_n_0 ,\sig_btt_cntr_im0[7]_i_7_n_0 ,\sig_btt_cntr_im0[7]_i_8_n_0 }),
        .O({\sig_btt_cntr_im0_reg[7]_i_1_n_8 ,\sig_btt_cntr_im0_reg[7]_i_1_n_9 ,\sig_btt_cntr_im0_reg[7]_i_1_n_10 ,\sig_btt_cntr_im0_reg[7]_i_1_n_11 ,\sig_btt_cntr_im0_reg[7]_i_1_n_12 ,\sig_btt_cntr_im0_reg[7]_i_1_n_13 ,\sig_btt_cntr_im0_reg[7]_i_1_n_14 ,\sig_btt_cntr_im0_reg[7]_i_1_n_15 }),
        .S({\sig_btt_cntr_im0[7]_i_9_n_0 ,\sig_btt_cntr_im0[7]_i_10_n_0 ,\sig_btt_cntr_im0[7]_i_11_n_0 ,\sig_btt_cntr_im0[7]_i_12_n_0 ,\sig_btt_cntr_im0[7]_i_13_n_0 ,\sig_btt_cntr_im0[7]_i_14_n_0 ,\sig_btt_cntr_im0[7]_i_15_n_0 ,\sig_btt_cntr_im0[7]_i_16_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[8] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[15]_i_1_n_15 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[8] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_btt_cntr_im0_reg[9] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ),
        .D(\sig_btt_cntr_im0_reg[15]_i_1_n_14 ),
        .Q(\sig_btt_cntr_im0_reg_n_0_[9] ),
        .R(sig_init_reg));
  LUT5 #(
    .INIT(32'h20000000)) 
    sig_btt_eq_b2mbaa_ireg1_i_1
       (.I0(sig_btt_eq_b2mbaa_ireg1_i_2_n_0),
        .I1(sig_addr_aligned_im0),
        .I2(sig_brst_cnt_eq_zero_im0),
        .I3(sig_btt_eq_b2mbaa_ireg1_i_3_n_0),
        .I4(sig_btt_eq_b2mbaa_ireg1_i_4_n_0),
        .O(sig_btt_eq_b2mbaa_im0));
  LUT6 #(
    .INIT(64'h015402A85402A801)) 
    sig_btt_eq_b2mbaa_ireg1_i_2
       (.I0(\sig_btt_cntr_im0_reg_n_0_[3] ),
        .I1(sig_mbaa_addr_cntr_slice_im0[1]),
        .I2(sig_mbaa_addr_cntr_slice_im0[0]),
        .I3(sig_mbaa_addr_cntr_slice_im0[2]),
        .I4(sig_mbaa_addr_cntr_slice_im0[3]),
        .I5(\sig_btt_cntr_im0_reg_n_0_[2] ),
        .O(sig_btt_eq_b2mbaa_ireg1_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT4 #(
    .INIT(16'h6009)) 
    sig_btt_eq_b2mbaa_ireg1_i_3
       (.I0(\sig_btt_cntr_im0_reg_n_0_[1] ),
        .I1(sig_mbaa_addr_cntr_slice_im0[1]),
        .I2(sig_mbaa_addr_cntr_slice_im0[0]),
        .I3(\sig_btt_cntr_im0_reg_n_0_[0] ),
        .O(sig_btt_eq_b2mbaa_ireg1_i_3_n_0));
  LUT5 #(
    .INIT(32'h41821824)) 
    sig_btt_eq_b2mbaa_ireg1_i_4
       (.I0(\sig_btt_cntr_im0_reg_n_0_[5] ),
        .I1(sig_btt_lt_b2mbaa_im01_carry_i_8_n_0),
        .I2(sig_mbaa_addr_cntr_slice_im0[4]),
        .I3(sig_mbaa_addr_cntr_slice_im0[5]),
        .I4(\sig_btt_cntr_im0_reg_n_0_[4] ),
        .O(sig_btt_eq_b2mbaa_ireg1_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_btt_eq_b2mbaa_ireg1_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_btt_eq_b2mbaa_im0),
        .Q(sig_btt_eq_b2mbaa_ireg1),
        .R(sig_init_reg));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY8 sig_btt_lt_b2mbaa_im01_carry
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({NLW_sig_btt_lt_b2mbaa_im01_carry_CO_UNCONNECTED[7:4],sig_btt_lt_b2mbaa_im01,sig_btt_lt_b2mbaa_im01_carry_n_5,sig_btt_lt_b2mbaa_im01_carry_n_6,sig_btt_lt_b2mbaa_im01_carry_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,sig_addr_aligned_im0,sig_btt_lt_b2mbaa_im01_carry_i_1_n_0,sig_btt_lt_b2mbaa_im01_carry_i_2_n_0,sig_btt_lt_b2mbaa_im01_carry_i_3_n_0}),
        .O(NLW_sig_btt_lt_b2mbaa_im01_carry_O_UNCONNECTED[7:0]),
        .S({1'b0,1'b0,1'b0,1'b0,sig_btt_lt_b2mbaa_im01_carry_i_4_n_0,sig_btt_lt_b2mbaa_im01_carry_i_5_n_0,sig_btt_lt_b2mbaa_im01_carry_i_6_n_0,sig_btt_lt_b2mbaa_im01_carry_i_7_n_0}));
  LUT5 #(
    .INIT(32'h10017C37)) 
    sig_btt_lt_b2mbaa_im01_carry_i_1
       (.I0(\sig_btt_cntr_im0_reg_n_0_[4] ),
        .I1(sig_mbaa_addr_cntr_slice_im0[5]),
        .I2(sig_mbaa_addr_cntr_slice_im0[4]),
        .I3(sig_btt_lt_b2mbaa_im01_carry_i_8_n_0),
        .I4(\sig_btt_cntr_im0_reg_n_0_[5] ),
        .O(sig_btt_lt_b2mbaa_im01_carry_i_1_n_0));
  LUT6 #(
    .INIT(64'h010101103737377C)) 
    sig_btt_lt_b2mbaa_im01_carry_i_2
       (.I0(\sig_btt_cntr_im0_reg_n_0_[2] ),
        .I1(sig_mbaa_addr_cntr_slice_im0[3]),
        .I2(sig_mbaa_addr_cntr_slice_im0[2]),
        .I3(sig_mbaa_addr_cntr_slice_im0[0]),
        .I4(sig_mbaa_addr_cntr_slice_im0[1]),
        .I5(\sig_btt_cntr_im0_reg_n_0_[3] ),
        .O(sig_btt_lt_b2mbaa_im01_carry_i_2_n_0));
  LUT4 #(
    .INIT(16'h1370)) 
    sig_btt_lt_b2mbaa_im01_carry_i_3
       (.I0(\sig_btt_cntr_im0_reg_n_0_[0] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[1] ),
        .I2(sig_mbaa_addr_cntr_slice_im0[0]),
        .I3(sig_mbaa_addr_cntr_slice_im0[1]),
        .O(sig_btt_lt_b2mbaa_im01_carry_i_3_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    sig_btt_lt_b2mbaa_im01_carry_i_4
       (.I0(sig_mbaa_addr_cntr_slice_im0[5]),
        .I1(sig_mbaa_addr_cntr_slice_im0[3]),
        .I2(sig_mbaa_addr_cntr_slice_im0[1]),
        .I3(sig_mbaa_addr_cntr_slice_im0[0]),
        .I4(sig_mbaa_addr_cntr_slice_im0[2]),
        .I5(sig_mbaa_addr_cntr_slice_im0[4]),
        .O(sig_btt_lt_b2mbaa_im01_carry_i_4_n_0));
  LUT5 #(
    .INIT(32'h41821824)) 
    sig_btt_lt_b2mbaa_im01_carry_i_5
       (.I0(\sig_btt_cntr_im0_reg_n_0_[5] ),
        .I1(sig_btt_lt_b2mbaa_im01_carry_i_8_n_0),
        .I2(sig_mbaa_addr_cntr_slice_im0[4]),
        .I3(sig_mbaa_addr_cntr_slice_im0[5]),
        .I4(\sig_btt_cntr_im0_reg_n_0_[4] ),
        .O(sig_btt_lt_b2mbaa_im01_carry_i_5_n_0));
  LUT6 #(
    .INIT(64'h015402A85402A801)) 
    sig_btt_lt_b2mbaa_im01_carry_i_6
       (.I0(\sig_btt_cntr_im0_reg_n_0_[3] ),
        .I1(sig_mbaa_addr_cntr_slice_im0[1]),
        .I2(sig_mbaa_addr_cntr_slice_im0[0]),
        .I3(sig_mbaa_addr_cntr_slice_im0[2]),
        .I4(sig_mbaa_addr_cntr_slice_im0[3]),
        .I5(\sig_btt_cntr_im0_reg_n_0_[2] ),
        .O(sig_btt_lt_b2mbaa_im01_carry_i_6_n_0));
  LUT4 #(
    .INIT(16'h6009)) 
    sig_btt_lt_b2mbaa_im01_carry_i_7
       (.I0(\sig_btt_cntr_im0_reg_n_0_[1] ),
        .I1(sig_mbaa_addr_cntr_slice_im0[1]),
        .I2(sig_mbaa_addr_cntr_slice_im0[0]),
        .I3(\sig_btt_cntr_im0_reg_n_0_[0] ),
        .O(sig_btt_lt_b2mbaa_im01_carry_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    sig_btt_lt_b2mbaa_im01_carry_i_8
       (.I0(sig_mbaa_addr_cntr_slice_im0[2]),
        .I1(sig_mbaa_addr_cntr_slice_im0[0]),
        .I2(sig_mbaa_addr_cntr_slice_im0[1]),
        .I3(sig_mbaa_addr_cntr_slice_im0[3]),
        .O(sig_btt_lt_b2mbaa_im01_carry_i_8_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    sig_btt_lt_b2mbaa_ireg1_i_1
       (.I0(sig_btt_lt_b2mbaa_im01),
        .I1(sig_brst_cnt_eq_zero_im0),
        .O(sig_btt_lt_b2mbaa_im0));
  FDRE #(
    .INIT(1'b0)) 
    sig_btt_lt_b2mbaa_ireg1_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_btt_lt_b2mbaa_im0),
        .Q(sig_btt_lt_b2mbaa_ireg1),
        .R(sig_init_reg));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \sig_bytes_to_mbaa_ireg1[1]_i_1 
       (.I0(sig_mbaa_addr_cntr_slice_im0[1]),
        .I1(sig_mbaa_addr_cntr_slice_im0[0]),
        .O(sig_bytes_to_mbaa_im0[1]));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT3 #(
    .INIT(8'h1E)) 
    \sig_bytes_to_mbaa_ireg1[2]_i_1 
       (.I0(sig_mbaa_addr_cntr_slice_im0[0]),
        .I1(sig_mbaa_addr_cntr_slice_im0[1]),
        .I2(sig_mbaa_addr_cntr_slice_im0[2]),
        .O(sig_bytes_to_mbaa_im0[2]));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT4 #(
    .INIT(16'h01FE)) 
    \sig_bytes_to_mbaa_ireg1[3]_i_1 
       (.I0(sig_mbaa_addr_cntr_slice_im0[1]),
        .I1(sig_mbaa_addr_cntr_slice_im0[0]),
        .I2(sig_mbaa_addr_cntr_slice_im0[2]),
        .I3(sig_mbaa_addr_cntr_slice_im0[3]),
        .O(sig_bytes_to_mbaa_im0[3]));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT5 #(
    .INIT(32'h0001FFFE)) 
    \sig_bytes_to_mbaa_ireg1[4]_i_1 
       (.I0(sig_mbaa_addr_cntr_slice_im0[2]),
        .I1(sig_mbaa_addr_cntr_slice_im0[0]),
        .I2(sig_mbaa_addr_cntr_slice_im0[1]),
        .I3(sig_mbaa_addr_cntr_slice_im0[3]),
        .I4(sig_mbaa_addr_cntr_slice_im0[4]),
        .O(sig_bytes_to_mbaa_im0[4]));
  LUT6 #(
    .INIT(64'h00000001FFFFFFFE)) 
    \sig_bytes_to_mbaa_ireg1[5]_i_1 
       (.I0(sig_mbaa_addr_cntr_slice_im0[3]),
        .I1(sig_mbaa_addr_cntr_slice_im0[1]),
        .I2(sig_mbaa_addr_cntr_slice_im0[0]),
        .I3(sig_mbaa_addr_cntr_slice_im0[2]),
        .I4(sig_mbaa_addr_cntr_slice_im0[4]),
        .I5(sig_mbaa_addr_cntr_slice_im0[5]),
        .O(sig_bytes_to_mbaa_im0[5]));
  FDRE #(
    .INIT(1'b0)) 
    \sig_bytes_to_mbaa_ireg1_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_mbaa_addr_cntr_slice_im0[0]),
        .Q(sig_bytes_to_mbaa_ireg1[0]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_bytes_to_mbaa_ireg1_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_bytes_to_mbaa_im0[1]),
        .Q(sig_bytes_to_mbaa_ireg1[1]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_bytes_to_mbaa_ireg1_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_bytes_to_mbaa_im0[2]),
        .Q(sig_bytes_to_mbaa_ireg1[2]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_bytes_to_mbaa_ireg1_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_bytes_to_mbaa_im0[3]),
        .Q(sig_bytes_to_mbaa_ireg1[3]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_bytes_to_mbaa_ireg1_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_bytes_to_mbaa_im0[4]),
        .Q(sig_bytes_to_mbaa_ireg1[4]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_bytes_to_mbaa_ireg1_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_bytes_to_mbaa_im0[5]),
        .Q(sig_bytes_to_mbaa_ireg1[5]),
        .R(sig_init_reg));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT4 #(
    .INIT(16'hFF80)) 
    sig_calc_error_pushed_i_1
       (.I0(in[37]),
        .I1(sig_ld_xfer_reg),
        .I2(sig_xfer_reg_empty),
        .I3(sig_calc_error_pushed),
        .O(sig_calc_error_pushed_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_calc_error_pushed_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_calc_error_pushed_i_1_n_0),
        .Q(sig_calc_error_pushed),
        .R(sig_init_reg));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    sig_calc_error_reg_i_1
       (.I0(sig_calc_error_reg_i_2_n_0),
        .I1(sig_calc_error_reg_i_3_n_0),
        .I2(sig_calc_error_reg_i_4_n_0),
        .I3(sig_calc_error_reg_i_5_n_0),
        .I4(Q[0]),
        .I5(Q[1]),
        .O(sig_btt_is_zero));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    sig_calc_error_reg_i_2
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(Q[7]),
        .I5(Q[6]),
        .O(sig_calc_error_reg_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    sig_calc_error_reg_i_3
       (.I0(Q[22]),
        .I1(Q[23]),
        .I2(Q[20]),
        .I3(Q[21]),
        .I4(Q[25]),
        .I5(Q[24]),
        .O(sig_calc_error_reg_i_3_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    sig_calc_error_reg_i_4
       (.I0(Q[16]),
        .I1(Q[17]),
        .I2(Q[14]),
        .I3(Q[15]),
        .I4(Q[19]),
        .I5(Q[18]),
        .O(sig_calc_error_reg_i_4_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    sig_calc_error_reg_i_5
       (.I0(Q[10]),
        .I1(Q[11]),
        .I2(Q[8]),
        .I3(Q[9]),
        .I4(Q[13]),
        .I5(Q[12]),
        .O(sig_calc_error_reg_i_5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_calc_error_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(sig_btt_is_zero),
        .Q(in[37]),
        .R(sig_init_reg));
  LUT5 #(
    .INIT(32'h50554444)) 
    sig_cmd2addr_valid_i_1
       (.I0(sig_init_reg),
        .I1(sig_sm_ld_calc3_reg),
        .I2(sig_cmd2addr_valid_reg_0),
        .I3(sig_inhibit_rdy_n_1),
        .I4(sig_mstr2addr_cmd_valid),
        .O(sig_cmd2addr_valid_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_cmd2addr_valid_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_cmd2addr_valid_i_1_n_0),
        .Q(sig_mstr2addr_cmd_valid),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h50554444)) 
    sig_cmd2data_valid_i_1
       (.I0(sig_init_reg),
        .I1(sig_sm_ld_calc3_reg),
        .I2(sig_cmd2data_valid_reg_0),
        .I3(sig_inhibit_rdy_n),
        .I4(sig_mstr2data_cmd_valid),
        .O(sig_cmd2data_valid_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_cmd2data_valid_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_cmd2data_valid_i_1_n_0),
        .Q(sig_mstr2data_cmd_valid),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h5500404055554040)) 
    sig_cmd2dre_valid_i_1
       (.I0(sig_init_reg),
        .I1(sig_sm_ld_calc3_reg),
        .I2(sig_first_xfer_im0),
        .I3(sig_cmd2dre_valid_reg_0),
        .I4(sig_mstr2sf_cmd_valid),
        .I5(sig_inhibit_rdy_n_0),
        .O(sig_cmd2dre_valid_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_cmd2dre_valid_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_cmd2dre_valid_i_1_n_0),
        .Q(sig_mstr2sf_cmd_valid),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0054)) 
    sig_first_xfer_im0_i_1
       (.I0(sig_init_reg),
        .I1(sig_push_input_reg11_out),
        .I2(sig_first_xfer_im0),
        .I3(\FSM_onehot_sig_pcc_sm_state[6]_i_2_n_0 ),
        .O(sig_first_xfer_im0_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_first_xfer_im0_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_first_xfer_im0_i_1_n_0),
        .Q(sig_first_xfer_im0),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFE)) 
    sig_input_burst_type_reg_i_1
       (.I0(sig_calc_error_pushed),
        .I1(sig_init_reg),
        .I2(sig_sm_pop_input_reg),
        .O(sig_input_cache_type_reg0));
  LUT4 #(
    .INIT(16'h0400)) 
    sig_input_burst_type_reg_i_2
       (.I0(in[37]),
        .I1(sig_input_reg_empty),
        .I2(sig_sm_halt_reg),
        .I3(sig_cmd2mstr_cmd_valid),
        .O(sig_push_input_reg11_out));
  FDRE #(
    .INIT(1'b0)) 
    sig_input_burst_type_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[26]),
        .Q(in[36]),
        .R(sig_input_cache_type_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_input_eof_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(Q[27]),
        .Q(sig_calc_error_reg_reg_0[0]),
        .R(sig_input_cache_type_reg0));
  FDSE #(
    .INIT(1'b0)) 
    sig_input_reg_empty_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_input_reg11_out),
        .D(1'b0),
        .Q(sig_input_reg_empty),
        .S(sig_input_cache_type_reg0));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT2 #(
    .INIT(4'h9)) 
    sig_last_addr_offset_im2
       (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ),
        .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ),
        .O(sig_last_addr_offset_im2__0));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT4 #(
    .INIT(16'h0454)) 
    sig_ld_xfer_reg_i_1
       (.I0(sig_init_reg),
        .I1(sig_sm_ld_calc3_reg),
        .I2(sig_ld_xfer_reg),
        .I3(sig_xfer_reg_empty),
        .O(sig_ld_xfer_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_ld_xfer_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_ld_xfer_reg_i_1_n_0),
        .Q(sig_ld_xfer_reg),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0054)) 
    sig_ld_xfer_reg_tmp_i_1
       (.I0(sig_init_reg),
        .I1(sig_sm_ld_calc3_reg),
        .I2(sig_ld_xfer_reg_tmp),
        .I3(\FSM_onehot_sig_pcc_sm_state[6]_i_2_n_0 ),
        .O(sig_ld_xfer_reg_tmp_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_ld_xfer_reg_tmp_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_ld_xfer_reg_tmp_i_1_n_0),
        .Q(sig_ld_xfer_reg_tmp),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    sig_mmap_reset_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(SS),
        .Q(sig_init_reg),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    sig_no_btt_residue_ireg1_i_1
       (.I0(\sig_btt_cntr_im0_reg_n_0_[2] ),
        .I1(\sig_btt_cntr_im0_reg_n_0_[3] ),
        .I2(\sig_btt_cntr_im0_reg_n_0_[0] ),
        .I3(\sig_btt_cntr_im0_reg_n_0_[1] ),
        .I4(\sig_btt_cntr_im0_reg_n_0_[5] ),
        .I5(\sig_btt_cntr_im0_reg_n_0_[4] ),
        .O(sig_no_btt_residue_im0));
  FDRE #(
    .INIT(1'b0)) 
    sig_no_btt_residue_ireg1_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg_ns),
        .D(sig_no_btt_residue_im0),
        .Q(sig_no_btt_residue_ireg1),
        .R(sig_init_reg));
  LUT5 #(
    .INIT(32'h00001510)) 
    sig_parent_done_i_1
       (.I0(sig_init_reg),
        .I1(sig_calc_error_reg_reg_0[10]),
        .I2(sig_ld_xfer_reg_tmp),
        .I3(sig_parent_done),
        .I4(sig_push_input_reg11_out),
        .O(sig_parent_done_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_parent_done_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_parent_done_i_1_n_0),
        .Q(sig_parent_done),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h6)) 
    \sig_predict_addr_lsh_ireg3[7]_i_2 
       (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ),
        .I1(\sig_addr_cntr_incr_ireg2_reg_n_0_[6] ),
        .O(\sig_predict_addr_lsh_ireg3[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \sig_predict_addr_lsh_ireg3[7]_i_3 
       (.I0(sig_mbaa_addr_cntr_slice_im0[5]),
        .I1(\sig_addr_cntr_incr_ireg2_reg_n_0_[5] ),
        .O(\sig_predict_addr_lsh_ireg3[7]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \sig_predict_addr_lsh_ireg3[7]_i_4 
       (.I0(sig_mbaa_addr_cntr_slice_im0[4]),
        .I1(\sig_addr_cntr_incr_ireg2_reg_n_0_[4] ),
        .O(\sig_predict_addr_lsh_ireg3[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \sig_predict_addr_lsh_ireg3[7]_i_5 
       (.I0(sig_mbaa_addr_cntr_slice_im0[3]),
        .I1(\sig_addr_cntr_incr_ireg2_reg_n_0_[3] ),
        .O(\sig_predict_addr_lsh_ireg3[7]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \sig_predict_addr_lsh_ireg3[7]_i_6 
       (.I0(sig_mbaa_addr_cntr_slice_im0[2]),
        .I1(\sig_addr_cntr_incr_ireg2_reg_n_0_[2] ),
        .O(\sig_predict_addr_lsh_ireg3[7]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \sig_predict_addr_lsh_ireg3[7]_i_7 
       (.I0(sig_mbaa_addr_cntr_slice_im0[1]),
        .I1(\sig_addr_cntr_incr_ireg2_reg_n_0_[1] ),
        .O(\sig_predict_addr_lsh_ireg3[7]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \sig_predict_addr_lsh_ireg3[7]_i_8 
       (.I0(sig_mbaa_addr_cntr_slice_im0[0]),
        .I1(\sig_addr_cntr_incr_ireg2_reg_n_0_[0] ),
        .O(\sig_predict_addr_lsh_ireg3[7]_i_8_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[0]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[0] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[10] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[10]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[10] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[11] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[11]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[11] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[12] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[12]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[12] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[13] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[13]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[13] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[14] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[14]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[14] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[15] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[15]),
        .Q(sig_predict_addr_lsh_ireg3),
        .R(sig_init_reg));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \sig_predict_addr_lsh_ireg3_reg[15]_i_1 
       (.CI(\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0 ),
        .CI_TOP(1'b0),
        .CO({\NLW_sig_predict_addr_lsh_ireg3_reg[15]_i_1_CO_UNCONNECTED [7],\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_1 ,\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_2 ,\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_3 ,\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_4 ,\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_5 ,\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_6 ,\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_7 }),
        .DI({1'b0,\sig_addr_cntr_lsh_im0_reg_n_0_[14] ,\sig_addr_cntr_lsh_im0_reg_n_0_[13] ,\sig_addr_cntr_lsh_im0_reg_n_0_[12] ,\sig_addr_cntr_lsh_im0_reg_n_0_[11] ,\sig_addr_cntr_lsh_im0_reg_n_0_[10] ,\sig_addr_cntr_lsh_im0_reg_n_0_[9] ,\sig_addr_cntr_lsh_im0_reg_n_0_[8] }),
        .O(sig_predict_addr_lsh_im2[15:8]),
        .S({p_1_in_0,\sig_addr_cntr_lsh_im0_reg_n_0_[14] ,\sig_addr_cntr_lsh_im0_reg_n_0_[13] ,\sig_addr_cntr_lsh_im0_reg_n_0_[12] ,\sig_addr_cntr_lsh_im0_reg_n_0_[11] ,\sig_addr_cntr_lsh_im0_reg_n_0_[10] ,\sig_addr_cntr_lsh_im0_reg_n_0_[9] ,\sig_addr_cntr_lsh_im0_reg_n_0_[8] }));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[1]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[1] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[2]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[2] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[3]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[3] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[4]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[4] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[5]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[5] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[6]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[6] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[7] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[7]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[7] ),
        .R(sig_init_reg));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \sig_predict_addr_lsh_ireg3_reg[7]_i_1 
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_1 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_2 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_3 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_4 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_5 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_6 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_7 }),
        .DI({\sig_addr_cntr_lsh_im0_reg_n_0_[7] ,\sig_addr_cntr_lsh_im0_reg_n_0_[6] ,sig_mbaa_addr_cntr_slice_im0}),
        .O(sig_predict_addr_lsh_im2[7:0]),
        .S({\sig_addr_cntr_lsh_im0_reg_n_0_[7] ,\sig_predict_addr_lsh_ireg3[7]_i_2_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_3_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_4_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_5_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_6_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_7_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_8_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[8] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[8]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[8] ),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_predict_addr_lsh_ireg3_reg[9] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_predict_addr_lsh_im2[9]),
        .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[9] ),
        .R(sig_init_reg));
  LUT4 #(
    .INIT(16'hFEEE)) 
    sig_sm_halt_reg_i_1
       (.I0(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[0] ),
        .I1(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[7] ),
        .I2(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[6] ),
        .I3(sig_calc_error_pushed),
        .O(sig_sm_halt_ns));
  FDSE #(
    .INIT(1'b0)) 
    sig_sm_halt_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_sm_halt_ns),
        .Q(sig_sm_halt_reg),
        .S(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    sig_sm_ld_calc2_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_sm_ld_calc2_reg_ns),
        .Q(sig_sm_ld_calc2_reg),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    sig_sm_ld_calc3_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_sm_ld_calc2_reg),
        .Q(sig_sm_ld_calc3_reg),
        .R(sig_init_reg));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT3 #(
    .INIT(8'h40)) 
    sig_sm_pop_input_reg_i_1
       (.I0(sig_calc_error_pushed),
        .I1(sig_parent_done),
        .I2(\FSM_onehot_sig_pcc_sm_state_reg_n_0_[6] ),
        .O(sig_sm_pop_input_reg_ns));
  FDRE #(
    .INIT(1'b0)) 
    sig_sm_pop_input_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_sm_pop_input_reg_ns),
        .Q(sig_sm_pop_input_reg),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strbgen_addr_ireg2_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(sig_mbaa_addr_cntr_slice_im0[0]),
        .Q(sig_strbgen_addr_ireg2[0]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strbgen_addr_ireg2_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(sig_mbaa_addr_cntr_slice_im0[1]),
        .Q(sig_strbgen_addr_ireg2[1]),
        .R(sig_init_reg));
  LUT2 #(
    .INIT(4'hE)) 
    \sig_strbgen_bytes_ireg2[1]_i_1 
       (.I0(sig_strbgen_bytes_ireg2),
        .I1(sig_init_reg),
        .O(\sig_strbgen_bytes_ireg2[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA8)) 
    \sig_strbgen_bytes_ireg2[1]_i_2 
       (.I0(sig_sm_ld_calc2_reg),
        .I1(\sig_addr_cntr_incr_ireg2[3]_i_1_n_0 ),
        .I2(\sig_addr_cntr_incr_ireg2[6]_i_1_n_0 ),
        .I3(\sig_addr_cntr_incr_ireg2[4]_i_1_n_0 ),
        .I4(\sig_addr_cntr_incr_ireg2[5]_i_1_n_0 ),
        .I5(\sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ),
        .O(sig_strbgen_bytes_ireg2));
  LUT4 #(
    .INIT(16'hFBF8)) 
    \sig_strbgen_bytes_ireg2[2]_i_1 
       (.I0(\sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ),
        .I1(sig_sm_ld_calc2_reg),
        .I2(sig_strbgen_bytes_ireg2),
        .I3(\sig_strbgen_bytes_ireg2_reg_n_0_[2] ),
        .O(\sig_strbgen_bytes_ireg2[2]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strbgen_bytes_ireg2_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(\sig_addr_cntr_incr_ireg2[0]_i_1_n_0 ),
        .Q(\sig_strbgen_bytes_ireg2_reg_n_0_[0] ),
        .R(\sig_strbgen_bytes_ireg2[1]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strbgen_bytes_ireg2_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc2_reg),
        .D(\sig_addr_cntr_incr_ireg2[1]_i_1_n_0 ),
        .Q(\sig_strbgen_bytes_ireg2_reg_n_0_[1] ),
        .R(\sig_strbgen_bytes_ireg2[1]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strbgen_bytes_ireg2_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\sig_strbgen_bytes_ireg2[2]_i_1_n_0 ),
        .Q(\sig_strbgen_bytes_ireg2_reg_n_0_[2] ),
        .R(sig_init_reg));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \sig_xfer_end_strb_ireg3[1]_i_1 
       (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ),
        .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ),
        .O(\sig_xfer_end_strb_ireg3[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \sig_xfer_end_strb_ireg3[3]_i_1 
       (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ),
        .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ),
        .O(\sig_xfer_end_strb_ireg3[3]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_xfer_end_strb_ireg3_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(1'b1),
        .Q(sig_xfer_end_strb_ireg3[0]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_xfer_end_strb_ireg3_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(\sig_xfer_end_strb_ireg3[1]_i_1_n_0 ),
        .Q(sig_xfer_end_strb_ireg3[1]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_xfer_end_strb_ireg3_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_last_addr_offset_im2__0),
        .Q(sig_xfer_end_strb_ireg3[2]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_xfer_end_strb_ireg3_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(\sig_xfer_end_strb_ireg3[3]_i_1_n_0 ),
        .Q(sig_xfer_end_strb_ireg3[3]),
        .R(sig_init_reg));
  LUT6 #(
    .INIT(64'h0000000001010110)) 
    sig_xfer_len_eq_0_ireg3_i_1
       (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ),
        .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ),
        .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ),
        .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ),
        .I4(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ),
        .I5(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ),
        .O(sig_xfer_len_eq_0_im2));
  FDRE #(
    .INIT(1'b0)) 
    sig_xfer_len_eq_0_ireg3_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_xfer_len_eq_0_im2),
        .Q(sig_xfer_len_eq_0_ireg3),
        .R(sig_init_reg));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT4 #(
    .INIT(16'hBFAE)) 
    sig_xfer_reg_empty_i_1
       (.I0(sig_init_reg),
        .I1(sig_xfer_reg_empty),
        .I2(sig_ld_xfer_reg),
        .I3(\FSM_onehot_sig_pcc_sm_state[6]_i_2_n_0 ),
        .O(sig_xfer_reg_empty_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_xfer_reg_empty_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_xfer_reg_empty_i_1_n_0),
        .Q(sig_xfer_reg_empty),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT4 #(
    .INIT(16'h00FE)) 
    \sig_xfer_strt_strb_ireg3[1]_i_1 
       (.I0(\sig_strbgen_bytes_ireg2_reg_n_0_[1] ),
        .I1(\sig_strbgen_bytes_ireg2_reg_n_0_[2] ),
        .I2(sig_strbgen_addr_ireg2[0]),
        .I3(sig_strbgen_addr_ireg2[1]),
        .O(\sig_xfer_strt_strb_ireg3[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT5 #(
    .INIT(32'h1555FEF0)) 
    \sig_xfer_strt_strb_ireg3[2]_i_1 
       (.I0(sig_strbgen_addr_ireg2[0]),
        .I1(\sig_strbgen_bytes_ireg2_reg_n_0_[0] ),
        .I2(\sig_strbgen_bytes_ireg2_reg_n_0_[2] ),
        .I3(\sig_strbgen_bytes_ireg2_reg_n_0_[1] ),
        .I4(sig_strbgen_addr_ireg2[1]),
        .O(sig_xfer_strt_strb_im2));
  FDRE #(
    .INIT(1'b0)) 
    \sig_xfer_strt_strb_ireg3_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(\GEN_4BIT_CASE.lsig_start_vect ),
        .Q(sig_xfer_strt_strb_ireg3[0]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_xfer_strt_strb_ireg3_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(\sig_xfer_strt_strb_ireg3[1]_i_1_n_0 ),
        .Q(sig_xfer_strt_strb_ireg3[1]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_xfer_strt_strb_ireg3_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(sig_xfer_strt_strb_im2),
        .Q(sig_xfer_strt_strb_ireg3[2]),
        .R(sig_init_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_xfer_strt_strb_ireg3_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_sm_ld_calc3_reg),
        .D(\GEN_4BIT_CASE.lsig_end_vect ),
        .Q(sig_xfer_strt_strb_ireg3[3]),
        .R(sig_init_reg));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_rd_sf
   (full,
    dout,
    empty,
    FIFO_Full_reg,
    sig_init_done,
    sig_sf_allow_addr_req,
    \OMIT_UNPACKING.lsig_cmd_loaded ,
    sig_inhibit_rdy_n_reg,
    sig_inhibit_rdy_n,
    sig_last_skid_mux_out,
    sig_slast_with_stop,
    \gen_fwft.empty_fwft_i_reg ,
    SS,
    m_axi_mm2s_aclk,
    wr_en,
    din,
    sig_init_done_reg,
    sig_mstr2sf_cmd_valid,
    sig_sstrb_stop_mask,
    out,
    sig_last_skid_reg,
    \OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ,
    sig_ok_to_post_rd_addr_reg_0,
    \sig_token_cntr_reg[2]_0 ,
    sig_mmap_rst_reg_n);
  output full;
  output [35:0]dout;
  output empty;
  output FIFO_Full_reg;
  output sig_init_done;
  output sig_sf_allow_addr_req;
  output \OMIT_UNPACKING.lsig_cmd_loaded ;
  output sig_inhibit_rdy_n_reg;
  output sig_inhibit_rdy_n;
  output sig_last_skid_mux_out;
  output sig_slast_with_stop;
  output \gen_fwft.empty_fwft_i_reg ;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input wr_en;
  input [37:0]din;
  input sig_init_done_reg;
  input sig_mstr2sf_cmd_valid;
  input [0:0]sig_sstrb_stop_mask;
  input out;
  input sig_last_skid_reg;
  input \OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ;
  input sig_ok_to_post_rd_addr_reg_0;
  input \sig_token_cntr_reg[2]_0 ;
  input sig_mmap_rst_reg_n;

  wire FIFO_Full_reg;
  wire I_DATA_FIFO_n_40;
  wire I_DATA_FIFO_n_41;
  wire I_DATA_FIFO_n_43;
  wire I_DATA_FIFO_n_44;
  wire \OMIT_UNPACKING.lsig_cmd_loaded ;
  wire \OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ;
  wire [0:0]SS;
  wire \USE_SRL_FIFO.sig_rd_empty ;
  wire [37:0]din;
  wire [35:0]dout;
  wire empty;
  wire full;
  wire \gen_fwft.empty_fwft_i_reg ;
  wire m_axi_mm2s_aclk;
  wire out;
  wire sig_inhibit_rdy_n;
  wire sig_inhibit_rdy_n_reg;
  wire sig_init_done;
  wire sig_init_done_reg;
  wire sig_last_skid_mux_out;
  wire sig_last_skid_reg;
  wire sig_mmap_rst_reg_n;
  wire sig_mstr2sf_cmd_valid;
  wire sig_ok_to_post_rd_addr_i_2_n_0;
  wire sig_ok_to_post_rd_addr_i_5_n_0;
  wire sig_ok_to_post_rd_addr_reg_0;
  wire sig_sf_allow_addr_req;
  wire sig_slast_with_stop;
  wire [0:0]sig_sstrb_stop_mask;
  wire \sig_token_cntr[0]_i_1_n_0 ;
  wire \sig_token_cntr[1]_i_1_n_0 ;
  wire \sig_token_cntr[2]_i_1_n_0 ;
  wire \sig_token_cntr[3]_i_1_n_0 ;
  wire \sig_token_cntr[3]_i_2_n_0 ;
  wire [3:0]sig_token_cntr_reg;
  wire \sig_token_cntr_reg[2]_0 ;
  wire wr_en;

  Loopback_axi_dma_1_0_axi_datamover_sfifo_autord I_DATA_FIFO
       (.\INFERRED_GEN.cnt_i_reg[2] (I_DATA_FIFO_n_44),
        .\OMIT_UNPACKING.lsig_cmd_loaded_reg (\OMIT_UNPACKING.lsig_cmd_loaded ),
        .\OMIT_UNPACKING.lsig_cmd_loaded_reg_0 (\OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ),
        .Q(\USE_SRL_FIFO.sig_rd_empty ),
        .SS(SS),
        .din(din),
        .dout(dout),
        .empty(empty),
        .full(full),
        .\gen_fwft.empty_fwft_i_reg (\gen_fwft.empty_fwft_i_reg ),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .out(out),
        .sig_last_skid_mux_out(sig_last_skid_mux_out),
        .sig_last_skid_reg(sig_last_skid_reg),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_i_2_n_0),
        .sig_ok_to_post_rd_addr_reg_0(sig_ok_to_post_rd_addr_reg_0),
        .sig_ok_to_post_rd_addr_reg_1(sig_token_cntr_reg),
        .sig_ok_to_post_rd_addr_reg_2(sig_ok_to_post_rd_addr_i_5_n_0),
        .sig_posted_to_axi_2_reg(I_DATA_FIFO_n_43),
        .sig_s_ready_out_reg(I_DATA_FIFO_n_40),
        .sig_s_ready_out_reg_0(I_DATA_FIFO_n_41),
        .sig_slast_with_stop(sig_slast_with_stop),
        .sig_sstrb_stop_mask(sig_sstrb_stop_mask),
        .wr_en(wr_en));
  Loopback_axi_dma_1_0_axi_datamover_fifo__parameterized3 \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO 
       (.FIFO_Full_reg(FIFO_Full_reg),
        .FIFO_Full_reg_0(\OMIT_UNPACKING.lsig_cmd_loaded ),
        .\INFERRED_GEN.cnt_i_reg[1] (I_DATA_FIFO_n_40),
        .\INFERRED_GEN.cnt_i_reg[2] (I_DATA_FIFO_n_41),
        .Q(\USE_SRL_FIFO.sig_rd_empty ),
        .SS(SS),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .sig_inhibit_rdy_n_reg_0(sig_inhibit_rdy_n_reg),
        .sig_inhibit_rdy_n_reg_1(sig_inhibit_rdy_n),
        .sig_init_done(sig_init_done),
        .sig_init_done_reg_0(sig_init_done_reg),
        .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid));
  FDRE #(
    .INIT(1'b0)) 
    \OMIT_UNPACKING.lsig_cmd_loaded_reg 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(I_DATA_FIFO_n_44),
        .Q(\OMIT_UNPACKING.lsig_cmd_loaded ),
        .R(SS));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    sig_ok_to_post_rd_addr_i_2
       (.I0(sig_token_cntr_reg[3]),
        .I1(sig_token_cntr_reg[2]),
        .I2(sig_token_cntr_reg[1]),
        .I3(sig_token_cntr_reg[0]),
        .O(sig_ok_to_post_rd_addr_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    sig_ok_to_post_rd_addr_i_5
       (.I0(sig_token_cntr_reg[2]),
        .I1(sig_token_cntr_reg[3]),
        .I2(sig_token_cntr_reg[1]),
        .I3(sig_token_cntr_reg[0]),
        .O(sig_ok_to_post_rd_addr_i_5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_ok_to_post_rd_addr_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(I_DATA_FIFO_n_43),
        .Q(sig_sf_allow_addr_req),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \sig_token_cntr[0]_i_1 
       (.I0(sig_token_cntr_reg[0]),
        .O(\sig_token_cntr[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAFF55005500B8FF)) 
    \sig_token_cntr[1]_i_1 
       (.I0(sig_ok_to_post_rd_addr_reg_0),
        .I1(sig_token_cntr_reg[2]),
        .I2(sig_token_cntr_reg[3]),
        .I3(\sig_token_cntr_reg[2]_0 ),
        .I4(sig_token_cntr_reg[0]),
        .I5(sig_token_cntr_reg[1]),
        .O(\sig_token_cntr[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBDBDFCFC43400303)) 
    \sig_token_cntr[2]_i_1 
       (.I0(sig_ok_to_post_rd_addr_reg_0),
        .I1(sig_token_cntr_reg[0]),
        .I2(sig_token_cntr_reg[1]),
        .I3(sig_token_cntr_reg[3]),
        .I4(\sig_token_cntr_reg[2]_0 ),
        .I5(sig_token_cntr_reg[2]),
        .O(\sig_token_cntr[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5555555EAAAAAAA2)) 
    \sig_token_cntr[3]_i_1 
       (.I0(\sig_token_cntr_reg[2]_0 ),
        .I1(sig_token_cntr_reg[3]),
        .I2(sig_token_cntr_reg[2]),
        .I3(sig_token_cntr_reg[1]),
        .I4(sig_token_cntr_reg[0]),
        .I5(sig_ok_to_post_rd_addr_reg_0),
        .O(\sig_token_cntr[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCCCC6CCCCCC1CCC1)) 
    \sig_token_cntr[3]_i_2 
       (.I0(\sig_token_cntr_reg[2]_0 ),
        .I1(sig_token_cntr_reg[3]),
        .I2(sig_token_cntr_reg[1]),
        .I3(sig_token_cntr_reg[0]),
        .I4(sig_ok_to_post_rd_addr_reg_0),
        .I5(sig_token_cntr_reg[2]),
        .O(\sig_token_cntr[3]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_token_cntr_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_token_cntr[3]_i_1_n_0 ),
        .D(\sig_token_cntr[0]_i_1_n_0 ),
        .Q(sig_token_cntr_reg[0]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \sig_token_cntr_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_token_cntr[3]_i_1_n_0 ),
        .D(\sig_token_cntr[1]_i_1_n_0 ),
        .Q(sig_token_cntr_reg[1]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \sig_token_cntr_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_token_cntr[3]_i_1_n_0 ),
        .D(\sig_token_cntr[2]_i_1_n_0 ),
        .Q(sig_token_cntr_reg[2]),
        .R(SS));
  FDSE #(
    .INIT(1'b0)) 
    \sig_token_cntr_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_token_cntr[3]_i_1_n_0 ),
        .D(\sig_token_cntr[3]_i_2_n_0 ),
        .Q(sig_token_cntr_reg[3]),
        .S(SS));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_rd_status_cntl
   (sig_rd_sts_slverr_reg_reg_0,
    sig_rsc2stat_status_valid,
    sig_rsc2data_ready,
    sig_coelsc_tag_reg,
    m_axi_mm2s_aclk,
    sig_rd_sts_interr_reg0,
    sig_rd_sts_slverr_reg0,
    sig_stat2rsc_status_ready,
    sig_mmap_rst_reg_n,
    sig_data2rsc_decerr,
    sig_data2rsc_valid);
  output [3:0]sig_rd_sts_slverr_reg_reg_0;
  output sig_rsc2stat_status_valid;
  output sig_rsc2data_ready;
  input [0:0]sig_coelsc_tag_reg;
  input m_axi_mm2s_aclk;
  input sig_rd_sts_interr_reg0;
  input sig_rd_sts_slverr_reg0;
  input sig_stat2rsc_status_ready;
  input sig_mmap_rst_reg_n;
  input sig_data2rsc_decerr;
  input sig_data2rsc_valid;

  wire m_axi_mm2s_aclk;
  wire [0:0]sig_coelsc_tag_reg;
  wire sig_data2rsc_decerr;
  wire sig_data2rsc_valid;
  wire sig_mmap_rst_reg_n;
  wire sig_push_rd_sts_reg;
  wire sig_rd_sts_decerr_reg0;
  wire sig_rd_sts_interr_reg0;
  wire sig_rd_sts_slverr_reg0;
  wire [3:0]sig_rd_sts_slverr_reg_reg_0;
  wire sig_rd_sts_tag_reg0;
  wire sig_rsc2data_ready;
  wire sig_rsc2stat_status_valid;
  wire sig_stat2rsc_status_ready;

  LUT2 #(
    .INIT(4'hE)) 
    sig_rd_sts_decerr_reg_i_1__0
       (.I0(sig_rd_sts_slverr_reg_reg_0[2]),
        .I1(sig_data2rsc_decerr),
        .O(sig_rd_sts_decerr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_rd_sts_decerr_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_rd_sts_reg),
        .D(sig_rd_sts_decerr_reg0),
        .Q(sig_rd_sts_slverr_reg_reg_0[2]),
        .R(sig_rd_sts_tag_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_rd_sts_interr_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_rd_sts_reg),
        .D(sig_rd_sts_interr_reg0),
        .Q(sig_rd_sts_slverr_reg_reg_0[1]),
        .R(sig_rd_sts_tag_reg0));
  FDSE #(
    .INIT(1'b0)) 
    sig_rd_sts_reg_empty_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_rd_sts_reg),
        .D(1'b0),
        .Q(sig_rsc2data_ready),
        .S(sig_rd_sts_tag_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_rd_sts_reg_full_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_rd_sts_reg),
        .D(1'b1),
        .Q(sig_rsc2stat_status_valid),
        .R(sig_rd_sts_tag_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_rd_sts_slverr_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_rd_sts_reg),
        .D(sig_rd_sts_slverr_reg0),
        .Q(sig_rd_sts_slverr_reg_reg_0[3]),
        .R(sig_rd_sts_tag_reg0));
  LUT3 #(
    .INIT(8'h8F)) 
    \sig_rd_sts_tag_reg[0]_i_1 
       (.I0(sig_rsc2stat_status_valid),
        .I1(sig_stat2rsc_status_ready),
        .I2(sig_mmap_rst_reg_n),
        .O(sig_rd_sts_tag_reg0));
  LUT2 #(
    .INIT(4'h8)) 
    \sig_rd_sts_tag_reg[0]_i_2 
       (.I0(sig_rsc2data_ready),
        .I1(sig_data2rsc_valid),
        .O(sig_push_rd_sts_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_rd_sts_tag_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_rd_sts_reg),
        .D(sig_coelsc_tag_reg),
        .Q(sig_rd_sts_slverr_reg_reg_0[0]),
        .R(sig_rd_sts_tag_reg0));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_rddata_cntl
   (sig_coelsc_tag_reg,
    FIFO_Full_reg,
    sig_data2rsc_valid,
    sig_last_mmap_dbeat_reg_reg_0,
    sig_data2addr_stop_req,
    sig_halt_reg_dly2,
    sig_halt_reg_dly3,
    sig_data2rsc_decerr,
    sig_init_done,
    sig_rd_sts_interr_reg0,
    sig_rd_sts_slverr_reg0,
    sig_inhibit_rdy_n,
    FIFO_Full_reg_0,
    din,
    wr_en,
    m_axi_mm2s_rready,
    \sig_addr_posted_cntr_reg[2]_0 ,
    sig_halt_reg_dly2_reg_0,
    sig_halt_reg_dly3_reg_0,
    m_axi_mm2s_aclk,
    SS,
    sig_init_done_reg,
    sig_mmap_rst_reg_n,
    sig_rd_sts_slverr_reg_reg,
    sig_mstr2data_cmd_valid,
    m_axi_mm2s_rlast,
    sig_rsc2stat_status_valid,
    sig_stat2rsc_status_ready,
    \sig_addr_posted_cntr_reg[1]_0 ,
    m_axi_mm2s_rvalid,
    full,
    sig_rsc2data_ready,
    sig_stream_rst_reg_n,
    sig_sstrb_stop_mask,
    sig_s_ready_dup_reg,
    m_axi_mm2s_rresp,
    in,
    sig_rst2all_stop_request);
  output [0:0]sig_coelsc_tag_reg;
  output FIFO_Full_reg;
  output sig_data2rsc_valid;
  output sig_last_mmap_dbeat_reg_reg_0;
  output sig_data2addr_stop_req;
  output sig_halt_reg_dly2;
  output sig_halt_reg_dly3;
  output sig_data2rsc_decerr;
  output sig_init_done;
  output sig_rd_sts_interr_reg0;
  output sig_rd_sts_slverr_reg0;
  output sig_inhibit_rdy_n;
  output FIFO_Full_reg_0;
  output [5:0]din;
  output wr_en;
  output m_axi_mm2s_rready;
  output \sig_addr_posted_cntr_reg[2]_0 ;
  output sig_halt_reg_dly2_reg_0;
  output sig_halt_reg_dly3_reg_0;
  input m_axi_mm2s_aclk;
  input [0:0]SS;
  input sig_init_done_reg;
  input sig_mmap_rst_reg_n;
  input [1:0]sig_rd_sts_slverr_reg_reg;
  input sig_mstr2data_cmd_valid;
  input m_axi_mm2s_rlast;
  input sig_rsc2stat_status_valid;
  input sig_stat2rsc_status_ready;
  input \sig_addr_posted_cntr_reg[1]_0 ;
  input m_axi_mm2s_rvalid;
  input full;
  input sig_rsc2data_ready;
  input sig_stream_rst_reg_n;
  input [0:0]sig_sstrb_stop_mask;
  input sig_s_ready_dup_reg;
  input [1:0]m_axi_mm2s_rresp;
  input [16:0]in;
  input sig_rst2all_stop_request;

  wire FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_11 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_12 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_13 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_14 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_15 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_30 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_31 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_32 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ;
  wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9 ;
  wire [0:0]SS;
  wire [5:0]din;
  wire full;
  wire [16:0]in;
  wire m_axi_mm2s_aclk;
  wire m_axi_mm2s_rlast;
  wire m_axi_mm2s_rready;
  wire [1:0]m_axi_mm2s_rresp;
  wire m_axi_mm2s_rvalid;
  wire [2:0]sig_addr_posted_cntr;
  wire \sig_addr_posted_cntr[0]_i_1__0_n_0 ;
  wire \sig_addr_posted_cntr[1]_i_1__0_n_0 ;
  wire \sig_addr_posted_cntr[2]_i_1__0_n_0 ;
  wire \sig_addr_posted_cntr[2]_i_2__0_n_0 ;
  wire \sig_addr_posted_cntr_reg[1]_0 ;
  wire \sig_addr_posted_cntr_reg[2]_0 ;
  wire sig_clr_dqual_reg;
  wire sig_cmd_cmplt_last_dbeat;
  wire [26:0]sig_cmd_fifo_data_out;
  wire sig_coelsc_decerr_reg0;
  wire sig_coelsc_interr_reg0;
  wire sig_coelsc_slverr_reg0;
  wire [0:0]sig_coelsc_tag_reg;
  wire sig_coelsc_tag_reg0;
  wire sig_data2addr_stop_req;
  wire sig_data2rsc_calc_err;
  wire sig_data2rsc_decerr;
  wire sig_data2rsc_slverr;
  wire sig_data2rsc_valid;
  wire [7:0]sig_dbeat_cntr;
  wire \sig_dbeat_cntr[5]_i_2_n_0 ;
  wire \sig_dbeat_cntr[7]_i_3__0_n_0 ;
  wire \sig_dbeat_cntr[7]_i_4__0_n_0 ;
  wire \sig_dbeat_cntr[7]_i_5_n_0 ;
  wire \sig_dbeat_cntr[7]_i_6_n_0 ;
  wire \sig_dbeat_cntr[7]_i_7_n_0 ;
  wire sig_dqual_reg_empty;
  wire sig_dqual_reg_full;
  wire sig_first_dbeat_reg_n_0;
  wire sig_halt_reg_dly1;
  wire sig_halt_reg_dly2;
  wire sig_halt_reg_dly2_reg_0;
  wire sig_halt_reg_dly3;
  wire sig_halt_reg_dly3_reg_0;
  wire sig_halt_reg_i_1_n_0;
  wire sig_inhibit_rdy_n;
  wire sig_init_done;
  wire sig_init_done_reg;
  wire sig_last_dbeat_i_3_n_0;
  wire sig_last_dbeat_i_4_n_0;
  wire sig_last_dbeat_reg_n_0;
  wire sig_last_mmap_dbeat;
  wire sig_last_mmap_dbeat_reg_reg_0;
  wire sig_ld_new_cmd_reg;
  wire sig_mmap_rst_reg_n;
  wire sig_mstr2data_cmd_valid;
  wire sig_next_calc_error_reg;
  wire sig_next_cmd_cmplt_reg;
  wire sig_next_eof_reg;
  wire [3:0]sig_next_last_strb_reg;
  wire sig_next_sequential_reg;
  wire [3:0]sig_next_strt_strb_reg;
  wire [0:0]sig_next_tag_reg;
  wire sig_push_coelsc_reg;
  wire sig_push_dqual_reg;
  wire sig_rd_sts_interr_reg0;
  wire sig_rd_sts_slverr_reg0;
  wire [1:0]sig_rd_sts_slverr_reg_reg;
  wire sig_rsc2data_ready;
  wire sig_rsc2stat_status_valid;
  wire sig_rst2all_stop_request;
  wire sig_s_ready_dup_reg;
  wire [0:0]sig_sstrb_stop_mask;
  wire sig_stat2rsc_status_ready;
  wire sig_stream_rst_reg_n;
  wire wr_en;
  wire \xpm_fifo_instance.xpm_fifo_sync_inst_i_10_n_0 ;

  Loopback_axi_dma_1_0_axi_datamover_fifo__parameterized2 \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO 
       (.D({\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_11 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_12 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_13 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_14 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_15 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 }),
        .E(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ),
        .FIFO_Full_reg(FIFO_Full_reg),
        .FIFO_Full_reg_0(FIFO_Full_reg_0),
        .Q(sig_dbeat_cntr),
        .SR(sig_clr_dqual_reg),
        .SS(SS),
        .full(full),
        .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg (\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ),
        .in(in),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axi_mm2s_rlast(m_axi_mm2s_rlast),
        .m_axi_mm2s_rready(sig_addr_posted_cntr),
        .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid),
        .out({sig_cmd_fifo_data_out[26:23],sig_cmd_fifo_data_out[21:14],sig_cmd_fifo_data_out[0]}),
        .\sig_dbeat_cntr_reg[5] (\sig_dbeat_cntr[5]_i_2_n_0 ),
        .\sig_dbeat_cntr_reg[6] (\sig_dbeat_cntr[7]_i_4__0_n_0 ),
        .sig_dqual_reg_empty(sig_dqual_reg_empty),
        .sig_dqual_reg_empty_reg(sig_last_dbeat_reg_n_0),
        .sig_dqual_reg_empty_reg_0(sig_data2addr_stop_req),
        .sig_dqual_reg_empty_reg_1(sig_data2rsc_valid),
        .sig_dqual_reg_full(sig_dqual_reg_full),
        .sig_first_dbeat_reg(sig_first_dbeat_reg_n_0),
        .sig_first_dbeat_reg_0(\sig_dbeat_cntr[7]_i_3__0_n_0 ),
        .sig_inhibit_rdy_n_reg_0(sig_inhibit_rdy_n),
        .sig_init_done(sig_init_done),
        .sig_init_done_reg_0(sig_init_done_reg),
        .sig_last_dbeat_reg(sig_last_dbeat_i_3_n_0),
        .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mmap_rst_reg_n_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2 ),
        .sig_mmap_rst_reg_n_reg_0(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_30 ),
        .sig_mmap_rst_reg_n_reg_1(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_32 ),
        .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid),
        .sig_next_calc_error_reg(sig_next_calc_error_reg),
        .sig_next_calc_error_reg_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_31 ),
        .sig_next_sequential_reg(sig_next_sequential_reg),
        .sig_push_dqual_reg(sig_push_dqual_reg),
        .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid),
        .sig_stat2rsc_status_ready(sig_stat2rsc_status_ready));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT4 #(
    .INIT(16'h0045)) 
    m_axi_mm2s_rready_INST_0
       (.I0(sig_data2rsc_valid),
        .I1(sig_data2addr_stop_req),
        .I2(full),
        .I3(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_31 ),
        .O(m_axi_mm2s_rready));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \sig_addr_posted_cntr[0]_i_1__0 
       (.I0(sig_addr_posted_cntr[0]),
        .O(\sig_addr_posted_cntr[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT5 #(
    .INIT(32'hF4B44B4B)) 
    \sig_addr_posted_cntr[1]_i_1__0 
       (.I0(sig_last_mmap_dbeat_reg_reg_0),
        .I1(\sig_addr_posted_cntr_reg[1]_0 ),
        .I2(sig_addr_posted_cntr[1]),
        .I3(sig_addr_posted_cntr[2]),
        .I4(sig_addr_posted_cntr[0]),
        .O(\sig_addr_posted_cntr[1]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00FE7F00)) 
    \sig_addr_posted_cntr[2]_i_1__0 
       (.I0(sig_addr_posted_cntr[2]),
        .I1(sig_addr_posted_cntr[1]),
        .I2(sig_addr_posted_cntr[0]),
        .I3(\sig_addr_posted_cntr_reg[1]_0 ),
        .I4(sig_last_mmap_dbeat_reg_reg_0),
        .O(\sig_addr_posted_cntr[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT5 #(
    .INIT(32'hA9EAA9A9)) 
    \sig_addr_posted_cntr[2]_i_2__0 
       (.I0(sig_addr_posted_cntr[2]),
        .I1(sig_addr_posted_cntr[0]),
        .I2(sig_addr_posted_cntr[1]),
        .I3(sig_last_mmap_dbeat_reg_reg_0),
        .I4(\sig_addr_posted_cntr_reg[1]_0 ),
        .O(\sig_addr_posted_cntr[2]_i_2__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_posted_cntr_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_posted_cntr[2]_i_1__0_n_0 ),
        .D(\sig_addr_posted_cntr[0]_i_1__0_n_0 ),
        .Q(sig_addr_posted_cntr[0]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_posted_cntr_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_posted_cntr[2]_i_1__0_n_0 ),
        .D(\sig_addr_posted_cntr[1]_i_1__0_n_0 ),
        .Q(sig_addr_posted_cntr[1]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_posted_cntr_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(\sig_addr_posted_cntr[2]_i_1__0_n_0 ),
        .D(\sig_addr_posted_cntr[2]_i_2__0_n_0 ),
        .Q(sig_addr_posted_cntr[2]),
        .R(SS));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    sig_coelsc_cmd_cmplt_reg_i_1
       (.I0(sig_next_cmd_cmplt_reg),
        .I1(m_axi_mm2s_rlast),
        .I2(sig_next_calc_error_reg),
        .O(sig_cmd_cmplt_last_dbeat));
  FDRE #(
    .INIT(1'b0)) 
    sig_coelsc_cmd_cmplt_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_coelsc_reg),
        .D(sig_cmd_cmplt_last_dbeat),
        .Q(sig_data2rsc_valid),
        .R(sig_coelsc_tag_reg0));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT4 #(
    .INIT(16'hFF80)) 
    sig_coelsc_decerr_reg_i_1
       (.I0(m_axi_mm2s_rresp[0]),
        .I1(m_axi_mm2s_rresp[1]),
        .I2(m_axi_mm2s_rvalid),
        .I3(sig_data2rsc_decerr),
        .O(sig_coelsc_decerr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_coelsc_decerr_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_coelsc_reg),
        .D(sig_coelsc_decerr_reg0),
        .Q(sig_data2rsc_decerr),
        .R(sig_coelsc_tag_reg0));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT2 #(
    .INIT(4'hE)) 
    sig_coelsc_interr_reg_i_1
       (.I0(sig_data2rsc_calc_err),
        .I1(sig_next_calc_error_reg),
        .O(sig_coelsc_interr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_coelsc_interr_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_coelsc_reg),
        .D(sig_coelsc_interr_reg0),
        .Q(sig_data2rsc_calc_err),
        .R(sig_coelsc_tag_reg0));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT4 #(
    .INIT(16'hFF40)) 
    sig_coelsc_slverr_reg_i_1
       (.I0(m_axi_mm2s_rresp[0]),
        .I1(m_axi_mm2s_rresp[1]),
        .I2(m_axi_mm2s_rvalid),
        .I3(sig_data2rsc_slverr),
        .O(sig_coelsc_slverr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_coelsc_slverr_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_coelsc_reg),
        .D(sig_coelsc_slverr_reg0),
        .Q(sig_data2rsc_slverr),
        .R(sig_coelsc_tag_reg0));
  LUT6 #(
    .INIT(64'h07000000FFFFFFFF)) 
    \sig_coelsc_tag_reg[0]_i_1 
       (.I0(sig_next_calc_error_reg),
        .I1(sig_ld_new_cmd_reg),
        .I2(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ),
        .I3(sig_rsc2data_ready),
        .I4(sig_data2rsc_valid),
        .I5(sig_mmap_rst_reg_n),
        .O(sig_coelsc_tag_reg0));
  LUT3 #(
    .INIT(8'hF8)) 
    \sig_coelsc_tag_reg[0]_i_2 
       (.I0(sig_next_calc_error_reg),
        .I1(sig_ld_new_cmd_reg),
        .I2(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ),
        .O(sig_push_coelsc_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_coelsc_tag_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_coelsc_reg),
        .D(sig_next_tag_reg),
        .Q(sig_coelsc_tag_reg),
        .R(sig_coelsc_tag_reg0));
  LUT2 #(
    .INIT(4'h1)) 
    \sig_dbeat_cntr[5]_i_2 
       (.I0(sig_dbeat_cntr[0]),
        .I1(sig_dbeat_cntr[1]),
        .O(\sig_dbeat_cntr[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000D000)) 
    \sig_dbeat_cntr[7]_i_3__0 
       (.I0(\sig_dbeat_cntr[7]_i_5_n_0 ),
        .I1(\sig_dbeat_cntr[7]_i_6_n_0 ),
        .I2(\sig_dbeat_cntr[7]_i_7_n_0 ),
        .I3(m_axi_mm2s_rvalid),
        .I4(sig_data2rsc_valid),
        .I5(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_31 ),
        .O(\sig_dbeat_cntr[7]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \sig_dbeat_cntr[7]_i_4__0 
       (.I0(sig_dbeat_cntr[4]),
        .I1(sig_dbeat_cntr[3]),
        .I2(sig_dbeat_cntr[2]),
        .I3(sig_dbeat_cntr[1]),
        .I4(sig_dbeat_cntr[0]),
        .I5(sig_dbeat_cntr[5]),
        .O(\sig_dbeat_cntr[7]_i_4__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \sig_dbeat_cntr[7]_i_5 
       (.I0(sig_dbeat_cntr[3]),
        .I1(sig_dbeat_cntr[2]),
        .I2(sig_dbeat_cntr[1]),
        .I3(sig_dbeat_cntr[0]),
        .O(\sig_dbeat_cntr[7]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \sig_dbeat_cntr[7]_i_6 
       (.I0(sig_dbeat_cntr[6]),
        .I1(sig_dbeat_cntr[7]),
        .I2(sig_dbeat_cntr[5]),
        .I3(sig_dbeat_cntr[4]),
        .O(\sig_dbeat_cntr[7]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \sig_dbeat_cntr[7]_i_7 
       (.I0(sig_data2addr_stop_req),
        .I1(full),
        .O(\sig_dbeat_cntr[7]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ),
        .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ),
        .Q(sig_dbeat_cntr[0]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ),
        .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_15 ),
        .Q(sig_dbeat_cntr[1]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ),
        .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_14 ),
        .Q(sig_dbeat_cntr[2]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ),
        .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_13 ),
        .Q(sig_dbeat_cntr[3]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ),
        .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_12 ),
        .Q(sig_dbeat_cntr[4]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ),
        .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_11 ),
        .Q(sig_dbeat_cntr[5]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ),
        .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10 ),
        .Q(sig_dbeat_cntr[6]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[7] 
       (.C(m_axi_mm2s_aclk),
        .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ),
        .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9 ),
        .Q(sig_dbeat_cntr[7]),
        .R(SS));
  FDSE #(
    .INIT(1'b0)) 
    sig_dqual_reg_empty_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(1'b0),
        .Q(sig_dqual_reg_empty),
        .S(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    sig_dqual_reg_full_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(1'b1),
        .Q(sig_dqual_reg_full),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    sig_first_dbeat_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2 ),
        .Q(sig_first_dbeat_reg_n_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT4 #(
    .INIT(16'hFF01)) 
    sig_halt_cmplt_i_3
       (.I0(sig_addr_posted_cntr[2]),
        .I1(sig_addr_posted_cntr[0]),
        .I2(sig_addr_posted_cntr[1]),
        .I3(sig_next_calc_error_reg),
        .O(\sig_addr_posted_cntr_reg[2]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    sig_halt_reg_dly1_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_data2addr_stop_req),
        .Q(sig_halt_reg_dly1),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    sig_halt_reg_dly2_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_halt_reg_dly1),
        .Q(sig_halt_reg_dly2),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    sig_halt_reg_dly3_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_halt_reg_dly2),
        .Q(sig_halt_reg_dly3),
        .R(SS));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT2 #(
    .INIT(4'hE)) 
    sig_halt_reg_i_1
       (.I0(sig_rst2all_stop_request),
        .I1(sig_data2addr_stop_req),
        .O(sig_halt_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_halt_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_halt_reg_i_1_n_0),
        .Q(sig_data2addr_stop_req),
        .R(SS));
  LUT6 #(
    .INIT(64'h0040000000000000)) 
    sig_last_dbeat_i_3
       (.I0(\sig_dbeat_cntr[7]_i_6_n_0 ),
        .I1(sig_mmap_rst_reg_n),
        .I2(sig_dbeat_cntr[0]),
        .I3(sig_dbeat_cntr[1]),
        .I4(sig_last_dbeat_i_4_n_0),
        .I5(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ),
        .O(sig_last_dbeat_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT2 #(
    .INIT(4'h1)) 
    sig_last_dbeat_i_4
       (.I0(sig_dbeat_cntr[2]),
        .I1(sig_dbeat_cntr[3]),
        .O(sig_last_dbeat_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_last_dbeat_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_32 ),
        .Q(sig_last_dbeat_reg_n_0),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    sig_last_mmap_dbeat_reg_i_1__0
       (.I0(m_axi_mm2s_rlast),
        .I1(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ),
        .O(sig_last_mmap_dbeat));
  FDRE #(
    .INIT(1'b0)) 
    sig_last_mmap_dbeat_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_last_mmap_dbeat),
        .Q(sig_last_mmap_dbeat_reg_reg_0),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    sig_ld_new_cmd_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_30 ),
        .Q(sig_ld_new_cmd_reg),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    sig_next_calc_error_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[26]),
        .Q(sig_next_calc_error_reg),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    sig_next_cmd_cmplt_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[25]),
        .Q(sig_next_cmd_cmplt_reg),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    sig_next_eof_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[23]),
        .Q(sig_next_eof_reg),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_last_strb_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[18]),
        .Q(sig_next_last_strb_reg[0]),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_last_strb_reg_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[19]),
        .Q(sig_next_last_strb_reg[1]),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_last_strb_reg_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[20]),
        .Q(sig_next_last_strb_reg[2]),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_last_strb_reg_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[21]),
        .Q(sig_next_last_strb_reg[3]),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    sig_next_sequential_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[24]),
        .Q(sig_next_sequential_reg),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_strt_strb_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[14]),
        .Q(sig_next_strt_strb_reg[0]),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_strt_strb_reg_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[15]),
        .Q(sig_next_strt_strb_reg[1]),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_strt_strb_reg_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[16]),
        .Q(sig_next_strt_strb_reg[2]),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_strt_strb_reg_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[17]),
        .Q(sig_next_strt_strb_reg[3]),
        .R(sig_clr_dqual_reg));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_tag_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_push_dqual_reg),
        .D(sig_cmd_fifo_data_out[0]),
        .Q(sig_next_tag_reg),
        .R(sig_clr_dqual_reg));
  LUT2 #(
    .INIT(4'hE)) 
    sig_rd_sts_interr_reg_i_1
       (.I0(sig_data2rsc_calc_err),
        .I1(sig_rd_sts_slverr_reg_reg[0]),
        .O(sig_rd_sts_interr_reg0));
  LUT2 #(
    .INIT(4'hE)) 
    sig_rd_sts_slverr_reg_i_1
       (.I0(sig_data2rsc_slverr),
        .I1(sig_rd_sts_slverr_reg_reg[1]),
        .O(sig_rd_sts_slverr_reg0));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT5 #(
    .INIT(32'h00D00000)) 
    sig_s_ready_dup_i_1
       (.I0(sig_halt_reg_dly2),
        .I1(sig_halt_reg_dly3),
        .I2(sig_stream_rst_reg_n),
        .I3(sig_sstrb_stop_mask),
        .I4(sig_s_ready_dup_reg),
        .O(sig_halt_reg_dly2_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT3 #(
    .INIT(8'hF4)) 
    \sig_sstrb_stop_mask[3]_i_1 
       (.I0(sig_halt_reg_dly3),
        .I1(sig_halt_reg_dly2),
        .I2(sig_sstrb_stop_mask),
        .O(sig_halt_reg_dly3_reg_0));
  LUT6 #(
    .INIT(64'h0000000088888880)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_10 
       (.I0(sig_data2addr_stop_req),
        .I1(sig_dqual_reg_full),
        .I2(sig_addr_posted_cntr[2]),
        .I3(sig_addr_posted_cntr[0]),
        .I4(sig_addr_posted_cntr[1]),
        .I5(sig_next_calc_error_reg),
        .O(\xpm_fifo_instance.xpm_fifo_sync_inst_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT5 #(
    .INIT(32'h00002322)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_2 
       (.I0(sig_data2addr_stop_req),
        .I1(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_31 ),
        .I2(sig_data2rsc_valid),
        .I3(m_axi_mm2s_rvalid),
        .I4(full),
        .O(wr_en));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_3 
       (.I0(sig_next_cmd_cmplt_reg),
        .I1(m_axi_mm2s_rlast),
        .I2(\xpm_fifo_instance.xpm_fifo_sync_inst_i_10_n_0 ),
        .O(din[5]));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_4 
       (.I0(sig_next_eof_reg),
        .I1(m_axi_mm2s_rlast),
        .I2(\xpm_fifo_instance.xpm_fifo_sync_inst_i_10_n_0 ),
        .O(din[4]));
  LUT5 #(
    .INIT(32'hFFFDCCFD)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_5__0 
       (.I0(sig_last_dbeat_reg_n_0),
        .I1(sig_data2addr_stop_req),
        .I2(sig_next_last_strb_reg[3]),
        .I3(sig_first_dbeat_reg_n_0),
        .I4(sig_next_strt_strb_reg[3]),
        .O(din[3]));
  LUT5 #(
    .INIT(32'hFFFDCCFD)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_6__0 
       (.I0(sig_last_dbeat_reg_n_0),
        .I1(sig_data2addr_stop_req),
        .I2(sig_next_last_strb_reg[2]),
        .I3(sig_first_dbeat_reg_n_0),
        .I4(sig_next_strt_strb_reg[2]),
        .O(din[2]));
  LUT5 #(
    .INIT(32'hFFFDCCFD)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_7__0 
       (.I0(sig_last_dbeat_reg_n_0),
        .I1(sig_data2addr_stop_req),
        .I2(sig_next_last_strb_reg[1]),
        .I3(sig_first_dbeat_reg_n_0),
        .I4(sig_next_strt_strb_reg[1]),
        .O(din[1]));
  LUT5 #(
    .INIT(32'hFFFDCCFD)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_8__0 
       (.I0(sig_last_dbeat_reg_n_0),
        .I1(sig_data2addr_stop_req),
        .I2(sig_next_last_strb_reg[0]),
        .I3(sig_first_dbeat_reg_n_0),
        .I4(sig_next_strt_strb_reg[0]),
        .O(din[0]));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_reset
   (sig_cmd_stat_rst_int_reg_n,
    sig_rst2all_stop_request,
    SR,
    sig_mmap_rst_reg_n,
    sig_stream_rst_reg_n,
    sig_mmap_rst_reg_n_reg_0,
    sig_mmap_rst_reg_n_reg_1,
    SS,
    sig_stream_rst_reg_n_reg_0,
    mm2s_halt_cmplt,
    out,
    m_axi_mm2s_aclk,
    sig_s_h_halt_reg_reg_0,
    sig_init_done,
    sig_init_reg,
    sig_init_reg2,
    sig_init_done_0,
    sig_data2addr_stop_req,
    sig_halt_reg_dly3,
    sig_addr2rsc_calc_error,
    sig_addr_reg_empty,
    sig_halt_cmplt_reg_0);
  output sig_cmd_stat_rst_int_reg_n;
  output sig_rst2all_stop_request;
  output [0:0]SR;
  output sig_mmap_rst_reg_n;
  output sig_stream_rst_reg_n;
  output sig_mmap_rst_reg_n_reg_0;
  output sig_mmap_rst_reg_n_reg_1;
  output [0:0]SS;
  output [0:0]sig_stream_rst_reg_n_reg_0;
  output mm2s_halt_cmplt;
  input out;
  input m_axi_mm2s_aclk;
  input sig_s_h_halt_reg_reg_0;
  input sig_init_done;
  input sig_init_reg;
  input sig_init_reg2;
  input sig_init_done_0;
  input sig_data2addr_stop_req;
  input sig_halt_reg_dly3;
  input sig_addr2rsc_calc_error;
  input sig_addr_reg_empty;
  input sig_halt_cmplt_reg_0;

  wire [0:0]SR;
  wire [0:0]SS;
  wire m_axi_mm2s_aclk;
  wire mm2s_halt_cmplt;
  wire out;
  wire sig_addr2rsc_calc_error;
  wire sig_addr_reg_empty;
  wire sig_cmd_stat_rst_int_reg_n;
  (* RTL_KEEP = "true" *) wire sig_cmd_stat_rst_user_reg_n_cdc_from;
  wire sig_data2addr_stop_req;
  wire sig_halt_cmplt_i_2_n_0;
  wire sig_halt_cmplt_reg_0;
  wire sig_halt_reg_dly3;
  wire sig_init_done;
  wire sig_init_done_0;
  wire sig_init_reg;
  wire sig_init_reg2;
  wire sig_mmap_rst_reg_n;
  wire sig_mmap_rst_reg_n_reg_0;
  wire sig_mmap_rst_reg_n_reg_1;
  wire sig_rst2all_stop_request;
  wire sig_s_h_halt_reg_reg_0;
  wire sig_stream_rst_reg_n;
  wire [0:0]sig_stream_rst_reg_n_reg_0;

  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_cmd_stat_rst_int_reg_n_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(out),
        .Q(sig_cmd_stat_rst_int_reg_n),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(out),
        .Q(sig_cmd_stat_rst_user_reg_n_cdc_from),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    sig_halt_cmplt_i_1
       (.I0(sig_cmd_stat_rst_int_reg_n),
        .O(SR));
  LUT6 #(
    .INIT(64'hFFFFFFFF88800000)) 
    sig_halt_cmplt_i_2
       (.I0(sig_data2addr_stop_req),
        .I1(sig_halt_reg_dly3),
        .I2(sig_addr2rsc_calc_error),
        .I3(sig_addr_reg_empty),
        .I4(sig_halt_cmplt_reg_0),
        .I5(mm2s_halt_cmplt),
        .O(sig_halt_cmplt_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_halt_cmplt_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_halt_cmplt_i_2_n_0),
        .Q(mm2s_halt_cmplt),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    sig_init_done_i_1__5
       (.I0(sig_mmap_rst_reg_n),
        .I1(sig_init_done),
        .I2(sig_init_reg),
        .I3(sig_init_reg2),
        .O(sig_mmap_rst_reg_n_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    sig_init_done_i_1__6
       (.I0(sig_mmap_rst_reg_n),
        .I1(sig_init_done_0),
        .I2(sig_init_reg),
        .I3(sig_init_reg2),
        .O(sig_mmap_rst_reg_n_reg_1));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_mmap_rst_reg_n_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(out),
        .Q(sig_mmap_rst_reg_n),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    sig_reset_reg_i_1
       (.I0(sig_stream_rst_reg_n),
        .O(sig_stream_rst_reg_n_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_s_h_halt_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_s_h_halt_reg_reg_0),
        .Q(sig_rst2all_stop_request),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_stream_rst_reg_n_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(out),
        .Q(sig_stream_rst_reg_n),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_1__0 
       (.I0(sig_mmap_rst_reg_n),
        .O(SS));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_sfifo_autord
   (full,
    dout,
    empty,
    sig_last_skid_mux_out,
    sig_slast_with_stop,
    sig_s_ready_out_reg,
    sig_s_ready_out_reg_0,
    \gen_fwft.empty_fwft_i_reg ,
    sig_posted_to_axi_2_reg,
    \INFERRED_GEN.cnt_i_reg[2] ,
    SS,
    m_axi_mm2s_aclk,
    wr_en,
    din,
    \OMIT_UNPACKING.lsig_cmd_loaded_reg ,
    sig_sstrb_stop_mask,
    out,
    sig_last_skid_reg,
    \OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ,
    Q,
    sig_ok_to_post_rd_addr_reg,
    sig_ok_to_post_rd_addr_reg_0,
    sig_mmap_rst_reg_n,
    sig_ok_to_post_rd_addr_reg_1,
    sig_ok_to_post_rd_addr_reg_2);
  output full;
  output [35:0]dout;
  output empty;
  output sig_last_skid_mux_out;
  output sig_slast_with_stop;
  output sig_s_ready_out_reg;
  output sig_s_ready_out_reg_0;
  output \gen_fwft.empty_fwft_i_reg ;
  output sig_posted_to_axi_2_reg;
  output \INFERRED_GEN.cnt_i_reg[2] ;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input wr_en;
  input [37:0]din;
  input \OMIT_UNPACKING.lsig_cmd_loaded_reg ;
  input [0:0]sig_sstrb_stop_mask;
  input out;
  input sig_last_skid_reg;
  input \OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ;
  input [0:0]Q;
  input sig_ok_to_post_rd_addr_reg;
  input sig_ok_to_post_rd_addr_reg_0;
  input sig_mmap_rst_reg_n;
  input [3:0]sig_ok_to_post_rd_addr_reg_1;
  input sig_ok_to_post_rd_addr_reg_2;

  wire \INFERRED_GEN.cnt_i_reg[2] ;
  wire \OMIT_UNPACKING.lsig_cmd_loaded_reg ;
  wire \OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ;
  wire [0:0]Q;
  wire [0:0]SS;
  wire [37:0]din;
  wire [35:0]dout;
  wire empty;
  wire full;
  wire \gen_fwft.empty_fwft_i_reg ;
  wire m_axi_mm2s_aclk;
  wire out;
  wire sig_last_skid_mux_out;
  wire sig_last_skid_reg;
  wire sig_mmap_rst_reg_n;
  wire sig_ok_to_post_rd_addr_reg;
  wire sig_ok_to_post_rd_addr_reg_0;
  wire [3:0]sig_ok_to_post_rd_addr_reg_1;
  wire sig_ok_to_post_rd_addr_reg_2;
  wire sig_posted_to_axi_2_reg;
  wire sig_s_ready_out_reg;
  wire sig_s_ready_out_reg_0;
  wire sig_slast_with_stop;
  wire [0:0]sig_sstrb_stop_mask;
  wire wr_en;

  Loopback_axi_dma_1_0_sync_fifo_fg__parameterized0 \BLK_MEM.I_SYNC_FIFOGEN_FIFO 
       (.\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ),
        .\OMIT_UNPACKING.lsig_cmd_loaded_reg (\OMIT_UNPACKING.lsig_cmd_loaded_reg ),
        .\OMIT_UNPACKING.lsig_cmd_loaded_reg_0 (\OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ),
        .Q(Q),
        .SS(SS),
        .din(din),
        .dout(dout),
        .empty(empty),
        .full(full),
        .\gen_fwft.empty_fwft_i_reg (\gen_fwft.empty_fwft_i_reg ),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .out(out),
        .sig_last_skid_mux_out(sig_last_skid_mux_out),
        .sig_last_skid_reg(sig_last_skid_reg),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg),
        .sig_ok_to_post_rd_addr_reg_0(sig_ok_to_post_rd_addr_reg_0),
        .sig_ok_to_post_rd_addr_reg_1(sig_ok_to_post_rd_addr_reg_1),
        .sig_ok_to_post_rd_addr_reg_2(sig_ok_to_post_rd_addr_reg_2),
        .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg),
        .sig_s_ready_out_reg(sig_s_ready_out_reg),
        .sig_s_ready_out_reg_0(sig_s_ready_out_reg_0),
        .sig_slast_with_stop(sig_slast_with_stop),
        .sig_sstrb_stop_mask(sig_sstrb_stop_mask),
        .wr_en(wr_en));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_skid_buf
   (out,
    sig_s_ready_out_reg_0,
    m_axis_mm2s_tvalid,
    sig_last_skid_reg,
    m_axis_mm2s_tlast,
    sig_sstrb_stop_mask,
    sig_s_ready_dup_reg_0,
    m_axis_mm2s_tdata,
    m_axis_mm2s_tkeep,
    SR,
    m_axi_mm2s_aclk,
    sig_s_ready_dup_reg_1,
    sig_slast_with_stop,
    sig_last_skid_mux_out,
    \sig_sstrb_stop_mask_reg[3]_0 ,
    m_axis_mm2s_tready,
    sig_halt_reg_dly2,
    sig_halt_reg_dly3,
    \OMIT_UNPACKING.lsig_cmd_loaded ,
    empty,
    sig_m_valid_out_reg_0,
    sig_stream_rst_reg_n,
    dout);
  output out;
  output sig_s_ready_out_reg_0;
  output m_axis_mm2s_tvalid;
  output sig_last_skid_reg;
  output m_axis_mm2s_tlast;
  output [0:0]sig_sstrb_stop_mask;
  output sig_s_ready_dup_reg_0;
  output [31:0]m_axis_mm2s_tdata;
  output [3:0]m_axis_mm2s_tkeep;
  input [0:0]SR;
  input m_axi_mm2s_aclk;
  input sig_s_ready_dup_reg_1;
  input sig_slast_with_stop;
  input sig_last_skid_mux_out;
  input \sig_sstrb_stop_mask_reg[3]_0 ;
  input m_axis_mm2s_tready;
  input sig_halt_reg_dly2;
  input sig_halt_reg_dly3;
  input \OMIT_UNPACKING.lsig_cmd_loaded ;
  input empty;
  input sig_m_valid_out_reg_0;
  input sig_stream_rst_reg_n;
  input [35:0]dout;

  wire \OMIT_UNPACKING.lsig_cmd_loaded ;
  wire [0:0]SR;
  wire [35:0]dout;
  wire empty;
  wire m_axi_mm2s_aclk;
  wire [31:0]m_axis_mm2s_tdata;
  wire [3:0]m_axis_mm2s_tkeep;
  wire m_axis_mm2s_tlast;
  wire m_axis_mm2s_tready;
  wire sig_data_reg_out0;
  wire sig_data_reg_out_en;
  wire [31:0]sig_data_skid_mux_out;
  wire [31:0]sig_data_skid_reg;
  wire sig_halt_reg_dly2;
  wire sig_halt_reg_dly3;
  wire sig_last_skid_mux_out;
  wire sig_last_skid_reg;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_dup;
  wire sig_m_valid_dup_i_1_n_0;
  wire sig_m_valid_dup_i_2_n_0;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_out;
  wire sig_m_valid_out_reg_0;
  wire sig_mvalid_stop;
  wire sig_mvalid_stop_reg_i_1_n_0;
  wire sig_reset_reg;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_dup;
  wire sig_s_ready_dup_reg_0;
  wire sig_s_ready_dup_reg_1;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_out;
  wire sig_slast_with_stop;
  wire [0:0]sig_sstrb_stop_mask;
  wire \sig_sstrb_stop_mask_reg[3]_0 ;
  wire [3:0]sig_sstrb_with_stop;
  wire [3:0]sig_strb_skid_mux_out;
  wire [3:0]sig_strb_skid_reg;
  wire sig_stream_rst_reg_n;

  assign m_axis_mm2s_tvalid = sig_m_valid_out;
  assign out = sig_s_ready_dup;
  assign sig_s_ready_out_reg_0 = sig_s_ready_out;
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[0]_i_1 
       (.I0(dout[0]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[0]),
        .O(sig_data_skid_mux_out[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[10]_i_1 
       (.I0(dout[10]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[10]),
        .O(sig_data_skid_mux_out[10]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[11]_i_1 
       (.I0(dout[11]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[11]),
        .O(sig_data_skid_mux_out[11]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[12]_i_1 
       (.I0(dout[12]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[12]),
        .O(sig_data_skid_mux_out[12]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[13]_i_1 
       (.I0(dout[13]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[13]),
        .O(sig_data_skid_mux_out[13]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[14]_i_1 
       (.I0(dout[14]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[14]),
        .O(sig_data_skid_mux_out[14]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[15]_i_1 
       (.I0(dout[15]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[15]),
        .O(sig_data_skid_mux_out[15]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[16]_i_1 
       (.I0(dout[16]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[16]),
        .O(sig_data_skid_mux_out[16]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[17]_i_1 
       (.I0(dout[17]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[17]),
        .O(sig_data_skid_mux_out[17]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[18]_i_1 
       (.I0(dout[18]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[18]),
        .O(sig_data_skid_mux_out[18]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[19]_i_1 
       (.I0(dout[19]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[19]),
        .O(sig_data_skid_mux_out[19]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[1]_i_1 
       (.I0(dout[1]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[1]),
        .O(sig_data_skid_mux_out[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[20]_i_1 
       (.I0(dout[20]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[20]),
        .O(sig_data_skid_mux_out[20]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[21]_i_1 
       (.I0(dout[21]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[21]),
        .O(sig_data_skid_mux_out[21]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[22]_i_1 
       (.I0(dout[22]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[22]),
        .O(sig_data_skid_mux_out[22]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[23]_i_1 
       (.I0(dout[23]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[23]),
        .O(sig_data_skid_mux_out[23]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[24]_i_1 
       (.I0(dout[24]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[24]),
        .O(sig_data_skid_mux_out[24]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[25]_i_1 
       (.I0(dout[25]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[25]),
        .O(sig_data_skid_mux_out[25]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[26]_i_1 
       (.I0(dout[26]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[26]),
        .O(sig_data_skid_mux_out[26]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[27]_i_1 
       (.I0(dout[27]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[27]),
        .O(sig_data_skid_mux_out[27]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[28]_i_1 
       (.I0(dout[28]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[28]),
        .O(sig_data_skid_mux_out[28]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[29]_i_1 
       (.I0(dout[29]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[29]),
        .O(sig_data_skid_mux_out[29]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[2]_i_1 
       (.I0(dout[2]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[2]),
        .O(sig_data_skid_mux_out[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[30]_i_1 
       (.I0(dout[30]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[30]),
        .O(sig_data_skid_mux_out[30]));
  LUT2 #(
    .INIT(4'hB)) 
    \sig_data_reg_out[31]_i_1 
       (.I0(sig_mvalid_stop),
        .I1(sig_stream_rst_reg_n),
        .O(sig_data_reg_out0));
  LUT2 #(
    .INIT(4'hB)) 
    \sig_data_reg_out[31]_i_2 
       (.I0(m_axis_mm2s_tready),
        .I1(sig_m_valid_dup),
        .O(sig_data_reg_out_en));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[31]_i_3 
       (.I0(dout[31]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[31]),
        .O(sig_data_skid_mux_out[31]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[3]_i_1 
       (.I0(dout[3]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[3]),
        .O(sig_data_skid_mux_out[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[4]_i_1 
       (.I0(dout[4]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[4]),
        .O(sig_data_skid_mux_out[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[5]_i_1 
       (.I0(dout[5]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[5]),
        .O(sig_data_skid_mux_out[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[6]_i_1 
       (.I0(dout[6]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[6]),
        .O(sig_data_skid_mux_out[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[7]_i_1 
       (.I0(dout[7]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[7]),
        .O(sig_data_skid_mux_out[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[8]_i_1 
       (.I0(dout[8]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[8]),
        .O(sig_data_skid_mux_out[8]));
  LUT3 #(
    .INIT(8'hB8)) 
    \sig_data_reg_out[9]_i_1 
       (.I0(dout[9]),
        .I1(sig_s_ready_dup),
        .I2(sig_data_skid_reg[9]),
        .O(sig_data_skid_mux_out[9]));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[0]),
        .Q(m_axis_mm2s_tdata[0]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[10] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[10]),
        .Q(m_axis_mm2s_tdata[10]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[11] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[11]),
        .Q(m_axis_mm2s_tdata[11]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[12] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[12]),
        .Q(m_axis_mm2s_tdata[12]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[13] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[13]),
        .Q(m_axis_mm2s_tdata[13]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[14] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[14]),
        .Q(m_axis_mm2s_tdata[14]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[15] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[15]),
        .Q(m_axis_mm2s_tdata[15]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[16] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[16]),
        .Q(m_axis_mm2s_tdata[16]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[17] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[17]),
        .Q(m_axis_mm2s_tdata[17]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[18] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[18]),
        .Q(m_axis_mm2s_tdata[18]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[19] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[19]),
        .Q(m_axis_mm2s_tdata[19]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[1]),
        .Q(m_axis_mm2s_tdata[1]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[20] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[20]),
        .Q(m_axis_mm2s_tdata[20]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[21] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[21]),
        .Q(m_axis_mm2s_tdata[21]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[22] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[22]),
        .Q(m_axis_mm2s_tdata[22]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[23] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[23]),
        .Q(m_axis_mm2s_tdata[23]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[24] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[24]),
        .Q(m_axis_mm2s_tdata[24]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[25] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[25]),
        .Q(m_axis_mm2s_tdata[25]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[26] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[26]),
        .Q(m_axis_mm2s_tdata[26]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[27] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[27]),
        .Q(m_axis_mm2s_tdata[27]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[28] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[28]),
        .Q(m_axis_mm2s_tdata[28]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[29] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[29]),
        .Q(m_axis_mm2s_tdata[29]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[2]),
        .Q(m_axis_mm2s_tdata[2]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[30] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[30]),
        .Q(m_axis_mm2s_tdata[30]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[31] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[31]),
        .Q(m_axis_mm2s_tdata[31]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[3]),
        .Q(m_axis_mm2s_tdata[3]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[4]),
        .Q(m_axis_mm2s_tdata[4]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[5]),
        .Q(m_axis_mm2s_tdata[5]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[6]),
        .Q(m_axis_mm2s_tdata[6]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[7] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[7]),
        .Q(m_axis_mm2s_tdata[7]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[8] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[8]),
        .Q(m_axis_mm2s_tdata[8]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_reg_out_reg[9] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_data_skid_mux_out[9]),
        .Q(m_axis_mm2s_tdata[9]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[0]),
        .Q(sig_data_skid_reg[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[10] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[10]),
        .Q(sig_data_skid_reg[10]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[11] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[11]),
        .Q(sig_data_skid_reg[11]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[12] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[12]),
        .Q(sig_data_skid_reg[12]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[13] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[13]),
        .Q(sig_data_skid_reg[13]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[14] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[14]),
        .Q(sig_data_skid_reg[14]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[15] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[15]),
        .Q(sig_data_skid_reg[15]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[16] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[16]),
        .Q(sig_data_skid_reg[16]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[17] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[17]),
        .Q(sig_data_skid_reg[17]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[18] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[18]),
        .Q(sig_data_skid_reg[18]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[19] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[19]),
        .Q(sig_data_skid_reg[19]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[1]),
        .Q(sig_data_skid_reg[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[20] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[20]),
        .Q(sig_data_skid_reg[20]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[21] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[21]),
        .Q(sig_data_skid_reg[21]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[22] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[22]),
        .Q(sig_data_skid_reg[22]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[23] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[23]),
        .Q(sig_data_skid_reg[23]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[24] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[24]),
        .Q(sig_data_skid_reg[24]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[25] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[25]),
        .Q(sig_data_skid_reg[25]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[26] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[26]),
        .Q(sig_data_skid_reg[26]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[27] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[27]),
        .Q(sig_data_skid_reg[27]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[28] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[28]),
        .Q(sig_data_skid_reg[28]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[29] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[29]),
        .Q(sig_data_skid_reg[29]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[2]),
        .Q(sig_data_skid_reg[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[30] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[30]),
        .Q(sig_data_skid_reg[30]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[31] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[31]),
        .Q(sig_data_skid_reg[31]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[3]),
        .Q(sig_data_skid_reg[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[4] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[4]),
        .Q(sig_data_skid_reg[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[5] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[5]),
        .Q(sig_data_skid_reg[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[6] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[6]),
        .Q(sig_data_skid_reg[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[7] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[7]),
        .Q(sig_data_skid_reg[7]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[8] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[8]),
        .Q(sig_data_skid_reg[8]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_data_skid_reg_reg[9] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(dout[9]),
        .Q(sig_data_skid_reg[9]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    sig_last_reg_out_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_last_skid_mux_out),
        .Q(m_axis_mm2s_tlast),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    sig_last_skid_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(sig_slast_with_stop),
        .Q(sig_last_skid_reg),
        .R(SR));
  LUT6 #(
    .INIT(64'h08AA08AA082A08AA)) 
    sig_m_valid_dup_i_1
       (.I0(sig_m_valid_dup_i_2_n_0),
        .I1(sig_m_valid_dup),
        .I2(m_axis_mm2s_tready),
        .I3(sig_sstrb_stop_mask),
        .I4(sig_halt_reg_dly2),
        .I5(sig_halt_reg_dly3),
        .O(sig_m_valid_dup_i_1_n_0));
  LUT6 #(
    .INIT(64'h0101110111011101)) 
    sig_m_valid_dup_i_2
       (.I0(sig_reset_reg),
        .I1(sig_data_reg_out0),
        .I2(sig_m_valid_out_reg_0),
        .I3(sig_m_valid_dup),
        .I4(m_axis_mm2s_tready),
        .I5(sig_s_ready_dup),
        .O(sig_m_valid_dup_i_2_n_0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_m_valid_dup_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_m_valid_dup_i_1_n_0),
        .Q(sig_m_valid_dup),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_m_valid_out_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_m_valid_dup_i_1_n_0),
        .Q(sig_m_valid_out),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFD0D0D8D0)) 
    sig_mvalid_stop_reg_i_1
       (.I0(sig_m_valid_dup),
        .I1(m_axis_mm2s_tready),
        .I2(sig_sstrb_stop_mask),
        .I3(sig_halt_reg_dly2),
        .I4(sig_halt_reg_dly3),
        .I5(sig_mvalid_stop),
        .O(sig_mvalid_stop_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_mvalid_stop_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_mvalid_stop_reg_i_1_n_0),
        .Q(sig_mvalid_stop),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    sig_reset_reg_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(SR),
        .Q(sig_reset_reg),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFA2AA)) 
    sig_s_ready_dup_i_2
       (.I0(sig_s_ready_dup),
        .I1(\OMIT_UNPACKING.lsig_cmd_loaded ),
        .I2(empty),
        .I3(sig_m_valid_dup),
        .I4(m_axis_mm2s_tready),
        .I5(sig_reset_reg),
        .O(sig_s_ready_dup_reg_0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_s_ready_dup_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_s_ready_dup_reg_1),
        .Q(sig_s_ready_dup),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_s_ready_out_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(sig_s_ready_dup_reg_1),
        .Q(sig_s_ready_out),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_sstrb_stop_mask_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\sig_sstrb_stop_mask_reg[3]_0 ),
        .Q(sig_sstrb_stop_mask),
        .R(SR));
  LUT4 #(
    .INIT(16'hEFE0)) 
    \sig_strb_reg_out[0]_i_1 
       (.I0(sig_sstrb_stop_mask),
        .I1(dout[32]),
        .I2(sig_s_ready_dup),
        .I3(sig_strb_skid_reg[0]),
        .O(sig_strb_skid_mux_out[0]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    \sig_strb_reg_out[1]_i_1 
       (.I0(sig_sstrb_stop_mask),
        .I1(dout[33]),
        .I2(sig_s_ready_dup),
        .I3(sig_strb_skid_reg[1]),
        .O(sig_strb_skid_mux_out[1]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    \sig_strb_reg_out[2]_i_1 
       (.I0(sig_sstrb_stop_mask),
        .I1(dout[34]),
        .I2(sig_s_ready_dup),
        .I3(sig_strb_skid_reg[2]),
        .O(sig_strb_skid_mux_out[2]));
  LUT4 #(
    .INIT(16'hEFE0)) 
    \sig_strb_reg_out[3]_i_1 
       (.I0(sig_sstrb_stop_mask),
        .I1(dout[35]),
        .I2(sig_s_ready_dup),
        .I3(sig_strb_skid_reg[3]),
        .O(sig_strb_skid_mux_out[3]));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strb_reg_out_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_strb_skid_mux_out[0]),
        .Q(m_axis_mm2s_tkeep[0]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strb_reg_out_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_strb_skid_mux_out[1]),
        .Q(m_axis_mm2s_tkeep[1]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strb_reg_out_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_strb_skid_mux_out[2]),
        .Q(m_axis_mm2s_tkeep[2]),
        .R(sig_data_reg_out0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strb_reg_out_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_data_reg_out_en),
        .D(sig_strb_skid_mux_out[3]),
        .Q(m_axis_mm2s_tkeep[3]),
        .R(sig_data_reg_out0));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \sig_strb_skid_reg[0]_i_1 
       (.I0(sig_sstrb_stop_mask),
        .I1(dout[32]),
        .O(sig_sstrb_with_stop[0]));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \sig_strb_skid_reg[1]_i_1 
       (.I0(sig_sstrb_stop_mask),
        .I1(dout[33]),
        .O(sig_sstrb_with_stop[1]));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \sig_strb_skid_reg[2]_i_1 
       (.I0(sig_sstrb_stop_mask),
        .I1(dout[34]),
        .O(sig_sstrb_with_stop[2]));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \sig_strb_skid_reg[3]_i_1 
       (.I0(sig_sstrb_stop_mask),
        .I1(dout[35]),
        .O(sig_sstrb_with_stop[3]));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strb_skid_reg_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(sig_sstrb_with_stop[0]),
        .Q(sig_strb_skid_reg[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strb_skid_reg_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(sig_sstrb_with_stop[1]),
        .Q(sig_strb_skid_reg[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strb_skid_reg_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(sig_sstrb_with_stop[2]),
        .Q(sig_strb_skid_reg[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \sig_strb_skid_reg_reg[3] 
       (.C(m_axi_mm2s_aclk),
        .CE(sig_s_ready_dup),
        .D(sig_sstrb_with_stop[3]),
        .Q(sig_strb_skid_reg[3]),
        .R(SR));
endmodule

module Loopback_axi_dma_1_0_axi_datamover_strb_gen2
   (D,
    Q,
    \sig_xfer_strt_strb_ireg3_reg[3] ,
    \sig_xfer_strt_strb_ireg3_reg[3]_0 );
  output [1:0]D;
  input [1:0]Q;
  input [1:0]\sig_xfer_strt_strb_ireg3_reg[3] ;
  input \sig_xfer_strt_strb_ireg3_reg[3]_0 ;

  wire [1:0]D;
  wire [1:0]Q;
  wire [1:0]\sig_xfer_strt_strb_ireg3_reg[3] ;
  wire \sig_xfer_strt_strb_ireg3_reg[3]_0 ;

  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT5 #(
    .INIT(32'h1FFAF8F0)) 
    \GEN_4BIT_CASE.lsig_end_vect 
       (.I0(Q[0]),
        .I1(\sig_xfer_strt_strb_ireg3_reg[3] [0]),
        .I2(\sig_xfer_strt_strb_ireg3_reg[3]_0 ),
        .I3(\sig_xfer_strt_strb_ireg3_reg[3] [1]),
        .I4(Q[1]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \GEN_4BIT_CASE.lsig_start_vect 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(D[0]));
endmodule

(* C_DLYTMR_RESOLUTION = "125" *) (* C_ENABLE_MULTI_CHANNEL = "0" *) (* C_FAMILY = "zynquplus" *) 
(* C_INCLUDE_MM2S = "1" *) (* C_INCLUDE_MM2S_DRE = "0" *) (* C_INCLUDE_MM2S_SF = "1" *) 
(* C_INCLUDE_S2MM = "0" *) (* C_INCLUDE_S2MM_DRE = "0" *) (* C_INCLUDE_S2MM_SF = "1" *) 
(* C_INCLUDE_SG = "1" *) (* C_INCREASE_THROUGHPUT = "0" *) (* C_INSTANCE = "axi_dma" *) 
(* C_MICRO_DMA = "0" *) (* C_MM2S_BURST_SIZE = "16" *) (* C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH = "32" *) 
(* C_M_AXIS_MM2S_TDATA_WIDTH = "32" *) (* C_M_AXI_MM2S_ADDR_WIDTH = "32" *) (* C_M_AXI_MM2S_DATA_WIDTH = "32" *) 
(* C_M_AXI_S2MM_ADDR_WIDTH = "32" *) (* C_M_AXI_S2MM_DATA_WIDTH = "32" *) (* C_M_AXI_SG_ADDR_WIDTH = "32" *) 
(* C_M_AXI_SG_DATA_WIDTH = "32" *) (* C_NUM_MM2S_CHANNELS = "1" *) (* C_NUM_S2MM_CHANNELS = "1" *) 
(* C_PRMRY_IS_ACLK_ASYNC = "0" *) (* C_S2MM_BURST_SIZE = "16" *) (* C_SG_INCLUDE_STSCNTRL_STRM = "1" *) 
(* C_SG_LENGTH_WIDTH = "26" *) (* C_SG_USE_STSAPP_LENGTH = "0" *) (* C_S_AXIS_S2MM_STS_TDATA_WIDTH = "32" *) 
(* C_S_AXIS_S2MM_TDATA_WIDTH = "32" *) (* C_S_AXI_LITE_ADDR_WIDTH = "10" *) (* C_S_AXI_LITE_DATA_WIDTH = "32" *) 
(* downgradeipidentifiedwarnings = "yes" *) 
module Loopback_axi_dma_1_0_axi_dma
   (s_axi_lite_aclk,
    m_axi_sg_aclk,
    m_axi_mm2s_aclk,
    m_axi_s2mm_aclk,
    axi_resetn,
    s_axi_lite_awvalid,
    s_axi_lite_awready,
    s_axi_lite_awaddr,
    s_axi_lite_wvalid,
    s_axi_lite_wready,
    s_axi_lite_wdata,
    s_axi_lite_bresp,
    s_axi_lite_bvalid,
    s_axi_lite_bready,
    s_axi_lite_arvalid,
    s_axi_lite_arready,
    s_axi_lite_araddr,
    s_axi_lite_rvalid,
    s_axi_lite_rready,
    s_axi_lite_rdata,
    s_axi_lite_rresp,
    m_axi_sg_awaddr,
    m_axi_sg_awlen,
    m_axi_sg_awsize,
    m_axi_sg_awburst,
    m_axi_sg_awprot,
    m_axi_sg_awcache,
    m_axi_sg_awuser,
    m_axi_sg_awvalid,
    m_axi_sg_awready,
    m_axi_sg_wdata,
    m_axi_sg_wstrb,
    m_axi_sg_wlast,
    m_axi_sg_wvalid,
    m_axi_sg_wready,
    m_axi_sg_bresp,
    m_axi_sg_bvalid,
    m_axi_sg_bready,
    m_axi_sg_araddr,
    m_axi_sg_arlen,
    m_axi_sg_arsize,
    m_axi_sg_arburst,
    m_axi_sg_arprot,
    m_axi_sg_arcache,
    m_axi_sg_aruser,
    m_axi_sg_arvalid,
    m_axi_sg_arready,
    m_axi_sg_rdata,
    m_axi_sg_rresp,
    m_axi_sg_rlast,
    m_axi_sg_rvalid,
    m_axi_sg_rready,
    m_axi_mm2s_araddr,
    m_axi_mm2s_arlen,
    m_axi_mm2s_arsize,
    m_axi_mm2s_arburst,
    m_axi_mm2s_arprot,
    m_axi_mm2s_arcache,
    m_axi_mm2s_aruser,
    m_axi_mm2s_arvalid,
    m_axi_mm2s_arready,
    m_axi_mm2s_rdata,
    m_axi_mm2s_rresp,
    m_axi_mm2s_rlast,
    m_axi_mm2s_rvalid,
    m_axi_mm2s_rready,
    mm2s_prmry_reset_out_n,
    m_axis_mm2s_tdata,
    m_axis_mm2s_tkeep,
    m_axis_mm2s_tvalid,
    m_axis_mm2s_tready,
    m_axis_mm2s_tlast,
    m_axis_mm2s_tuser,
    m_axis_mm2s_tid,
    m_axis_mm2s_tdest,
    mm2s_cntrl_reset_out_n,
    m_axis_mm2s_cntrl_tdata,
    m_axis_mm2s_cntrl_tkeep,
    m_axis_mm2s_cntrl_tvalid,
    m_axis_mm2s_cntrl_tready,
    m_axis_mm2s_cntrl_tlast,
    m_axi_s2mm_awaddr,
    m_axi_s2mm_awlen,
    m_axi_s2mm_awsize,
    m_axi_s2mm_awburst,
    m_axi_s2mm_awprot,
    m_axi_s2mm_awcache,
    m_axi_s2mm_awuser,
    m_axi_s2mm_awvalid,
    m_axi_s2mm_awready,
    m_axi_s2mm_wdata,
    m_axi_s2mm_wstrb,
    m_axi_s2mm_wlast,
    m_axi_s2mm_wvalid,
    m_axi_s2mm_wready,
    m_axi_s2mm_bresp,
    m_axi_s2mm_bvalid,
    m_axi_s2mm_bready,
    s2mm_prmry_reset_out_n,
    s_axis_s2mm_tdata,
    s_axis_s2mm_tkeep,
    s_axis_s2mm_tvalid,
    s_axis_s2mm_tready,
    s_axis_s2mm_tlast,
    s_axis_s2mm_tuser,
    s_axis_s2mm_tid,
    s_axis_s2mm_tdest,
    s2mm_sts_reset_out_n,
    s_axis_s2mm_sts_tdata,
    s_axis_s2mm_sts_tkeep,
    s_axis_s2mm_sts_tvalid,
    s_axis_s2mm_sts_tready,
    s_axis_s2mm_sts_tlast,
    mm2s_introut,
    s2mm_introut,
    axi_dma_tstvec);
  input s_axi_lite_aclk;
  (* dont_touch = "true" *) input m_axi_sg_aclk;
  input m_axi_mm2s_aclk;
  input m_axi_s2mm_aclk;
  input axi_resetn;
  input s_axi_lite_awvalid;
  output s_axi_lite_awready;
  input [9:0]s_axi_lite_awaddr;
  input s_axi_lite_wvalid;
  output s_axi_lite_wready;
  input [31:0]s_axi_lite_wdata;
  output [1:0]s_axi_lite_bresp;
  output s_axi_lite_bvalid;
  input s_axi_lite_bready;
  input s_axi_lite_arvalid;
  output s_axi_lite_arready;
  input [9:0]s_axi_lite_araddr;
  output s_axi_lite_rvalid;
  input s_axi_lite_rready;
  output [31:0]s_axi_lite_rdata;
  output [1:0]s_axi_lite_rresp;
  output [31:0]m_axi_sg_awaddr;
  output [7:0]m_axi_sg_awlen;
  output [2:0]m_axi_sg_awsize;
  output [1:0]m_axi_sg_awburst;
  output [2:0]m_axi_sg_awprot;
  output [3:0]m_axi_sg_awcache;
  output [3:0]m_axi_sg_awuser;
  output m_axi_sg_awvalid;
  input m_axi_sg_awready;
  output [31:0]m_axi_sg_wdata;
  output [3:0]m_axi_sg_wstrb;
  output m_axi_sg_wlast;
  output m_axi_sg_wvalid;
  input m_axi_sg_wready;
  input [1:0]m_axi_sg_bresp;
  input m_axi_sg_bvalid;
  output m_axi_sg_bready;
  output [31:0]m_axi_sg_araddr;
  output [7:0]m_axi_sg_arlen;
  output [2:0]m_axi_sg_arsize;
  output [1:0]m_axi_sg_arburst;
  output [2:0]m_axi_sg_arprot;
  output [3:0]m_axi_sg_arcache;
  output [3:0]m_axi_sg_aruser;
  output m_axi_sg_arvalid;
  input m_axi_sg_arready;
  input [31:0]m_axi_sg_rdata;
  input [1:0]m_axi_sg_rresp;
  input m_axi_sg_rlast;
  input m_axi_sg_rvalid;
  output m_axi_sg_rready;
  output [31:0]m_axi_mm2s_araddr;
  output [7:0]m_axi_mm2s_arlen;
  output [2:0]m_axi_mm2s_arsize;
  output [1:0]m_axi_mm2s_arburst;
  output [2:0]m_axi_mm2s_arprot;
  output [3:0]m_axi_mm2s_arcache;
  output [3:0]m_axi_mm2s_aruser;
  output m_axi_mm2s_arvalid;
  input m_axi_mm2s_arready;
  input [31:0]m_axi_mm2s_rdata;
  input [1:0]m_axi_mm2s_rresp;
  input m_axi_mm2s_rlast;
  input m_axi_mm2s_rvalid;
  output m_axi_mm2s_rready;
  output mm2s_prmry_reset_out_n;
  output [31:0]m_axis_mm2s_tdata;
  output [3:0]m_axis_mm2s_tkeep;
  output m_axis_mm2s_tvalid;
  input m_axis_mm2s_tready;
  output m_axis_mm2s_tlast;
  output [3:0]m_axis_mm2s_tuser;
  output [4:0]m_axis_mm2s_tid;
  output [4:0]m_axis_mm2s_tdest;
  output mm2s_cntrl_reset_out_n;
  output [31:0]m_axis_mm2s_cntrl_tdata;
  output [3:0]m_axis_mm2s_cntrl_tkeep;
  output m_axis_mm2s_cntrl_tvalid;
  input m_axis_mm2s_cntrl_tready;
  output m_axis_mm2s_cntrl_tlast;
  output [31:0]m_axi_s2mm_awaddr;
  output [7:0]m_axi_s2mm_awlen;
  output [2:0]m_axi_s2mm_awsize;
  output [1:0]m_axi_s2mm_awburst;
  output [2:0]m_axi_s2mm_awprot;
  output [3:0]m_axi_s2mm_awcache;
  output [3:0]m_axi_s2mm_awuser;
  output m_axi_s2mm_awvalid;
  input m_axi_s2mm_awready;
  output [31:0]m_axi_s2mm_wdata;
  output [3:0]m_axi_s2mm_wstrb;
  output m_axi_s2mm_wlast;
  output m_axi_s2mm_wvalid;
  input m_axi_s2mm_wready;
  input [1:0]m_axi_s2mm_bresp;
  input m_axi_s2mm_bvalid;
  output m_axi_s2mm_bready;
  output s2mm_prmry_reset_out_n;
  input [31:0]s_axis_s2mm_tdata;
  input [3:0]s_axis_s2mm_tkeep;
  input s_axis_s2mm_tvalid;
  output s_axis_s2mm_tready;
  input s_axis_s2mm_tlast;
  input [3:0]s_axis_s2mm_tuser;
  input [4:0]s_axis_s2mm_tid;
  input [4:0]s_axis_s2mm_tdest;
  output s2mm_sts_reset_out_n;
  input [31:0]s_axis_s2mm_sts_tdata;
  input [3:0]s_axis_s2mm_sts_tkeep;
  input s_axis_s2mm_sts_tvalid;
  output s_axis_s2mm_sts_tready;
  input s_axis_s2mm_sts_tlast;
  output mm2s_introut;
  output s2mm_introut;
  output [31:0]axi_dma_tstvec;

  wire \<const0> ;
  wire \GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.rdy_to ;
  wire \GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.rdy_to2 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/ptr_queue_wren ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sinit ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts_queue_wren ;
  wire \GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/ch1_delay_cnt_en ;
  wire \GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/ch1_delay_count0 ;
  wire \GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/ch1_dly_fast_cnt0 ;
  wire \GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SM/cmnds_queued_shift0 ;
  wire \GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS/mm2s_decerr_i ;
  wire \GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS/mm2s_interr_i ;
  wire \GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS/mm2s_slverr_i ;
  wire \GEN_MM2S_DMA_CONTROL.I_MM2S_STS_MNGR/mm2s_halted_set0 ;
  wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request ;
  wire \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/sg_ftch_error0 ;
  wire \GEN_RESET_FOR_MM2S.RESET_I/s_halt0 ;
  wire \GEN_RESET_FOR_MM2S.RESET_I/soft_reset_d1 ;
  wire \GEN_RESET_FOR_MM2S.RESET_I/soft_reset_re ;
  wire \GEN_RESET_FOR_MM2S.RESET_I/soft_reset_re0 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_102 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_219 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_220 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_221 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_222 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_223 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_224 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_225 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_45 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_5 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_53 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_56 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_65 ;
  wire \GEN_SG_ENGINE.I_SG_ENGINE_n_66 ;
  wire \INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR_n_10 ;
  wire \INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR_n_11 ;
  wire \INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_SOFEOF_GEN_n_0 ;
  wire I_AXI_DMA_REG_MODULE_n_1;
  wire I_AXI_DMA_REG_MODULE_n_18;
  wire I_AXI_DMA_REG_MODULE_n_19;
  wire I_AXI_DMA_REG_MODULE_n_2;
  wire I_AXI_DMA_REG_MODULE_n_25;
  wire I_AXI_DMA_REG_MODULE_n_26;
  wire I_AXI_DMA_REG_MODULE_n_28;
  wire I_AXI_DMA_REG_MODULE_n_3;
  wire I_AXI_DMA_REG_MODULE_n_30;
  wire I_AXI_DMA_REG_MODULE_n_31;
  wire I_AXI_DMA_REG_MODULE_n_32;
  wire I_AXI_DMA_REG_MODULE_n_33;
  wire I_AXI_DMA_REG_MODULE_n_34;
  wire I_AXI_DMA_REG_MODULE_n_35;
  wire I_AXI_DMA_REG_MODULE_n_36;
  wire I_AXI_DMA_REG_MODULE_n_37;
  wire I_AXI_DMA_REG_MODULE_n_38;
  wire I_AXI_DMA_REG_MODULE_n_39;
  wire I_AXI_DMA_REG_MODULE_n_4;
  wire I_AXI_DMA_REG_MODULE_n_40;
  wire I_AXI_DMA_REG_MODULE_n_5;
  wire I_AXI_DMA_REG_MODULE_n_6;
  wire I_AXI_DMA_REG_MODULE_n_76;
  wire I_PRMRY_DATAMOVER_n_11;
  wire I_RST_MODULE_n_13;
  wire I_RST_MODULE_n_17;
  wire I_RST_MODULE_n_18;
  wire \I_SG_FETCH_MNGR/ch1_sg_idle ;
  wire \I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_MM2S.CONTROL_STREAM.I_MM2S_CNTRL_STREAM/sinit ;
  wire \I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_empty_new0 ;
  wire \I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_rden_new ;
  wire \I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_sinit0_out ;
  wire \I_SG_FETCH_QUEUE/sof_ftch_desc0 ;
  wire [4:0]\^axi_dma_tstvec ;
  wire axi_lite_reset_n;
  wire axi_resetn;
  wire [31:12]ch1_fetch_address_i;
  wire ch1_ftch_queue_empty;
  wire ch1_nxtdesc_wren;
  wire dm_m_axi_sg_aresetn;
  wire dma_mm2s_error;
  wire [31:6]ftch_error_addr;
  wire m_axi_mm2s_aclk;
  wire [31:0]m_axi_mm2s_araddr;
  wire [0:0]\^m_axi_mm2s_arburst ;
  wire m_axi_mm2s_aresetn;
  wire [3:0]\^m_axi_mm2s_arlen ;
  wire m_axi_mm2s_arready;
  wire [1:1]\^m_axi_mm2s_arsize ;
  wire m_axi_mm2s_arvalid;
  wire [31:0]m_axi_mm2s_rdata;
  wire m_axi_mm2s_rlast;
  wire m_axi_mm2s_rready;
  wire [1:0]m_axi_mm2s_rresp;
  wire m_axi_mm2s_rvalid;
  wire m_axi_sg_aclk;
  wire [31:6]\^m_axi_sg_araddr ;
  wire [0:0]\^m_axi_sg_arburst ;
  wire m_axi_sg_aresetn;
  wire [3:0]\^m_axi_sg_arlen ;
  wire m_axi_sg_arready;
  wire [1:1]\^m_axi_sg_arsize ;
  wire m_axi_sg_arvalid;
  wire [31:2]\^m_axi_sg_awaddr ;
  wire [0:0]\^m_axi_sg_awlen ;
  wire m_axi_sg_awready;
  wire [1:1]\^m_axi_sg_awsize ;
  wire m_axi_sg_awvalid;
  wire m_axi_sg_bready;
  wire [1:0]m_axi_sg_bresp;
  wire m_axi_sg_bvalid;
  wire m_axi_sg_hrdresetn;
  wire [31:0]m_axi_sg_rdata;
  wire m_axi_sg_rlast;
  wire m_axi_sg_rready;
  wire [1:0]m_axi_sg_rresp;
  wire m_axi_sg_rvalid;
  wire [31:0]\^m_axi_sg_wdata ;
  wire m_axi_sg_wlast;
  wire m_axi_sg_wready;
  wire [0:0]\^m_axi_sg_wstrb ;
  wire m_axi_sg_wvalid;
  wire [31:0]m_axis_mm2s_cntrl_tdata;
  wire m_axis_mm2s_cntrl_tlast;
  wire m_axis_mm2s_cntrl_tready;
  wire m_axis_mm2s_cntrl_tvalid;
  wire [96:0]m_axis_mm2s_ftch_tdata_new;
  wire m_axis_mm2s_ftch_tvalid_new;
  wire m_axis_mm2s_sts_tready;
  wire m_axis_mm2s_sts_tvalid_int;
  wire [31:0]m_axis_mm2s_tdata;
  wire [3:0]m_axis_mm2s_tkeep;
  wire m_axis_mm2s_tlast;
  wire m_axis_mm2s_tready;
  wire m_axis_mm2s_tvalid;
  wire mm2s_all_idle;
  wire mm2s_cntrl_reset_out_n;
  wire mm2s_cntrl_strm_stop;
  wire [31:6]mm2s_curdesc;
  wire mm2s_dly_irq_set;
  wire [23:0]mm2s_dmacr;
  wire mm2s_dmasr;
  wire mm2s_ftch_idle;
  wire mm2s_halt;
  wire mm2s_halt_cmplt;
  wire mm2s_introut;
  wire mm2s_ioc_irq_set;
  wire [7:0]mm2s_irqdelay_status;
  wire [7:0]mm2s_irqthresh_status;
  wire mm2s_irqthresh_wren;
  wire mm2s_prmry_reset_out_n;
  wire mm2s_prmry_resetn;
  wire mm2s_stop;
  wire mm2s_stop_i;
  wire mm2s_sts_received;
  wire [11:6]mm2s_taildesc;
  wire mm2s_updt_decerr_set;
  wire mm2s_updt_idle;
  wire mm2s_updt_interr_set;
  wire mm2s_updt_slverr_set;
  wire p_0_in;
  wire packet_in_progress;
  wire ptr_queue_full;
  wire s_axi_lite_aclk;
  wire [9:0]s_axi_lite_araddr;
  wire s_axi_lite_arready;
  wire s_axi_lite_arvalid;
  wire [9:0]s_axi_lite_awaddr;
  wire s_axi_lite_awvalid;
  wire s_axi_lite_bready;
  wire s_axi_lite_bvalid;
  wire [31:0]s_axi_lite_rdata;
  wire s_axi_lite_rready;
  wire s_axi_lite_rvalid;
  wire [31:0]s_axi_lite_wdata;
  wire s_axi_lite_wready;
  wire s_axi_lite_wvalid;
  wire [26:26]s_axis_mm2s_cmd_tdata_split;
  wire s_axis_mm2s_cmd_tready;
  wire s_axis_mm2s_cmd_tvalid_split;
  wire [31:6]s_axis_mm2s_updtptr_tdata;
  wire s_axis_mm2s_updtptr_tlast;
  wire [32:0]s_axis_mm2s_updtsts_tdata;
  wire soft_reset;
  wire soft_reset_clr;
  wire soft_reset_d1;
  wire soft_reset_d2;
  wire sts_queue_full;

  assign axi_dma_tstvec[31] = \<const0> ;
  assign axi_dma_tstvec[30] = \<const0> ;
  assign axi_dma_tstvec[29] = \<const0> ;
  assign axi_dma_tstvec[28] = \<const0> ;
  assign axi_dma_tstvec[27] = \<const0> ;
  assign axi_dma_tstvec[26] = \<const0> ;
  assign axi_dma_tstvec[25] = \<const0> ;
  assign axi_dma_tstvec[24] = \<const0> ;
  assign axi_dma_tstvec[23] = \<const0> ;
  assign axi_dma_tstvec[22] = \<const0> ;
  assign axi_dma_tstvec[21] = \<const0> ;
  assign axi_dma_tstvec[20] = \<const0> ;
  assign axi_dma_tstvec[19] = \<const0> ;
  assign axi_dma_tstvec[18] = \<const0> ;
  assign axi_dma_tstvec[17] = \<const0> ;
  assign axi_dma_tstvec[16] = \<const0> ;
  assign axi_dma_tstvec[15] = \<const0> ;
  assign axi_dma_tstvec[14] = \<const0> ;
  assign axi_dma_tstvec[13] = \<const0> ;
  assign axi_dma_tstvec[12] = \<const0> ;
  assign axi_dma_tstvec[11] = \<const0> ;
  assign axi_dma_tstvec[10] = \<const0> ;
  assign axi_dma_tstvec[9] = \<const0> ;
  assign axi_dma_tstvec[8] = \<const0> ;
  assign axi_dma_tstvec[7] = \<const0> ;
  assign axi_dma_tstvec[6] = \<const0> ;
  assign axi_dma_tstvec[5] = \<const0> ;
  assign axi_dma_tstvec[4] = \^axi_dma_tstvec [4];
  assign axi_dma_tstvec[3] = \<const0> ;
  assign axi_dma_tstvec[2] = \<const0> ;
  assign axi_dma_tstvec[1:0] = \^axi_dma_tstvec [1:0];
  assign m_axi_mm2s_arburst[1] = \<const0> ;
  assign m_axi_mm2s_arburst[0] = \^m_axi_mm2s_arburst [0];
  assign m_axi_mm2s_arcache[3] = \<const0> ;
  assign m_axi_mm2s_arcache[2] = \<const0> ;
  assign m_axi_mm2s_arcache[1] = \<const0> ;
  assign m_axi_mm2s_arcache[0] = \<const0> ;
  assign m_axi_mm2s_arlen[7] = \<const0> ;
  assign m_axi_mm2s_arlen[6] = \<const0> ;
  assign m_axi_mm2s_arlen[5] = \<const0> ;
  assign m_axi_mm2s_arlen[4] = \<const0> ;
  assign m_axi_mm2s_arlen[3:0] = \^m_axi_mm2s_arlen [3:0];
  assign m_axi_mm2s_arprot[2] = \<const0> ;
  assign m_axi_mm2s_arprot[1] = \<const0> ;
  assign m_axi_mm2s_arprot[0] = \<const0> ;
  assign m_axi_mm2s_arsize[2] = \<const0> ;
  assign m_axi_mm2s_arsize[1] = \^m_axi_mm2s_arsize [1];
  assign m_axi_mm2s_arsize[0] = \<const0> ;
  assign m_axi_mm2s_aruser[3] = \<const0> ;
  assign m_axi_mm2s_aruser[2] = \<const0> ;
  assign m_axi_mm2s_aruser[1] = \<const0> ;
  assign m_axi_mm2s_aruser[0] = \<const0> ;
  assign m_axi_s2mm_awaddr[31] = \<const0> ;
  assign m_axi_s2mm_awaddr[30] = \<const0> ;
  assign m_axi_s2mm_awaddr[29] = \<const0> ;
  assign m_axi_s2mm_awaddr[28] = \<const0> ;
  assign m_axi_s2mm_awaddr[27] = \<const0> ;
  assign m_axi_s2mm_awaddr[26] = \<const0> ;
  assign m_axi_s2mm_awaddr[25] = \<const0> ;
  assign m_axi_s2mm_awaddr[24] = \<const0> ;
  assign m_axi_s2mm_awaddr[23] = \<const0> ;
  assign m_axi_s2mm_awaddr[22] = \<const0> ;
  assign m_axi_s2mm_awaddr[21] = \<const0> ;
  assign m_axi_s2mm_awaddr[20] = \<const0> ;
  assign m_axi_s2mm_awaddr[19] = \<const0> ;
  assign m_axi_s2mm_awaddr[18] = \<const0> ;
  assign m_axi_s2mm_awaddr[17] = \<const0> ;
  assign m_axi_s2mm_awaddr[16] = \<const0> ;
  assign m_axi_s2mm_awaddr[15] = \<const0> ;
  assign m_axi_s2mm_awaddr[14] = \<const0> ;
  assign m_axi_s2mm_awaddr[13] = \<const0> ;
  assign m_axi_s2mm_awaddr[12] = \<const0> ;
  assign m_axi_s2mm_awaddr[11] = \<const0> ;
  assign m_axi_s2mm_awaddr[10] = \<const0> ;
  assign m_axi_s2mm_awaddr[9] = \<const0> ;
  assign m_axi_s2mm_awaddr[8] = \<const0> ;
  assign m_axi_s2mm_awaddr[7] = \<const0> ;
  assign m_axi_s2mm_awaddr[6] = \<const0> ;
  assign m_axi_s2mm_awaddr[5] = \<const0> ;
  assign m_axi_s2mm_awaddr[4] = \<const0> ;
  assign m_axi_s2mm_awaddr[3] = \<const0> ;
  assign m_axi_s2mm_awaddr[2] = \<const0> ;
  assign m_axi_s2mm_awaddr[1] = \<const0> ;
  assign m_axi_s2mm_awaddr[0] = \<const0> ;
  assign m_axi_s2mm_awburst[1] = \<const0> ;
  assign m_axi_s2mm_awburst[0] = \<const0> ;
  assign m_axi_s2mm_awcache[3] = \<const0> ;
  assign m_axi_s2mm_awcache[2] = \<const0> ;
  assign m_axi_s2mm_awcache[1] = \<const0> ;
  assign m_axi_s2mm_awcache[0] = \<const0> ;
  assign m_axi_s2mm_awlen[7] = \<const0> ;
  assign m_axi_s2mm_awlen[6] = \<const0> ;
  assign m_axi_s2mm_awlen[5] = \<const0> ;
  assign m_axi_s2mm_awlen[4] = \<const0> ;
  assign m_axi_s2mm_awlen[3] = \<const0> ;
  assign m_axi_s2mm_awlen[2] = \<const0> ;
  assign m_axi_s2mm_awlen[1] = \<const0> ;
  assign m_axi_s2mm_awlen[0] = \<const0> ;
  assign m_axi_s2mm_awprot[2] = \<const0> ;
  assign m_axi_s2mm_awprot[1] = \<const0> ;
  assign m_axi_s2mm_awprot[0] = \<const0> ;
  assign m_axi_s2mm_awsize[2] = \<const0> ;
  assign m_axi_s2mm_awsize[1] = \<const0> ;
  assign m_axi_s2mm_awsize[0] = \<const0> ;
  assign m_axi_s2mm_awuser[3] = \<const0> ;
  assign m_axi_s2mm_awuser[2] = \<const0> ;
  assign m_axi_s2mm_awuser[1] = \<const0> ;
  assign m_axi_s2mm_awuser[0] = \<const0> ;
  assign m_axi_s2mm_awvalid = \<const0> ;
  assign m_axi_s2mm_bready = \<const0> ;
  assign m_axi_s2mm_wdata[31] = \<const0> ;
  assign m_axi_s2mm_wdata[30] = \<const0> ;
  assign m_axi_s2mm_wdata[29] = \<const0> ;
  assign m_axi_s2mm_wdata[28] = \<const0> ;
  assign m_axi_s2mm_wdata[27] = \<const0> ;
  assign m_axi_s2mm_wdata[26] = \<const0> ;
  assign m_axi_s2mm_wdata[25] = \<const0> ;
  assign m_axi_s2mm_wdata[24] = \<const0> ;
  assign m_axi_s2mm_wdata[23] = \<const0> ;
  assign m_axi_s2mm_wdata[22] = \<const0> ;
  assign m_axi_s2mm_wdata[21] = \<const0> ;
  assign m_axi_s2mm_wdata[20] = \<const0> ;
  assign m_axi_s2mm_wdata[19] = \<const0> ;
  assign m_axi_s2mm_wdata[18] = \<const0> ;
  assign m_axi_s2mm_wdata[17] = \<const0> ;
  assign m_axi_s2mm_wdata[16] = \<const0> ;
  assign m_axi_s2mm_wdata[15] = \<const0> ;
  assign m_axi_s2mm_wdata[14] = \<const0> ;
  assign m_axi_s2mm_wdata[13] = \<const0> ;
  assign m_axi_s2mm_wdata[12] = \<const0> ;
  assign m_axi_s2mm_wdata[11] = \<const0> ;
  assign m_axi_s2mm_wdata[10] = \<const0> ;
  assign m_axi_s2mm_wdata[9] = \<const0> ;
  assign m_axi_s2mm_wdata[8] = \<const0> ;
  assign m_axi_s2mm_wdata[7] = \<const0> ;
  assign m_axi_s2mm_wdata[6] = \<const0> ;
  assign m_axi_s2mm_wdata[5] = \<const0> ;
  assign m_axi_s2mm_wdata[4] = \<const0> ;
  assign m_axi_s2mm_wdata[3] = \<const0> ;
  assign m_axi_s2mm_wdata[2] = \<const0> ;
  assign m_axi_s2mm_wdata[1] = \<const0> ;
  assign m_axi_s2mm_wdata[0] = \<const0> ;
  assign m_axi_s2mm_wlast = \<const0> ;
  assign m_axi_s2mm_wstrb[3] = \<const0> ;
  assign m_axi_s2mm_wstrb[2] = \<const0> ;
  assign m_axi_s2mm_wstrb[1] = \<const0> ;
  assign m_axi_s2mm_wstrb[0] = \<const0> ;
  assign m_axi_s2mm_wvalid = \<const0> ;
  assign m_axi_sg_araddr[31:6] = \^m_axi_sg_araddr [31:6];
  assign m_axi_sg_araddr[5] = \<const0> ;
  assign m_axi_sg_araddr[4] = \<const0> ;
  assign m_axi_sg_araddr[3] = \<const0> ;
  assign m_axi_sg_araddr[2] = \<const0> ;
  assign m_axi_sg_araddr[1] = \<const0> ;
  assign m_axi_sg_araddr[0] = \<const0> ;
  assign m_axi_sg_arburst[1] = \<const0> ;
  assign m_axi_sg_arburst[0] = \^m_axi_sg_arburst [0];
  assign m_axi_sg_arcache[3] = \<const0> ;
  assign m_axi_sg_arcache[2] = \<const0> ;
  assign m_axi_sg_arcache[1] = \<const0> ;
  assign m_axi_sg_arcache[0] = \<const0> ;
  assign m_axi_sg_arlen[7] = \<const0> ;
  assign m_axi_sg_arlen[6] = \<const0> ;
  assign m_axi_sg_arlen[5] = \<const0> ;
  assign m_axi_sg_arlen[4] = \<const0> ;
  assign m_axi_sg_arlen[3] = \^m_axi_sg_arlen [3];
  assign m_axi_sg_arlen[2] = \^m_axi_sg_arsize [1];
  assign m_axi_sg_arlen[1] = \^m_axi_sg_arlen [0];
  assign m_axi_sg_arlen[0] = \^m_axi_sg_arlen [0];
  assign m_axi_sg_arprot[2] = \<const0> ;
  assign m_axi_sg_arprot[1] = \<const0> ;
  assign m_axi_sg_arprot[0] = \<const0> ;
  assign m_axi_sg_arsize[2] = \<const0> ;
  assign m_axi_sg_arsize[1] = \^m_axi_sg_arsize [1];
  assign m_axi_sg_arsize[0] = \<const0> ;
  assign m_axi_sg_aruser[3] = \<const0> ;
  assign m_axi_sg_aruser[2] = \<const0> ;
  assign m_axi_sg_aruser[1] = \<const0> ;
  assign m_axi_sg_aruser[0] = \<const0> ;
  assign m_axi_sg_awaddr[31:6] = \^m_axi_sg_awaddr [31:6];
  assign m_axi_sg_awaddr[5] = \<const0> ;
  assign m_axi_sg_awaddr[4] = \^m_axi_sg_awaddr [4];
  assign m_axi_sg_awaddr[3] = \^m_axi_sg_awaddr [2];
  assign m_axi_sg_awaddr[2] = \^m_axi_sg_awaddr [2];
  assign m_axi_sg_awaddr[1] = \<const0> ;
  assign m_axi_sg_awaddr[0] = \<const0> ;
  assign m_axi_sg_awburst[1] = \<const0> ;
  assign m_axi_sg_awburst[0] = \^m_axi_sg_awaddr [2];
  assign m_axi_sg_awcache[3] = \<const0> ;
  assign m_axi_sg_awcache[2] = \<const0> ;
  assign m_axi_sg_awcache[1] = \<const0> ;
  assign m_axi_sg_awcache[0] = \<const0> ;
  assign m_axi_sg_awlen[7] = \<const0> ;
  assign m_axi_sg_awlen[6] = \<const0> ;
  assign m_axi_sg_awlen[5] = \<const0> ;
  assign m_axi_sg_awlen[4] = \<const0> ;
  assign m_axi_sg_awlen[3] = \<const0> ;
  assign m_axi_sg_awlen[2] = \^m_axi_sg_awlen [0];
  assign m_axi_sg_awlen[1] = \<const0> ;
  assign m_axi_sg_awlen[0] = \^m_axi_sg_awlen [0];
  assign m_axi_sg_awprot[2] = \<const0> ;
  assign m_axi_sg_awprot[1] = \<const0> ;
  assign m_axi_sg_awprot[0] = \<const0> ;
  assign m_axi_sg_awsize[2] = \<const0> ;
  assign m_axi_sg_awsize[1] = \^m_axi_sg_awsize [1];
  assign m_axi_sg_awsize[0] = \<const0> ;
  assign m_axi_sg_awuser[3] = \<const0> ;
  assign m_axi_sg_awuser[2] = \<const0> ;
  assign m_axi_sg_awuser[1] = \<const0> ;
  assign m_axi_sg_awuser[0] = \<const0> ;
  assign m_axi_sg_wdata[31:28] = \^m_axi_sg_wdata [31:28];
  assign m_axi_sg_wdata[27] = \<const0> ;
  assign m_axi_sg_wdata[26] = \<const0> ;
  assign m_axi_sg_wdata[25:0] = \^m_axi_sg_wdata [25:0];
  assign m_axi_sg_wstrb[3] = \^m_axi_sg_wstrb [0];
  assign m_axi_sg_wstrb[2] = \^m_axi_sg_wstrb [0];
  assign m_axi_sg_wstrb[1] = \^m_axi_sg_wstrb [0];
  assign m_axi_sg_wstrb[0] = \^m_axi_sg_wstrb [0];
  assign m_axis_mm2s_cntrl_tkeep[3] = \<const0> ;
  assign m_axis_mm2s_cntrl_tkeep[2] = \<const0> ;
  assign m_axis_mm2s_cntrl_tkeep[1] = \<const0> ;
  assign m_axis_mm2s_cntrl_tkeep[0] = \<const0> ;
  assign m_axis_mm2s_tdest[4] = \<const0> ;
  assign m_axis_mm2s_tdest[3] = \<const0> ;
  assign m_axis_mm2s_tdest[2] = \<const0> ;
  assign m_axis_mm2s_tdest[1] = \<const0> ;
  assign m_axis_mm2s_tdest[0] = \<const0> ;
  assign m_axis_mm2s_tid[4] = \<const0> ;
  assign m_axis_mm2s_tid[3] = \<const0> ;
  assign m_axis_mm2s_tid[2] = \<const0> ;
  assign m_axis_mm2s_tid[1] = \<const0> ;
  assign m_axis_mm2s_tid[0] = \<const0> ;
  assign m_axis_mm2s_tuser[3] = \<const0> ;
  assign m_axis_mm2s_tuser[2] = \<const0> ;
  assign m_axis_mm2s_tuser[1] = \<const0> ;
  assign m_axis_mm2s_tuser[0] = \<const0> ;
  assign s2mm_introut = \<const0> ;
  assign s2mm_prmry_reset_out_n = \<const0> ;
  assign s2mm_sts_reset_out_n = \<const0> ;
  assign s_axi_lite_awready = s_axi_lite_wready;
  assign s_axi_lite_bresp[1] = \<const0> ;
  assign s_axi_lite_bresp[0] = \<const0> ;
  assign s_axi_lite_rresp[1] = \<const0> ;
  assign s_axi_lite_rresp[0] = \<const0> ;
  assign s_axis_s2mm_sts_tready = \<const0> ;
  assign s_axis_s2mm_tready = \<const0> ;
  Loopback_axi_dma_1_0_axi_sg \GEN_SG_ENGINE.I_SG_ENGINE 
       (.CO(\GEN_SG_ENGINE.I_SG_ENGINE_n_45 ),
        .D({s_axis_mm2s_updtsts_tdata[32:28],s_axis_mm2s_updtsts_tdata[25:0]}),
        .E(\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/ptr_queue_wren ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_56 ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg_0 (\GEN_SG_ENGINE.I_SG_ENGINE_n_102 ),
        .\GEN_CH1_FETCH.ch1_active_i_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_53 ),
        .\GEN_CH1_FETCH.ch1_ftch_decerr_set_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_225 ),
        .\GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_223 ),
        .\GEN_CH1_FETCH.ch1_ftch_slverr_set_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_224 ),
        .\GEN_CH1_UPDATE.ch1_dma_decerr_set_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_222 ),
        .\GEN_CH1_UPDATE.ch1_dma_interr_set_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_220 ),
        .\GEN_CH1_UPDATE.ch1_dma_slverr_set_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_221 ),
        .\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg (\^axi_dma_tstvec [4]),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_5 ),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg (\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_SOFEOF_GEN_n_0 ),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] (I_AXI_DMA_REG_MODULE_n_76),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] (mm2s_irqdelay_status),
        .\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg (I_AXI_DMA_REG_MODULE_n_26),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2] (\GEN_SG_ENGINE.I_SG_ENGINE_n_65 ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] (\GEN_SG_ENGINE.I_SG_ENGINE_n_66 ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ({I_AXI_DMA_REG_MODULE_n_30,I_AXI_DMA_REG_MODULE_n_31,I_AXI_DMA_REG_MODULE_n_32}),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] (I_AXI_DMA_REG_MODULE_n_33),
        .\GEN_MM2S.queue_dout_new_reg[64] (\GEN_SG_ENGINE.I_SG_ENGINE_n_219 ),
        .\GEN_MM2S.queue_dout_new_reg[90] ({m_axis_mm2s_ftch_tdata_new[96:71],m_axis_mm2s_ftch_tdata_new[64],m_axis_mm2s_ftch_tdata_new[58:0]}),
        .\GEN_MM2S.queue_dout_new_reg[90]_0 (\I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_rden_new ),
        .\GEN_MM2S.reg1_reg[90] (\I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_sinit0_out ),
        .\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] (ch1_fetch_address_i),
        .\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 (mm2s_curdesc),
        .\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg (I_AXI_DMA_REG_MODULE_n_19),
        .\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31] (s_axis_mm2s_updtptr_tdata),
        .\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32] (\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts_queue_wren ),
        .\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg (I_AXI_DMA_REG_MODULE_n_25),
        .Q(mm2s_irqthresh_status),
        .S({I_AXI_DMA_REG_MODULE_n_34,I_AXI_DMA_REG_MODULE_n_35,I_AXI_DMA_REG_MODULE_n_36,I_AXI_DMA_REG_MODULE_n_37,I_AXI_DMA_REG_MODULE_n_38,I_AXI_DMA_REG_MODULE_n_39,I_AXI_DMA_REG_MODULE_n_40}),
        .SR(\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SM/cmnds_queued_shift0 ),
        .ch1_delay_cnt_en(\GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/ch1_delay_cnt_en ),
        .ch1_delay_count0(\GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/ch1_delay_count0 ),
        .ch1_dly_fast_cnt0(\GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/ch1_dly_fast_cnt0 ),
        .ch1_ftch_queue_empty(ch1_ftch_queue_empty),
        .ch1_nxtdesc_wren(ch1_nxtdesc_wren),
        .ch1_sg_idle(\I_SG_FETCH_MNGR/ch1_sg_idle ),
        .\ch1_sg_idle1_inferred__0/i__carry (mm2s_taildesc),
        .\counter_reg[1] (\I_SG_FETCH_QUEUE/sof_ftch_desc0 ),
        .dma_decerr_reg(I_AXI_DMA_REG_MODULE_n_3),
        .dma_interr_reg(I_AXI_DMA_REG_MODULE_n_1),
        .dma_mm2s_error(dma_mm2s_error),
        .dma_slverr_reg(I_AXI_DMA_REG_MODULE_n_2),
        .\ftch_error_addr_reg[31]_0 (ftch_error_addr),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_araddr(\^m_axi_sg_araddr ),
        .m_axi_sg_arburst(\^m_axi_sg_arburst ),
        .m_axi_sg_arlen({\^m_axi_sg_arlen [3],\^m_axi_sg_arsize ,\^m_axi_sg_arlen [0]}),
        .m_axi_sg_arready(m_axi_sg_arready),
        .m_axi_sg_arvalid(m_axi_sg_arvalid),
        .m_axi_sg_awaddr({\^m_axi_sg_awaddr [31:6],\^m_axi_sg_awaddr [4],\^m_axi_sg_awaddr [2]}),
        .m_axi_sg_awlen(\^m_axi_sg_awlen ),
        .m_axi_sg_awready(m_axi_sg_awready),
        .m_axi_sg_awsize(\^m_axi_sg_awsize ),
        .m_axi_sg_awvalid(m_axi_sg_awvalid),
        .m_axi_sg_bready(m_axi_sg_bready),
        .m_axi_sg_bresp(m_axi_sg_bresp),
        .m_axi_sg_bvalid(m_axi_sg_bvalid),
        .m_axi_sg_rdata(m_axi_sg_rdata),
        .m_axi_sg_rlast(m_axi_sg_rlast),
        .m_axi_sg_rready(m_axi_sg_rready),
        .m_axi_sg_rresp(m_axi_sg_rresp),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .m_axi_sg_wdata({\^m_axi_sg_wdata [31:28],\^m_axi_sg_wdata [25:0]}),
        .m_axi_sg_wlast(m_axi_sg_wlast),
        .m_axi_sg_wready(m_axi_sg_wready),
        .m_axi_sg_wvalid(m_axi_sg_wvalid),
        .m_axis_mm2s_cntrl_tdata(m_axis_mm2s_cntrl_tdata),
        .m_axis_mm2s_cntrl_tlast(m_axis_mm2s_cntrl_tlast),
        .m_axis_mm2s_cntrl_tready(m_axis_mm2s_cntrl_tready),
        .m_axis_mm2s_cntrl_tvalid(m_axis_mm2s_cntrl_tvalid),
        .m_axis_mm2s_ftch_tvalid_new(m_axis_mm2s_ftch_tvalid_new),
        .mm2s_cntrl_strm_stop(mm2s_cntrl_strm_stop),
        .mm2s_dly_irq_set(mm2s_dly_irq_set),
        .mm2s_dmacr({mm2s_dmacr[23:21],mm2s_dmacr[19:18],mm2s_dmacr[4],mm2s_dmacr[0]}),
        .mm2s_ftch_idle(mm2s_ftch_idle),
        .mm2s_ioc_irq_set(mm2s_ioc_irq_set),
        .mm2s_irqthresh_wren(mm2s_irqthresh_wren),
        .mm2s_stop_i(mm2s_stop_i),
        .mm2s_updt_decerr_set(mm2s_updt_decerr_set),
        .mm2s_updt_idle(mm2s_updt_idle),
        .mm2s_updt_interr_set(mm2s_updt_interr_set),
        .mm2s_updt_slverr_set(mm2s_updt_slverr_set),
        .out(m_axi_sg_aresetn),
        .packet_in_progress(packet_in_progress),
        .ptr_queue_full(ptr_queue_full),
        .queue_empty_new0(\I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_empty_new0 ),
        .rst(\I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_MM2S.CONTROL_STREAM.I_MM2S_CNTRL_STREAM/sinit ),
        .s_axis_mm2s_cmd_tready(s_axis_mm2s_cmd_tready),
        .s_axis_mm2s_cmd_tvalid_split(s_axis_mm2s_cmd_tvalid_split),
        .s_axis_mm2s_updtptr_tlast(s_axis_mm2s_updtptr_tlast),
        .sg_decerr_reg(I_AXI_DMA_REG_MODULE_n_6),
        .sg_ftch_error0(\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/sg_ftch_error0 ),
        .sg_interr_reg(I_AXI_DMA_REG_MODULE_n_4),
        .sg_slverr_reg(I_AXI_DMA_REG_MODULE_n_5),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(\^m_axi_sg_wstrb ),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0(dm_m_axi_sg_aresetn),
        .sinit(\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sinit ),
        .soft_reset(soft_reset),
        .soft_reset_d1(soft_reset_d1),
        .soft_reset_d2(soft_reset_d2),
        .sts_queue_full(sts_queue_full));
  GND GND
       (.G(\<const0> ));
  Loopback_axi_dma_1_0_axi_dma_mm2s_mngr \INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR 
       (.D({s_axis_mm2s_updtsts_tdata[32:28],s_axis_mm2s_updtsts_tdata[25:0]}),
        .E(\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/ptr_queue_wren ),
        .FIFO_Full_reg(\I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_rden_new ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR_n_11 ),
        .\GEN_MM2S.queue_empty_new_reg (\I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_sinit0_out ),
        .\GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_219 ),
        .\GEN_SYNC_FIFO.mm2s_stop_d1_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_53 ),
        .Q(s_axis_mm2s_updtptr_tdata),
        .SR(\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SM/cmnds_queued_shift0 ),
        .all_is_idle_d1_reg(I_AXI_DMA_REG_MODULE_n_25),
        .ch1_ftch_queue_empty(ch1_ftch_queue_empty),
        .dma_mm2s_error(dma_mm2s_error),
        .idle_reg(I_AXI_DMA_REG_MODULE_n_18),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_mm2s_ftch_tvalid_new(m_axis_mm2s_ftch_tvalid_new),
        .m_axis_mm2s_sts_tready(m_axis_mm2s_sts_tready),
        .m_axis_mm2s_sts_tvalid_int(m_axis_mm2s_sts_tvalid_int),
        .mm2s_all_idle(mm2s_all_idle),
        .mm2s_cntrl_strm_stop(mm2s_cntrl_strm_stop),
        .mm2s_decerr_i(\GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS/mm2s_decerr_i ),
        .mm2s_dmacr(mm2s_dmacr[0]),
        .mm2s_dmasr(mm2s_dmasr),
        .mm2s_ftch_idle(mm2s_ftch_idle),
        .mm2s_halt(mm2s_halt),
        .mm2s_halted_set0(\GEN_MM2S_DMA_CONTROL.I_MM2S_STS_MNGR/mm2s_halted_set0 ),
        .mm2s_halted_set_reg(\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR_n_10 ),
        .mm2s_interr_i(\GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS/mm2s_interr_i ),
        .mm2s_slverr_i(\GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS/mm2s_slverr_i ),
        .mm2s_stop(mm2s_stop),
        .mm2s_stop_i(mm2s_stop_i),
        .mm2s_sts_received(mm2s_sts_received),
        .\mm2s_tag_reg[0] (I_PRMRY_DATAMOVER_n_11),
        .mm2s_updt_idle(mm2s_updt_idle),
        .out(m_axi_sg_aresetn),
        .packet_in_progress(packet_in_progress),
        .packet_in_progress_reg(\GEN_SG_ENGINE.I_SG_ENGINE_n_102 ),
        .ptr_queue_full(ptr_queue_full),
        .queue_empty_new0(\I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_empty_new0 ),
        .rst(\I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_MM2S.CONTROL_STREAM.I_MM2S_CNTRL_STREAM/sinit ),
        .s_axis_mm2s_cmd_tvalid_split(s_axis_mm2s_cmd_tvalid_split),
        .s_axis_mm2s_updtptr_tlast(s_axis_mm2s_updtptr_tlast),
        .s_halt0(\GEN_RESET_FOR_MM2S.RESET_I/s_halt0 ),
        .sinit(\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sinit ),
        .soft_reset(soft_reset),
        .soft_reset_d1(soft_reset_d1),
        .soft_reset_d2(soft_reset_d2),
        .soft_reset_re(\GEN_RESET_FOR_MM2S.RESET_I/soft_reset_re ),
        .sts_queue_full(sts_queue_full),
        .updt_data_reg(\GEN_SG_ENGINE.I_SG_ENGINE_n_56 ),
        .\updt_desc_reg0_reg[31] ({m_axis_mm2s_ftch_tdata_new[96:71],m_axis_mm2s_ftch_tdata_new[64],m_axis_mm2s_ftch_tdata_new[57:32]}),
        .updt_sts_reg(\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts_queue_wren ));
  Loopback_axi_dma_1_0_axi_dma_sofeof_gen \INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_SOFEOF_GEN 
       (.\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg (\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_SOFEOF_GEN_n_0 ),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg_0 (I_AXI_DMA_REG_MODULE_n_28),
        .axi_dma_tstvec(\^axi_dma_tstvec [1:0]),
        .ch1_delay_cnt_en(\GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/ch1_delay_cnt_en ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_mm2s_tlast(m_axis_mm2s_tlast),
        .m_axis_mm2s_tready(m_axis_mm2s_tready),
        .m_axis_mm2s_tvalid(m_axis_mm2s_tvalid),
        .out(mm2s_prmry_resetn),
        .sinit(\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sinit ));
  Loopback_axi_dma_1_0_axi_dma_reg_module I_AXI_DMA_REG_MODULE
       (.CO(\GEN_SG_ENGINE.I_SG_ENGINE_n_45 ),
        .D(s_axis_mm2s_cmd_tdata_split),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23] (mm2s_irqthresh_status),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31] (mm2s_irqdelay_status),
        .\GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg (s_axi_lite_rvalid),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_sinit0_out ),
        .\GEN_ASYNC_WRITE.axi2ip_wrce_reg[4] (m_axi_sg_hrdresetn),
        .\GEN_ASYNC_WRITE.bvalid_i_reg (axi_lite_reset_n),
        .\GEN_ASYNC_WRITE.rdy_to2 (\GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.rdy_to2 ),
        .\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] (mm2s_curdesc),
        .\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 (m_axis_mm2s_ftch_tdata_new[96:71]),
        .\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 (ftch_error_addr),
        .\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[11] (mm2s_taildesc),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg (I_AXI_DMA_REG_MODULE_n_76),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] (\GEN_SG_ENGINE.I_SG_ENGINE_n_5 ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] (\GEN_SG_ENGINE.I_SG_ENGINE_n_65 ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 (\GEN_SG_ENGINE.I_SG_ENGINE_n_66 ),
        .\GEN_MM2S_DMA_CONTROL.mm2s_stop_reg (\GEN_SG_ENGINE.I_SG_ENGINE_n_53 ),
        .\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg (I_AXI_DMA_REG_MODULE_n_19),
        .Q(I_AXI_DMA_REG_MODULE_n_26),
        .S({I_AXI_DMA_REG_MODULE_n_34,I_AXI_DMA_REG_MODULE_n_35,I_AXI_DMA_REG_MODULE_n_36,I_AXI_DMA_REG_MODULE_n_37,I_AXI_DMA_REG_MODULE_n_38,I_AXI_DMA_REG_MODULE_n_39,I_AXI_DMA_REG_MODULE_n_40}),
        .SR(I_RST_MODULE_n_17),
        .axi_dma_tstvec(\^axi_dma_tstvec [0]),
        .ch1_delay_cnt_en(\GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/ch1_delay_cnt_en ),
        .ch1_delay_count0(\GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/ch1_delay_count0 ),
        .ch1_dly_fast_cnt0(\GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/ch1_dly_fast_cnt0 ),
        .ch1_nxtdesc_wren(ch1_nxtdesc_wren),
        .ch1_sg_idle(\I_SG_FETCH_MNGR/ch1_sg_idle ),
        .\ch1_sg_idle1_inferred__0/i__carry (ch1_fetch_address_i),
        .dma_decerr_reg(I_AXI_DMA_REG_MODULE_n_3),
        .dma_decerr_reg_0(\GEN_SG_ENGINE.I_SG_ENGINE_n_222 ),
        .dma_interr_reg(I_AXI_DMA_REG_MODULE_n_1),
        .dma_interr_reg_0(\GEN_SG_ENGINE.I_SG_ENGINE_n_220 ),
        .dma_slverr_reg(I_AXI_DMA_REG_MODULE_n_2),
        .dma_slverr_reg_0(\GEN_SG_ENGINE.I_SG_ENGINE_n_221 ),
        .\dmacr_i_reg[0] (I_AXI_DMA_REG_MODULE_n_28),
        .\dmacr_i_reg[0]_0 (I_RST_MODULE_n_13),
        .\dmacr_i_reg[20] ({I_AXI_DMA_REG_MODULE_n_30,I_AXI_DMA_REG_MODULE_n_31,I_AXI_DMA_REG_MODULE_n_32}),
        .\dmacr_i_reg[23] ({mm2s_dmacr[23:21],mm2s_dmacr[19:18],mm2s_dmacr[4],mm2s_dmacr[0]}),
        .halted_reg(\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR_n_11 ),
        .idle_reg(I_AXI_DMA_REG_MODULE_n_18),
        .idle_reg_0(\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR_n_10 ),
        .irqthresh_wren_reg(I_AXI_DMA_REG_MODULE_n_33),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_mm2s_ftch_tvalid_new(m_axis_mm2s_ftch_tvalid_new),
        .mm2s_all_idle(mm2s_all_idle),
        .mm2s_dly_irq_set(mm2s_dly_irq_set),
        .mm2s_dmasr(mm2s_dmasr),
        .mm2s_halt_cmplt(mm2s_halt_cmplt),
        .mm2s_halted_set0(\GEN_MM2S_DMA_CONTROL.I_MM2S_STS_MNGR/mm2s_halted_set0 ),
        .mm2s_introut(mm2s_introut),
        .mm2s_ioc_irq_set(mm2s_ioc_irq_set),
        .mm2s_irqthresh_wren(mm2s_irqthresh_wren),
        .mm2s_stop(mm2s_stop),
        .mm2s_stop_i(mm2s_stop_i),
        .mm2s_updt_decerr_set(mm2s_updt_decerr_set),
        .mm2s_updt_interr_set(mm2s_updt_interr_set),
        .mm2s_updt_slverr_set(mm2s_updt_slverr_set),
        .out(m_axi_sg_aresetn),
        .p_0_in(p_0_in),
        .packet_in_progress(packet_in_progress),
        .packet_in_progress_reg(I_AXI_DMA_REG_MODULE_n_25),
        .s_axi_lite_aclk(s_axi_lite_aclk),
        .s_axi_lite_araddr(s_axi_lite_araddr),
        .s_axi_lite_arready(s_axi_lite_arready),
        .s_axi_lite_arvalid(s_axi_lite_arvalid),
        .s_axi_lite_awaddr(s_axi_lite_awaddr[6:2]),
        .s_axi_lite_awvalid(s_axi_lite_awvalid),
        .s_axi_lite_bready(s_axi_lite_bready),
        .s_axi_lite_bvalid(s_axi_lite_bvalid),
        .s_axi_lite_rdata(s_axi_lite_rdata),
        .s_axi_lite_rready(s_axi_lite_rready),
        .s_axi_lite_wdata({s_axi_lite_wdata[31:6],s_axi_lite_wdata[4:2],s_axi_lite_wdata[0]}),
        .s_axi_lite_wready(s_axi_lite_wready),
        .s_axi_lite_wvalid(s_axi_lite_wvalid),
        .scndry_out(\GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.rdy_to ),
        .sg_decerr_reg(I_AXI_DMA_REG_MODULE_n_6),
        .sg_decerr_reg_0(\GEN_SG_ENGINE.I_SG_ENGINE_n_225 ),
        .sg_ftch_error0(\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/sg_ftch_error0 ),
        .sg_interr_reg(I_AXI_DMA_REG_MODULE_n_4),
        .sg_interr_reg_0(\GEN_SG_ENGINE.I_SG_ENGINE_n_223 ),
        .sg_slverr_reg(I_AXI_DMA_REG_MODULE_n_5),
        .sg_slverr_reg_0(\GEN_SG_ENGINE.I_SG_ENGINE_n_224 ),
        .sinit(\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sinit ),
        .soft_reset(soft_reset),
        .soft_reset_clr(soft_reset_clr),
        .soft_reset_d1(\GEN_RESET_FOR_MM2S.RESET_I/soft_reset_d1 ),
        .soft_reset_re0(\GEN_RESET_FOR_MM2S.RESET_I/soft_reset_re0 ));
  Loopback_axi_dma_1_0_axi_datamover I_PRMRY_DATAMOVER
       (.D({m_axis_mm2s_ftch_tdata_new[31:0],m_axis_mm2s_ftch_tdata_new[58],s_axis_mm2s_cmd_tdata_split,m_axis_mm2s_ftch_tdata_new[57:32]}),
        .\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[0] (I_PRMRY_DATAMOVER_n_11),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axi_mm2s_araddr(m_axi_mm2s_araddr),
        .m_axi_mm2s_arburst(\^m_axi_mm2s_arburst ),
        .m_axi_mm2s_arlen(\^m_axi_mm2s_arlen ),
        .m_axi_mm2s_arready(m_axi_mm2s_arready),
        .m_axi_mm2s_arsize(\^m_axi_mm2s_arsize ),
        .m_axi_mm2s_arvalid(m_axi_mm2s_arvalid),
        .m_axi_mm2s_rdata(m_axi_mm2s_rdata),
        .m_axi_mm2s_rlast(m_axi_mm2s_rlast),
        .m_axi_mm2s_rready(m_axi_mm2s_rready),
        .m_axi_mm2s_rresp(m_axi_mm2s_rresp),
        .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_mm2s_sts_tready(m_axis_mm2s_sts_tready),
        .m_axis_mm2s_sts_tvalid_int(m_axis_mm2s_sts_tvalid_int),
        .m_axis_mm2s_tdata(m_axis_mm2s_tdata),
        .m_axis_mm2s_tkeep(m_axis_mm2s_tkeep),
        .m_axis_mm2s_tlast(m_axis_mm2s_tlast),
        .m_axis_mm2s_tready(m_axis_mm2s_tready),
        .m_axis_mm2s_tvalid(m_axis_mm2s_tvalid),
        .mm2s_decerr_i(\GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS/mm2s_decerr_i ),
        .mm2s_halt_cmplt(mm2s_halt_cmplt),
        .mm2s_interr_i(\GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS/mm2s_interr_i ),
        .mm2s_slverr_i(\GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS/mm2s_slverr_i ),
        .mm2s_sts_received(mm2s_sts_received),
        .out(m_axi_mm2s_aresetn),
        .s_axis_mm2s_cmd_tready(s_axis_mm2s_cmd_tready),
        .s_axis_mm2s_cmd_tvalid_split(s_axis_mm2s_cmd_tvalid_split),
        .sig_rst2all_stop_request(\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request ),
        .sig_s_h_halt_reg_reg(I_RST_MODULE_n_18));
  Loopback_axi_dma_1_0_axi_dma_rst_module I_RST_MODULE
       (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (mm2s_prmry_resetn),
        .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (m_axi_mm2s_aresetn),
        .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 (m_axi_sg_hrdresetn),
        .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_2 (axi_lite_reset_n),
        .\GEN_ASYNC_RESET.halt_i_reg (I_RST_MODULE_n_18),
        .\GEN_ASYNC_RESET.s_soft_reset_i_reg (dm_m_axi_sg_aresetn),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (I_RST_MODULE_n_13),
        .\GEN_ASYNC_WRITE.rdy_to2 (\GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.rdy_to2 ),
        .SR(I_RST_MODULE_n_17),
        .axi_resetn(axi_resetn),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_rlast(m_axi_sg_rlast),
        .m_axi_sg_rlast_0(\I_SG_FETCH_QUEUE/sof_ftch_desc0 ),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .mm2s_all_idle(mm2s_all_idle),
        .mm2s_cntrl_reset_out_n(mm2s_cntrl_reset_out_n),
        .mm2s_halt(mm2s_halt),
        .mm2s_halt_cmplt(mm2s_halt_cmplt),
        .mm2s_prmry_reset_out_n(mm2s_prmry_reset_out_n),
        .out(m_axi_sg_aresetn),
        .p_0_in(p_0_in),
        .s_axi_lite_aclk(s_axi_lite_aclk),
        .s_halt0(\GEN_RESET_FOR_MM2S.RESET_I/s_halt0 ),
        .scndry_out(\GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.rdy_to ),
        .sig_rst2all_stop_request(\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request ),
        .sinit(\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sinit ),
        .soft_reset(soft_reset),
        .soft_reset_clr(soft_reset_clr),
        .soft_reset_d1(\GEN_RESET_FOR_MM2S.RESET_I/soft_reset_d1 ),
        .soft_reset_re(\GEN_RESET_FOR_MM2S.RESET_I/soft_reset_re ),
        .soft_reset_re0(\GEN_RESET_FOR_MM2S.RESET_I/soft_reset_re0 ));
endmodule

module Loopback_axi_dma_1_0_axi_dma_lite_if
   (s_axi_lite_arready,
    \GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg_0 ,
    E,
    axi2ip_wrce,
    p_0_in1_in,
    s_axi_lite_bvalid,
    irqthresh_wren0,
    scndry_vect_out,
    irqdelay_wren0,
    \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4]_0 ,
    SS,
    scndry_out,
    s_axi_lite_wready,
    \dmacr_i_reg[2] ,
    s_axi_lite_rdata,
    \GEN_ASYNC_WRITE.rdy_to2 ,
    s_axi_lite_aclk,
    p_0_in,
    s_axi_lite_arvalid,
    SR,
    m_axi_sg_aclk,
    s_axi_lite_awvalid,
    s_axi_lite_wvalid,
    Q,
    irqthresh_wren_reg,
    mm2s_dmacr,
    irqdelay_wren_reg,
    out,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[0]_0 ,
    mm2s_dmasr,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[1]_0 ,
    \dmacr_i_reg[2]_0 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[4]_0 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[4]_1 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[5]_0 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[6]_0 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[8]_0 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[9]_0 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[10]_0 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_0 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_1 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[12]_0 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[13]_0 ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 ,
    \GEN_ASYNC_WRITE.bvalid_i_reg_0 ,
    s_axi_lite_bready,
    \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4]_1 ,
    s_axi_lite_rready,
    soft_reset_clr,
    s_axi_lite_awaddr,
    s_axi_lite_wdata,
    s_axi_lite_araddr);
  output s_axi_lite_arready;
  output \GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg_0 ;
  output [0:0]E;
  output [1:0]axi2ip_wrce;
  output p_0_in1_in;
  output s_axi_lite_bvalid;
  output irqthresh_wren0;
  output [28:0]scndry_vect_out;
  output irqdelay_wren0;
  output \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4]_0 ;
  output [0:0]SS;
  output scndry_out;
  output s_axi_lite_wready;
  output \dmacr_i_reg[2] ;
  output [31:0]s_axi_lite_rdata;
  input \GEN_ASYNC_WRITE.rdy_to2 ;
  input s_axi_lite_aclk;
  input p_0_in;
  input s_axi_lite_arvalid;
  input [0:0]SR;
  input m_axi_sg_aclk;
  input s_axi_lite_awvalid;
  input s_axi_lite_wvalid;
  input [7:0]Q;
  input irqthresh_wren_reg;
  input [8:0]mm2s_dmacr;
  input irqdelay_wren_reg;
  input out;
  input \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[0]_0 ;
  input mm2s_dmasr;
  input \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[1]_0 ;
  input \dmacr_i_reg[2]_0 ;
  input [0:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[4]_0 ;
  input \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[4]_1 ;
  input \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[5]_0 ;
  input \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[6]_0 ;
  input [25:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 ;
  input [25:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 ;
  input \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[8]_0 ;
  input \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[9]_0 ;
  input \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[10]_0 ;
  input [2:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_0 ;
  input \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_1 ;
  input [7:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 ;
  input \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[12]_0 ;
  input \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[13]_0 ;
  input [7:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 ;
  input \GEN_ASYNC_WRITE.bvalid_i_reg_0 ;
  input s_axi_lite_bready;
  input \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4]_1 ;
  input s_axi_lite_rready;
  input soft_reset_clr;
  input [4:0]s_axi_lite_awaddr;
  input [29:0]s_axi_lite_wdata;
  input [9:0]s_axi_lite_araddr;

  wire [0:0]E;
  wire [9:0]\GEN_ASYNC_READ.araddr_d3 ;
  wire \GEN_ASYNC_READ.arready_d1 ;
  wire \GEN_ASYNC_READ.arready_d10 ;
  wire \GEN_ASYNC_READ.arready_d11 ;
  wire \GEN_ASYNC_READ.arready_d12 ;
  wire \GEN_ASYNC_READ.arready_d2 ;
  wire \GEN_ASYNC_READ.arready_d3 ;
  wire \GEN_ASYNC_READ.arready_d4 ;
  wire \GEN_ASYNC_READ.arready_d5 ;
  wire \GEN_ASYNC_READ.arready_d6 ;
  wire \GEN_ASYNC_READ.arready_d7 ;
  wire \GEN_ASYNC_READ.arready_d8 ;
  wire \GEN_ASYNC_READ.arready_d9 ;
  wire \GEN_ASYNC_READ.ip_arvalid_d2 ;
  wire \GEN_ASYNC_READ.ip_arvalid_d3 ;
  wire \GEN_ASYNC_READ.ip_arvalid_re ;
  (* async_reg = "true" *) wire [31:0]\GEN_ASYNC_READ.lite_rdata_cdc_from ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[12]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[13]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[14]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[16]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[17]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[18]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[19]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[20]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[21]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[22]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[23]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[24]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[25]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[26]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[27]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[28]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[29]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[30]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_3_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_8_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_9_n_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[0]_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[10]_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[12]_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[13]_0 ;
  wire [2:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_1 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[1]_0 ;
  wire [7:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 ;
  wire [25:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 ;
  wire [25:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 ;
  wire [7:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 ;
  wire [0:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[4]_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[4]_1 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[5]_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[6]_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[8]_0 ;
  wire \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[9]_0 ;
  wire [31:0]\GEN_ASYNC_READ.lite_rdata_d2 ;
  wire \GEN_ASYNC_READ.read_in_progress_i_1_n_0 ;
  wire \GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ;
  wire \GEN_ASYNC_READ.s_axi_lite_rvalid_i_i_1_n_0 ;
  wire \GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg_0 ;
  wire \GEN_ASYNC_WRITE.REG2_WREADY_n_0 ;
  wire \GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_0 ;
  wire \GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_1 ;
  wire \GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_2 ;
  wire \GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_3 ;
  wire \GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_4 ;
  wire \GEN_ASYNC_WRITE.awvalid_cdc_from ;
  wire \GEN_ASYNC_WRITE.awvalid_cdc_from_i_1_n_0 ;
  wire \GEN_ASYNC_WRITE.awvalid_d1_i_1_n_0 ;
  wire \GEN_ASYNC_WRITE.awvalid_to ;
  wire \GEN_ASYNC_WRITE.awvalid_to2 ;
  wire \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4]_0 ;
  wire \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4]_1 ;
  wire \GEN_ASYNC_WRITE.bvalid_i_reg_0 ;
  wire \GEN_ASYNC_WRITE.ip_addr_cap ;
  wire \GEN_ASYNC_WRITE.ip_addr_cap0 ;
  wire \GEN_ASYNC_WRITE.ip_addr_cap_i_2_n_0 ;
  wire \GEN_ASYNC_WRITE.ip_data_cap ;
  wire \GEN_ASYNC_WRITE.ip_data_cap_i_1_n_0 ;
  wire \GEN_ASYNC_WRITE.rdy_back ;
  wire \GEN_ASYNC_WRITE.rdy_back_to ;
  wire \GEN_ASYNC_WRITE.rdy_cdc_from ;
  wire \GEN_ASYNC_WRITE.rdy_cdc_from_i_1_n_0 ;
  wire \GEN_ASYNC_WRITE.rdy_i_1_n_0 ;
  wire \GEN_ASYNC_WRITE.rdy_to2 ;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire \GEN_ASYNC_WRITE.rdy_to2_cdc_from ;
  wire \GEN_ASYNC_WRITE.rdy_to2_reg_n_0 ;
  wire \GEN_ASYNC_WRITE.wvalid_cdc_from ;
  wire \GEN_ASYNC_WRITE.wvalid_cdc_from_i_1_n_0 ;
  wire \GEN_ASYNC_WRITE.wvalid_to ;
  wire \GEN_ASYNC_WRITE.wvalid_to2 ;
  wire [7:0]Q;
  wire [0:0]SR;
  wire [0:0]SS;
  wire arvalid;
  wire arvalid_d1;
  wire arvalid_d1_i_1_n_0;
  wire arvalid_re__0;
  wire awvalid;
  wire awvalid_d1;
  wire [9:0]axi2ip_rdaddr_i;
  wire [1:0]axi2ip_wrce;
  wire \dmacr_i_reg[2] ;
  wire \dmacr_i_reg[2]_0 ;
  wire [31:0]ip2axi_rddata;
  wire irqdelay_wren0;
  wire irqdelay_wren_reg;
  wire irqthresh_wren0;
  wire irqthresh_wren_reg;
  wire m_axi_sg_aclk;
  wire [8:0]mm2s_dmacr;
  wire mm2s_dmasr;
  wire out;
  wire p_0_in;
  wire p_0_in1_in;
  wire rdy;
  wire read_in_progress;
  wire rvalid;
  wire s_axi_lite_aclk;
  wire [9:0]s_axi_lite_araddr;
  wire s_axi_lite_arready;
  wire s_axi_lite_arvalid;
  wire [4:0]s_axi_lite_awaddr;
  wire s_axi_lite_awvalid;
  wire s_axi_lite_bready;
  wire s_axi_lite_bvalid;
  wire [31:0]s_axi_lite_rdata;
  wire s_axi_lite_rready;
  wire [29:0]s_axi_lite_wdata;
  wire s_axi_lite_wready;
  wire s_axi_lite_wvalid;
  wire scndry_out;
  wire [28:0]scndry_vect_out;
  wire soft_reset_clr;
  wire wvalid;
  wire wvalid_d1;

  Loopback_axi_dma_1_0_cdc_sync__parameterized3 \GEN_ASYNC_READ.REG_ARVALID_TO_IPCLK 
       (.E(\GEN_ASYNC_READ.ip_arvalid_re ),
        .\GEN_ASYNC_READ.ip_arvalid_d3 (\GEN_ASYNC_READ.ip_arvalid_d3 ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .s_axi_lite_arready(s_axi_lite_arready),
        .scndry_out(\GEN_ASYNC_READ.ip_arvalid_d2 ));
  Loopback_axi_dma_1_0_cdc_sync__parameterized4 \GEN_ASYNC_READ.REG_DATA2LITE_CLOCK 
       (.prmry_vect_in(\GEN_ASYNC_READ.lite_rdata_cdc_from ),
        .s_axi_lite_aclk(s_axi_lite_aclk),
        .scndry_vect_out(\GEN_ASYNC_READ.lite_rdata_d2 ));
  Loopback_axi_dma_1_0_cdc_sync__parameterized2 \GEN_ASYNC_READ.REG_RADDR_TO_IPCLK 
       (.m_axi_sg_aclk(m_axi_sg_aclk),
        .s_axi_lite_araddr(s_axi_lite_araddr),
        .scndry_vect_out(\GEN_ASYNC_READ.araddr_d3 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d10_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.arready_d9 ),
        .Q(\GEN_ASYNC_READ.arready_d10 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d11_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.arready_d10 ),
        .Q(\GEN_ASYNC_READ.arready_d11 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d12_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.arready_d11 ),
        .Q(\GEN_ASYNC_READ.arready_d12 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d1_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(s_axi_lite_arready),
        .Q(\GEN_ASYNC_READ.arready_d1 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d2_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.arready_d1 ),
        .Q(\GEN_ASYNC_READ.arready_d2 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d3_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.arready_d2 ),
        .Q(\GEN_ASYNC_READ.arready_d3 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d4_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.arready_d3 ),
        .Q(\GEN_ASYNC_READ.arready_d4 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d5_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.arready_d4 ),
        .Q(\GEN_ASYNC_READ.arready_d5 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d6_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.arready_d5 ),
        .Q(\GEN_ASYNC_READ.arready_d6 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d7_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.arready_d6 ),
        .Q(\GEN_ASYNC_READ.arready_d7 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d8_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.arready_d7 ),
        .Q(\GEN_ASYNC_READ.arready_d8 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.arready_d9_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.arready_d8 ),
        .Q(\GEN_ASYNC_READ.arready_d9 ),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.axi2ip_rdaddr_i_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_ASYNC_READ.ip_arvalid_re ),
        .D(\GEN_ASYNC_READ.araddr_d3 [0]),
        .Q(axi2ip_rdaddr_i[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.axi2ip_rdaddr_i_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_ASYNC_READ.ip_arvalid_re ),
        .D(\GEN_ASYNC_READ.araddr_d3 [1]),
        .Q(axi2ip_rdaddr_i[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.axi2ip_rdaddr_i_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_ASYNC_READ.ip_arvalid_re ),
        .D(\GEN_ASYNC_READ.araddr_d3 [2]),
        .Q(axi2ip_rdaddr_i[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.axi2ip_rdaddr_i_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_ASYNC_READ.ip_arvalid_re ),
        .D(\GEN_ASYNC_READ.araddr_d3 [3]),
        .Q(axi2ip_rdaddr_i[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.axi2ip_rdaddr_i_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_ASYNC_READ.ip_arvalid_re ),
        .D(\GEN_ASYNC_READ.araddr_d3 [4]),
        .Q(axi2ip_rdaddr_i[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.axi2ip_rdaddr_i_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_ASYNC_READ.ip_arvalid_re ),
        .D(\GEN_ASYNC_READ.araddr_d3 [5]),
        .Q(axi2ip_rdaddr_i[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.axi2ip_rdaddr_i_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_ASYNC_READ.ip_arvalid_re ),
        .D(\GEN_ASYNC_READ.araddr_d3 [6]),
        .Q(axi2ip_rdaddr_i[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.axi2ip_rdaddr_i_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_ASYNC_READ.ip_arvalid_re ),
        .D(\GEN_ASYNC_READ.araddr_d3 [7]),
        .Q(axi2ip_rdaddr_i[7]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.axi2ip_rdaddr_i_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_ASYNC_READ.ip_arvalid_re ),
        .D(\GEN_ASYNC_READ.araddr_d3 [8]),
        .Q(axi2ip_rdaddr_i[8]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.axi2ip_rdaddr_i_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_ASYNC_READ.ip_arvalid_re ),
        .D(\GEN_ASYNC_READ.araddr_d3 [9]),
        .Q(axi2ip_rdaddr_i[9]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.ip_arvalid_d3_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.ip_arvalid_d2 ),
        .Q(\GEN_ASYNC_READ.ip_arvalid_d3 ),
        .R(SR));
  LUT5 #(
    .INIT(32'h44FFF400)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[0]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I1(mm2s_dmasr),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[0]_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .O(ip2axi_rddata[0]));
  LUT6 #(
    .INIT(64'hFF50505088888888)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[10]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[10]_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [4]),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [4]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[10]));
  LUT5 #(
    .INIT(32'h8F008800)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[11]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [5]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [5]),
        .O(ip2axi_rddata[11]));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[12]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [6]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[12]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [6]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[12]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[12]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[12]_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_0 [0]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[13]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [7]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[13]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [7]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[13]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[13]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[13]_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_0 [1]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFF0080800000808)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[14]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [8]),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_0 [2]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[14]_i_2_n_0 ),
        .O(ip2axi_rddata[14]));
  LUT5 #(
    .INIT(32'hFFF777F7)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[14]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_1 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [8]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[14]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h8F008800)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[15]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [9]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [9]),
        .O(ip2axi_rddata[15]));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[16]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [10]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[16]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [10]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[16]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[16]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 [0]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(Q[0]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[16]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[17]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [11]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[17]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [11]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[17]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[17]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 [1]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(Q[1]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[17]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[18]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [12]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[18]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [12]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[18]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[18]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 [2]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(Q[2]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[18]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[19]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [13]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[19]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [13]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[19]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[19]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 [3]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(Q[3]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[19]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT4 #(
    .INIT(16'h66E6)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[1]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[1]_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[1]));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[20]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [14]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[20]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [14]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[20]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[20]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 [4]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(Q[4]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[20]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[21]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [15]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[21]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [15]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[21]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[21]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 [5]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(Q[5]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[21]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[22]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [16]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[22]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [16]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[22]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[22]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 [6]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(Q[6]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[22]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[23]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [17]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[23]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [17]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[23]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[23]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 [7]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(Q[7]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[23]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[24]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [18]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[24]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [18]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[24]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[24]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 [0]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(mm2s_dmacr[1]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[24]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[25]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [19]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[25]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [19]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[25]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[25]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 [1]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(mm2s_dmacr[2]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[25]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFF0080800000808)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[26]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [20]),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I3(mm2s_dmacr[3]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[26]_i_2_n_0 ),
        .O(ip2axi_rddata[26]));
  LUT5 #(
    .INIT(32'hFFF777F7)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[26]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 [2]),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [20]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[26]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFF0080800000808)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[27]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [21]),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I3(mm2s_dmacr[4]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[27]_i_2_n_0 ),
        .O(ip2axi_rddata[27]));
  LUT5 #(
    .INIT(32'hFFF777F7)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[27]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 [3]),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [21]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[27]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[28]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [22]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[28]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [22]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[28]));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[28]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 [4]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(mm2s_dmacr[5]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[28]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFF0080800000808)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[29]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [23]),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I3(mm2s_dmacr[6]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[29]_i_2_n_0 ),
        .O(ip2axi_rddata[29]));
  LUT5 #(
    .INIT(32'hFFF777F7)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[29]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 [5]),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [23]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[29]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[2]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\dmacr_i_reg[2]_0 ),
        .O(ip2axi_rddata[2]));
  LUT6 #(
    .INIT(64'hFFF0080800000808)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[30]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [24]),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I3(mm2s_dmacr[7]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[30]_i_2_n_0 ),
        .O(ip2axi_rddata[30]));
  LUT5 #(
    .INIT(32'hFFF777F7)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[30]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 [6]),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [24]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[30]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCC0E2E2C0C0C0C0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [25]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_3_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [25]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[31]));
  LUT4 #(
    .INIT(16'h0222)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I1(axi2ip_rdaddr_i[5]),
        .I2(axi2ip_rdaddr_i[3]),
        .I3(axi2ip_rdaddr_i[2]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h2FFF2000)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_3 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 [7]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ),
        .I4(mm2s_dmacr[8]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h8220)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ),
        .I1(axi2ip_rdaddr_i[5]),
        .I2(axi2ip_rdaddr_i[3]),
        .I3(axi2ip_rdaddr_i[2]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5 
       (.I0(axi2ip_rdaddr_i[8]),
        .I1(axi2ip_rdaddr_i[9]),
        .I2(axi2ip_rdaddr_i[6]),
        .I3(axi2ip_rdaddr_i[7]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_8_n_0 ),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h0100)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6 
       (.I0(axi2ip_rdaddr_i[0]),
        .I1(axi2ip_rdaddr_i[1]),
        .I2(axi2ip_rdaddr_i[4]),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_9_n_0 ),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'h86)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7 
       (.I0(axi2ip_rdaddr_i[2]),
        .I1(axi2ip_rdaddr_i[3]),
        .I2(axi2ip_rdaddr_i[5]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF8)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_8 
       (.I0(axi2ip_rdaddr_i[4]),
        .I1(axi2ip_rdaddr_i[3]),
        .I2(axi2ip_rdaddr_i[2]),
        .I3(axi2ip_rdaddr_i[5]),
        .I4(axi2ip_rdaddr_i[0]),
        .I5(axi2ip_rdaddr_i[1]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_9 
       (.I0(axi2ip_rdaddr_i[7]),
        .I1(axi2ip_rdaddr_i[6]),
        .I2(axi2ip_rdaddr_i[9]),
        .I3(axi2ip_rdaddr_i[8]),
        .O(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT4 #(
    .INIT(16'h2F00)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[3]_i_1 
       (.I0(mm2s_dmacr[0]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .O(ip2axi_rddata[3]));
  LUT5 #(
    .INIT(32'h2200F200)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[4]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[4]_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[4]_1 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[4]));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[5]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[5]_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .O(ip2axi_rddata[5]));
  LUT6 #(
    .INIT(64'hFF50505088888888)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[6]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[6]_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [0]),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [0]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[6]));
  LUT5 #(
    .INIT(32'h8F008800)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[7]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [1]),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [1]),
        .O(ip2axi_rddata[7]));
  LUT6 #(
    .INIT(64'hFF50505088888888)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[8]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[8]_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [2]),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [2]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[8]));
  LUT6 #(
    .INIT(64'hFF50505088888888)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from[9]_i_1 
       (.I0(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_2_n_0 ),
        .I1(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[9]_0 ),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 [3]),
        .I3(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 [3]),
        .I4(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_4_n_0 ),
        .I5(\GEN_ASYNC_READ.lite_rdata_cdc_from[31]_i_5_n_0 ),
        .O(ip2axi_rddata[9]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[0]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[10]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [10]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[11]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [11]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[12]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [12]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[13]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [13]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[14]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [14]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[15]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [15]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[16]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [16]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[17]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [17]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[18]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [18]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[19]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [19]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[1]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[20]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [20]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[21]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [21]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[22]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [22]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[23]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [23]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[24]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [24]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[25]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [25]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[26]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [26]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[27]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [27]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[28]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [28]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[29]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [29]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[2]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [2]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[30]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [30]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[31]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [31]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[3]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [3]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[4]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [4]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[5]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [5]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[6]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [6]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[7]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [7]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[8]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [8]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(rvalid),
        .D(ip2axi_rddata[9]),
        .Q(\GEN_ASYNC_READ.lite_rdata_cdc_from [9]),
        .R(SR));
  LUT3 #(
    .INIT(8'hF4)) 
    \GEN_ASYNC_READ.read_in_progress_i_1 
       (.I0(arvalid_d1),
        .I1(arvalid),
        .I2(read_in_progress),
        .O(\GEN_ASYNC_READ.read_in_progress_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.read_in_progress_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.read_in_progress_i_1_n_0 ),
        .Q(read_in_progress),
        .R(arvalid_d1_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.rvalid_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.ip_arvalid_re ),
        .Q(rvalid),
        .R(SR));
  LUT3 #(
    .INIT(8'h8F)) 
    \GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1 
       (.I0(s_axi_lite_rready),
        .I1(\GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg_0 ),
        .I2(\GEN_ASYNC_WRITE.bvalid_i_reg_0 ),
        .O(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[0] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [0]),
        .Q(s_axi_lite_rdata[0]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[10] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [10]),
        .Q(s_axi_lite_rdata[10]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[11] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [11]),
        .Q(s_axi_lite_rdata[11]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[12] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [12]),
        .Q(s_axi_lite_rdata[12]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[13] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [13]),
        .Q(s_axi_lite_rdata[13]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[14] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [14]),
        .Q(s_axi_lite_rdata[14]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[15] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [15]),
        .Q(s_axi_lite_rdata[15]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[16] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [16]),
        .Q(s_axi_lite_rdata[16]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[17] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [17]),
        .Q(s_axi_lite_rdata[17]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[18] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [18]),
        .Q(s_axi_lite_rdata[18]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[19] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [19]),
        .Q(s_axi_lite_rdata[19]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[1] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [1]),
        .Q(s_axi_lite_rdata[1]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[20] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [20]),
        .Q(s_axi_lite_rdata[20]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[21] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [21]),
        .Q(s_axi_lite_rdata[21]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[22] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [22]),
        .Q(s_axi_lite_rdata[22]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[23] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [23]),
        .Q(s_axi_lite_rdata[23]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[24] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [24]),
        .Q(s_axi_lite_rdata[24]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[25] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [25]),
        .Q(s_axi_lite_rdata[25]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[26] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [26]),
        .Q(s_axi_lite_rdata[26]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[27] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [27]),
        .Q(s_axi_lite_rdata[27]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[28] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [28]),
        .Q(s_axi_lite_rdata[28]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[29] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [29]),
        .Q(s_axi_lite_rdata[29]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[2] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [2]),
        .Q(s_axi_lite_rdata[2]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[30] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [30]),
        .Q(s_axi_lite_rdata[30]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[31] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [31]),
        .Q(s_axi_lite_rdata[31]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[3] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [3]),
        .Q(s_axi_lite_rdata[3]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[4] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [4]),
        .Q(s_axi_lite_rdata[4]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[5] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [5]),
        .Q(s_axi_lite_rdata[5]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[6] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [6]),
        .Q(s_axi_lite_rdata[6]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[7] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [7]),
        .Q(s_axi_lite_rdata[7]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[8] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [8]),
        .Q(s_axi_lite_rdata[8]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  FDRE \GEN_ASYNC_READ.s_axi_lite_rdata_reg[9] 
       (.C(s_axi_lite_aclk),
        .CE(\GEN_ASYNC_READ.arready_d12 ),
        .D(\GEN_ASYNC_READ.lite_rdata_d2 [9]),
        .Q(s_axi_lite_rdata[9]),
        .R(\GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h08C8)) 
    \GEN_ASYNC_READ.s_axi_lite_rvalid_i_i_1 
       (.I0(\GEN_ASYNC_READ.arready_d12 ),
        .I1(\GEN_ASYNC_WRITE.bvalid_i_reg_0 ),
        .I2(\GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg_0 ),
        .I3(s_axi_lite_rready),
        .O(\GEN_ASYNC_READ.s_axi_lite_rvalid_i_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_READ.s_axi_lite_rvalid_i_i_1_n_0 ),
        .Q(\GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg_0 ),
        .R(1'b0));
  Loopback_axi_dma_1_0_cdc_sync_9 \GEN_ASYNC_WRITE.AWVLD_CDC_TO 
       (.m_axi_sg_aclk(m_axi_sg_aclk),
        .prmry_in(\GEN_ASYNC_WRITE.awvalid_cdc_from ),
        .scndry_out(\GEN_ASYNC_WRITE.awvalid_to ));
  Loopback_axi_dma_1_0_cdc_sync_10 \GEN_ASYNC_WRITE.REG2_WREADY 
       (.\GEN_ASYNC_WRITE.bvalid_i_reg (\GEN_ASYNC_WRITE.rdy_to2_reg_n_0 ),
        .\GEN_ASYNC_WRITE.bvalid_i_reg_0 (\GEN_ASYNC_WRITE.bvalid_i_reg_0 ),
        .\GEN_ASYNC_WRITE.rdy_to2_reg (\GEN_ASYNC_WRITE.REG2_WREADY_n_0 ),
        .prmry_in(\GEN_ASYNC_WRITE.rdy_cdc_from ),
        .s_axi_lite_aclk(s_axi_lite_aclk),
        .s_axi_lite_bready(s_axi_lite_bready),
        .s_axi_lite_bvalid(s_axi_lite_bvalid),
        .s_axi_lite_wready(s_axi_lite_wready),
        .scndry_out(scndry_out));
  Loopback_axi_dma_1_0_cdc_sync_11 \GEN_ASYNC_WRITE.REG3_WREADY 
       (.\GEN_ASYNC_WRITE.ip_addr_cap0 (\GEN_ASYNC_WRITE.ip_addr_cap0 ),
        .\GEN_ASYNC_WRITE.rdy_back (\GEN_ASYNC_WRITE.rdy_back ),
        .\GEN_ASYNC_WRITE.rdy_cdc_from_reg (\GEN_ASYNC_WRITE.axi2ip_wrce_reg[4]_1 ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .prmry_in(\GEN_ASYNC_WRITE.rdy_to2_cdc_from ),
        .scndry_out(\GEN_ASYNC_WRITE.rdy_back_to ));
  Loopback_axi_dma_1_0_cdc_sync__parameterized0 \GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK 
       (.\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_0 (\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_0 ),
        .\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_0 (\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_1 ),
        .\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_1 (\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_2 ),
        .\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_2 (\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_3 ),
        .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_4 ),
        .\GEN_ASYNC_WRITE.axi2ip_wrce_reg[4] (\GEN_ASYNC_WRITE.axi2ip_wrce_reg[4]_1 ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .rdy(rdy),
        .s_axi_lite_awaddr(s_axi_lite_awaddr));
  Loopback_axi_dma_1_0_cdc_sync__parameterized1 \GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1 
       (.Q(Q[7:6]),
        .SS(SS),
        .\dmacr_i_reg[23] (axi2ip_wrce[0]),
        .\dmacr_i_reg[2] (\dmacr_i_reg[2] ),
        .\dmacr_i_reg[2]_0 (\dmacr_i_reg[2]_0 ),
        .irqdelay_wren0(irqdelay_wren0),
        .irqdelay_wren_reg(irqdelay_wren_reg),
        .irqthresh_wren0(irqthresh_wren0),
        .irqthresh_wren_reg(irqthresh_wren_reg),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .mm2s_dmacr(mm2s_dmacr[8:7]),
        .out(out),
        .s_axi_lite_wdata(s_axi_lite_wdata),
        .scndry_vect_out(scndry_vect_out),
        .soft_reset_clr(soft_reset_clr));
  Loopback_axi_dma_1_0_cdc_sync_12 \GEN_ASYNC_WRITE.WVLD_CDC_TO 
       (.m_axi_sg_aclk(m_axi_sg_aclk),
        .prmry_in(\GEN_ASYNC_WRITE.wvalid_cdc_from ),
        .scndry_out(\GEN_ASYNC_WRITE.wvalid_to ));
  LUT3 #(
    .INIT(8'hF4)) 
    \GEN_ASYNC_WRITE.awvalid_cdc_from_i_1 
       (.I0(awvalid_d1),
        .I1(awvalid),
        .I2(\GEN_ASYNC_WRITE.awvalid_cdc_from ),
        .O(\GEN_ASYNC_WRITE.awvalid_cdc_from_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.awvalid_cdc_from_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.awvalid_cdc_from_i_1_n_0 ),
        .Q(\GEN_ASYNC_WRITE.awvalid_cdc_from ),
        .R(\GEN_ASYNC_WRITE.awvalid_d1_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \GEN_ASYNC_WRITE.awvalid_d1_i_1 
       (.I0(s_axi_lite_bvalid),
        .I1(\GEN_ASYNC_WRITE.bvalid_i_reg_0 ),
        .O(\GEN_ASYNC_WRITE.awvalid_d1_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.awvalid_d1_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(awvalid),
        .Q(awvalid_d1),
        .R(\GEN_ASYNC_WRITE.awvalid_d1_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.awvalid_to2_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.awvalid_to ),
        .Q(\GEN_ASYNC_WRITE.awvalid_to2 ),
        .R(SR));
  FDRE \GEN_ASYNC_WRITE.axi2ip_wrce_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_3 ),
        .Q(axi2ip_wrce[0]),
        .R(\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_4 ));
  FDRE \GEN_ASYNC_WRITE.axi2ip_wrce_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_2 ),
        .Q(p_0_in1_in),
        .R(\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_4 ));
  FDRE \GEN_ASYNC_WRITE.axi2ip_wrce_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_1 ),
        .Q(axi2ip_wrce[1]),
        .R(\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_4 ));
  FDRE \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_0 ),
        .Q(E),
        .R(\GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK_n_4 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.bvalid_i_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.REG2_WREADY_n_0 ),
        .Q(s_axi_lite_bvalid),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT3 #(
    .INIT(8'hF4)) 
    \GEN_ASYNC_WRITE.ip_addr_cap_i_2 
       (.I0(\GEN_ASYNC_WRITE.awvalid_to2 ),
        .I1(\GEN_ASYNC_WRITE.awvalid_to ),
        .I2(\GEN_ASYNC_WRITE.ip_addr_cap ),
        .O(\GEN_ASYNC_WRITE.ip_addr_cap_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.ip_addr_cap_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.ip_addr_cap_i_2_n_0 ),
        .Q(\GEN_ASYNC_WRITE.ip_addr_cap ),
        .R(\GEN_ASYNC_WRITE.ip_addr_cap0 ));
  LUT3 #(
    .INIT(8'hF4)) 
    \GEN_ASYNC_WRITE.ip_data_cap_i_1 
       (.I0(\GEN_ASYNC_WRITE.wvalid_to2 ),
        .I1(\GEN_ASYNC_WRITE.wvalid_to ),
        .I2(\GEN_ASYNC_WRITE.ip_data_cap ),
        .O(\GEN_ASYNC_WRITE.ip_data_cap_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.ip_data_cap_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.ip_data_cap_i_1_n_0 ),
        .Q(\GEN_ASYNC_WRITE.ip_data_cap ),
        .R(\GEN_ASYNC_WRITE.ip_addr_cap0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.rdy_back_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.rdy_back_to ),
        .Q(\GEN_ASYNC_WRITE.rdy_back ),
        .R(SR));
  LUT2 #(
    .INIT(4'hE)) 
    \GEN_ASYNC_WRITE.rdy_cdc_from_i_1 
       (.I0(rdy),
        .I1(\GEN_ASYNC_WRITE.rdy_cdc_from ),
        .O(\GEN_ASYNC_WRITE.rdy_cdc_from_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.rdy_cdc_from_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.rdy_cdc_from_i_1_n_0 ),
        .Q(\GEN_ASYNC_WRITE.rdy_cdc_from ),
        .R(\GEN_ASYNC_WRITE.ip_addr_cap0 ));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \GEN_ASYNC_WRITE.rdy_i_1 
       (.I0(\GEN_ASYNC_WRITE.ip_addr_cap ),
        .I1(\GEN_ASYNC_WRITE.ip_data_cap ),
        .I2(rdy),
        .O(\GEN_ASYNC_WRITE.rdy_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.rdy_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.rdy_i_1_n_0 ),
        .Q(rdy),
        .R(\GEN_ASYNC_WRITE.ip_addr_cap0 ));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.rdy_to2_cdc_from_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.rdy_to2 ),
        .Q(\GEN_ASYNC_WRITE.rdy_to2_cdc_from ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.rdy_to2_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.rdy_to2 ),
        .Q(\GEN_ASYNC_WRITE.rdy_to2_reg_n_0 ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF4)) 
    \GEN_ASYNC_WRITE.wvalid_cdc_from_i_1 
       (.I0(wvalid_d1),
        .I1(wvalid),
        .I2(\GEN_ASYNC_WRITE.wvalid_cdc_from ),
        .O(\GEN_ASYNC_WRITE.wvalid_cdc_from_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.wvalid_cdc_from_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.wvalid_cdc_from_i_1_n_0 ),
        .Q(\GEN_ASYNC_WRITE.wvalid_cdc_from ),
        .R(\GEN_ASYNC_WRITE.awvalid_d1_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.wvalid_d1_reg 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(wvalid),
        .Q(wvalid_d1),
        .R(\GEN_ASYNC_WRITE.awvalid_d1_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_WRITE.wvalid_to2_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_WRITE.wvalid_to ),
        .Q(\GEN_ASYNC_WRITE.wvalid_to2 ),
        .R(SR));
  LUT3 #(
    .INIT(8'h80)) 
    \GEN_DESC_REG_FOR_SG.GEN_TAILUPDATE_EQL32.tailpntr_updated_d1_i_1 
       (.I0(E),
        .I1(out),
        .I2(\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[0]_0 ),
        .O(\GEN_ASYNC_WRITE.axi2ip_wrce_reg[4]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    arready_i_reg
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(arvalid_re__0),
        .Q(s_axi_lite_arready),
        .R(p_0_in));
  LUT2 #(
    .INIT(4'hB)) 
    arvalid_d1_i_1
       (.I0(\GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg_0 ),
        .I1(\GEN_ASYNC_WRITE.bvalid_i_reg_0 ),
        .O(arvalid_d1_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    arvalid_d1_reg
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(arvalid),
        .Q(arvalid_d1),
        .R(arvalid_d1_i_1_n_0));
  LUT4 #(
    .INIT(16'h0002)) 
    arvalid_re
       (.I0(arvalid),
        .I1(read_in_progress),
        .I2(arvalid_d1),
        .I3(\GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg_0 ),
        .O(arvalid_re__0));
  FDRE #(
    .INIT(1'b0)) 
    arvalid_reg
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(s_axi_lite_arvalid),
        .Q(arvalid),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    awvalid_reg
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(s_axi_lite_awvalid),
        .Q(awvalid),
        .R(p_0_in));
  FDRE #(
    .INIT(1'b0)) 
    wvalid_reg
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wvalid),
        .Q(wvalid),
        .R(p_0_in));
endmodule

module Loopback_axi_dma_1_0_axi_dma_mm2s_cmdsts_if
   (mm2s_interr,
    mm2s_slverr,
    mm2s_decerr,
    mm2s_tag,
    sts_received_i_reg_0,
    s_axis_mm2s_cmd_tvalid_split,
    m_axis_mm2s_sts_tready,
    \GEN_ASYNC_RESET.halt_i_reg ,
    dma_mm2s_error,
    sinit,
    mm2s_interr_i,
    m_axi_sg_aclk,
    mm2s_slverr_i,
    mm2s_decerr_i,
    \mm2s_tag_reg[0]_0 ,
    sts_received_i_reg_1,
    \GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg_0 ,
    out,
    m_axis_mm2s_sts_tvalid_int,
    mm2s_halt,
    sts_received_d1,
    mm2s_error_reg_0,
    m_axis_mm2s_ftch_tvalid_new);
  output mm2s_interr;
  output mm2s_slverr;
  output mm2s_decerr;
  output [0:0]mm2s_tag;
  output sts_received_i_reg_0;
  output s_axis_mm2s_cmd_tvalid_split;
  output m_axis_mm2s_sts_tready;
  output \GEN_ASYNC_RESET.halt_i_reg ;
  output dma_mm2s_error;
  input sinit;
  input mm2s_interr_i;
  input m_axi_sg_aclk;
  input mm2s_slverr_i;
  input mm2s_decerr_i;
  input \mm2s_tag_reg[0]_0 ;
  input sts_received_i_reg_1;
  input \GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg_0 ;
  input out;
  input m_axis_mm2s_sts_tvalid_int;
  input mm2s_halt;
  input sts_received_d1;
  input [0:0]mm2s_error_reg_0;
  input m_axis_mm2s_ftch_tvalid_new;

  wire \GEN_ASYNC_RESET.halt_i_reg ;
  wire \GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg_0 ;
  wire dma_mm2s_error;
  wire m_axi_sg_aclk;
  wire m_axis_mm2s_ftch_tvalid_new;
  wire m_axis_mm2s_sts_tready;
  wire m_axis_mm2s_sts_tvalid_int;
  wire mm2s_decerr;
  wire mm2s_decerr_i;
  wire mm2s_error_i_1_n_0;
  wire [0:0]mm2s_error_reg_0;
  wire mm2s_halt;
  wire mm2s_interr;
  wire mm2s_interr_i;
  wire mm2s_slverr;
  wire mm2s_slverr_i;
  wire [0:0]mm2s_tag;
  wire \mm2s_tag_reg[0]_0 ;
  wire out;
  wire s_axis_mm2s_cmd_tvalid_split;
  wire sinit;
  wire sts_received_d1;
  wire sts_received_i_reg_0;
  wire sts_received_i_reg_1;
  wire sts_tready_i_1_n_0;

  FDRE \GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg_0 ),
        .Q(s_axis_mm2s_cmd_tvalid_split),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    mm2s_decerr_i_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_decerr_i),
        .Q(mm2s_decerr),
        .R(sinit));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEEE)) 
    mm2s_error_i_1
       (.I0(mm2s_interr),
        .I1(mm2s_slverr),
        .I2(mm2s_error_reg_0),
        .I3(m_axis_mm2s_ftch_tvalid_new),
        .I4(mm2s_decerr),
        .I5(dma_mm2s_error),
        .O(mm2s_error_i_1_n_0));
  FDRE mm2s_error_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_error_i_1_n_0),
        .Q(dma_mm2s_error),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    mm2s_interr_i_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_interr_i),
        .Q(mm2s_interr),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    mm2s_slverr_i_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_slverr_i),
        .Q(mm2s_slverr),
        .R(sinit));
  FDRE \mm2s_tag_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\mm2s_tag_reg[0]_0 ),
        .Q(mm2s_tag),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    sts_received_i_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sts_received_i_reg_1),
        .Q(sts_received_i_reg_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h02A2)) 
    sts_tready_i_1
       (.I0(out),
        .I1(sts_received_i_reg_0),
        .I2(m_axis_mm2s_sts_tready),
        .I3(m_axis_mm2s_sts_tvalid_int),
        .O(sts_tready_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sts_tready_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sts_tready_i_1_n_0),
        .Q(m_axis_mm2s_sts_tready),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h04)) 
    \updt_desc_reg2[32]_i_1 
       (.I0(mm2s_halt),
        .I1(sts_received_i_reg_0),
        .I2(sts_received_d1),
        .O(\GEN_ASYNC_RESET.halt_i_reg ));
endmodule

module Loopback_axi_dma_1_0_axi_dma_mm2s_mngr
   (mm2s_sts_received,
    mm2s_all_idle,
    mm2s_stop,
    soft_reset_d1,
    soft_reset_d2,
    s_axis_mm2s_updtptr_tlast,
    packet_in_progress,
    s_axis_mm2s_cmd_tvalid_split,
    m_axis_mm2s_sts_tready,
    s_halt0,
    mm2s_halted_set_reg,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    queue_empty_new0,
    FIFO_Full_reg,
    rst,
    mm2s_cntrl_strm_stop,
    E,
    D,
    updt_sts_reg,
    Q,
    dma_mm2s_error,
    sinit,
    m_axi_sg_aclk,
    mm2s_interr_i,
    mm2s_slverr_i,
    mm2s_decerr_i,
    \mm2s_tag_reg[0] ,
    mm2s_dmacr,
    mm2s_halted_set0,
    mm2s_stop_i,
    soft_reset,
    updt_data_reg,
    packet_in_progress_reg,
    \GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg ,
    soft_reset_re,
    out,
    idle_reg,
    mm2s_dmasr,
    \GEN_MM2S.queue_empty_new_reg ,
    \GEN_SYNC_FIFO.mm2s_stop_d1_reg ,
    ch1_ftch_queue_empty,
    all_is_idle_d1_reg,
    mm2s_updt_idle,
    mm2s_ftch_idle,
    ptr_queue_full,
    m_axis_mm2s_sts_tvalid_int,
    sts_queue_full,
    m_axis_mm2s_ftch_tvalid_new,
    mm2s_halt,
    \updt_desc_reg0_reg[31] ,
    SR);
  output mm2s_sts_received;
  output mm2s_all_idle;
  output mm2s_stop;
  output soft_reset_d1;
  output soft_reset_d2;
  output s_axis_mm2s_updtptr_tlast;
  output packet_in_progress;
  output s_axis_mm2s_cmd_tvalid_split;
  output m_axis_mm2s_sts_tready;
  output s_halt0;
  output mm2s_halted_set_reg;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  output queue_empty_new0;
  output [0:0]FIFO_Full_reg;
  output rst;
  output mm2s_cntrl_strm_stop;
  output [0:0]E;
  output [30:0]D;
  output [0:0]updt_sts_reg;
  output [25:0]Q;
  output dma_mm2s_error;
  input sinit;
  input m_axi_sg_aclk;
  input mm2s_interr_i;
  input mm2s_slverr_i;
  input mm2s_decerr_i;
  input \mm2s_tag_reg[0] ;
  input [0:0]mm2s_dmacr;
  input mm2s_halted_set0;
  input mm2s_stop_i;
  input soft_reset;
  input updt_data_reg;
  input packet_in_progress_reg;
  input \GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg ;
  input soft_reset_re;
  input out;
  input idle_reg;
  input mm2s_dmasr;
  input [0:0]\GEN_MM2S.queue_empty_new_reg ;
  input \GEN_SYNC_FIFO.mm2s_stop_d1_reg ;
  input ch1_ftch_queue_empty;
  input all_is_idle_d1_reg;
  input mm2s_updt_idle;
  input mm2s_ftch_idle;
  input ptr_queue_full;
  input m_axis_mm2s_sts_tvalid_int;
  input sts_queue_full;
  input m_axis_mm2s_ftch_tvalid_new;
  input mm2s_halt;
  input [52:0]\updt_desc_reg0_reg[31] ;
  input [0:0]SR;

  wire [30:0]D;
  wire [0:0]E;
  wire [0:0]FIFO_Full_reg;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire [0:0]\GEN_MM2S.queue_empty_new_reg ;
  wire \GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_11 ;
  wire \GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_14 ;
  wire \GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_8 ;
  wire \GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_9 ;
  wire \GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SM_n_0 ;
  wire \GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS_n_7 ;
  wire \GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg ;
  wire \GEN_SYNC_FIFO.mm2s_stop_d1_reg ;
  wire [25:0]Q;
  wire [0:0]SR;
  wire all_is_idle_d1_reg;
  wire ch1_ftch_queue_empty;
  wire desc_update_done;
  wire dma_mm2s_error;
  wire idle_reg;
  wire m_axi_sg_aclk;
  wire m_axis_mm2s_ftch_tvalid_new;
  wire m_axis_mm2s_sts_tready;
  wire m_axis_mm2s_sts_tvalid_int;
  wire mm2s_all_idle;
  wire mm2s_cntrl_strm_stop;
  wire [1:0]mm2s_cs;
  wire mm2s_decerr;
  wire mm2s_decerr_i;
  wire [0:0]mm2s_dmacr;
  wire mm2s_dmasr;
  wire mm2s_ftch_idle;
  wire mm2s_halt;
  wire mm2s_halted_set0;
  wire mm2s_halted_set_reg;
  wire mm2s_interr;
  wire mm2s_interr_i;
  wire [1:1]mm2s_ns__0;
  wire mm2s_slverr;
  wire mm2s_slverr_i;
  wire mm2s_stop;
  wire mm2s_stop_i;
  wire mm2s_sts_received;
  wire [0:0]mm2s_tag;
  wire \mm2s_tag_reg[0] ;
  wire mm2s_updt_idle;
  wire out;
  wire packet_in_progress;
  wire packet_in_progress_reg;
  wire ptr_queue_full;
  wire queue_empty_new0;
  wire rst;
  wire s_axis_mm2s_cmd_tvalid_split;
  wire s_axis_mm2s_updtptr_tlast;
  wire s_halt0;
  wire sinit;
  wire soft_reset;
  wire soft_reset_d1;
  wire soft_reset_d2;
  wire soft_reset_re;
  wire sts_queue_full;
  wire sts_received_d1;
  wire updt_data_reg;
  wire [52:0]\updt_desc_reg0_reg[31] ;
  wire [0:0]updt_sts_reg;
  wire write_cmnd_cmb;

  LUT2 #(
    .INIT(4'hE)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.s_halt_i_1 
       (.I0(mm2s_stop),
        .I1(soft_reset_re),
        .O(s_halt0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S_DMA_CONTROL.GEN_CNTRL_STREAM.soft_reset_d1_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(soft_reset),
        .Q(soft_reset_d1),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S_DMA_CONTROL.GEN_CNTRL_STREAM.soft_reset_d2_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(soft_reset_d1),
        .Q(soft_reset_d2),
        .R(sinit));
  Loopback_axi_dma_1_0_axi_dma_mm2s_sg_if \GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF 
       (.D(mm2s_ns__0),
        .E(E),
        .FIFO_Full_reg(FIFO_Full_reg),
        .FIFO_Full_reg_0(\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_8 ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_11 ),
        .\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg (s_axis_mm2s_cmd_tvalid_split),
        .\GEN_MM2S.queue_dout_new_reg[90] (all_is_idle_d1_reg),
        .\GEN_MM2S.queue_empty_new_reg (\GEN_MM2S.queue_empty_new_reg ),
        .\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg_0 (mm2s_sts_received),
        .Q(mm2s_cs),
        .\QUEUE_COUNT.cmnds_queued_shift_reg[3] (\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SM_n_0 ),
        .ch1_ftch_queue_empty(ch1_ftch_queue_empty),
        .desc_update_done(desc_update_done),
        .desc_update_done_reg_0(\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_14 ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_mm2s_ftch_tvalid_new(m_axis_mm2s_ftch_tvalid_new),
        .m_axis_mm2s_sts_tvalid_int(m_axis_mm2s_sts_tvalid_int),
        .mm2s_decerr(mm2s_decerr),
        .mm2s_halt(mm2s_halt),
        .mm2s_interr(mm2s_interr),
        .mm2s_slverr(mm2s_slverr),
        .mm2s_tag(mm2s_tag),
        .out(out),
        .packet_in_progress(packet_in_progress),
        .packet_in_progress_reg_0(packet_in_progress_reg),
        .ptr_queue_full(ptr_queue_full),
        .queue_empty_new0(queue_empty_new0),
        .sinit(sinit),
        .sts_queue_full(sts_queue_full),
        .sts_received_d1(sts_received_d1),
        .updt_data_reg_0(s_axis_mm2s_updtptr_tlast),
        .updt_data_reg_1(\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_9 ),
        .updt_data_reg_2(updt_data_reg),
        .\updt_desc_reg0_reg[31]_0 (Q),
        .\updt_desc_reg0_reg[31]_1 ({\updt_desc_reg0_reg[31] [52:27],\updt_desc_reg0_reg[31] [25:0]}),
        .\updt_desc_reg2_reg[31]_0 (D[29]),
        .\updt_desc_reg2_reg[32]_0 ({D[30],D[28:0]}),
        .\updt_desc_reg2_reg[32]_1 (\GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS_n_7 ),
        .updt_sts_reg_0(updt_sts_reg),
        .write_cmnd_cmb(write_cmnd_cmb));
  Loopback_axi_dma_1_0_axi_dma_mm2s_sm \GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SM 
       (.D(mm2s_ns__0),
        .E(\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_14 ),
        .\FSM_sequential_mm2s_cs_reg[0]_0 (s_axis_mm2s_cmd_tvalid_split),
        .\FSM_sequential_mm2s_cs_reg[0]_1 (\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_9 ),
        .\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg_0 (\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SM_n_0 ),
        .Q(mm2s_cs),
        .SR(SR),
        .all_is_idle_d1_reg(all_is_idle_d1_reg),
        .all_is_idle_d1_reg_0(\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_8 ),
        .ch1_ftch_queue_empty(ch1_ftch_queue_empty),
        .desc_update_done(desc_update_done),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .mm2s_all_idle(mm2s_all_idle),
        .mm2s_dmacr(mm2s_dmacr),
        .mm2s_ftch_idle(mm2s_ftch_idle),
        .mm2s_stop_i(mm2s_stop_i),
        .mm2s_updt_idle(mm2s_updt_idle),
        .packet_in_progress(packet_in_progress),
        .sinit(sinit),
        .write_cmnd_cmb(write_cmnd_cmb));
  Loopback_axi_dma_1_0_axi_dma_mm2s_cmdsts_if \GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS 
       (.\GEN_ASYNC_RESET.halt_i_reg (\GEN_MM2S_DMA_CONTROL.I_MM2S_CMDSTS_n_7 ),
        .\GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg_0 (\GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_reg ),
        .dma_mm2s_error(dma_mm2s_error),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_mm2s_ftch_tvalid_new(m_axis_mm2s_ftch_tvalid_new),
        .m_axis_mm2s_sts_tready(m_axis_mm2s_sts_tready),
        .m_axis_mm2s_sts_tvalid_int(m_axis_mm2s_sts_tvalid_int),
        .mm2s_decerr(mm2s_decerr),
        .mm2s_decerr_i(mm2s_decerr_i),
        .mm2s_error_reg_0(\updt_desc_reg0_reg[31] [26]),
        .mm2s_halt(mm2s_halt),
        .mm2s_interr(mm2s_interr),
        .mm2s_interr_i(mm2s_interr_i),
        .mm2s_slverr(mm2s_slverr),
        .mm2s_slverr_i(mm2s_slverr_i),
        .mm2s_tag(mm2s_tag),
        .\mm2s_tag_reg[0]_0 (\mm2s_tag_reg[0] ),
        .out(out),
        .s_axis_mm2s_cmd_tvalid_split(s_axis_mm2s_cmd_tvalid_split),
        .sinit(sinit),
        .sts_received_d1(sts_received_d1),
        .sts_received_i_reg_0(mm2s_sts_received),
        .sts_received_i_reg_1(\GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF_n_11 ));
  Loopback_axi_dma_1_0_axi_dma_mm2s_sts_mngr \GEN_MM2S_DMA_CONTROL.I_MM2S_STS_MNGR 
       (.\GEN_ASYNC_RESET.scndry_resetn_reg (\GEN_ASYNC_RESET.scndry_resetn_reg ),
        .idle_reg(idle_reg),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .mm2s_all_idle(mm2s_all_idle),
        .mm2s_dmacr(mm2s_dmacr),
        .mm2s_dmasr(mm2s_dmasr),
        .mm2s_halted_set0(mm2s_halted_set0),
        .mm2s_halted_set_reg_0(mm2s_halted_set_reg),
        .out(out),
        .sinit(sinit));
  FDRE \GEN_MM2S_DMA_CONTROL.mm2s_stop_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_stop_i),
        .Q(mm2s_stop),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT3 #(
    .INIT(8'hF4)) 
    \GEN_SYNC_FIFO.mm2s_stop_d1_i_1 
       (.I0(soft_reset_d2),
        .I1(soft_reset_d1),
        .I2(\GEN_SYNC_FIFO.mm2s_stop_d1_reg ),
        .O(mm2s_cntrl_strm_stop));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT4 #(
    .INIT(16'hAEFF)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_1 
       (.I0(\GEN_SYNC_FIFO.mm2s_stop_d1_reg ),
        .I1(soft_reset_d1),
        .I2(soft_reset_d2),
        .I3(out),
        .O(rst));
endmodule

module Loopback_axi_dma_1_0_axi_dma_mm2s_sg_if
   (sts_received_d1,
    desc_update_done,
    updt_data_reg_0,
    packet_in_progress,
    queue_empty_new0,
    FIFO_Full_reg,
    D,
    write_cmnd_cmb,
    FIFO_Full_reg_0,
    updt_data_reg_1,
    E,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    \updt_desc_reg2_reg[31]_0 ,
    updt_sts_reg_0,
    desc_update_done_reg_0,
    \updt_desc_reg0_reg[31]_0 ,
    \updt_desc_reg2_reg[32]_0 ,
    sinit,
    m_axi_sg_aclk,
    \GEN_UPDT_FOR_QUEUE.sts_received_d1_reg_0 ,
    updt_data_reg_2,
    packet_in_progress_reg_0,
    \GEN_MM2S.queue_empty_new_reg ,
    \GEN_MM2S.queue_dout_new_reg[90] ,
    Q,
    \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ,
    ch1_ftch_queue_empty,
    ptr_queue_full,
    out,
    m_axis_mm2s_sts_tvalid_int,
    sts_queue_full,
    \QUEUE_COUNT.cmnds_queued_shift_reg[3] ,
    m_axis_mm2s_ftch_tvalid_new,
    mm2s_halt,
    \updt_desc_reg0_reg[31]_1 ,
    \updt_desc_reg2_reg[32]_1 ,
    mm2s_tag,
    mm2s_decerr,
    mm2s_slverr,
    mm2s_interr);
  output sts_received_d1;
  output desc_update_done;
  output updt_data_reg_0;
  output packet_in_progress;
  output queue_empty_new0;
  output [0:0]FIFO_Full_reg;
  output [0:0]D;
  output write_cmnd_cmb;
  output FIFO_Full_reg_0;
  output updt_data_reg_1;
  output [0:0]E;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  output \updt_desc_reg2_reg[31]_0 ;
  output [0:0]updt_sts_reg_0;
  output [0:0]desc_update_done_reg_0;
  output [25:0]\updt_desc_reg0_reg[31]_0 ;
  output [29:0]\updt_desc_reg2_reg[32]_0 ;
  input sinit;
  input m_axi_sg_aclk;
  input \GEN_UPDT_FOR_QUEUE.sts_received_d1_reg_0 ;
  input updt_data_reg_2;
  input packet_in_progress_reg_0;
  input [0:0]\GEN_MM2S.queue_empty_new_reg ;
  input \GEN_MM2S.queue_dout_new_reg[90] ;
  input [1:0]Q;
  input \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ;
  input ch1_ftch_queue_empty;
  input ptr_queue_full;
  input out;
  input m_axis_mm2s_sts_tvalid_int;
  input sts_queue_full;
  input \QUEUE_COUNT.cmnds_queued_shift_reg[3] ;
  input m_axis_mm2s_ftch_tvalid_new;
  input mm2s_halt;
  input [51:0]\updt_desc_reg0_reg[31]_1 ;
  input \updt_desc_reg2_reg[32]_1 ;
  input [0:0]mm2s_tag;
  input mm2s_decerr;
  input mm2s_slverr;
  input mm2s_interr;

  wire [0:0]D;
  wire [0:0]E;
  wire [0:0]FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ;
  wire \GEN_MM2S.queue_dout_new_reg[90] ;
  wire [0:0]\GEN_MM2S.queue_empty_new_reg ;
  wire \GEN_UPDT_FOR_QUEUE.sts_received_d1_reg_0 ;
  wire [1:0]Q;
  wire \QUEUE_COUNT.cmnds_queued_shift_reg[3] ;
  wire ch1_ftch_queue_empty;
  wire desc_update_done;
  wire [0:0]desc_update_done_reg_0;
  wire m_axi_sg_aclk;
  wire m_axis_mm2s_ftch_tvalid_new;
  wire m_axis_mm2s_sts_tvalid_int;
  wire mm2s_decerr;
  wire mm2s_halt;
  wire mm2s_interr;
  wire mm2s_slverr;
  wire mm2s_sts_received_clr;
  wire [0:0]mm2s_tag;
  wire [25:0]mm2s_xferd_bytes;
  wire out;
  wire packet_in_progress;
  wire packet_in_progress_reg_0;
  wire ptr_queue_full;
  wire queue_empty_new0;
  wire s_axis_mm2s_updtsts_tvalid;
  wire sinit;
  wire sts_queue_full;
  wire sts_received_d1;
  wire sts_received_re;
  wire updt_data_reg_0;
  wire updt_data_reg_1;
  wire updt_data_reg_2;
  wire [25:0]\updt_desc_reg0_reg[31]_0 ;
  wire [51:0]\updt_desc_reg0_reg[31]_1 ;
  wire \updt_desc_reg2[31]_i_1_n_0 ;
  wire \updt_desc_reg2_reg[31]_0 ;
  wire [29:0]\updt_desc_reg2_reg[32]_0 ;
  wire \updt_desc_reg2_reg[32]_1 ;
  wire updt_sts_i_1_n_0;
  wire [0:0]updt_sts_reg_0;
  wire write_cmnd_cmb;

  LUT2 #(
    .INIT(4'h2)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout[31]_i_1 
       (.I0(updt_data_reg_0),
        .I1(ptr_queue_full),
        .O(E));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_full_i_2 
       (.I0(s_axis_mm2s_updtsts_tvalid),
        .I1(sts_queue_full),
        .O(updt_sts_reg_0));
  Loopback_axi_dma_1_0_srl_fifo_f__parameterized1 \GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO 
       (.D(D),
        .FIFO_Full_reg(FIFO_Full_reg),
        .FIFO_Full_reg_0(FIFO_Full_reg_0),
        .\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg (\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ),
        .\GEN_MM2S.queue_dout_new_reg[90] (updt_data_reg_0),
        .\GEN_MM2S.queue_dout_new_reg[90]_0 (\GEN_MM2S.queue_dout_new_reg[90] ),
        .\GEN_MM2S.queue_empty_new_reg (\GEN_MM2S.queue_empty_new_reg ),
        .\INFERRED_GEN.cnt_i_reg[0] (sts_received_d1),
        .\INFERRED_GEN.cnt_i_reg[1] (\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg_0 ),
        .Q(Q),
        .ch1_ftch_queue_empty(ch1_ftch_queue_empty),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_mm2s_ftch_tvalid_new(m_axis_mm2s_ftch_tvalid_new),
        .mm2s_halt(mm2s_halt),
        .out(mm2s_xferd_bytes),
        .queue_empty_new0(queue_empty_new0),
        .sinit(sinit),
        .sts_received_re(sts_received_re),
        .updt_data_reg(updt_data_reg_1),
        .\updt_desc_reg2_reg[25] (\updt_desc_reg0_reg[31]_1 [25:0]),
        .write_cmnd_cmb(write_cmnd_cmb));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_UPDT_FOR_QUEUE.sts_received_d1_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg_0 ),
        .Q(sts_received_d1),
        .R(sinit));
  LUT2 #(
    .INIT(4'h6)) 
    \QUEUE_COUNT.cmnds_queued_shift[3]_i_2 
       (.I0(desc_update_done),
        .I1(\QUEUE_COUNT.cmnds_queued_shift_reg[3] ),
        .O(desc_update_done_reg_0));
  LUT3 #(
    .INIT(8'h40)) 
    desc_update_done_i_1
       (.I0(sts_queue_full),
        .I1(s_axis_mm2s_updtsts_tvalid),
        .I2(\updt_desc_reg2_reg[31]_0 ),
        .O(mm2s_sts_received_clr));
  FDRE desc_update_done_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_sts_received_clr),
        .Q(desc_update_done),
        .R(sinit));
  FDRE packet_in_progress_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(packet_in_progress_reg_0),
        .Q(packet_in_progress),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hA8A8A8A800A8A8A8)) 
    sts_received_i_i_1
       (.I0(out),
        .I1(m_axis_mm2s_sts_tvalid_int),
        .I2(\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg_0 ),
        .I3(\updt_desc_reg2_reg[31]_0 ),
        .I4(s_axis_mm2s_updtsts_tvalid),
        .I5(sts_queue_full),
        .O(\GEN_ASYNC_RESET.scndry_resetn_reg ));
  FDRE #(
    .INIT(1'b0)) 
    updt_data_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_data_reg_2),
        .Q(updt_data_reg_0),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [30]),
        .Q(\updt_desc_reg0_reg[31]_0 [4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [31]),
        .Q(\updt_desc_reg0_reg[31]_0 [5]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [32]),
        .Q(\updt_desc_reg0_reg[31]_0 [6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [33]),
        .Q(\updt_desc_reg0_reg[31]_0 [7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [34]),
        .Q(\updt_desc_reg0_reg[31]_0 [8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [35]),
        .Q(\updt_desc_reg0_reg[31]_0 [9]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [36]),
        .Q(\updt_desc_reg0_reg[31]_0 [10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [37]),
        .Q(\updt_desc_reg0_reg[31]_0 [11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [38]),
        .Q(\updt_desc_reg0_reg[31]_0 [12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [39]),
        .Q(\updt_desc_reg0_reg[31]_0 [13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [40]),
        .Q(\updt_desc_reg0_reg[31]_0 [14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [41]),
        .Q(\updt_desc_reg0_reg[31]_0 [15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [42]),
        .Q(\updt_desc_reg0_reg[31]_0 [16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [43]),
        .Q(\updt_desc_reg0_reg[31]_0 [17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [44]),
        .Q(\updt_desc_reg0_reg[31]_0 [18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [45]),
        .Q(\updt_desc_reg0_reg[31]_0 [19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [46]),
        .Q(\updt_desc_reg0_reg[31]_0 [20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [47]),
        .Q(\updt_desc_reg0_reg[31]_0 [21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [48]),
        .Q(\updt_desc_reg0_reg[31]_0 [22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [49]),
        .Q(\updt_desc_reg0_reg[31]_0 [23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [50]),
        .Q(\updt_desc_reg0_reg[31]_0 [24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [51]),
        .Q(\updt_desc_reg0_reg[31]_0 [25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [26]),
        .Q(\updt_desc_reg0_reg[31]_0 [0]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [27]),
        .Q(\updt_desc_reg0_reg[31]_0 [1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [28]),
        .Q(\updt_desc_reg0_reg[31]_0 [2]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg0_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .D(\updt_desc_reg0_reg[31]_1 [29]),
        .Q(\updt_desc_reg0_reg[31]_0 [3]),
        .R(sinit));
  LUT5 #(
    .INIT(32'hFF000400)) 
    \updt_desc_reg2[31]_i_1 
       (.I0(mm2s_halt),
        .I1(\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg_0 ),
        .I2(sts_received_d1),
        .I3(out),
        .I4(\updt_desc_reg2_reg[31]_0 ),
        .O(\updt_desc_reg2[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[0]),
        .Q(\updt_desc_reg2_reg[32]_0 [0]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[10]),
        .Q(\updt_desc_reg2_reg[32]_0 [10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[11]),
        .Q(\updt_desc_reg2_reg[32]_0 [11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[12]),
        .Q(\updt_desc_reg2_reg[32]_0 [12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[13]),
        .Q(\updt_desc_reg2_reg[32]_0 [13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[14]),
        .Q(\updt_desc_reg2_reg[32]_0 [14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[15]),
        .Q(\updt_desc_reg2_reg[32]_0 [15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[16]),
        .Q(\updt_desc_reg2_reg[32]_0 [16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[17]),
        .Q(\updt_desc_reg2_reg[32]_0 [17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[18]),
        .Q(\updt_desc_reg2_reg[32]_0 [18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[19]),
        .Q(\updt_desc_reg2_reg[32]_0 [19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[1]),
        .Q(\updt_desc_reg2_reg[32]_0 [1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[20]),
        .Q(\updt_desc_reg2_reg[32]_0 [20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[21]),
        .Q(\updt_desc_reg2_reg[32]_0 [21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[22]),
        .Q(\updt_desc_reg2_reg[32]_0 [22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[23]),
        .Q(\updt_desc_reg2_reg[32]_0 [23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[24]),
        .Q(\updt_desc_reg2_reg[32]_0 [24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[25]),
        .Q(\updt_desc_reg2_reg[32]_0 [25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_interr),
        .Q(\updt_desc_reg2_reg[32]_0 [26]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_slverr),
        .Q(\updt_desc_reg2_reg[32]_0 [27]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[2]),
        .Q(\updt_desc_reg2_reg[32]_0 [2]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_decerr),
        .Q(\updt_desc_reg2_reg[32]_0 [28]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\updt_desc_reg2[31]_i_1_n_0 ),
        .Q(\updt_desc_reg2_reg[31]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[32] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_tag),
        .Q(\updt_desc_reg2_reg[32]_0 [29]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[3]),
        .Q(\updt_desc_reg2_reg[32]_0 [3]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[4]),
        .Q(\updt_desc_reg2_reg[32]_0 [4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[5]),
        .Q(\updt_desc_reg2_reg[32]_0 [5]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[6]),
        .Q(\updt_desc_reg2_reg[32]_0 [6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[7]),
        .Q(\updt_desc_reg2_reg[32]_0 [7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[8]),
        .Q(\updt_desc_reg2_reg[32]_0 [8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \updt_desc_reg2_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(\updt_desc_reg2_reg[32]_1 ),
        .D(mm2s_xferd_bytes[9]),
        .Q(\updt_desc_reg2_reg[32]_0 [9]),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT5 #(
    .INIT(32'hAA880A88)) 
    updt_sts_i_1
       (.I0(out),
        .I1(sts_received_re),
        .I2(\updt_desc_reg2_reg[31]_0 ),
        .I3(s_axis_mm2s_updtsts_tvalid),
        .I4(sts_queue_full),
        .O(updt_sts_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    updt_sts_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_sts_i_1_n_0),
        .Q(s_axis_mm2s_updtsts_tvalid),
        .R(1'b0));
endmodule

module Loopback_axi_dma_1_0_axi_dma_mm2s_sm
   (\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg_0 ,
    Q,
    mm2s_all_idle,
    sinit,
    write_cmnd_cmb,
    m_axi_sg_aclk,
    D,
    packet_in_progress,
    mm2s_dmacr,
    mm2s_stop_i,
    \FSM_sequential_mm2s_cs_reg[0]_0 ,
    ch1_ftch_queue_empty,
    all_is_idle_d1_reg,
    \FSM_sequential_mm2s_cs_reg[0]_1 ,
    mm2s_updt_idle,
    mm2s_ftch_idle,
    all_is_idle_d1_reg_0,
    desc_update_done,
    SR,
    E);
  output \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg_0 ;
  output [1:0]Q;
  output mm2s_all_idle;
  input sinit;
  input write_cmnd_cmb;
  input m_axi_sg_aclk;
  input [0:0]D;
  input packet_in_progress;
  input [0:0]mm2s_dmacr;
  input mm2s_stop_i;
  input \FSM_sequential_mm2s_cs_reg[0]_0 ;
  input ch1_ftch_queue_empty;
  input all_is_idle_d1_reg;
  input \FSM_sequential_mm2s_cs_reg[0]_1 ;
  input mm2s_updt_idle;
  input mm2s_ftch_idle;
  input all_is_idle_d1_reg_0;
  input desc_update_done;
  input [0:0]SR;
  input [0:0]E;

  wire [0:0]D;
  wire [0:0]E;
  wire \FSM_sequential_mm2s_cs[1]_i_1_n_0 ;
  wire \FSM_sequential_mm2s_cs_reg[0]_0 ;
  wire \FSM_sequential_mm2s_cs_reg[0]_1 ;
  wire \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg_0 ;
  wire [1:0]Q;
  wire \QUEUE_COUNT.cmnds_queued_shift[0]_i_1_n_0 ;
  wire \QUEUE_COUNT.cmnds_queued_shift[1]_i_1_n_0 ;
  wire \QUEUE_COUNT.cmnds_queued_shift[2]_i_1_n_0 ;
  wire \QUEUE_COUNT.cmnds_queued_shift[3]_i_3_n_0 ;
  wire [0:0]SR;
  wire all_is_idle_d1_i_3_n_0;
  wire all_is_idle_d1_reg;
  wire all_is_idle_d1_reg_0;
  wire ch1_ftch_queue_empty;
  wire [3:0]cmnds_queued_shift;
  wire desc_update_done;
  wire m_axi_sg_aclk;
  wire mm2s_all_idle;
  wire [0:0]mm2s_dmacr;
  wire mm2s_ftch_idle;
  wire [0:0]mm2s_ns__0;
  wire mm2s_stop_i;
  wire mm2s_updt_idle;
  wire packet_in_progress;
  wire sinit;
  wire write_cmnd_cmb;

  LUT6 #(
    .INIT(64'h00000E000000FFFF)) 
    \FSM_sequential_mm2s_cs[0]_i_1 
       (.I0(packet_in_progress),
        .I1(mm2s_dmacr),
        .I2(mm2s_stop_i),
        .I3(\FSM_sequential_mm2s_cs_reg[0]_0 ),
        .I4(Q[1]),
        .I5(Q[0]),
        .O(mm2s_ns__0));
  LUT6 #(
    .INIT(64'hFFCCFFDDFFCCFFC0)) 
    \FSM_sequential_mm2s_cs[1]_i_1 
       (.I0(ch1_ftch_queue_empty),
        .I1(Q[0]),
        .I2(\FSM_sequential_mm2s_cs_reg[0]_0 ),
        .I3(Q[1]),
        .I4(all_is_idle_d1_reg),
        .I5(\FSM_sequential_mm2s_cs_reg[0]_1 ),
        .O(\FSM_sequential_mm2s_cs[1]_i_1_n_0 ));
  (* FSM_ENCODED_STATES = "fetch_descriptor:01,iSTATE:10,wait_status:10,idle:00" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_mm2s_cs_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(\FSM_sequential_mm2s_cs[1]_i_1_n_0 ),
        .D(mm2s_ns__0),
        .Q(Q[0]),
        .R(sinit));
  (* FSM_ENCODED_STATES = "fetch_descriptor:01,iSTATE:10,wait_status:10,idle:00" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_mm2s_cs_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(\FSM_sequential_mm2s_cs[1]_i_1_n_0 ),
        .D(D),
        .Q(Q[1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(write_cmnd_cmb),
        .Q(\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg_0 ),
        .R(sinit));
  LUT5 #(
    .INIT(32'h0000BE8E)) 
    \QUEUE_COUNT.cmnds_queued_shift[0]_i_1 
       (.I0(cmnds_queued_shift[0]),
        .I1(\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg_0 ),
        .I2(desc_update_done),
        .I3(cmnds_queued_shift[1]),
        .I4(SR),
        .O(\QUEUE_COUNT.cmnds_queued_shift[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT4 #(
    .INIT(16'hFB08)) 
    \QUEUE_COUNT.cmnds_queued_shift[1]_i_1 
       (.I0(cmnds_queued_shift[0]),
        .I1(\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg_0 ),
        .I2(desc_update_done),
        .I3(cmnds_queued_shift[2]),
        .O(\QUEUE_COUNT.cmnds_queued_shift[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \QUEUE_COUNT.cmnds_queued_shift[2]_i_1 
       (.I0(cmnds_queued_shift[1]),
        .I1(\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg_0 ),
        .I2(desc_update_done),
        .I3(cmnds_queued_shift[3]),
        .O(\QUEUE_COUNT.cmnds_queued_shift[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \QUEUE_COUNT.cmnds_queued_shift[3]_i_3 
       (.I0(cmnds_queued_shift[2]),
        .I1(desc_update_done),
        .I2(\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg_0 ),
        .O(\QUEUE_COUNT.cmnds_queued_shift[3]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \QUEUE_COUNT.cmnds_queued_shift_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\QUEUE_COUNT.cmnds_queued_shift[0]_i_1_n_0 ),
        .Q(cmnds_queued_shift[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \QUEUE_COUNT.cmnds_queued_shift_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\QUEUE_COUNT.cmnds_queued_shift[1]_i_1_n_0 ),
        .Q(cmnds_queued_shift[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \QUEUE_COUNT.cmnds_queued_shift_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\QUEUE_COUNT.cmnds_queued_shift[2]_i_1_n_0 ),
        .Q(cmnds_queued_shift[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \QUEUE_COUNT.cmnds_queued_shift_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\QUEUE_COUNT.cmnds_queued_shift[3]_i_3_n_0 ),
        .Q(cmnds_queued_shift[3]),
        .R(SR));
  LUT6 #(
    .INIT(64'h4040004000000000)) 
    all_is_idle_d1_i_1
       (.I0(cmnds_queued_shift[0]),
        .I1(mm2s_updt_idle),
        .I2(mm2s_ftch_idle),
        .I3(all_is_idle_d1_reg_0),
        .I4(all_is_idle_d1_reg),
        .I5(all_is_idle_d1_i_3_n_0),
        .O(mm2s_all_idle));
  LUT2 #(
    .INIT(4'h1)) 
    all_is_idle_d1_i_3
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(all_is_idle_d1_i_3_n_0));
endmodule

module Loopback_axi_dma_1_0_axi_dma_mm2s_sts_mngr
   (mm2s_halted_set_reg_0,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    sinit,
    mm2s_dmacr,
    m_axi_sg_aclk,
    mm2s_halted_set0,
    mm2s_all_idle,
    out,
    idle_reg,
    mm2s_dmasr);
  output mm2s_halted_set_reg_0;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  input sinit;
  input [0:0]mm2s_dmacr;
  input m_axi_sg_aclk;
  input mm2s_halted_set0;
  input mm2s_all_idle;
  input out;
  input idle_reg;
  input mm2s_dmasr;

  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire all_is_idle_d1;
  wire idle_reg;
  wire m_axi_sg_aclk;
  wire mm2s_all_idle;
  wire [0:0]mm2s_dmacr;
  wire mm2s_dmasr;
  wire mm2s_halted_clr;
  wire mm2s_halted_set;
  wire mm2s_halted_set0;
  wire mm2s_halted_set_reg_0;
  wire out;
  wire sinit;

  FDRE #(
    .INIT(1'b0)) 
    all_is_idle_d1_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_all_idle),
        .Q(all_is_idle_d1),
        .R(sinit));
  LUT4 #(
    .INIT(16'hDFDD)) 
    halted_i_1
       (.I0(out),
        .I1(mm2s_halted_set),
        .I2(mm2s_halted_clr),
        .I3(mm2s_dmasr),
        .O(\GEN_ASYNC_RESET.scndry_resetn_reg ));
  LUT6 #(
    .INIT(64'h4400444000004400)) 
    idle_i_1
       (.I0(mm2s_halted_set),
        .I1(out),
        .I2(mm2s_dmacr),
        .I3(idle_reg),
        .I4(all_is_idle_d1),
        .I5(mm2s_all_idle),
        .O(mm2s_halted_set_reg_0));
  FDRE mm2s_halted_clr_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_dmacr),
        .Q(mm2s_halted_clr),
        .R(sinit));
  FDRE mm2s_halted_set_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_halted_set0),
        .Q(mm2s_halted_set),
        .R(sinit));
endmodule

module Loopback_axi_dma_1_0_axi_dma_reg_module
   (s_axi_lite_arready,
    dma_interr_reg,
    dma_slverr_reg,
    dma_decerr_reg,
    sg_interr_reg,
    sg_slverr_reg,
    sg_decerr_reg,
    mm2s_irqthresh_wren,
    \GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg ,
    \dmacr_i_reg[23] ,
    s_axi_lite_bvalid,
    mm2s_dmasr,
    idle_reg,
    \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg ,
    mm2s_stop_i,
    soft_reset_re0,
    soft_reset,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    mm2s_halted_set0,
    packet_in_progress_reg,
    Q,
    ch1_dly_fast_cnt0,
    \dmacr_i_reg[0] ,
    ch1_delay_count0,
    \dmacr_i_reg[20] ,
    irqthresh_wren_reg,
    S,
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[11] ,
    D,
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] ,
    scndry_out,
    s_axi_lite_wready,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ,
    mm2s_introut,
    s_axi_lite_rdata,
    \GEN_ASYNC_WRITE.rdy_to2 ,
    s_axi_lite_aclk,
    p_0_in,
    s_axi_lite_arvalid,
    SR,
    m_axi_sg_aclk,
    sinit,
    dma_interr_reg_0,
    dma_slverr_reg_0,
    dma_decerr_reg_0,
    sg_interr_reg_0,
    sg_slverr_reg_0,
    sg_decerr_reg_0,
    s_axi_lite_awvalid,
    s_axi_lite_wvalid,
    sg_ftch_error0,
    halted_reg,
    idle_reg_0,
    \dmacr_i_reg[0]_0 ,
    mm2s_stop,
    CO,
    ch1_nxtdesc_wren,
    ch1_sg_idle,
    soft_reset_d1,
    mm2s_updt_decerr_set,
    mm2s_updt_interr_set,
    mm2s_updt_slverr_set,
    m_axis_mm2s_ftch_tvalid_new,
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 ,
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 ,
    out,
    packet_in_progress,
    \GEN_MM2S_DMA_CONTROL.mm2s_stop_reg ,
    mm2s_all_idle,
    mm2s_halt_cmplt,
    axi_dma_tstvec,
    ch1_delay_cnt_en,
    mm2s_dly_irq_set,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31] ,
    \GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23] ,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ,
    \ch1_sg_idle1_inferred__0/i__carry ,
    \GEN_ASYNC_WRITE.bvalid_i_reg ,
    s_axi_lite_bready,
    \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4] ,
    s_axi_lite_rready,
    s_axi_lite_awaddr,
    s_axi_lite_wdata,
    s_axi_lite_araddr,
    soft_reset_clr,
    mm2s_ioc_irq_set);
  output s_axi_lite_arready;
  output dma_interr_reg;
  output dma_slverr_reg;
  output dma_decerr_reg;
  output sg_interr_reg;
  output sg_slverr_reg;
  output sg_decerr_reg;
  output mm2s_irqthresh_wren;
  output \GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg ;
  output [6:0]\dmacr_i_reg[23] ;
  output s_axi_lite_bvalid;
  output mm2s_dmasr;
  output idle_reg;
  output \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg ;
  output mm2s_stop_i;
  output soft_reset_re0;
  output soft_reset;
  output [0:0]\GEN_ASYNC_RESET.scndry_resetn_reg ;
  output mm2s_halted_set0;
  output packet_in_progress_reg;
  output [0:0]Q;
  output ch1_dly_fast_cnt0;
  output \dmacr_i_reg[0] ;
  output ch1_delay_count0;
  output [2:0]\dmacr_i_reg[20] ;
  output irqthresh_wren_reg;
  output [6:0]S;
  output [5:0]\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[11] ;
  output [0:0]D;
  output [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] ;
  output scndry_out;
  output s_axi_lite_wready;
  output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ;
  output mm2s_introut;
  output [31:0]s_axi_lite_rdata;
  input \GEN_ASYNC_WRITE.rdy_to2 ;
  input s_axi_lite_aclk;
  input p_0_in;
  input s_axi_lite_arvalid;
  input [0:0]SR;
  input m_axi_sg_aclk;
  input sinit;
  input dma_interr_reg_0;
  input dma_slverr_reg_0;
  input dma_decerr_reg_0;
  input sg_interr_reg_0;
  input sg_slverr_reg_0;
  input sg_decerr_reg_0;
  input s_axi_lite_awvalid;
  input s_axi_lite_wvalid;
  input sg_ftch_error0;
  input halted_reg;
  input idle_reg_0;
  input \dmacr_i_reg[0]_0 ;
  input mm2s_stop;
  input [0:0]CO;
  input ch1_nxtdesc_wren;
  input ch1_sg_idle;
  input soft_reset_d1;
  input mm2s_updt_decerr_set;
  input mm2s_updt_interr_set;
  input mm2s_updt_slverr_set;
  input m_axis_mm2s_ftch_tvalid_new;
  input [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 ;
  input [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 ;
  input out;
  input packet_in_progress;
  input \GEN_MM2S_DMA_CONTROL.mm2s_stop_reg ;
  input mm2s_all_idle;
  input mm2s_halt_cmplt;
  input [0:0]axi_dma_tstvec;
  input ch1_delay_cnt_en;
  input mm2s_dly_irq_set;
  input [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ;
  input [7:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31] ;
  input [7:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23] ;
  input \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ;
  input \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ;
  input [19:0]\ch1_sg_idle1_inferred__0/i__carry ;
  input \GEN_ASYNC_WRITE.bvalid_i_reg ;
  input s_axi_lite_bready;
  input \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4] ;
  input s_axi_lite_rready;
  input [4:0]s_axi_lite_awaddr;
  input [29:0]s_axi_lite_wdata;
  input [9:0]s_axi_lite_araddr;
  input soft_reset_clr;
  input mm2s_ioc_irq_set;

  wire [0:0]CO;
  wire [0:0]D;
  wire [7:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23] ;
  wire [7:0]\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31] ;
  wire \GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg ;
  wire [0:0]\GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4] ;
  wire \GEN_ASYNC_WRITE.bvalid_i_reg ;
  wire \GEN_ASYNC_WRITE.rdy_to2 ;
  wire \GEN_AXI_LITE_IF.AXI_LITE_IF_I_n_38 ;
  wire \GEN_AXI_LITE_IF.AXI_LITE_IF_I_n_42 ;
  wire [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] ;
  wire [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 ;
  wire [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 ;
  wire [5:0]\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[11] ;
  wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ;
  wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ;
  wire \GEN_MM2S_DMA_CONTROL.mm2s_stop_reg ;
  wire \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_15 ;
  wire \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_34 ;
  wire \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_38 ;
  wire \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_39 ;
  wire \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_41 ;
  wire \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_42 ;
  wire \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_43 ;
  wire \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg ;
  wire [0:0]Q;
  wire [6:0]S;
  wire [0:0]SR;
  wire [2:0]axi2ip_wrce;
  wire [31:0]axi2ip_wrdata;
  wire [0:0]axi_dma_tstvec;
  wire ch1_delay_cnt_en;
  wire ch1_delay_count0;
  wire ch1_dly_fast_cnt0;
  wire ch1_nxtdesc_wren;
  wire ch1_sg_idle;
  wire [19:0]\ch1_sg_idle1_inferred__0/i__carry ;
  wire dma_decerr_reg;
  wire dma_decerr_reg_0;
  wire dma_interr_reg;
  wire dma_interr_reg_0;
  wire dma_slverr_reg;
  wire dma_slverr_reg_0;
  wire [23:23]dmacr_i;
  wire \dmacr_i_reg[0] ;
  wire \dmacr_i_reg[0]_0 ;
  wire [2:0]\dmacr_i_reg[20] ;
  wire [6:0]\dmacr_i_reg[23] ;
  wire halted_reg;
  wire idle_reg;
  wire idle_reg_0;
  wire irqdelay_wren0;
  wire irqthresh_wren0;
  wire irqthresh_wren_reg;
  wire m_axi_sg_aclk;
  wire m_axis_mm2s_ftch_tvalid_new;
  wire mm2s_all_idle;
  wire mm2s_dly_irq_set;
  wire [31:3]mm2s_dmacr;
  wire mm2s_dmasr;
  wire mm2s_halt_cmplt;
  wire mm2s_halted_set0;
  wire mm2s_introut;
  wire mm2s_introut_i_cdc_from;
  wire mm2s_ioc_irq_set;
  wire mm2s_irqthresh_wren;
  wire mm2s_stop;
  wire mm2s_stop_i;
  wire [31:12]mm2s_taildesc;
  wire mm2s_updt_decerr_set;
  wire mm2s_updt_interr_set;
  wire mm2s_updt_slverr_set;
  wire out;
  wire p_0_in;
  wire p_0_in1_in;
  wire p_1_in;
  wire packet_in_progress;
  wire packet_in_progress_reg;
  wire s_axi_lite_aclk;
  wire [9:0]s_axi_lite_araddr;
  wire s_axi_lite_arready;
  wire s_axi_lite_arvalid;
  wire [4:0]s_axi_lite_awaddr;
  wire s_axi_lite_awvalid;
  wire s_axi_lite_bready;
  wire s_axi_lite_bvalid;
  wire [31:0]s_axi_lite_rdata;
  wire s_axi_lite_rready;
  wire [29:0]s_axi_lite_wdata;
  wire s_axi_lite_wready;
  wire s_axi_lite_wvalid;
  wire scndry_out;
  wire sg_decerr_reg;
  wire sg_decerr_reg_0;
  wire sg_ftch_error0;
  wire sg_interr_reg;
  wire sg_interr_reg_0;
  wire sg_slverr_reg;
  wire sg_slverr_reg_0;
  wire sinit;
  wire soft_reset;
  wire soft_reset_clr;
  wire soft_reset_d1;
  wire soft_reset_re0;
  (* async_reg = "true" *) wire strm_valid_int2;
  (* async_reg = "true" *) wire strm_valid_int_cdc_to;

  Loopback_axi_dma_1_0_axi_dma_lite_if \GEN_AXI_LITE_IF.AXI_LITE_IF_I 
       (.E(p_1_in),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[0]_0 (\dmacr_i_reg[23] [0]),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[10]_0 (sg_decerr_reg),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[12]_0 (\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_38 ),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[13]_0 (\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_43 ),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_0 ({\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_39 ,Q,\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_41 }),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[14]_1 (\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_42 ),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[1]_0 (idle_reg),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23]_0 (\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23] ),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_0 ({mm2s_taildesc,\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[11] }),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_1 (\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] ),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31]_2 (\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31] ),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[4]_0 (\dmacr_i_reg[23] [1]),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[4]_1 (dma_interr_reg),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[5]_0 (dma_slverr_reg),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[6]_0 (dma_decerr_reg),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[8]_0 (sg_interr_reg),
        .\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[9]_0 (sg_slverr_reg),
        .\GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg_0 (\GEN_ASYNC_READ.s_axi_lite_rvalid_i_reg ),
        .\GEN_ASYNC_WRITE.axi2ip_wrce_reg[4]_0 (\GEN_AXI_LITE_IF.AXI_LITE_IF_I_n_38 ),
        .\GEN_ASYNC_WRITE.axi2ip_wrce_reg[4]_1 (\GEN_ASYNC_WRITE.axi2ip_wrce_reg[4] ),
        .\GEN_ASYNC_WRITE.bvalid_i_reg_0 (\GEN_ASYNC_WRITE.bvalid_i_reg ),
        .\GEN_ASYNC_WRITE.rdy_to2 (\GEN_ASYNC_WRITE.rdy_to2 ),
        .Q({\dmacr_i_reg[23] [6:4],mm2s_dmacr[20],\dmacr_i_reg[23] [3:2],mm2s_dmacr[17:16]}),
        .SR(SR),
        .SS(dmacr_i),
        .axi2ip_wrce({axi2ip_wrce[2],axi2ip_wrce[0]}),
        .\dmacr_i_reg[2] (\GEN_AXI_LITE_IF.AXI_LITE_IF_I_n_42 ),
        .\dmacr_i_reg[2]_0 (soft_reset),
        .irqdelay_wren0(irqdelay_wren0),
        .irqdelay_wren_reg(\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_34 ),
        .irqthresh_wren0(irqthresh_wren0),
        .irqthresh_wren_reg(\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_15 ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .mm2s_dmacr({mm2s_dmacr[31:24],mm2s_dmacr[3]}),
        .mm2s_dmasr(mm2s_dmasr),
        .out(out),
        .p_0_in(p_0_in),
        .p_0_in1_in(p_0_in1_in),
        .s_axi_lite_aclk(s_axi_lite_aclk),
        .s_axi_lite_araddr(s_axi_lite_araddr),
        .s_axi_lite_arready(s_axi_lite_arready),
        .s_axi_lite_arvalid(s_axi_lite_arvalid),
        .s_axi_lite_awaddr(s_axi_lite_awaddr),
        .s_axi_lite_awvalid(s_axi_lite_awvalid),
        .s_axi_lite_bready(s_axi_lite_bready),
        .s_axi_lite_bvalid(s_axi_lite_bvalid),
        .s_axi_lite_rdata(s_axi_lite_rdata),
        .s_axi_lite_rready(s_axi_lite_rready),
        .s_axi_lite_wdata(s_axi_lite_wdata),
        .s_axi_lite_wready(s_axi_lite_wready),
        .s_axi_lite_wvalid(s_axi_lite_wvalid),
        .scndry_out(scndry_out),
        .scndry_vect_out({axi2ip_wrdata[31:6],axi2ip_wrdata[4:3],axi2ip_wrdata[0]}),
        .soft_reset_clr(soft_reset_clr));
  Loopback_axi_dma_1_0_cdc_sync_8 \GEN_MM2S_REGISTERS.GEN_INTROUT_ASYNC.PROC_REG_INTR2LITE 
       (.mm2s_introut(mm2s_introut),
        .prmry_in(mm2s_introut_i_cdc_from),
        .s_axi_lite_aclk(s_axi_lite_aclk));
  Loopback_axi_dma_1_0_axi_dma_register \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER 
       (.CO(CO),
        .D(D),
        .E(p_1_in),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\GEN_ASYNC_RESET.scndry_resetn_reg ),
        .\GEN_DESC_REG_FOR_SG.GEN_TAILUPDATE_EQL32.tailpntr_updated_d1_reg_0 (\GEN_AXI_LITE_IF.AXI_LITE_IF_I_n_38 ),
        .\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 (\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] ),
        .\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 (\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 ),
        .\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 (\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 ),
        .\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 ({mm2s_taildesc,\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[11] }),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 (\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[31] ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ({\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23] [4],\GEN_ASYNC_READ.lite_rdata_cdc_from_reg[23] [1:0]}),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 (\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 (\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ),
        .\GEN_MM2S_DMA_CONTROL.mm2s_stop_reg (\GEN_MM2S_DMA_CONTROL.mm2s_stop_reg ),
        .\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg (\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg ),
        .Q({\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_39 ,Q,\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_41 }),
        .S(S),
        .SS(dmacr_i),
        .axi2ip_wrce({axi2ip_wrce[2],axi2ip_wrce[0]}),
        .axi_dma_tstvec(axi_dma_tstvec),
        .ch1_delay_cnt_en(ch1_delay_cnt_en),
        .ch1_delay_count0(ch1_delay_count0),
        .ch1_dly_fast_cnt0(ch1_dly_fast_cnt0),
        .ch1_nxtdesc_wren(ch1_nxtdesc_wren),
        .ch1_sg_idle(ch1_sg_idle),
        .\ch1_sg_idle1_inferred__0/i__carry (\ch1_sg_idle1_inferred__0/i__carry ),
        .dly_irq_reg_0(\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_43 ),
        .dma_decerr_reg_0(dma_decerr_reg),
        .dma_decerr_reg_1(dma_decerr_reg_0),
        .dma_interr_reg_0(dma_interr_reg),
        .dma_interr_reg_1(dma_interr_reg_0),
        .dma_slverr_reg_0(dma_slverr_reg),
        .dma_slverr_reg_1(dma_slverr_reg_0),
        .\dmacr_i_reg[0]_0 (\dmacr_i_reg[23] [0]),
        .\dmacr_i_reg[0]_1 (\dmacr_i_reg[0] ),
        .\dmacr_i_reg[0]_2 (\dmacr_i_reg[0]_0 ),
        .\dmacr_i_reg[17]_0 (\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_15 ),
        .\dmacr_i_reg[20]_0 (\dmacr_i_reg[20] ),
        .\dmacr_i_reg[23]_0 (\dmacr_i_reg[23] [6:1]),
        .\dmacr_i_reg[24]_0 (\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_34 ),
        .\dmacr_i_reg[2]_0 (soft_reset),
        .\dmacr_i_reg[2]_1 (\GEN_AXI_LITE_IF.AXI_LITE_IF_I_n_42 ),
        .err_irq_reg_0(\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_42 ),
        .halted_reg_0(halted_reg),
        .idle_reg_0(idle_reg),
        .idle_reg_1(idle_reg_0),
        .ioc_irq_reg_0(\GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER_n_38 ),
        .irqdelay_wren0(irqdelay_wren0),
        .irqthresh_wren0(irqthresh_wren0),
        .irqthresh_wren_reg_0(mm2s_irqthresh_wren),
        .irqthresh_wren_reg_1(irqthresh_wren_reg),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_mm2s_ftch_tvalid_new(m_axis_mm2s_ftch_tvalid_new),
        .mm2s_all_idle(mm2s_all_idle),
        .mm2s_dly_irq_set(mm2s_dly_irq_set),
        .mm2s_dmacr({mm2s_dmacr[31:24],mm2s_dmacr[20],mm2s_dmacr[17:16],mm2s_dmacr[3]}),
        .mm2s_dmasr(mm2s_dmasr),
        .mm2s_halt_cmplt(mm2s_halt_cmplt),
        .mm2s_halted_set0(mm2s_halted_set0),
        .mm2s_ioc_irq_set(mm2s_ioc_irq_set),
        .mm2s_stop(mm2s_stop),
        .mm2s_stop_i(mm2s_stop_i),
        .mm2s_updt_decerr_set(mm2s_updt_decerr_set),
        .mm2s_updt_interr_set(mm2s_updt_interr_set),
        .mm2s_updt_slverr_set(mm2s_updt_slverr_set),
        .out(out),
        .p_0_in1_in(p_0_in1_in),
        .packet_in_progress(packet_in_progress),
        .packet_in_progress_reg(packet_in_progress_reg),
        .prmry_in(mm2s_introut_i_cdc_from),
        .scndry_vect_out({axi2ip_wrdata[31:6],axi2ip_wrdata[4:3],axi2ip_wrdata[0]}),
        .sg_decerr_reg_0(sg_decerr_reg),
        .sg_decerr_reg_1(sg_decerr_reg_0),
        .sg_ftch_error0(sg_ftch_error0),
        .sg_interr_reg_0(sg_interr_reg),
        .sg_interr_reg_1(sg_interr_reg_0),
        .sg_slverr_reg_0(sg_slverr_reg),
        .sg_slverr_reg_1(sg_slverr_reg_0),
        .sinit(sinit),
        .soft_reset_d1(soft_reset_d1),
        .soft_reset_re0(soft_reset_re0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(strm_valid_int2));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(strm_valid_int_cdc_to));
endmodule

module Loopback_axi_dma_1_0_axi_dma_register
   (dma_interr_reg_0,
    dma_slverr_reg_0,
    dma_decerr_reg_0,
    sg_interr_reg_0,
    sg_slverr_reg_0,
    sg_decerr_reg_0,
    irqthresh_wren_reg_0,
    \dmacr_i_reg[0]_0 ,
    mm2s_dmasr,
    idle_reg_0,
    prmry_in,
    \dmacr_i_reg[2]_0 ,
    \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg ,
    mm2s_stop_i,
    soft_reset_re0,
    \dmacr_i_reg[17]_0 ,
    mm2s_dmacr,
    \dmacr_i_reg[23]_0 ,
    \dmacr_i_reg[24]_0 ,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    mm2s_halted_set0,
    packet_in_progress_reg,
    ioc_irq_reg_0,
    Q,
    err_irq_reg_0,
    dly_irq_reg_0,
    ch1_dly_fast_cnt0,
    \dmacr_i_reg[0]_1 ,
    ch1_delay_count0,
    \dmacr_i_reg[20]_0 ,
    irqthresh_wren_reg_1,
    S,
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 ,
    D,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ,
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 ,
    sinit,
    dma_interr_reg_1,
    m_axi_sg_aclk,
    dma_slverr_reg_1,
    dma_decerr_reg_1,
    sg_interr_reg_1,
    sg_slverr_reg_1,
    sg_decerr_reg_1,
    irqthresh_wren0,
    irqdelay_wren0,
    sg_ftch_error0,
    halted_reg_0,
    idle_reg_1,
    \GEN_DESC_REG_FOR_SG.GEN_TAILUPDATE_EQL32.tailpntr_updated_d1_reg_0 ,
    \dmacr_i_reg[2]_1 ,
    \dmacr_i_reg[0]_2 ,
    axi2ip_wrce,
    scndry_vect_out,
    mm2s_stop,
    CO,
    ch1_nxtdesc_wren,
    ch1_sg_idle,
    soft_reset_d1,
    mm2s_updt_decerr_set,
    mm2s_updt_interr_set,
    mm2s_updt_slverr_set,
    m_axis_mm2s_ftch_tvalid_new,
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 ,
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 ,
    out,
    packet_in_progress,
    \GEN_MM2S_DMA_CONTROL.mm2s_stop_reg ,
    mm2s_all_idle,
    mm2s_halt_cmplt,
    axi_dma_tstvec,
    ch1_delay_cnt_en,
    mm2s_dly_irq_set,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 ,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 ,
    \ch1_sg_idle1_inferred__0/i__carry ,
    SS,
    p_0_in1_in,
    mm2s_ioc_irq_set,
    E);
  output dma_interr_reg_0;
  output dma_slverr_reg_0;
  output dma_decerr_reg_0;
  output sg_interr_reg_0;
  output sg_slverr_reg_0;
  output sg_decerr_reg_0;
  output irqthresh_wren_reg_0;
  output \dmacr_i_reg[0]_0 ;
  output mm2s_dmasr;
  output idle_reg_0;
  output prmry_in;
  output \dmacr_i_reg[2]_0 ;
  output \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg ;
  output mm2s_stop_i;
  output soft_reset_re0;
  output \dmacr_i_reg[17]_0 ;
  output [11:0]mm2s_dmacr;
  output [5:0]\dmacr_i_reg[23]_0 ;
  output \dmacr_i_reg[24]_0 ;
  output [0:0]\GEN_ASYNC_RESET.scndry_resetn_reg ;
  output mm2s_halted_set0;
  output packet_in_progress_reg;
  output ioc_irq_reg_0;
  output [2:0]Q;
  output err_irq_reg_0;
  output dly_irq_reg_0;
  output ch1_dly_fast_cnt0;
  output \dmacr_i_reg[0]_1 ;
  output ch1_delay_count0;
  output [2:0]\dmacr_i_reg[20]_0 ;
  output irqthresh_wren_reg_1;
  output [6:0]S;
  output [25:0]\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 ;
  output [0:0]D;
  output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ;
  output [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 ;
  input sinit;
  input dma_interr_reg_1;
  input m_axi_sg_aclk;
  input dma_slverr_reg_1;
  input dma_decerr_reg_1;
  input sg_interr_reg_1;
  input sg_slverr_reg_1;
  input sg_decerr_reg_1;
  input irqthresh_wren0;
  input irqdelay_wren0;
  input sg_ftch_error0;
  input halted_reg_0;
  input idle_reg_1;
  input \GEN_DESC_REG_FOR_SG.GEN_TAILUPDATE_EQL32.tailpntr_updated_d1_reg_0 ;
  input \dmacr_i_reg[2]_1 ;
  input \dmacr_i_reg[0]_2 ;
  input [1:0]axi2ip_wrce;
  input [28:0]scndry_vect_out;
  input mm2s_stop;
  input [0:0]CO;
  input ch1_nxtdesc_wren;
  input ch1_sg_idle;
  input soft_reset_d1;
  input mm2s_updt_decerr_set;
  input mm2s_updt_interr_set;
  input mm2s_updt_slverr_set;
  input m_axis_mm2s_ftch_tvalid_new;
  input [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 ;
  input [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 ;
  input out;
  input packet_in_progress;
  input \GEN_MM2S_DMA_CONTROL.mm2s_stop_reg ;
  input mm2s_all_idle;
  input mm2s_halt_cmplt;
  input [0:0]axi_dma_tstvec;
  input ch1_delay_cnt_en;
  input mm2s_dly_irq_set;
  input [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ;
  input [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 ;
  input [2:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ;
  input \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ;
  input \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 ;
  input [19:0]\ch1_sg_idle1_inferred__0/i__carry ;
  input [0:0]SS;
  input p_0_in1_in;
  input mm2s_ioc_irq_set;
  input [0:0]E;

  wire [0:0]CO;
  wire [0:0]D;
  wire [0:0]E;
  wire [0:0]\GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \GEN_DESC_REG_FOR_SG.GEN_TAILUPDATE_EQL32.tailpntr_updated_d1_reg_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[10]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[11]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[12]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[13]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[14]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[15]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[16]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[17]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[18]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[19]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[20]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[21]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[22]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[23]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[24]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[25]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[26]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[27]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[28]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[29]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[30]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[31]_i_2_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[6]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[7]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[8]_i_1_n_0 ;
  wire \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[9]_i_1_n_0 ;
  wire [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 ;
  wire [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 ;
  wire [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 ;
  wire [25:0]\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_3_n_0 ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_4_n_0 ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_6_n_0 ;
  wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ;
  wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_2_n_0 ;
  wire [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0 ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0 ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count[1]_i_2_n_0 ;
  wire [2:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 ;
  wire \GEN_MM2S_DMA_CONTROL.mm2s_stop_reg ;
  wire \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg ;
  wire \GEN_PNTR_FOR_CH1.ch1_sg_idle_i_2_n_0 ;
  wire \GEN_PNTR_FOR_CH1.ch1_sg_idle_i_3_n_0 ;
  wire [2:0]Q;
  wire [6:0]S;
  wire [0:0]SS;
  wire [1:0]axi2ip_wrce;
  wire [0:0]axi_dma_tstvec;
  wire ch1_delay_cnt_en;
  wire ch1_delay_count0;
  wire ch1_dly_fast_cnt0;
  wire ch1_nxtdesc_wren;
  wire ch1_sg_idle;
  wire [19:0]\ch1_sg_idle1_inferred__0/i__carry ;
  wire curdesc_lsb_i;
  wire curdesc_lsb_i1;
  wire dly_irq_i_1_n_0;
  wire dly_irq_reg_0;
  wire dma_decerr_reg_0;
  wire dma_decerr_reg_1;
  wire dma_interr_reg_0;
  wire dma_interr_reg_1;
  wire dma_slverr_reg_0;
  wire dma_slverr_reg_1;
  wire \dmacr_i[0]_i_1_n_0 ;
  wire \dmacr_i_reg[0]_0 ;
  wire \dmacr_i_reg[0]_1 ;
  wire \dmacr_i_reg[0]_2 ;
  wire \dmacr_i_reg[17]_0 ;
  wire [2:0]\dmacr_i_reg[20]_0 ;
  wire [5:0]\dmacr_i_reg[23]_0 ;
  wire \dmacr_i_reg[24]_0 ;
  wire \dmacr_i_reg[2]_0 ;
  wire \dmacr_i_reg[2]_1 ;
  wire err_irq_i_1_n_0;
  wire err_irq_i_2_n_0;
  wire err_irq_reg_0;
  wire error_d1;
  wire error_d1_i_1_n_0;
  wire error_pointer_set;
  wire halted_reg_0;
  wire idle_reg_0;
  wire idle_reg_1;
  wire introut_i_1_n_0;
  wire introut_i_2_n_0;
  wire ioc_irq_i_1_n_0;
  wire ioc_irq_reg_0;
  wire irqdelay_wren0;
  wire irqdelay_wren_i_3_n_0;
  wire irqdelay_wren_i_4_n_0;
  wire irqthresh_wren0;
  wire irqthresh_wren_i_3_n_0;
  wire irqthresh_wren_i_4_n_0;
  wire irqthresh_wren_reg_0;
  wire irqthresh_wren_reg_1;
  wire m_axi_sg_aclk;
  wire m_axis_mm2s_ftch_tvalid_new;
  wire mm2s_all_idle;
  wire mm2s_dly_irq_set;
  wire [11:0]mm2s_dmacr;
  wire mm2s_dmasr;
  wire mm2s_halt_cmplt;
  wire mm2s_halted_set0;
  wire mm2s_ioc_irq_set;
  wire mm2s_irqdelay_wren;
  wire mm2s_stop;
  wire mm2s_stop_i;
  wire mm2s_updt_decerr_set;
  wire mm2s_updt_interr_set;
  wire mm2s_updt_slverr_set;
  wire out;
  wire p_0_in1_in;
  wire packet_in_progress;
  wire packet_in_progress_reg;
  wire prmry_in;
  wire [28:0]scndry_vect_out;
  wire sg_decerr_reg_0;
  wire sg_decerr_reg_1;
  wire sg_ftch_error;
  wire sg_ftch_error0;
  wire sg_interr_reg_0;
  wire sg_interr_reg_1;
  wire sg_slverr_reg_0;
  wire sg_slverr_reg_1;
  wire sg_updt_error;
  wire sg_updt_error0;
  wire sinit;
  wire soft_reset_d1;
  wire soft_reset_re0;
  wire tailpntr_updated_d1;
  wire tailpntr_updated_d2;

  FDRE \GEN_DESC_REG_FOR_SG.GEN_TAILUPDATE_EQL32.tailpntr_updated_d1_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_DESC_REG_FOR_SG.GEN_TAILUPDATE_EQL32.tailpntr_updated_d1_reg_0 ),
        .Q(tailpntr_updated_d1),
        .R(1'b0));
  FDRE \GEN_DESC_REG_FOR_SG.GEN_TAILUPDATE_EQL32.tailpntr_updated_d2_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(tailpntr_updated_d1),
        .Q(tailpntr_updated_d2),
        .R(sinit));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[10]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [4]),
        .I3(scndry_vect_out[7]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [4]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[11]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [5]),
        .I3(scndry_vect_out[8]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [5]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[12]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [6]),
        .I3(scndry_vect_out[9]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [6]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[12]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[13]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [7]),
        .I3(scndry_vect_out[10]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [7]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[13]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[14]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [8]),
        .I3(scndry_vect_out[11]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [8]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[14]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[15]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [9]),
        .I3(scndry_vect_out[12]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [9]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[15]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[16]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [10]),
        .I3(scndry_vect_out[13]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [10]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[16]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[17]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [11]),
        .I3(scndry_vect_out[14]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [11]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[17]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[18]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [12]),
        .I3(scndry_vect_out[15]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [12]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[18]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[19]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [13]),
        .I3(scndry_vect_out[16]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [13]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[19]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[20]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [14]),
        .I3(scndry_vect_out[17]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [14]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[20]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[21]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [15]),
        .I3(scndry_vect_out[18]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [15]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[21]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[22]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [16]),
        .I3(scndry_vect_out[19]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [16]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[22]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[23]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [17]),
        .I3(scndry_vect_out[20]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [17]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[23]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[24]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [18]),
        .I3(scndry_vect_out[21]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [18]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[24]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[25]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [19]),
        .I3(scndry_vect_out[22]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [19]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[25]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[26]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [20]),
        .I3(scndry_vect_out[23]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [20]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[26]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[27]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [21]),
        .I3(scndry_vect_out[24]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [21]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[27]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[28]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [22]),
        .I3(scndry_vect_out[25]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [22]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[28]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[29]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [23]),
        .I3(scndry_vect_out[26]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [23]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[29]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[30]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [24]),
        .I3(scndry_vect_out[27]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [24]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[30]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFEAEAEA)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[31]_i_1 
       (.I0(curdesc_lsb_i1),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\dmacr_i_reg[0]_0 ),
        .I3(mm2s_dmasr),
        .I4(axi2ip_wrce[1]),
        .I5(error_pointer_set),
        .O(curdesc_lsb_i));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[31]_i_2 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [25]),
        .I3(scndry_vect_out[28]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [25]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[6]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [0]),
        .I3(scndry_vect_out[3]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [0]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[7]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [1]),
        .I3(scndry_vect_out[4]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [1]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[8]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [2]),
        .I3(scndry_vect_out[5]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [2]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF7800000F780)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i[9]_i_1 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_1 [3]),
        .I3(scndry_vect_out[6]),
        .I4(curdesc_lsb_i1),
        .I5(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_2 [3]),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[10]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[11]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [5]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[12]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[13]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[14]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[15]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [9]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[16]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[17]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[18]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[19]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[20]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[21]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[22]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[23]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[24]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[25]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[26]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[27]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[28]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[29]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[30]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[31]_i_2_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[6]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [0]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[7]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[8]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [2]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i[9]_i_1_n_0 ),
        .Q(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31]_0 [3]),
        .R(sinit));
  LUT2 #(
    .INIT(4'hE)) 
    \GEN_DESC_REG_FOR_SG.error_pointer_set_i_1 
       (.I0(sg_updt_error),
        .I1(sg_ftch_error),
        .O(curdesc_lsb_i1));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.error_pointer_set_reg 
       (.C(m_axi_sg_aclk),
        .CE(curdesc_lsb_i),
        .D(curdesc_lsb_i1),
        .Q(error_pointer_set),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[7]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[8]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [5]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[9]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[10]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[11]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[12]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [9]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[13]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[14]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[15]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[16]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[17]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[18]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[19]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[20]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[21]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[22]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[23]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[24]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[25]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[26]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[27]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[28]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[3]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [0]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[4]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[5]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [2]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(scndry_vect_out[6]),
        .Q(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [3]),
        .R(sinit));
  LUT5 #(
    .INIT(32'hFFFFFFEF)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_1 
       (.I0(axi_dma_tstvec),
        .I1(mm2s_irqdelay_wren),
        .I2(ch1_delay_cnt_en),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_3_n_0 ),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_4_n_0 ),
        .O(ch1_dly_fast_cnt0));
  LUT5 #(
    .INIT(32'h00010000)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_3 
       (.I0(mm2s_dmacr[8]),
        .I1(mm2s_dmacr[9]),
        .I2(mm2s_dmacr[10]),
        .I3(mm2s_dmacr[11]),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_6_n_0 ),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT4 #(
    .INIT(16'hEFFF)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_4 
       (.I0(dly_irq_reg_0),
        .I1(mm2s_dly_irq_set),
        .I2(out),
        .I3(\dmacr_i_reg[0]_0 ),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_6 
       (.I0(mm2s_dmacr[5]),
        .I1(mm2s_dmacr[4]),
        .I2(mm2s_dmacr[7]),
        .I3(mm2s_dmacr[6]),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_2 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(out),
        .I2(mm2s_dly_irq_set),
        .I3(dly_irq_reg_0),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_3_n_0 ),
        .O(\dmacr_i_reg[0]_1 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000002)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_2_n_0 ),
        .I2(axi_dma_tstvec),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_3_n_0 ),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0 ),
        .I5(ch1_dly_fast_cnt0),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_2_n_0 ),
        .I2(axi_dma_tstvec),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_3_n_0 ),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0 ),
        .O(ch1_delay_count0));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_2 
       (.I0(mm2s_dmacr[9]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 [5]),
        .I2(mm2s_dmacr[7]),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 [3]),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0 ),
        .I1(mm2s_dmacr[5]),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 [1]),
        .I3(mm2s_dmacr[6]),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 [2]),
        .I5(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0 ),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4 
       (.I0(mm2s_dmacr[4]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 [0]),
        .I2(mm2s_dmacr[8]),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 [4]),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5 
       (.I0(mm2s_dmacr[10]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 [6]),
        .I2(mm2s_dmacr[11]),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_0 [7]),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0015FFFF00150015)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[0]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] [0]),
        .I1(mm2s_dly_irq_set),
        .I2(Q[1]),
        .I3(irqthresh_wren_reg_0),
        .I4(irqthresh_wren_reg_1),
        .I5(mm2s_dmacr[1]),
        .O(\dmacr_i_reg[20]_0 [0]));
  LUT5 #(
    .INIT(32'hF22222F2)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[1]_i_1 
       (.I0(mm2s_dmacr[2]),
        .I1(irqthresh_wren_reg_1),
        .I2(\GEN_INCLUDE_MM2S.ch1_thresh_count[1]_i_2_n_0 ),
        .I3(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] [0]),
        .I4(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] [1]),
        .O(\dmacr_i_reg[20]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT3 #(
    .INIT(8'h07)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[1]_i_2 
       (.I0(mm2s_dly_irq_set),
        .I1(Q[1]),
        .I2(irqthresh_wren_reg_0),
        .O(\GEN_INCLUDE_MM2S.ch1_thresh_count[1]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h3ACA)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[4]_i_1 
       (.I0(mm2s_dmacr[3]),
        .I1(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ),
        .I2(irqthresh_wren_reg_1),
        .I3(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] [2]),
        .O(\dmacr_i_reg[20]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT4 #(
    .INIT(16'h0015)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[7]_i_4 
       (.I0(irqthresh_wren_reg_0),
        .I1(Q[1]),
        .I2(mm2s_dly_irq_set),
        .I3(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 ),
        .O(irqthresh_wren_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT4 #(
    .INIT(16'hFFF1)) 
    \GEN_MM2S.queue_dout_new[90]_i_2 
       (.I0(packet_in_progress),
        .I1(\dmacr_i_reg[0]_0 ),
        .I2(\GEN_MM2S_DMA_CONTROL.mm2s_stop_reg ),
        .I3(\dmacr_i_reg[2]_0 ),
        .O(packet_in_progress_reg));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT5 #(
    .INIT(32'hFFFFDDDF)) 
    \GEN_MM2S.reg1[90]_i_1 
       (.I0(out),
        .I1(\dmacr_i_reg[2]_0 ),
        .I2(\dmacr_i_reg[0]_0 ),
        .I3(packet_in_progress),
        .I4(\GEN_MM2S_DMA_CONTROL.mm2s_stop_reg ),
        .O(\GEN_ASYNC_RESET.scndry_resetn_reg ));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \GEN_MM2S_DMA_CONTROL.mm2s_stop_i_1 
       (.I0(\dmacr_i_reg[2]_0 ),
        .I1(\GEN_MM2S_DMA_CONTROL.mm2s_stop_reg ),
        .O(mm2s_stop_i));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAFFAAEA)) 
    \GEN_PNTR_FOR_CH1.ch1_sg_idle_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_sg_idle_i_2_n_0 ),
        .I1(CO),
        .I2(ch1_nxtdesc_wren),
        .I3(\GEN_PNTR_FOR_CH1.ch1_sg_idle_i_3_n_0 ),
        .I4(ch1_sg_idle),
        .I5(mm2s_stop_i),
        .O(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg ));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \GEN_PNTR_FOR_CH1.ch1_sg_idle_i_2 
       (.I0(\dmacr_i_reg[0]_0 ),
        .I1(out),
        .O(\GEN_PNTR_FOR_CH1.ch1_sg_idle_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \GEN_PNTR_FOR_CH1.ch1_sg_idle_i_3 
       (.I0(tailpntr_updated_d1),
        .I1(tailpntr_updated_d2),
        .O(\GEN_PNTR_FOR_CH1.ch1_sg_idle_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg[26]_i_1 
       (.I0(mm2s_dmacr[0]),
        .O(D));
  LUT4 #(
    .INIT(16'hF7F0)) 
    dly_irq_i_1
       (.I0(scndry_vect_out[10]),
        .I1(p_0_in1_in),
        .I2(mm2s_dly_irq_set),
        .I3(dly_irq_reg_0),
        .O(dly_irq_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    dly_irq_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(dly_irq_i_1_n_0),
        .Q(dly_irq_reg_0),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    dma_decerr_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(dma_decerr_reg_1),
        .Q(dma_decerr_reg_0),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    dma_interr_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(dma_interr_reg_1),
        .Q(dma_interr_reg_0),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    dma_slverr_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(dma_slverr_reg_1),
        .Q(dma_slverr_reg_0),
        .R(sinit));
  LUT6 #(
    .INIT(64'h0000A80800000000)) 
    \dmacr_i[0]_i_1 
       (.I0(\dmacr_i_reg[0]_2 ),
        .I1(\dmacr_i_reg[0]_0 ),
        .I2(axi2ip_wrce[0]),
        .I3(scndry_vect_out[0]),
        .I4(mm2s_stop),
        .I5(err_irq_i_2_n_0),
        .O(\dmacr_i[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\dmacr_i[0]_i_1_n_0 ),
        .Q(\dmacr_i_reg[0]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[9]),
        .Q(Q[0]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[10]),
        .Q(Q[1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[11]),
        .Q(Q[2]),
        .R(sinit));
  FDSE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[13]),
        .Q(mm2s_dmacr[1]),
        .S(SS));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[14]),
        .Q(mm2s_dmacr[2]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[15]),
        .Q(\dmacr_i_reg[23]_0 [1]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[16]),
        .Q(\dmacr_i_reg[23]_0 [2]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[17]),
        .Q(mm2s_dmacr[3]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[18]),
        .Q(\dmacr_i_reg[23]_0 [3]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[19]),
        .Q(\dmacr_i_reg[23]_0 [4]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[20]),
        .Q(\dmacr_i_reg[23]_0 [5]),
        .R(SS));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[21]),
        .Q(mm2s_dmacr[4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[22]),
        .Q(mm2s_dmacr[5]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[23]),
        .Q(mm2s_dmacr[6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[24]),
        .Q(mm2s_dmacr[7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[25]),
        .Q(mm2s_dmacr[8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[26]),
        .Q(mm2s_dmacr[9]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\dmacr_i_reg[2]_1 ),
        .Q(\dmacr_i_reg[2]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[27]),
        .Q(mm2s_dmacr[10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[28]),
        .Q(mm2s_dmacr[11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[1]),
        .Q(mm2s_dmacr[0]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \dmacr_i_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(axi2ip_wrce[0]),
        .D(scndry_vect_out[2]),
        .Q(\dmacr_i_reg[23]_0 [0]),
        .R(sinit));
  LUT5 #(
    .INIT(32'h57FF0303)) 
    err_irq_i_1
       (.I0(scndry_vect_out[11]),
        .I1(err_irq_i_2_n_0),
        .I2(error_d1),
        .I3(p_0_in1_in),
        .I4(err_irq_reg_0),
        .O(err_irq_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    err_irq_i_2
       (.I0(sg_interr_reg_0),
        .I1(sg_slverr_reg_0),
        .I2(sg_decerr_reg_0),
        .I3(dma_interr_reg_0),
        .I4(dma_slverr_reg_0),
        .I5(dma_decerr_reg_0),
        .O(err_irq_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    err_irq_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(err_irq_i_1_n_0),
        .Q(err_irq_reg_0),
        .R(sinit));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    error_d1_i_1
       (.I0(dma_decerr_reg_0),
        .I1(dma_slverr_reg_0),
        .I2(dma_interr_reg_0),
        .I3(sg_decerr_reg_0),
        .I4(sg_slverr_reg_0),
        .I5(sg_interr_reg_0),
        .O(error_d1_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    error_d1_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(error_d1_i_1_n_0),
        .Q(error_d1),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    halted_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(halted_reg_0),
        .Q(mm2s_dmasr),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h9009)) 
    i__carry_i_2
       (.I0(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [25]),
        .I1(\ch1_sg_idle1_inferred__0/i__carry [19]),
        .I2(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [24]),
        .I3(\ch1_sg_idle1_inferred__0/i__carry [18]),
        .O(S[6]));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    i__carry_i_3
       (.I0(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [22]),
        .I1(\ch1_sg_idle1_inferred__0/i__carry [16]),
        .I2(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [21]),
        .I3(\ch1_sg_idle1_inferred__0/i__carry [15]),
        .I4(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [23]),
        .I5(\ch1_sg_idle1_inferred__0/i__carry [17]),
        .O(S[5]));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    i__carry_i_4
       (.I0(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [19]),
        .I1(\ch1_sg_idle1_inferred__0/i__carry [13]),
        .I2(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [18]),
        .I3(\ch1_sg_idle1_inferred__0/i__carry [12]),
        .I4(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [20]),
        .I5(\ch1_sg_idle1_inferred__0/i__carry [14]),
        .O(S[4]));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    i__carry_i_5
       (.I0(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [15]),
        .I1(\ch1_sg_idle1_inferred__0/i__carry [9]),
        .I2(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [17]),
        .I3(\ch1_sg_idle1_inferred__0/i__carry [11]),
        .I4(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [16]),
        .I5(\ch1_sg_idle1_inferred__0/i__carry [10]),
        .O(S[3]));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    i__carry_i_6
       (.I0(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [13]),
        .I1(\ch1_sg_idle1_inferred__0/i__carry [7]),
        .I2(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [12]),
        .I3(\ch1_sg_idle1_inferred__0/i__carry [6]),
        .I4(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [14]),
        .I5(\ch1_sg_idle1_inferred__0/i__carry [8]),
        .O(S[2]));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    i__carry_i_7
       (.I0(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [10]),
        .I1(\ch1_sg_idle1_inferred__0/i__carry [4]),
        .I2(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [9]),
        .I3(\ch1_sg_idle1_inferred__0/i__carry [3]),
        .I4(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [11]),
        .I5(\ch1_sg_idle1_inferred__0/i__carry [5]),
        .O(S[1]));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    i__carry_i_8
       (.I0(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [7]),
        .I1(\ch1_sg_idle1_inferred__0/i__carry [1]),
        .I2(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [6]),
        .I3(\ch1_sg_idle1_inferred__0/i__carry [0]),
        .I4(\GEN_DESC_REG_FOR_SG.taildesc_lsb_i2_reg[31]_0 [8]),
        .I5(\ch1_sg_idle1_inferred__0/i__carry [2]),
        .O(S[0]));
  FDRE #(
    .INIT(1'b0)) 
    idle_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(idle_reg_1),
        .Q(idle_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hAEAAAAAA)) 
    introut_i_1
       (.I0(introut_i_2_n_0),
        .I1(out),
        .I2(\dmacr_i_reg[2]_0 ),
        .I3(ioc_irq_reg_0),
        .I4(Q[0]),
        .O(introut_i_1_n_0));
  LUT6 #(
    .INIT(64'h00F0008000800080)) 
    introut_i_2
       (.I0(err_irq_reg_0),
        .I1(Q[2]),
        .I2(out),
        .I3(\dmacr_i_reg[2]_0 ),
        .I4(dly_irq_reg_0),
        .I5(Q[1]),
        .O(introut_i_2_n_0));
  FDRE introut_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(introut_i_1_n_0),
        .Q(prmry_in),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hF7F0)) 
    ioc_irq_i_1
       (.I0(scndry_vect_out[9]),
        .I1(p_0_in1_in),
        .I2(mm2s_ioc_irq_set),
        .I3(ioc_irq_reg_0),
        .O(ioc_irq_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ioc_irq_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ioc_irq_i_1_n_0),
        .Q(ioc_irq_reg_0),
        .R(sinit));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    irqdelay_wren_i_2
       (.I0(irqdelay_wren_i_3_n_0),
        .I1(mm2s_dmacr[4]),
        .I2(scndry_vect_out[21]),
        .I3(mm2s_dmacr[8]),
        .I4(scndry_vect_out[25]),
        .I5(irqdelay_wren_i_4_n_0),
        .O(\dmacr_i_reg[24]_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    irqdelay_wren_i_3
       (.I0(mm2s_dmacr[9]),
        .I1(scndry_vect_out[26]),
        .I2(mm2s_dmacr[7]),
        .I3(scndry_vect_out[24]),
        .O(irqdelay_wren_i_3_n_0));
  LUT4 #(
    .INIT(16'h6FF6)) 
    irqdelay_wren_i_4
       (.I0(mm2s_dmacr[5]),
        .I1(scndry_vect_out[22]),
        .I2(mm2s_dmacr[6]),
        .I3(scndry_vect_out[23]),
        .O(irqdelay_wren_i_4_n_0));
  FDRE irqdelay_wren_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(irqdelay_wren0),
        .Q(mm2s_irqdelay_wren),
        .R(sinit));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    irqthresh_wren_i_2
       (.I0(irqthresh_wren_i_3_n_0),
        .I1(mm2s_dmacr[2]),
        .I2(scndry_vect_out[14]),
        .I3(\dmacr_i_reg[23]_0 [2]),
        .I4(scndry_vect_out[16]),
        .I5(irqthresh_wren_i_4_n_0),
        .O(\dmacr_i_reg[17]_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    irqthresh_wren_i_3
       (.I0(mm2s_dmacr[3]),
        .I1(scndry_vect_out[17]),
        .I2(\dmacr_i_reg[23]_0 [3]),
        .I3(scndry_vect_out[18]),
        .O(irqthresh_wren_i_3_n_0));
  LUT4 #(
    .INIT(16'h6FF6)) 
    irqthresh_wren_i_4
       (.I0(mm2s_dmacr[1]),
        .I1(scndry_vect_out[13]),
        .I2(\dmacr_i_reg[23]_0 [1]),
        .I3(scndry_vect_out[15]),
        .O(irqthresh_wren_i_4_n_0));
  FDRE irqthresh_wren_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(irqthresh_wren0),
        .Q(irqthresh_wren_reg_0),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT4 #(
    .INIT(16'h2202)) 
    mm2s_halted_set_i_1
       (.I0(mm2s_all_idle),
        .I1(\dmacr_i_reg[0]_0 ),
        .I2(mm2s_stop_i),
        .I3(mm2s_halt_cmplt),
        .O(mm2s_halted_set0));
  FDRE #(
    .INIT(1'b0)) 
    sg_decerr_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sg_decerr_reg_1),
        .Q(sg_decerr_reg_0),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    sg_ftch_error_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sg_ftch_error0),
        .Q(sg_ftch_error),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    sg_interr_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sg_interr_reg_1),
        .Q(sg_interr_reg_0),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    sg_slverr_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sg_slverr_reg_1),
        .Q(sg_slverr_reg_0),
        .R(sinit));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    sg_updt_error_i_1
       (.I0(dma_interr_reg_0),
        .I1(dma_slverr_reg_0),
        .I2(dma_decerr_reg_0),
        .I3(mm2s_updt_decerr_set),
        .I4(mm2s_updt_interr_set),
        .I5(mm2s_updt_slverr_set),
        .O(sg_updt_error0));
  FDRE #(
    .INIT(1'b0)) 
    sg_updt_error_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sg_updt_error0),
        .Q(sg_updt_error),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT2 #(
    .INIT(4'h2)) 
    soft_reset_re_i_1
       (.I0(\dmacr_i_reg[2]_0 ),
        .I1(soft_reset_d1),
        .O(soft_reset_re0));
endmodule

module Loopback_axi_dma_1_0_axi_dma_reset
   (out,
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ,
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ,
    \GEN_ASYNC_RESET.s_soft_reset_i_reg_0 ,
    mm2s_prmry_reset_out_n,
    mm2s_cntrl_reset_out_n,
    soft_reset_d1,
    soft_reset_re,
    mm2s_halt,
    sinit,
    \GEN_ASYNC_RESET.scndry_resetn_reg_0 ,
    m_axi_sg_rlast_0,
    \GEN_ASYNC_RESET.halt_i_reg_0 ,
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.min_assert_sftrst_reg_0 ,
    m_axi_sg_aclk,
    mm2s_all_idle,
    mm2s_halt_cmplt,
    m_axi_mm2s_aclk,
    soft_reset,
    soft_reset_re0,
    s_halt0,
    soft_reset_clr,
    m_axi_sg_rlast,
    m_axi_sg_rvalid,
    sig_rst2all_stop_request,
    scndry_out);
  output out;
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
  output \GEN_ASYNC_RESET.s_soft_reset_i_reg_0 ;
  output mm2s_prmry_reset_out_n;
  output mm2s_cntrl_reset_out_n;
  output soft_reset_d1;
  output soft_reset_re;
  output mm2s_halt;
  output sinit;
  output \GEN_ASYNC_RESET.scndry_resetn_reg_0 ;
  output [0:0]m_axi_sg_rlast_0;
  output \GEN_ASYNC_RESET.halt_i_reg_0 ;
  output \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.min_assert_sftrst_reg_0 ;
  input m_axi_sg_aclk;
  input mm2s_all_idle;
  input mm2s_halt_cmplt;
  input m_axi_mm2s_aclk;
  input soft_reset;
  input soft_reset_re0;
  input s_halt0;
  input soft_reset_clr;
  input m_axi_sg_rlast;
  input m_axi_sg_rvalid;
  input sig_rst2all_stop_request;
  input scndry_out;

  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
  wire \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.min_assert_sftrst_i_1_n_0 ;
  wire \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.min_assert_sftrst_reg_0 ;
  wire \GEN_ASYNC_RESET.REG_HALT_CMPLT_IN_n_0 ;
  wire \GEN_ASYNC_RESET.REG_RESET_OUT_n_0 ;
  wire \GEN_ASYNC_RESET.halt_i_reg_0 ;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire \GEN_ASYNC_RESET.s_soft_reset_i_reg_0 ;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg_0 ;
  wire assert_sftrst_d1;
  wire halt_cmplt_reg;
  wire m_axi_mm2s_aclk;
  wire m_axi_sg_aclk;
  wire m_axi_sg_rlast;
  wire [0:0]m_axi_sg_rlast_0;
  wire m_axi_sg_rvalid;
  wire min_assert_sftrst;
  wire mm2s_all_idle;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire mm2s_cntrl_reset_out_n;
  wire mm2s_halt;
  wire mm2s_halt_cmplt;
  wire n_0_957;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire out;
  wire p_halt;
  wire s_halt;
  wire s_halt0;
  wire s_soft_reset_i;
  wire s_soft_reset_i_d1;
  wire s_soft_reset_i_re;
  wire scndry_out;
  wire scndry_resetn_i;
  wire sft_rst_dly1;
  wire sft_rst_dly10;
  wire sft_rst_dly11;
  wire sft_rst_dly12;
  wire sft_rst_dly13;
  wire sft_rst_dly14;
  wire sft_rst_dly15;
  wire sft_rst_dly16;
  wire sft_rst_dly2;
  wire sft_rst_dly3;
  wire sft_rst_dly4;
  wire sft_rst_dly5;
  wire sft_rst_dly6;
  wire sft_rst_dly7;
  wire sft_rst_dly8;
  wire sft_rst_dly9;
  wire sig_rst2all_stop_request;
  wire sinit;
  wire soft_reset;
  wire soft_reset_clr;
  wire soft_reset_d1;
  wire soft_reset_re;
  wire soft_reset_re0;

  assign mm2s_prmry_reset_out_n = mm2s_cntrl_reset_out_n;
  Loopback_axi_dma_1_0_cdc_sync_1 \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.HALT_PROCESS 
       (.m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .prmry_in(s_halt),
        .scndry_out(p_halt));
  LUT4 #(
    .INIT(16'h4F44)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.min_assert_sftrst_i_1 
       (.I0(sft_rst_dly16),
        .I1(min_assert_sftrst),
        .I2(s_soft_reset_i_d1),
        .I3(s_soft_reset_i),
        .O(\GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.min_assert_sftrst_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.min_assert_sftrst_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.min_assert_sftrst_i_1_n_0 ),
        .Q(min_assert_sftrst),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.s_halt_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_halt0),
        .Q(s_halt),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly10_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly9),
        .Q(sft_rst_dly10),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly11_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly10),
        .Q(sft_rst_dly11),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly12_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly11),
        .Q(sft_rst_dly12),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly13_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly12),
        .Q(sft_rst_dly13),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly14_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly13),
        .Q(sft_rst_dly14),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly15_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly14),
        .Q(sft_rst_dly15),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly16_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly15),
        .Q(sft_rst_dly16),
        .R(s_soft_reset_i_re));
  LUT2 #(
    .INIT(4'h2)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly1_i_1 
       (.I0(s_soft_reset_i),
        .I1(s_soft_reset_i_d1),
        .O(s_soft_reset_i_re));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly1_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(1'b0),
        .Q(sft_rst_dly1),
        .S(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly2_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly1),
        .Q(sft_rst_dly2),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly3_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly2),
        .Q(sft_rst_dly3),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly4_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly3),
        .Q(sft_rst_dly4),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly5_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly4),
        .Q(sft_rst_dly5),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly6_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly5),
        .Q(sft_rst_dly6),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly7_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly6),
        .Q(sft_rst_dly7),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly8_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly7),
        .Q(sft_rst_dly8),
        .R(s_soft_reset_i_re));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly9_reg 
       (.C(m_axi_sg_aclk),
        .CE(mm2s_all_idle),
        .D(sft_rst_dly8),
        .Q(sft_rst_dly9),
        .R(s_soft_reset_i_re));
  Loopback_axi_dma_1_0_cdc_sync_2 \GEN_ASYNC_RESET.REG_HALT_CMPLT_IN 
       (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (\GEN_ASYNC_RESET.REG_HALT_CMPLT_IN_n_0 ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .mm2s_all_idle(mm2s_all_idle),
        .prmry_in(halt_cmplt_reg),
        .s_soft_reset_i(s_soft_reset_i),
        .soft_reset(soft_reset),
        .soft_reset_clr(soft_reset_clr));
  Loopback_axi_dma_1_0_cdc_sync_3 \GEN_ASYNC_RESET.REG_RESET_OUT 
       (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (\GEN_ASYNC_RESET.REG_RESET_OUT_n_0 ),
        .\GEN_ASYNC_RESET.halt_i_reg (p_halt),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .mm2s_halt(mm2s_halt),
        .prmry_in(scndry_resetn_i),
        .scndry_out(mm2s_cntrl_reset_out_n));
  FDRE \GEN_ASYNC_RESET.halt_cmplt_reg_reg 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(mm2s_halt_cmplt),
        .Q(halt_cmplt_reg),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.halt_i_reg 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_RESET.REG_RESET_OUT_n_0 ),
        .Q(mm2s_halt),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_ASYNC_RESET.s_soft_reset_i_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_RESET.REG_HALT_CMPLT_IN_n_0 ),
        .Q(s_soft_reset_i),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \GEN_ASYNC_RESET.scndry_resetn_i_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_RESET.s_soft_reset_i_reg_0 ),
        .Q(scndry_resetn_i),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \GEN_ASYNC_RESET.scndry_resetn_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_ASYNC_RESET.s_soft_reset_i_reg_0 ),
        .Q(out),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/sig_s_h_halt_reg_i_1 
       (.I0(mm2s_halt),
        .I1(sig_rst2all_stop_request),
        .O(\GEN_ASYNC_RESET.halt_i_reg_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \GEN_RESET_FOR_MM2S.mm2s_soft_reset_done_i_1 
       (.I0(min_assert_sftrst),
        .I1(assert_sftrst_d1),
        .I2(scndry_out),
        .I3(soft_reset_clr),
        .O(\GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.min_assert_sftrst_reg_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s[31]_i_1 
       (.I0(out),
        .O(sinit));
  FDRE #(
    .INIT(1'b0)) 
    assert_sftrst_d1_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(min_assert_sftrst),
        .Q(assert_sftrst_d1),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h8F)) 
    \counter[7]_i_1 
       (.I0(m_axi_sg_rlast),
        .I1(m_axi_sg_rvalid),
        .I2(out),
        .O(m_axi_sg_rlast_0));
  LUT1 #(
    .INIT(2'h2)) 
    dm_prmry_resetn_inst
       (.I0(mm2s_cntrl_reset_out_n),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \dmacr_i[0]_i_2 
       (.I0(out),
        .I1(soft_reset),
        .O(\GEN_ASYNC_RESET.scndry_resetn_reg_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    i_957
       (.I0(out),
        .O(n_0_957));
  LUT1 #(
    .INIT(2'h2)) 
    prmry_resetn_inst
       (.I0(mm2s_cntrl_reset_out_n),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ));
  LUT3 #(
    .INIT(8'h04)) 
    resetn_i
       (.I0(s_soft_reset_i),
        .I1(scndry_out),
        .I2(min_assert_sftrst),
        .O(\GEN_ASYNC_RESET.s_soft_reset_i_reg_0 ));
  FDRE #(
    .INIT(1'b0)) 
    s_soft_reset_i_d1_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_soft_reset_i),
        .Q(s_soft_reset_i_d1),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    soft_reset_d1_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(soft_reset),
        .Q(soft_reset_d1),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    soft_reset_re_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(soft_reset_re0),
        .Q(soft_reset_re),
        .R(1'b0));
endmodule

module Loopback_axi_dma_1_0_axi_dma_rst_module
   (out,
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ,
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ,
    \GEN_ASYNC_RESET.s_soft_reset_i_reg ,
    mm2s_prmry_reset_out_n,
    mm2s_cntrl_reset_out_n,
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 ,
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_2 ,
    soft_reset_d1,
    soft_reset_re,
    soft_reset_clr,
    mm2s_halt,
    sinit,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    m_axi_sg_rlast_0,
    \GEN_ASYNC_WRITE.rdy_to2 ,
    p_0_in,
    SR,
    \GEN_ASYNC_RESET.halt_i_reg ,
    m_axi_sg_aclk,
    mm2s_all_idle,
    mm2s_halt_cmplt,
    m_axi_mm2s_aclk,
    soft_reset,
    soft_reset_re0,
    s_halt0,
    m_axi_sg_rlast,
    m_axi_sg_rvalid,
    scndry_out,
    sig_rst2all_stop_request,
    axi_resetn,
    s_axi_lite_aclk);
  output out;
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
  output \GEN_ASYNC_RESET.s_soft_reset_i_reg ;
  output mm2s_prmry_reset_out_n;
  output mm2s_cntrl_reset_out_n;
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 ;
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_2 ;
  output soft_reset_d1;
  output soft_reset_re;
  output soft_reset_clr;
  output mm2s_halt;
  output sinit;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  output [0:0]m_axi_sg_rlast_0;
  output \GEN_ASYNC_WRITE.rdy_to2 ;
  output p_0_in;
  output [0:0]SR;
  output \GEN_ASYNC_RESET.halt_i_reg ;
  input m_axi_sg_aclk;
  input mm2s_all_idle;
  input mm2s_halt_cmplt;
  input m_axi_mm2s_aclk;
  input soft_reset;
  input soft_reset_re0;
  input s_halt0;
  input m_axi_sg_rlast;
  input m_axi_sg_rvalid;
  input scndry_out;
  input sig_rst2all_stop_request;
  input axi_resetn;
  input s_axi_lite_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 ;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_2 ;
  wire \GEN_ASYNC_RESET.halt_i_reg ;
  wire \GEN_ASYNC_RESET.s_soft_reset_i_reg ;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \GEN_ASYNC_WRITE.rdy_to2 ;
  wire \GEN_RESET_FOR_MM2S.RESET_I_n_13 ;
  wire [0:0]SR;
  wire axi_resetn;
  wire m_axi_mm2s_aclk;
  wire m_axi_sg_aclk;
  wire m_axi_sg_rlast;
  wire [0:0]m_axi_sg_rlast_0;
  wire m_axi_sg_rvalid;
  wire mm2s_all_idle;
  wire mm2s_cntrl_reset_out_n;
  wire mm2s_halt;
  wire mm2s_halt_cmplt;
  wire mm2s_prmry_reset_out_n;
  wire out;
  wire p_0_in;
  wire s_axi_lite_aclk;
  wire s_halt0;
  wire scndry_out;
  wire sig_rst2all_stop_request;
  wire sinit;
  wire soft_reset;
  wire soft_reset_clr;
  wire soft_reset_d1;
  wire soft_reset_re;
  wire soft_reset_re0;

  LUT1 #(
    .INIT(2'h1)) 
    \GEN_ASYNC_WRITE.awvalid_to2_i_1 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 ),
        .O(SR));
  LUT2 #(
    .INIT(4'h8)) 
    \GEN_ASYNC_WRITE.rdy_to2_i_1 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_2 ),
        .I1(scndry_out),
        .O(\GEN_ASYNC_WRITE.rdy_to2 ));
  Loopback_axi_dma_1_0_axi_dma_reset \GEN_RESET_FOR_MM2S.RESET_I 
       (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ),
        .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ),
        .\GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.min_assert_sftrst_reg_0 (\GEN_RESET_FOR_MM2S.RESET_I_n_13 ),
        .\GEN_ASYNC_RESET.halt_i_reg_0 (\GEN_ASYNC_RESET.halt_i_reg ),
        .\GEN_ASYNC_RESET.s_soft_reset_i_reg_0 (\GEN_ASYNC_RESET.s_soft_reset_i_reg ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg_0 (\GEN_ASYNC_RESET.scndry_resetn_reg ),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_rlast(m_axi_sg_rlast),
        .m_axi_sg_rlast_0(m_axi_sg_rlast_0),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .mm2s_all_idle(mm2s_all_idle),
        .mm2s_cntrl_reset_out_n(mm2s_cntrl_reset_out_n),
        .mm2s_halt(mm2s_halt),
        .mm2s_halt_cmplt(mm2s_halt_cmplt),
        .mm2s_prmry_reset_out_n(mm2s_prmry_reset_out_n),
        .out(out),
        .s_halt0(s_halt0),
        .scndry_out(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 ),
        .sig_rst2all_stop_request(sig_rst2all_stop_request),
        .sinit(sinit),
        .soft_reset(soft_reset),
        .soft_reset_clr(soft_reset_clr),
        .soft_reset_d1(soft_reset_d1),
        .soft_reset_re(soft_reset_re),
        .soft_reset_re0(soft_reset_re0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_RESET_FOR_MM2S.mm2s_soft_reset_done_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_RESET_FOR_MM2S.RESET_I_n_13 ),
        .Q(soft_reset_clr),
        .R(1'b0));
  Loopback_axi_dma_1_0_cdc_sync REG_HRD_RST
       (.axi_resetn(axi_resetn),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .scndry_out(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1 ));
  Loopback_axi_dma_1_0_cdc_sync_0 REG_HRD_RST_OUT
       (.axi_resetn(axi_resetn),
        .s_axi_lite_aclk(s_axi_lite_aclk),
        .scndry_out(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    arready_i_i_1
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_2 ),
        .O(p_0_in));
endmodule

module Loopback_axi_dma_1_0_axi_dma_sofeof_gen
   (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ,
    axi_dma_tstvec,
    sinit,
    m_axi_sg_aclk,
    m_axis_mm2s_tvalid,
    m_axis_mm2s_tready,
    m_axis_mm2s_tlast,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg_0 ,
    ch1_delay_cnt_en,
    out);
  output \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ;
  output [1:0]axi_dma_tstvec;
  input sinit;
  input m_axi_sg_aclk;
  input m_axis_mm2s_tvalid;
  input m_axis_mm2s_tready;
  input m_axis_mm2s_tlast;
  input \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg_0 ;
  input ch1_delay_cnt_en;
  input out;

  wire \GEN_FOR_SYNC.s_sof_generated_i_1_n_0 ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg_0 ;
  wire [1:0]axi_dma_tstvec;
  wire ch1_delay_cnt_en;
  wire m_axi_sg_aclk;
  wire m_axis_mm2s_tlast;
  wire m_axis_mm2s_tready;
  wire m_axis_mm2s_tvalid;
  wire out;
  wire p_3_in;
  wire s_last;
  wire s_last_d1;
  wire s_last_d10;
  wire s_ready;
  wire s_sof_d1_cdc_tig;
  wire s_sof_generated;
  wire s_valid;
  wire s_valid_d1;
  wire sinit;

  LUT3 #(
    .INIT(8'h80)) 
    \GEN_FOR_SYNC.s_last_d1_i_1 
       (.I0(s_last),
        .I1(s_ready),
        .I2(s_valid),
        .O(s_last_d10));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_FOR_SYNC.s_last_d1_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_last_d10),
        .Q(s_last_d1),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_FOR_SYNC.s_last_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(m_axis_mm2s_tlast),
        .Q(s_last),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_FOR_SYNC.s_ready_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(m_axis_mm2s_tready),
        .Q(s_ready),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_FOR_SYNC.s_sof_d1_cdc_tig_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_sof_generated),
        .Q(s_sof_d1_cdc_tig),
        .R(sinit));
  LUT6 #(
    .INIT(64'h00000000FFA20000)) 
    \GEN_FOR_SYNC.s_sof_generated_i_1 
       (.I0(p_3_in),
        .I1(s_valid_d1),
        .I2(s_sof_d1_cdc_tig),
        .I3(s_sof_generated),
        .I4(out),
        .I5(axi_dma_tstvec[1]),
        .O(\GEN_FOR_SYNC.s_sof_generated_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_FOR_SYNC.s_sof_generated_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_FOR_SYNC.s_sof_generated_i_1_n_0 ),
        .Q(s_sof_generated),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \GEN_FOR_SYNC.s_valid_d1_i_1 
       (.I0(s_valid),
        .I1(s_ready),
        .O(p_3_in));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_FOR_SYNC.s_valid_d1_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(p_3_in),
        .Q(s_valid_d1),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_FOR_SYNC.s_valid_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(m_axis_mm2s_tvalid),
        .Q(s_valid),
        .R(sinit));
  LUT4 #(
    .INIT(16'h4544)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg_0 ),
        .I1(axi_dma_tstvec[1]),
        .I2(axi_dma_tstvec[0]),
        .I3(ch1_delay_cnt_en),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT5 #(
    .INIT(32'h00008808)) 
    \axi_dma_tstvec[0]_INST_0 
       (.I0(s_ready),
        .I1(s_valid),
        .I2(s_valid_d1),
        .I3(s_sof_d1_cdc_tig),
        .I4(s_sof_generated),
        .O(axi_dma_tstvec[0]));
  LUT6 #(
    .INIT(64'h2F00000000000000)) 
    \axi_dma_tstvec[1]_INST_0 
       (.I0(s_sof_d1_cdc_tig),
        .I1(s_sof_generated),
        .I2(s_last_d1),
        .I3(s_last),
        .I4(s_ready),
        .I5(s_valid),
        .O(axi_dma_tstvec[1]));
endmodule

module Loopback_axi_dma_1_0_axi_sg
   (ch1_ftch_queue_empty,
    ch1_nxtdesc_wren,
    \GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg ,
    ptr_queue_full,
    sts_queue_full,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ,
    mm2s_dly_irq_set,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg,
    m_axi_sg_arburst,
    m_axi_sg_arvalid,
    m_axi_sg_rready,
    m_axi_sg_awlen,
    m_axi_sg_awsize,
    m_axi_sg_awvalid,
    m_axi_sg_awaddr,
    m_axi_sg_arlen,
    CO,
    mm2s_ftch_idle,
    ch1_sg_idle,
    m_axis_mm2s_ftch_tvalid_new,
    mm2s_updt_idle,
    ch1_delay_cnt_en,
    mm2s_ioc_irq_set,
    SR,
    \GEN_CH1_FETCH.ch1_active_i_reg ,
    m_axis_mm2s_cntrl_tlast,
    m_axis_mm2s_cntrl_tvalid,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    Q,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2] ,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ,
    m_axi_sg_bready,
    m_axi_sg_wvalid,
    m_axi_sg_wlast,
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] ,
    sg_ftch_error0,
    mm2s_updt_slverr_set,
    mm2s_updt_interr_set,
    mm2s_updt_decerr_set,
    \GEN_ASYNC_RESET.scndry_resetn_reg_0 ,
    \GEN_MM2S.queue_dout_new_reg[90] ,
    m_axi_sg_wdata,
    \GEN_MM2S.queue_dout_new_reg[64] ,
    \GEN_CH1_UPDATE.ch1_dma_interr_set_reg ,
    \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg ,
    \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg ,
    \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg ,
    \GEN_CH1_FETCH.ch1_ftch_slverr_set_reg ,
    \GEN_CH1_FETCH.ch1_ftch_decerr_set_reg ,
    \ftch_error_addr_reg[31]_0 ,
    m_axis_mm2s_cntrl_tdata,
    m_axi_sg_araddr,
    rst,
    m_axi_sg_aclk,
    m_axi_sg_rlast,
    sinit,
    mm2s_dmacr,
    out,
    m_axi_sg_rresp,
    m_axi_sg_rvalid,
    mm2s_cntrl_strm_stop,
    queue_empty_new0,
    E,
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32] ,
    ch1_dly_fast_cnt0,
    ch1_delay_count0,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0,
    S,
    \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg ,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ,
    soft_reset,
    \GEN_MM2S.queue_dout_new_reg[90]_0 ,
    \GEN_MM2S.reg1_reg[90] ,
    m_axis_mm2s_cntrl_tready,
    soft_reset_d1,
    soft_reset_d2,
    \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ,
    mm2s_stop_i,
    dma_mm2s_error,
    m_axi_sg_rdata,
    s_axis_mm2s_updtptr_tlast,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ,
    \GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg ,
    mm2s_irqthresh_wren,
    m_axi_sg_bvalid,
    m_axi_sg_wready,
    \ch1_sg_idle1_inferred__0/i__carry ,
    packet_in_progress,
    m_axi_sg_arready,
    m_axi_sg_awready,
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 ,
    s_axis_mm2s_cmd_tready,
    s_axis_mm2s_cmd_tvalid_split,
    dma_interr_reg,
    dma_slverr_reg,
    dma_decerr_reg,
    sg_interr_reg,
    sg_slverr_reg,
    sg_decerr_reg,
    m_axi_sg_bresp,
    \counter_reg[1] ,
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31] ,
    D,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] );
  output ch1_ftch_queue_empty;
  output ch1_nxtdesc_wren;
  output \GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg ;
  output ptr_queue_full;
  output sts_queue_full;
  output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ;
  output mm2s_dly_irq_set;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  output [0:0]m_axi_sg_arburst;
  output m_axi_sg_arvalid;
  output m_axi_sg_rready;
  output [0:0]m_axi_sg_awlen;
  output [0:0]m_axi_sg_awsize;
  output m_axi_sg_awvalid;
  output [27:0]m_axi_sg_awaddr;
  output [2:0]m_axi_sg_arlen;
  output [0:0]CO;
  output mm2s_ftch_idle;
  output ch1_sg_idle;
  output m_axis_mm2s_ftch_tvalid_new;
  output mm2s_updt_idle;
  output ch1_delay_cnt_en;
  output mm2s_ioc_irq_set;
  output [0:0]SR;
  output \GEN_CH1_FETCH.ch1_active_i_reg ;
  output m_axis_mm2s_cntrl_tlast;
  output m_axis_mm2s_cntrl_tvalid;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  output [7:0]Q;
  output \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2] ;
  output \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ;
  output m_axi_sg_bready;
  output m_axi_sg_wvalid;
  output m_axi_sg_wlast;
  output [19:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ;
  output [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] ;
  output sg_ftch_error0;
  output mm2s_updt_slverr_set;
  output mm2s_updt_interr_set;
  output mm2s_updt_decerr_set;
  output \GEN_ASYNC_RESET.scndry_resetn_reg_0 ;
  output [85:0]\GEN_MM2S.queue_dout_new_reg[90] ;
  output [29:0]m_axi_sg_wdata;
  output \GEN_MM2S.queue_dout_new_reg[64] ;
  output \GEN_CH1_UPDATE.ch1_dma_interr_set_reg ;
  output \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg ;
  output \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg ;
  output \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg ;
  output \GEN_CH1_FETCH.ch1_ftch_slverr_set_reg ;
  output \GEN_CH1_FETCH.ch1_ftch_decerr_set_reg ;
  output [25:0]\ftch_error_addr_reg[31]_0 ;
  output [31:0]m_axis_mm2s_cntrl_tdata;
  output [25:0]m_axi_sg_araddr;
  input rst;
  input m_axi_sg_aclk;
  input m_axi_sg_rlast;
  input sinit;
  input [6:0]mm2s_dmacr;
  input out;
  input [1:0]m_axi_sg_rresp;
  input m_axi_sg_rvalid;
  input mm2s_cntrl_strm_stop;
  input queue_empty_new0;
  input [0:0]E;
  input [0:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32] ;
  input ch1_dly_fast_cnt0;
  input ch1_delay_count0;
  input sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  input [6:0]S;
  input \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg ;
  input \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ;
  input soft_reset;
  input [0:0]\GEN_MM2S.queue_dout_new_reg[90]_0 ;
  input [0:0]\GEN_MM2S.reg1_reg[90] ;
  input m_axis_mm2s_cntrl_tready;
  input soft_reset_d1;
  input soft_reset_d2;
  input \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ;
  input mm2s_stop_i;
  input dma_mm2s_error;
  input [31:0]m_axi_sg_rdata;
  input s_axis_mm2s_updtptr_tlast;
  input \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ;
  input [0:0]\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg ;
  input mm2s_irqthresh_wren;
  input m_axi_sg_bvalid;
  input m_axi_sg_wready;
  input [5:0]\ch1_sg_idle1_inferred__0/i__carry ;
  input packet_in_progress;
  input m_axi_sg_arready;
  input m_axi_sg_awready;
  input [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 ;
  input s_axis_mm2s_cmd_tready;
  input s_axis_mm2s_cmd_tvalid_split;
  input dma_interr_reg;
  input dma_slverr_reg;
  input dma_decerr_reg;
  input sg_interr_reg;
  input sg_slverr_reg;
  input sg_decerr_reg;
  input [1:0]m_axi_sg_bresp;
  input [0:0]\counter_reg[1] ;
  input [25:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31] ;
  input [30:0]D;
  input [2:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ;
  input [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ;

  wire [0:0]CO;
  wire [30:0]D;
  wire [0:0]E;
  wire \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg_0 ;
  wire \GEN_CH1_FETCH.ch1_active_i_reg ;
  wire \GEN_CH1_FETCH.ch1_ftch_decerr_set_reg ;
  wire \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg ;
  wire \GEN_CH1_FETCH.ch1_ftch_slverr_set_reg ;
  wire \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg ;
  wire \GEN_CH1_UPDATE.ch1_dma_interr_set_reg ;
  wire \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg ;
  wire \GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_5 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_10 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_11 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_12 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_13 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_14 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_15 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_16 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_17 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_18 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_19 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_20 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_21 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_22 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_23 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_24 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_25 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_26 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_27 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_28 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_29 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_30 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_31 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_32 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_33 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_34 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_35 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_36 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_37 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_38 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_39 ;
  wire \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_40 ;
  wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ;
  wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ;
  wire [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] ;
  wire [0:0]\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2] ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ;
  wire [2:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ;
  wire \GEN_MM2S.queue_dout_new_reg[64] ;
  wire [85:0]\GEN_MM2S.queue_dout_new_reg[90] ;
  wire [0:0]\GEN_MM2S.queue_dout_new_reg[90]_0 ;
  wire [0:0]\GEN_MM2S.reg1_reg[90] ;
  wire [19:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ;
  wire [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 ;
  wire \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg ;
  wire \GEN_QUEUE.FTCH_QUEUE_I/current_bd0 ;
  wire \GEN_QUEUE.I_UPDT_DESC_QUEUE/follower_empty_mm2s ;
  wire \GEN_QUEUE.I_UPDT_DESC_QUEUE/follower_full_mm2s ;
  wire \GEN_QUEUE.I_UPDT_DESC_QUEUE/follower_full_mm2s0 ;
  wire \GEN_QUEUE.I_UPDT_DESC_QUEUE/ptr_queue_empty ;
  wire [25:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31] ;
  wire [0:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32] ;
  wire \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ;
  wire \I_FTCH_CMDSTS_IF/ftch_decerr_i ;
  wire \I_FTCH_CMDSTS_IF/ftch_slverr_i ;
  wire \I_FTCH_PNTR_MNGR/ch1_use_crntdesc ;
  wire I_SG_AXI_DATAMOVER_n_40;
  wire I_SG_AXI_DATAMOVER_n_48;
  wire I_SG_AXI_DATAMOVER_n_51;
  wire I_SG_FETCH_MNGR_n_37;
  wire I_SG_FETCH_MNGR_n_38;
  wire I_SG_FETCH_MNGR_n_66;
  wire I_SG_FETCH_MNGR_n_67;
  wire I_SG_FETCH_MNGR_n_68;
  wire I_SG_FETCH_MNGR_n_69;
  wire I_SG_FETCH_MNGR_n_70;
  wire I_SG_FETCH_MNGR_n_71;
  wire I_SG_FETCH_MNGR_n_72;
  wire I_SG_FETCH_MNGR_n_73;
  wire I_SG_FETCH_MNGR_n_74;
  wire I_SG_FETCH_MNGR_n_75;
  wire I_SG_FETCH_MNGR_n_76;
  wire I_SG_FETCH_MNGR_n_77;
  wire I_SG_FETCH_MNGR_n_78;
  wire I_SG_FETCH_MNGR_n_79;
  wire I_SG_FETCH_MNGR_n_80;
  wire I_SG_FETCH_MNGR_n_81;
  wire I_SG_FETCH_MNGR_n_82;
  wire I_SG_FETCH_MNGR_n_83;
  wire I_SG_FETCH_MNGR_n_84;
  wire I_SG_FETCH_MNGR_n_85;
  wire I_SG_FETCH_MNGR_n_86;
  wire I_SG_FETCH_MNGR_n_87;
  wire I_SG_FETCH_MNGR_n_88;
  wire I_SG_FETCH_MNGR_n_89;
  wire I_SG_FETCH_MNGR_n_90;
  wire I_SG_FETCH_MNGR_n_91;
  wire I_SG_FETCH_MNGR_n_93;
  wire I_SG_FETCH_QUEUE_n_8;
  wire I_SG_FETCH_QUEUE_n_9;
  wire \I_UPDT_CMDSTS_IF/updt_decerr_i ;
  wire \I_UPDT_CMDSTS_IF/updt_interr_i ;
  wire \I_UPDT_CMDSTS_IF/updt_slverr_i ;
  wire [31:4]\I_UPDT_SG/update_address ;
  wire [31:6]L;
  wire [7:0]Q;
  wire [6:0]S;
  wire [0:0]SR;
  wire \USE_SINGLE_REG.sig_data_in0 ;
  wire ch1_delay_cnt_en;
  wire ch1_delay_count0;
  wire ch1_dly_fast_cnt0;
  wire ch1_dma_decerr;
  wire ch1_dma_interr;
  wire ch1_dma_slverr;
  wire [11:6]ch1_fetch_address_i;
  wire ch1_ftch_pause;
  wire ch1_ftch_queue_empty;
  wire ch1_nxtdesc_wren;
  wire ch1_sg_idle;
  wire [5:0]\ch1_sg_idle1_inferred__0/i__carry ;
  wire ch1_updt_active;
  wire ch1_updt_curdesc_wren;
  wire ch1_updt_ioc;
  wire [0:0]\counter_reg[1] ;
  wire dma_decerr_reg;
  wire dma_interr_reg;
  wire dma_mm2s_error;
  wire dma_slverr_reg;
  wire [63:2]ftch_cmnd_data;
  wire ftch_error;
  wire [25:0]\ftch_error_addr_reg[31]_0 ;
  wire ftch_stale_desc;
  wire m_axi_sg_aclk;
  wire [25:0]m_axi_sg_araddr;
  wire [0:0]m_axi_sg_arburst;
  wire [2:0]m_axi_sg_arlen;
  wire m_axi_sg_arready;
  wire m_axi_sg_arvalid;
  wire [27:0]m_axi_sg_awaddr;
  wire [0:0]m_axi_sg_awlen;
  wire m_axi_sg_awready;
  wire [0:0]m_axi_sg_awsize;
  wire m_axi_sg_awvalid;
  wire m_axi_sg_bready;
  wire [1:0]m_axi_sg_bresp;
  wire m_axi_sg_bvalid;
  wire [31:0]m_axi_sg_rdata;
  wire m_axi_sg_rlast;
  wire m_axi_sg_rready;
  wire [1:0]m_axi_sg_rresp;
  wire m_axi_sg_rvalid;
  wire [29:0]m_axi_sg_wdata;
  wire m_axi_sg_wlast;
  wire m_axi_sg_wready;
  wire m_axi_sg_wvalid;
  wire [31:0]m_axis_mm2s_cntrl_tdata;
  wire m_axis_mm2s_cntrl_tlast;
  wire m_axis_mm2s_cntrl_tready;
  wire m_axis_mm2s_cntrl_tvalid;
  wire m_axis_mm2s_ftch_tvalid_new;
  wire m_axis_updt_sts_tready;
  wire mm2s_cntrl_strm_stop;
  wire mm2s_dly_irq_set;
  wire mm2s_dma_decerr_set;
  wire mm2s_dma_interr_set;
  wire mm2s_dma_slverr_set;
  wire [6:0]mm2s_dmacr;
  wire mm2s_ftch_idle;
  wire mm2s_ioc_irq_set;
  wire mm2s_irqthresh_wren;
  wire mm2s_stop_i;
  wire mm2s_updt_decerr_set;
  wire mm2s_updt_idle;
  wire mm2s_updt_interr_set;
  wire mm2s_updt_slverr_set;
  wire out;
  wire p_0_in9_in;
  wire [31:6]p_2_in;
  wire packet_in_progress;
  wire ptr_queue_full;
  wire queue_empty_new0;
  wire rst;
  wire s_axis_ftch_cmd_tready;
  wire s_axis_ftch_cmd_tvalid;
  wire s_axis_mm2s_cmd_tready;
  wire s_axis_mm2s_cmd_tvalid_split;
  wire s_axis_mm2s_updtptr_tlast;
  wire s_axis_updt_cmd_tready;
  wire s_axis_updt_cmd_tvalid;
  wire sg_decerr_reg;
  wire sg_ftch_error0;
  wire sg_interr_reg;
  wire sg_slverr_reg;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  wire sinit;
  wire soft_reset;
  wire soft_reset_d1;
  wire soft_reset_d2;
  wire sts_queue_full;
  wire updt_error;
  wire [31:6]updt_error_addr_1;

  Loopback_axi_dma_1_0_axi_sg_updt_mngr \GEN_DESC_UPDATE.I_SG_UPDATE_MNGR 
       (.D({\I_UPDT_SG/update_address [31:6],\I_UPDT_SG/update_address [4],\USE_SINGLE_REG.sig_data_in0 }),
        .E(ch1_updt_curdesc_wren),
        .\GEN_CH1_UPDATE.ch1_dma_decerr_set_reg (\GEN_CH1_UPDATE.ch1_dma_decerr_set_reg ),
        .\GEN_CH1_UPDATE.ch1_dma_interr_set_reg (\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_0 (\GEN_CH1_UPDATE.ch1_dma_interr_set_reg ),
        .\GEN_CH1_UPDATE.ch1_dma_slverr_set_reg (\GEN_CH1_UPDATE.ch1_dma_slverr_set_reg ),
        .\GEN_CH1_UPDATE.ch1_updt_decerr_set_reg (mm2s_updt_decerr_set),
        .\GEN_CH1_UPDATE.ch1_updt_idle_reg (\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_40 ),
        .\GEN_CH1_UPDATE.ch1_updt_interr_set_reg (mm2s_updt_interr_set),
        .\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg (\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg ),
        .\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_0 (\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_5 ),
        .\GEN_CH1_UPDATE.ch1_updt_slverr_set_reg (mm2s_updt_slverr_set),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] (\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg ),
        .Q({\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_10 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_11 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_12 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_13 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_14 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_15 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_16 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_17 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_18 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_19 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_20 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_21 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_22 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_23 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_24 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_25 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_26 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_27 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_28 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_29 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_30 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_31 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_32 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_33 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_34 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_35 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_36 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_37 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_38 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_39 }),
        .ch1_dma_decerr(ch1_dma_decerr),
        .ch1_dma_interr(ch1_dma_interr),
        .ch1_dma_slverr(ch1_dma_slverr),
        .ch1_updt_active(ch1_updt_active),
        .ch1_updt_ioc(ch1_updt_ioc),
        .dma_decerr_reg(dma_decerr_reg),
        .dma_interr_reg(dma_interr_reg),
        .dma_slverr_reg(dma_slverr_reg),
        .follower_empty_mm2s(\GEN_QUEUE.I_UPDT_DESC_QUEUE/follower_empty_mm2s ),
        .ftch_error(ftch_error),
        .\ftch_error_addr_reg[8] (I_SG_FETCH_MNGR_n_93),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_wdata(m_axi_sg_wdata),
        .mm2s_dly_irq_set(mm2s_dly_irq_set),
        .mm2s_dma_decerr_set(mm2s_dma_decerr_set),
        .mm2s_dma_interr_set(mm2s_dma_interr_set),
        .mm2s_dma_slverr_set(mm2s_dma_slverr_set),
        .mm2s_irqthresh_wren(mm2s_irqthresh_wren),
        .mm2s_updt_idle(mm2s_updt_idle),
        .out(out),
        .ptr_queue_empty(\GEN_QUEUE.I_UPDT_DESC_QUEUE/ptr_queue_empty ),
        .s_axis_updt_cmd_tready(s_axis_updt_cmd_tready),
        .s_axis_updt_cmd_tvalid(s_axis_updt_cmd_tvalid),
        .sinit(sinit),
        .\update_address_reg[31] (L),
        .updt_decerr_i(\I_UPDT_CMDSTS_IF/updt_decerr_i ),
        .updt_done_reg(I_SG_AXI_DATAMOVER_n_51),
        .updt_error(updt_error),
        .\updt_error_addr_reg[31] (updt_error_addr_1),
        .updt_interr_i(\I_UPDT_CMDSTS_IF/updt_interr_i ),
        .updt_slverr_i(\I_UPDT_CMDSTS_IF/updt_slverr_i ));
  Loopback_axi_dma_1_0_axi_sg_updt_q_mngr \GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE 
       (.D(D),
        .E(E),
        .\FSM_sequential_pntr_cs_reg[1] (I_SG_AXI_DATAMOVER_n_48),
        .\GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg (\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_40 ),
        .\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31] (\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31] ),
        .\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32] (\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32] ),
        .Q({\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_10 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_11 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_12 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_13 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_14 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_15 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_16 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_17 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_18 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_19 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_20 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_21 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_22 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_23 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_24 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_25 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_26 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_27 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_28 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_29 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_30 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_31 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_32 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_33 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_34 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_35 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_36 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_37 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_38 ,\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_39 }),
        .ch1_dma_decerr(ch1_dma_decerr),
        .ch1_dma_interr(ch1_dma_interr),
        .ch1_dma_slverr(ch1_dma_slverr),
        .ch1_updt_active(ch1_updt_active),
        .ch1_updt_ioc(ch1_updt_ioc),
        .follower_empty_mm2s(\GEN_QUEUE.I_UPDT_DESC_QUEUE/follower_empty_mm2s ),
        .follower_full_mm2s(\GEN_QUEUE.I_UPDT_DESC_QUEUE/follower_full_mm2s ),
        .follower_full_mm2s0(\GEN_QUEUE.I_UPDT_DESC_QUEUE/follower_full_mm2s0 ),
        .ftch_error(ftch_error),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .mm2s_dma_decerr_set(mm2s_dma_decerr_set),
        .mm2s_dma_interr_set(mm2s_dma_interr_set),
        .mm2s_dma_slverr_set(mm2s_dma_slverr_set),
        .out(out),
        .ptr_queue_empty(\GEN_QUEUE.I_UPDT_DESC_QUEUE/ptr_queue_empty ),
        .ptr_queue_full(ptr_queue_full),
        .sinit(sinit),
        .sts_queue_full(sts_queue_full),
        .\updt_curdesc_reg[31] (L),
        .updt_curdesc_wren_reg(ch1_updt_curdesc_wren),
        .updt_ioc_reg(\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg ));
  Loopback_axi_dma_1_0_axi_sg_intrpt \GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT 
       (.E(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg ),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg_0 (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ),
        .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] ),
        .\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg_0 (\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg ),
        .\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg_1 (\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2]_0 (\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2] ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 (\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 (\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_0 (\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 (\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_5 ),
        .Q(Q),
        .ch1_delay_cnt_en(ch1_delay_cnt_en),
        .ch1_delay_count0(ch1_delay_count0),
        .ch1_dly_fast_cnt0(ch1_dly_fast_cnt0),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .mm2s_dly_irq_set(mm2s_dly_irq_set),
        .mm2s_dmacr(mm2s_dmacr[6:2]),
        .mm2s_ioc_irq_set(mm2s_ioc_irq_set),
        .mm2s_irqthresh_wren(mm2s_irqthresh_wren),
        .out(out),
        .sinit(sinit));
  Loopback_axi_dma_1_0_axi_sg_datamover I_SG_AXI_DATAMOVER
       (.D({\I_UPDT_SG/update_address [31:6],\I_UPDT_SG/update_address [4],\USE_SINGLE_REG.sig_data_in0 }),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (I_SG_AXI_DATAMOVER_n_51),
        .\GEN_CH1_UPDATE.ch1_active_i_reg (I_SG_AXI_DATAMOVER_n_48),
        .Q(\GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE_n_10 ),
        .\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] (I_SG_AXI_DATAMOVER_n_40),
        .ch1_updt_active(ch1_updt_active),
        .follower_full_mm2s(\GEN_QUEUE.I_UPDT_DESC_QUEUE/follower_full_mm2s ),
        .follower_full_mm2s0(\GEN_QUEUE.I_UPDT_DESC_QUEUE/follower_full_mm2s0 ),
        .ftch_cmnd_data({ftch_cmnd_data[63:38],ftch_cmnd_data[2]}),
        .ftch_decerr_i(\I_FTCH_CMDSTS_IF/ftch_decerr_i ),
        .ftch_slverr_i(\I_FTCH_CMDSTS_IF/ftch_slverr_i ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_araddr(m_axi_sg_araddr),
        .m_axi_sg_arburst(m_axi_sg_arburst),
        .m_axi_sg_arlen(m_axi_sg_arlen),
        .m_axi_sg_arready(m_axi_sg_arready),
        .m_axi_sg_arvalid(m_axi_sg_arvalid),
        .m_axi_sg_awaddr(m_axi_sg_awaddr),
        .m_axi_sg_awlen(m_axi_sg_awlen),
        .m_axi_sg_awready(m_axi_sg_awready),
        .m_axi_sg_awsize(m_axi_sg_awsize),
        .m_axi_sg_awvalid(m_axi_sg_awvalid),
        .m_axi_sg_bready(m_axi_sg_bready),
        .m_axi_sg_bresp(m_axi_sg_bresp),
        .m_axi_sg_bvalid(m_axi_sg_bvalid),
        .m_axi_sg_rlast(m_axi_sg_rlast),
        .m_axi_sg_rready(m_axi_sg_rready),
        .m_axi_sg_rresp(m_axi_sg_rresp),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .m_axi_sg_wlast(m_axi_sg_wlast),
        .m_axi_sg_wready(m_axi_sg_wready),
        .m_axi_sg_wvalid(m_axi_sg_wvalid),
        .m_axis_updt_sts_tready(m_axis_updt_sts_tready),
        .out(out),
        .s_axis_ftch_cmd_tready(s_axis_ftch_cmd_tready),
        .s_axis_ftch_cmd_tvalid(s_axis_ftch_cmd_tvalid),
        .s_axis_updt_cmd_tready(s_axis_updt_cmd_tready),
        .s_axis_updt_cmd_tvalid(s_axis_updt_cmd_tvalid),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0),
        .updt_decerr_i(\I_UPDT_CMDSTS_IF/updt_decerr_i ),
        .updt_interr_i(\I_UPDT_CMDSTS_IF/updt_interr_i ),
        .updt_slverr_i(\I_UPDT_CMDSTS_IF/updt_slverr_i ));
  Loopback_axi_dma_1_0_axi_sg_ftch_mngr I_SG_FETCH_MNGR
       (.CO(CO),
        .D({I_SG_FETCH_MNGR_n_66,I_SG_FETCH_MNGR_n_67,I_SG_FETCH_MNGR_n_68,I_SG_FETCH_MNGR_n_69,I_SG_FETCH_MNGR_n_70,I_SG_FETCH_MNGR_n_71,I_SG_FETCH_MNGR_n_72,I_SG_FETCH_MNGR_n_73,I_SG_FETCH_MNGR_n_74,I_SG_FETCH_MNGR_n_75,I_SG_FETCH_MNGR_n_76,I_SG_FETCH_MNGR_n_77,I_SG_FETCH_MNGR_n_78,I_SG_FETCH_MNGR_n_79,I_SG_FETCH_MNGR_n_80,I_SG_FETCH_MNGR_n_81,I_SG_FETCH_MNGR_n_82,I_SG_FETCH_MNGR_n_83,I_SG_FETCH_MNGR_n_84,I_SG_FETCH_MNGR_n_85,I_SG_FETCH_MNGR_n_86,I_SG_FETCH_MNGR_n_87,I_SG_FETCH_MNGR_n_88,I_SG_FETCH_MNGR_n_89,I_SG_FETCH_MNGR_n_90,I_SG_FETCH_MNGR_n_91}),
        .E(\GEN_QUEUE.FTCH_QUEUE_I/current_bd0 ),
        .\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 (\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ),
        .\GEN_CH1_FETCH.ch1_active_i_reg (\GEN_CH1_FETCH.ch1_active_i_reg ),
        .\GEN_CH1_FETCH.ch1_active_i_reg_0 (I_SG_FETCH_MNGR_n_38),
        .\GEN_CH1_FETCH.ch1_ftch_decerr_set_reg (\GEN_CH1_FETCH.ch1_ftch_decerr_set_reg ),
        .\GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg (I_SG_FETCH_MNGR_n_93),
        .\GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_0 (\GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg ),
        .\GEN_CH1_FETCH.ch1_ftch_slverr_set_reg (\GEN_CH1_FETCH.ch1_ftch_slverr_set_reg ),
        .\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ({\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ,ch1_fetch_address_i}),
        .\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 (p_2_in),
        .\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6] (I_SG_FETCH_QUEUE_n_9),
        .\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg (ch1_sg_idle),
        .\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_0 (\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg ),
        .\GEN_PNTR_FOR_CH1.ch1_use_crntdesc_reg (ch1_nxtdesc_wren),
        .Q({p_0_in9_in,I_SG_FETCH_QUEUE_n_8}),
        .S(S),
        .SR(SR),
        .ch1_ftch_pause(ch1_ftch_pause),
        .ch1_ftch_queue_empty(ch1_ftch_queue_empty),
        .\ch1_sg_idle1_inferred__0/i__carry (\ch1_sg_idle1_inferred__0/i__carry ),
        .ch1_use_crntdesc(\I_FTCH_PNTR_MNGR/ch1_use_crntdesc ),
        .dma_mm2s_error(dma_mm2s_error),
        .ftch_cmnd_data({ftch_cmnd_data[63:38],ftch_cmnd_data[2]}),
        .ftch_decerr_i(\I_FTCH_CMDSTS_IF/ftch_decerr_i ),
        .ftch_done_reg(I_SG_AXI_DATAMOVER_n_40),
        .ftch_error(ftch_error),
        .\ftch_error_addr_reg[31] (updt_error_addr_1),
        .ftch_slverr_i(\I_FTCH_CMDSTS_IF/ftch_slverr_i ),
        .ftch_stale_desc(ftch_stale_desc),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_rdata(m_axi_sg_rdata[31]),
        .m_axi_sg_rresp(m_axi_sg_rresp[1]),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .m_axi_sg_rvalid_0(I_SG_FETCH_MNGR_n_37),
        .m_axis_updt_sts_tready(m_axis_updt_sts_tready),
        .mm2s_dmacr(mm2s_dmacr[1:0]),
        .mm2s_ftch_idle(mm2s_ftch_idle),
        .mm2s_stop_i(mm2s_stop_i),
        .mm2s_updt_decerr_set(mm2s_updt_decerr_set),
        .mm2s_updt_interr_set(mm2s_updt_interr_set),
        .mm2s_updt_slverr_set(mm2s_updt_slverr_set),
        .out(out),
        .s_axis_ftch_cmd_tready(s_axis_ftch_cmd_tready),
        .s_axis_ftch_cmd_tvalid(s_axis_ftch_cmd_tvalid),
        .sg_decerr_reg(sg_decerr_reg),
        .sg_ftch_error0(sg_ftch_error0),
        .sg_interr_reg(sg_interr_reg),
        .sg_slverr_reg(sg_slverr_reg),
        .sinit(sinit),
        .soft_reset(soft_reset),
        .updt_error(updt_error));
  Loopback_axi_dma_1_0_axi_sg_ftch_q_mngr I_SG_FETCH_QUEUE
       (.D({\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ,ch1_fetch_address_i}),
        .E(\GEN_QUEUE.FTCH_QUEUE_I/current_bd0 ),
        .\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 (\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\GEN_ASYNC_RESET.scndry_resetn_reg ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg_0 (\GEN_ASYNC_RESET.scndry_resetn_reg_0 ),
        .\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] (p_2_in),
        .\GEN_MM2S.queue_dout_new_reg[64] (\GEN_MM2S.queue_dout_new_reg[64] ),
        .\GEN_MM2S.queue_dout_new_reg[90] (\GEN_MM2S.queue_dout_new_reg[90] ),
        .\GEN_MM2S.queue_dout_new_reg[90]_0 (\GEN_MM2S.queue_dout_new_reg[90]_0 ),
        .\GEN_MM2S.queue_dout_valid_reg (m_axis_mm2s_ftch_tvalid_new),
        .\GEN_MM2S.reg1_reg[90] (\GEN_MM2S.reg1_reg[90] ),
        .\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 (ch1_nxtdesc_wren),
        .\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_1 (I_SG_FETCH_QUEUE_n_9),
        .\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_2 (I_SG_FETCH_MNGR_n_38),
        .\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] (\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 ),
        .\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 (\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ),
        .\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_1 (I_SG_FETCH_MNGR_n_37),
        .Q({p_0_in9_in,I_SG_FETCH_QUEUE_n_8}),
        .ch1_ftch_pause(ch1_ftch_pause),
        .ch1_ftch_queue_empty(ch1_ftch_queue_empty),
        .ch1_use_crntdesc(\I_FTCH_PNTR_MNGR/ch1_use_crntdesc ),
        .\counter_reg[1]_0 (\counter_reg[1] ),
        .ftch_cmnd_data(ftch_cmnd_data[2]),
        .ftch_stale_desc(ftch_stale_desc),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_rdata(m_axi_sg_rdata),
        .m_axi_sg_rlast(m_axi_sg_rlast),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .m_axis_mm2s_cntrl_tdata(m_axis_mm2s_cntrl_tdata),
        .m_axis_mm2s_cntrl_tlast(m_axis_mm2s_cntrl_tlast),
        .m_axis_mm2s_cntrl_tready(m_axis_mm2s_cntrl_tready),
        .m_axis_mm2s_cntrl_tvalid(m_axis_mm2s_cntrl_tvalid),
        .m_axis_mm2s_cntrl_tvalid_0(\GEN_CH1_FETCH.ch1_active_i_reg ),
        .mm2s_cntrl_strm_stop(mm2s_cntrl_strm_stop),
        .mm2s_dmacr(mm2s_dmacr[1]),
        .out(out),
        .packet_in_progress(packet_in_progress),
        .ptr_queue_full(ptr_queue_full),
        .queue_empty_new0(queue_empty_new0),
        .rst(rst),
        .s_axis_mm2s_cmd_tready(s_axis_mm2s_cmd_tready),
        .s_axis_mm2s_cmd_tvalid_split(s_axis_mm2s_cmd_tvalid_split),
        .s_axis_mm2s_updtptr_tlast(s_axis_mm2s_updtptr_tlast),
        .sinit(sinit),
        .soft_reset_d1(soft_reset_d1),
        .soft_reset_d2(soft_reset_d2));
  FDRE \ftch_error_addr_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_87),
        .Q(\ftch_error_addr_reg[31]_0 [4]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_86),
        .Q(\ftch_error_addr_reg[31]_0 [5]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_85),
        .Q(\ftch_error_addr_reg[31]_0 [6]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_84),
        .Q(\ftch_error_addr_reg[31]_0 [7]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_83),
        .Q(\ftch_error_addr_reg[31]_0 [8]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_82),
        .Q(\ftch_error_addr_reg[31]_0 [9]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_81),
        .Q(\ftch_error_addr_reg[31]_0 [10]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_80),
        .Q(\ftch_error_addr_reg[31]_0 [11]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_79),
        .Q(\ftch_error_addr_reg[31]_0 [12]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_78),
        .Q(\ftch_error_addr_reg[31]_0 [13]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_77),
        .Q(\ftch_error_addr_reg[31]_0 [14]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_76),
        .Q(\ftch_error_addr_reg[31]_0 [15]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_75),
        .Q(\ftch_error_addr_reg[31]_0 [16]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_74),
        .Q(\ftch_error_addr_reg[31]_0 [17]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_73),
        .Q(\ftch_error_addr_reg[31]_0 [18]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_72),
        .Q(\ftch_error_addr_reg[31]_0 [19]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_71),
        .Q(\ftch_error_addr_reg[31]_0 [20]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_70),
        .Q(\ftch_error_addr_reg[31]_0 [21]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_69),
        .Q(\ftch_error_addr_reg[31]_0 [22]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_68),
        .Q(\ftch_error_addr_reg[31]_0 [23]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_67),
        .Q(\ftch_error_addr_reg[31]_0 [24]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_66),
        .Q(\ftch_error_addr_reg[31]_0 [25]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_91),
        .Q(\ftch_error_addr_reg[31]_0 [0]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_90),
        .Q(\ftch_error_addr_reg[31]_0 [1]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_89),
        .Q(\ftch_error_addr_reg[31]_0 [2]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_DESC_UPDATE.I_SG_UPDATE_MNGR_n_6 ),
        .D(I_SG_FETCH_MNGR_n_88),
        .Q(\ftch_error_addr_reg[31]_0 [3]),
        .R(sinit));
endmodule

module Loopback_axi_dma_1_0_axi_sg_addr_cntl
   (sig_addr2rsc_cmd_fifo_empty,
    m_axi_sg_arburst,
    m_axi_sg_arvalid,
    m_axi_sg_arlen,
    sig_addr_reg_empty_reg_0,
    m_axi_sg_araddr,
    m_axi_sg_aclk,
    sm_set_error,
    sig_cmd_burst_reg,
    sig_addr_valid_reg_reg_0,
    sig_posted_to_axi_reg_0,
    sig_addr_valid_reg_reg_1,
    sig_mstr2addr_cmd_valid,
    m_axi_sg_arready,
    Q,
    D);
  output sig_addr2rsc_cmd_fifo_empty;
  output [0:0]m_axi_sg_arburst;
  output m_axi_sg_arvalid;
  output [2:0]m_axi_sg_arlen;
  output sig_addr_reg_empty_reg_0;
  output [25:0]m_axi_sg_araddr;
  input m_axi_sg_aclk;
  input sm_set_error;
  input [0:0]sig_cmd_burst_reg;
  input sig_addr_valid_reg_reg_0;
  input sig_posted_to_axi_reg_0;
  input sig_addr_valid_reg_reg_1;
  input sig_mstr2addr_cmd_valid;
  input m_axi_sg_arready;
  input [25:0]Q;
  input [1:0]D;

  wire [1:0]D;
  wire [25:0]Q;
  wire m_axi_sg_aclk;
  wire [25:0]m_axi_sg_araddr;
  wire [0:0]m_axi_sg_arburst;
  wire [2:0]m_axi_sg_arlen;
  wire m_axi_sg_arready;
  wire m_axi_sg_arvalid;
  wire sig_addr2rsc_calc_error;
  wire sig_addr2rsc_cmd_fifo_empty;
  wire sig_addr_reg_empty_reg_0;
  wire sig_addr_valid_reg_reg_0;
  wire sig_addr_valid_reg_reg_1;
  wire [0:0]sig_cmd_burst_reg;
  wire sig_mstr2addr_cmd_valid;
  wire sig_next_addr_reg0;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_posted_to_axi;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_posted_to_axi_2;
  wire sig_posted_to_axi_reg_0;
  wire sig_push_addr_reg1_out;
  wire sm_set_error;

  FDSE #(
    .INIT(1'b0)) 
    sig_addr_reg_empty_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(1'b0),
        .Q(sig_addr2rsc_cmd_fifo_empty),
        .S(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_addr_valid_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_addr_valid_reg_reg_0),
        .Q(m_axi_sg_arvalid),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_calc_error_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sm_set_error),
        .Q(sig_addr2rsc_calc_error),
        .R(sig_next_addr_reg0));
  LUT2 #(
    .INIT(4'h7)) 
    sig_cmd_reg_empty_i_1
       (.I0(sig_addr2rsc_cmd_fifo_empty),
        .I1(sig_addr_valid_reg_reg_1),
        .O(sig_addr_reg_empty_reg_0));
  LUT4 #(
    .INIT(16'h40FF)) 
    \sig_next_addr_reg[31]_i_1 
       (.I0(sig_addr2rsc_calc_error),
        .I1(m_axi_sg_arready),
        .I2(m_axi_sg_arlen[1]),
        .I3(sig_addr_valid_reg_reg_1),
        .O(sig_next_addr_reg0));
  LUT2 #(
    .INIT(4'h8)) 
    \sig_next_addr_reg[31]_i_2 
       (.I0(sig_addr2rsc_cmd_fifo_empty),
        .I1(sig_mstr2addr_cmd_valid),
        .O(sig_push_addr_reg1_out));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[4]),
        .Q(m_axi_sg_araddr[4]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[5]),
        .Q(m_axi_sg_araddr[5]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[6]),
        .Q(m_axi_sg_araddr[6]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[7]),
        .Q(m_axi_sg_araddr[7]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[8]),
        .Q(m_axi_sg_araddr[8]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[9]),
        .Q(m_axi_sg_araddr[9]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[10]),
        .Q(m_axi_sg_araddr[10]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[11]),
        .Q(m_axi_sg_araddr[11]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[12]),
        .Q(m_axi_sg_araddr[12]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[13]),
        .Q(m_axi_sg_araddr[13]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[14]),
        .Q(m_axi_sg_araddr[14]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[15]),
        .Q(m_axi_sg_araddr[15]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[16]),
        .Q(m_axi_sg_araddr[16]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[17]),
        .Q(m_axi_sg_araddr[17]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[18]),
        .Q(m_axi_sg_araddr[18]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[19]),
        .Q(m_axi_sg_araddr[19]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[20]),
        .Q(m_axi_sg_araddr[20]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[21]),
        .Q(m_axi_sg_araddr[21]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[22]),
        .Q(m_axi_sg_araddr[22]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[23]),
        .Q(m_axi_sg_araddr[23]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[24]),
        .Q(m_axi_sg_araddr[24]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[25]),
        .Q(m_axi_sg_araddr[25]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[0]),
        .Q(m_axi_sg_araddr[0]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[1]),
        .Q(m_axi_sg_araddr[1]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[2]),
        .Q(m_axi_sg_araddr[2]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[3]),
        .Q(m_axi_sg_araddr[3]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_burst_reg_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_cmd_burst_reg),
        .Q(m_axi_sg_arburst),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_len_reg_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(D[0]),
        .Q(m_axi_sg_arlen[0]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_len_reg_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(1'b1),
        .Q(m_axi_sg_arlen[1]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_len_reg_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(D[1]),
        .Q(m_axi_sg_arlen[2]),
        .R(sig_next_addr_reg0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_posted_to_axi_2_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_posted_to_axi_reg_0),
        .Q(sig_posted_to_axi_2),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_posted_to_axi_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_posted_to_axi_reg_0),
        .Q(sig_posted_to_axi),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "axi_sg_addr_cntl" *) 
module Loopback_axi_dma_1_0_axi_sg_addr_cntl__parameterized0
   (out,
    sig_addr2wsc_cmd_fifo_empty,
    m_axi_sg_awlen,
    m_axi_sg_awsize,
    m_axi_sg_awvalid,
    m_axi_sg_awaddr,
    sig_addr_reg_empty_reg_0,
    sig_push_addr_reg1_out,
    m_axi_sg_aclk,
    sig_calc2dm_calc_err,
    sig_mstr2data_len,
    sig_addr_valid_reg_reg_0,
    sig_posted_to_axi_2_reg_0,
    \sig_next_addr_reg_reg[3]_0 ,
    sig_data2all_tlast_error,
    sig_addr_valid_reg_reg_1,
    m_axi_sg_awready,
    Q);
  output out;
  output sig_addr2wsc_cmd_fifo_empty;
  output [0:0]m_axi_sg_awlen;
  output [0:0]m_axi_sg_awsize;
  output m_axi_sg_awvalid;
  output [27:0]m_axi_sg_awaddr;
  output sig_addr_reg_empty_reg_0;
  input sig_push_addr_reg1_out;
  input m_axi_sg_aclk;
  input sig_calc2dm_calc_err;
  input [0:0]sig_mstr2data_len;
  input sig_addr_valid_reg_reg_0;
  input sig_posted_to_axi_2_reg_0;
  input \sig_next_addr_reg_reg[3]_0 ;
  input sig_data2all_tlast_error;
  input sig_addr_valid_reg_reg_1;
  input m_axi_sg_awready;
  input [26:0]Q;

  wire [26:0]Q;
  wire m_axi_sg_aclk;
  wire [27:0]m_axi_sg_awaddr;
  wire [0:0]m_axi_sg_awlen;
  wire m_axi_sg_awready;
  wire [0:0]m_axi_sg_awsize;
  wire m_axi_sg_awvalid;
  wire sig_addr2wsc_calc_error;
  wire sig_addr2wsc_cmd_fifo_empty;
  wire sig_addr_reg_empty_reg_0;
  wire sig_addr_valid_reg_reg_0;
  wire sig_addr_valid_reg_reg_1;
  wire sig_calc2dm_calc_err;
  wire sig_data2all_tlast_error;
  wire [0:0]sig_mstr2data_len;
  wire sig_next_addr_reg0;
  wire \sig_next_addr_reg_reg[3]_0 ;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_posted_to_axi;
  (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_posted_to_axi_2;
  wire sig_posted_to_axi_2_reg_0;
  wire sig_push_addr_reg1_out;

  assign out = sig_posted_to_axi;
  FDSE #(
    .INIT(1'b0)) 
    sig_addr_reg_empty_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(1'b0),
        .Q(sig_addr2wsc_cmd_fifo_empty),
        .S(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_addr_valid_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_addr_valid_reg_reg_0),
        .Q(m_axi_sg_awvalid),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_calc_error_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_calc2dm_calc_err),
        .Q(sig_addr2wsc_calc_error),
        .R(sig_next_addr_reg0));
  LUT3 #(
    .INIT(8'hDF)) 
    sig_cmd_reg_empty_i_1__0
       (.I0(sig_addr2wsc_cmd_fifo_empty),
        .I1(sig_data2all_tlast_error),
        .I2(sig_addr_valid_reg_reg_1),
        .O(sig_addr_reg_empty_reg_0));
  LUT4 #(
    .INIT(16'h40FF)) 
    \sig_next_addr_reg[31]_i_1__0 
       (.I0(sig_addr2wsc_calc_error),
        .I1(m_axi_sg_awready),
        .I2(m_axi_sg_awsize),
        .I3(sig_addr_valid_reg_reg_1),
        .O(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[5]),
        .Q(m_axi_sg_awaddr[6]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[6]),
        .Q(m_axi_sg_awaddr[7]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[7]),
        .Q(m_axi_sg_awaddr[8]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[8]),
        .Q(m_axi_sg_awaddr[9]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[9]),
        .Q(m_axi_sg_awaddr[10]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[10]),
        .Q(m_axi_sg_awaddr[11]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[11]),
        .Q(m_axi_sg_awaddr[12]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[12]),
        .Q(m_axi_sg_awaddr[13]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[13]),
        .Q(m_axi_sg_awaddr[14]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[14]),
        .Q(m_axi_sg_awaddr[15]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[15]),
        .Q(m_axi_sg_awaddr[16]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[16]),
        .Q(m_axi_sg_awaddr[17]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[17]),
        .Q(m_axi_sg_awaddr[18]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[18]),
        .Q(m_axi_sg_awaddr[19]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[19]),
        .Q(m_axi_sg_awaddr[20]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[20]),
        .Q(m_axi_sg_awaddr[21]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[21]),
        .Q(m_axi_sg_awaddr[22]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[22]),
        .Q(m_axi_sg_awaddr[23]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[23]),
        .Q(m_axi_sg_awaddr[24]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[24]),
        .Q(m_axi_sg_awaddr[25]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[25]),
        .Q(m_axi_sg_awaddr[26]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[26]),
        .Q(m_axi_sg_awaddr[27]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(\sig_next_addr_reg_reg[3]_0 ),
        .Q(m_axi_sg_awaddr[0]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[0]),
        .Q(m_axi_sg_awaddr[1]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[1]),
        .Q(m_axi_sg_awaddr[2]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[2]),
        .Q(m_axi_sg_awaddr[3]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[3]),
        .Q(m_axi_sg_awaddr[4]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_addr_reg_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(Q[4]),
        .Q(m_axi_sg_awaddr[5]),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_len_reg_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(sig_mstr2data_len),
        .Q(m_axi_sg_awlen),
        .R(sig_next_addr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \sig_next_size_reg_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_addr_reg1_out),
        .D(1'b1),
        .Q(m_axi_sg_awsize),
        .R(sig_next_addr_reg0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_posted_to_axi_2_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_posted_to_axi_2_reg_0),
        .Q(sig_posted_to_axi_2),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    sig_posted_to_axi_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_posted_to_axi_2_reg_0),
        .Q(sig_posted_to_axi),
        .R(1'b0));
endmodule

module Loopback_axi_dma_1_0_axi_sg_cmd_status
   (sig_init_done,
    s_axis_updt_cmd_tready,
    sig_init_done_0,
    sig_stat2wsc_status_ready,
    updt_decerr_i,
    updt_interr_i,
    updt_slverr_i,
    sig_load_input_cmd,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    Q,
    m_axi_sg_aclk,
    sig_init_done_reg,
    sig_stream_rst,
    sig_init_done_reg_0,
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg ,
    sig_data2all_tlast_error,
    sig_addr2wsc_cmd_fifo_empty,
    sig_cmd_reg_empty,
    s_axis_updt_cmd_tvalid,
    sig_wsc2stat_status_valid,
    m_axis_updt_sts_tready,
    out,
    D,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63] );
  output sig_init_done;
  output s_axis_updt_cmd_tready;
  output sig_init_done_0;
  output sig_stat2wsc_status_ready;
  output updt_decerr_i;
  output updt_interr_i;
  output updt_slverr_i;
  output sig_load_input_cmd;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  output [29:0]Q;
  input m_axi_sg_aclk;
  input sig_init_done_reg;
  input sig_stream_rst;
  input sig_init_done_reg_0;
  input \USE_SINGLE_REG.sig_regfifo_full_reg_reg ;
  input sig_data2all_tlast_error;
  input sig_addr2wsc_cmd_fifo_empty;
  input sig_cmd_reg_empty;
  input s_axis_updt_cmd_tvalid;
  input sig_wsc2stat_status_valid;
  input m_axis_updt_sts_tready;
  input out;
  input [3:0]D;
  input [28:0]\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63] ;

  wire [3:0]D;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire [29:0]Q;
  wire [28:0]\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63] ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_reg ;
  wire m_axi_sg_aclk;
  wire m_axis_updt_sts_tready;
  wire out;
  wire s_axis_updt_cmd_tready;
  wire s_axis_updt_cmd_tvalid;
  wire sig_addr2wsc_cmd_fifo_empty;
  wire sig_cmd_reg_empty;
  wire sig_data2all_tlast_error;
  wire sig_init_done;
  wire sig_init_done_0;
  wire sig_init_done_reg;
  wire sig_init_done_reg_0;
  wire sig_load_input_cmd;
  wire sig_stat2wsc_status_ready;
  wire sig_stream_rst;
  wire sig_wsc2stat_status_valid;
  wire updt_decerr_i;
  wire updt_interr_i;
  wire updt_slverr_i;

  Loopback_axi_dma_1_0_axi_sg_fifo__parameterized0 \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO 
       (.D(D),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\GEN_ASYNC_RESET.scndry_resetn_reg ),
        .\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 (sig_stat2wsc_status_ready),
        .\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 (\USE_SINGLE_REG.sig_regfifo_full_reg_reg ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_updt_sts_tready(m_axis_updt_sts_tready),
        .out(out),
        .sig_init_done_0(sig_init_done_0),
        .sig_init_done_reg_0(sig_init_done_reg_0),
        .sig_stream_rst(sig_stream_rst),
        .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid),
        .updt_decerr_i(updt_decerr_i),
        .updt_interr_i(updt_interr_i),
        .updt_slverr_i(updt_slverr_i));
  Loopback_axi_dma_1_0_axi_sg_fifo I_CMD_FIFO
       (.Q(Q),
        .\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 (\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63] ),
        .\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 (\USE_SINGLE_REG.sig_regfifo_full_reg_reg ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .s_axis_updt_cmd_tready(s_axis_updt_cmd_tready),
        .s_axis_updt_cmd_tvalid(s_axis_updt_cmd_tvalid),
        .sig_addr2wsc_cmd_fifo_empty(sig_addr2wsc_cmd_fifo_empty),
        .sig_cmd_reg_empty(sig_cmd_reg_empty),
        .sig_data2all_tlast_error(sig_data2all_tlast_error),
        .sig_init_done(sig_init_done),
        .sig_init_done_reg_0(sig_init_done_reg),
        .sig_load_input_cmd(sig_load_input_cmd),
        .sig_stream_rst(sig_stream_rst));
endmodule

(* ORIG_REF_NAME = "axi_sg_cmd_status" *) 
module Loopback_axi_dma_1_0_axi_sg_cmd_status_21
   (\USE_SINGLE_REG.sig_regfifo_empty_reg_reg ,
    sig_stat2rsc_status_ready,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ,
    ftch_decerr_i,
    ftch_slverr_i,
    sig_load_input_cmd,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2,
    Q,
    sig_init_reg_reg,
    m_axi_sg_aclk,
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg ,
    s_axis_ftch_cmd_tvalid,
    sig_addr2rsc_cmd_fifo_empty,
    sig_cmd_reg_empty,
    sig_rsc2stat_status_valid,
    m_axis_updt_sts_tready,
    sig_init_done,
    sig_init_done_0,
    sig_init_done_1,
    sig_init_done_2,
    D,
    ftch_cmnd_data);
  output \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ;
  output sig_stat2rsc_status_ready;
  output \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ;
  output ftch_decerr_i;
  output ftch_slverr_i;
  output sig_load_input_cmd;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2;
  output [27:0]Q;
  input sig_init_reg_reg;
  input m_axi_sg_aclk;
  input \USE_SINGLE_REG.sig_regfifo_full_reg_reg ;
  input s_axis_ftch_cmd_tvalid;
  input sig_addr2rsc_cmd_fifo_empty;
  input sig_cmd_reg_empty;
  input sig_rsc2stat_status_valid;
  input m_axis_updt_sts_tready;
  input sig_init_done;
  input sig_init_done_0;
  input sig_init_done_1;
  input sig_init_done_2;
  input [2:0]D;
  input [26:0]ftch_cmnd_data;

  wire [2:0]D;
  wire I_CMD_FIFO_n_2;
  wire [27:0]Q;
  wire \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_reg ;
  wire [26:0]ftch_cmnd_data;
  wire ftch_decerr_i;
  wire ftch_slverr_i;
  wire m_axi_sg_aclk;
  wire m_axis_updt_sts_tready;
  wire s_axis_ftch_cmd_tvalid;
  wire sig_addr2rsc_cmd_fifo_empty;
  wire sig_cmd_reg_empty;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2;
  wire sig_init_done;
  wire sig_init_done_0;
  wire sig_init_done_1;
  wire sig_init_done_2;
  wire sig_init_done_3;
  wire sig_init_reg_reg;
  wire sig_load_input_cmd;
  wire sig_rsc2stat_status_valid;
  wire sig_stat2rsc_status_ready;

  Loopback_axi_dma_1_0_axi_sg_fifo__parameterized0_22 \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO 
       (.D(D),
        .\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7]_0 (\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ),
        .\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 (sig_stat2rsc_status_ready),
        .\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_1 (sig_init_reg_reg),
        .\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 (\USE_SINGLE_REG.sig_regfifo_full_reg_reg ),
        .ftch_decerr_i(ftch_decerr_i),
        .ftch_slverr_i(ftch_slverr_i),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_updt_sts_tready(m_axis_updt_sts_tready),
        .sig_init_done(sig_init_done_3),
        .sig_init_done_reg_0(I_CMD_FIFO_n_2),
        .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid));
  Loopback_axi_dma_1_0_axi_sg_fifo_23 I_CMD_FIFO
       (.Q(Q),
        .\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 (\USE_SINGLE_REG.sig_regfifo_empty_reg_reg ),
        .\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 (\USE_SINGLE_REG.sig_regfifo_full_reg_reg ),
        .ftch_cmnd_data(ftch_cmnd_data),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .s_axis_ftch_cmd_tvalid(s_axis_ftch_cmd_tvalid),
        .sig_addr2rsc_cmd_fifo_empty(sig_addr2rsc_cmd_fifo_empty),
        .sig_cmd_reg_empty(sig_cmd_reg_empty),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(I_CMD_FIFO_n_2),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2),
        .sig_init_done(sig_init_done),
        .sig_init_done_0(sig_init_done_0),
        .sig_init_done_1(sig_init_done_1),
        .sig_init_done_2(sig_init_done_2),
        .sig_init_done_3(sig_init_done_3),
        .sig_init_reg_reg_0(sig_init_reg_reg),
        .sig_load_input_cmd(sig_load_input_cmd));
endmodule

module Loopback_axi_dma_1_0_axi_sg_cntrl_strm
   (m_axis_mm2s_cntrl_tlast,
    m_axis_mm2s_cntrl_tvalid,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    \counter_reg[0] ,
    m_axis_mm2s_cntrl_tdata,
    rst,
    m_axi_sg_aclk,
    m_axi_sg_rlast,
    sinit,
    mm2s_cntrl_strm_stop,
    m_axis_mm2s_cntrl_tready,
    m_axis_mm2s_cntrl_tvalid_0,
    soft_reset_d1,
    soft_reset_d2,
    \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ,
    out,
    m_axi_sg_rvalid,
    Q,
    \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ,
    \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ,
    ftch_cmnd_data,
    sof_ftch_desc,
    m_axi_sg_rdata,
    sof_ftch_desc_del1);
  output m_axis_mm2s_cntrl_tlast;
  output m_axis_mm2s_cntrl_tvalid;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  output \counter_reg[0] ;
  output [31:0]m_axis_mm2s_cntrl_tdata;
  input rst;
  input m_axi_sg_aclk;
  input m_axi_sg_rlast;
  input sinit;
  input mm2s_cntrl_strm_stop;
  input m_axis_mm2s_cntrl_tready;
  input m_axis_mm2s_cntrl_tvalid_0;
  input soft_reset_d1;
  input soft_reset_d2;
  input \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  input out;
  input m_axi_sg_rvalid;
  input [2:0]Q;
  input \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ;
  input \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ;
  input [0:0]ftch_cmnd_data;
  input sof_ftch_desc;
  input [31:0]m_axi_sg_rdata;
  input sof_ftch_desc_del1;

  wire \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ;
  wire \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ;
  wire \GEN_SYNC_FIFO.mm2s_stop_d1 ;
  wire \GEN_SYNC_FIFO.xfer_in_progress ;
  wire \GEN_SYNC_FIFO.xfer_in_progress_i_1_n_0 ;
  wire [2:0]Q;
  wire [32:0]cntrl_fifo_dout;
  wire cntrl_fifo_rden;
  wire \counter_reg[0] ;
  wire follower_empty_mm2s;
  wire follower_full_mm2s;
  wire follower_full_mm2s0;
  wire [0:0]ftch_cmnd_data;
  wire m_axi_sg_aclk;
  wire [31:0]m_axi_sg_rdata;
  wire m_axi_sg_rlast;
  wire m_axi_sg_rvalid;
  wire [31:0]m_axis_mm2s_cntrl_tdata;
  wire m_axis_mm2s_cntrl_tlast;
  wire m_axis_mm2s_cntrl_tlast_INST_0_i_1_n_0;
  wire m_axis_mm2s_cntrl_tready;
  wire m_axis_mm2s_cntrl_tvalid;
  wire m_axis_mm2s_cntrl_tvalid_0;
  wire mm2s_cntrl_strm_stop;
  wire out;
  wire p_0_in;
  wire rst;
  wire sinit;
  wire sof_ftch_desc;
  wire sof_ftch_desc_del1;
  wire soft_reset_d1;
  wire soft_reset_d2;

  Loopback_axi_dma_1_0_sync_fifo_fg \GEN_SYNC_FIFO.I_CNTRL_FIFO 
       (.D(cntrl_fifo_dout),
        .E(cntrl_fifo_rden),
        .\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 (\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\GEN_ASYNC_RESET.scndry_resetn_reg ),
        .\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg (\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ),
        .\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 (\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ),
        .Q(Q),
        .\counter_reg[0] (\counter_reg[0] ),
        .follower_empty_mm2s(follower_empty_mm2s),
        .ftch_cmnd_data(ftch_cmnd_data),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_rdata(m_axi_sg_rdata),
        .m_axi_sg_rlast(m_axi_sg_rlast),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .out(out),
        .rst(rst),
        .sof_ftch_desc(sof_ftch_desc),
        .sof_ftch_desc_del1(sof_ftch_desc_del1));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_empty_mm2s_reg 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(1'b0),
        .Q(follower_empty_mm2s),
        .S(follower_full_mm2s0));
  LUT3 #(
    .INIT(8'h8F)) 
    \GEN_SYNC_FIFO.follower_full_mm2s_i_1 
       (.I0(m_axis_mm2s_cntrl_tready),
        .I1(follower_full_mm2s),
        .I2(out),
        .O(follower_full_mm2s0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_full_mm2s_reg 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(1'b1),
        .Q(follower_full_mm2s),
        .R(follower_full_mm2s0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[0]),
        .Q(m_axis_mm2s_cntrl_tdata[0]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[10]),
        .Q(m_axis_mm2s_cntrl_tdata[10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[11]),
        .Q(m_axis_mm2s_cntrl_tdata[11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[12]),
        .Q(m_axis_mm2s_cntrl_tdata[12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[13]),
        .Q(m_axis_mm2s_cntrl_tdata[13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[14]),
        .Q(m_axis_mm2s_cntrl_tdata[14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[15]),
        .Q(m_axis_mm2s_cntrl_tdata[15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[16]),
        .Q(m_axis_mm2s_cntrl_tdata[16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[17]),
        .Q(m_axis_mm2s_cntrl_tdata[17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[18]),
        .Q(m_axis_mm2s_cntrl_tdata[18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[19]),
        .Q(m_axis_mm2s_cntrl_tdata[19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[1]),
        .Q(m_axis_mm2s_cntrl_tdata[1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[20]),
        .Q(m_axis_mm2s_cntrl_tdata[20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[21]),
        .Q(m_axis_mm2s_cntrl_tdata[21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[22]),
        .Q(m_axis_mm2s_cntrl_tdata[22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[23]),
        .Q(m_axis_mm2s_cntrl_tdata[23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[24]),
        .Q(m_axis_mm2s_cntrl_tdata[24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[25]),
        .Q(m_axis_mm2s_cntrl_tdata[25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[26]),
        .Q(m_axis_mm2s_cntrl_tdata[26]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[27]),
        .Q(m_axis_mm2s_cntrl_tdata[27]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[28]),
        .Q(m_axis_mm2s_cntrl_tdata[28]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[29]),
        .Q(m_axis_mm2s_cntrl_tdata[29]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[2]),
        .Q(m_axis_mm2s_cntrl_tdata[2]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[30]),
        .Q(m_axis_mm2s_cntrl_tdata[30]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[31]),
        .Q(m_axis_mm2s_cntrl_tdata[31]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[32] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[32]),
        .Q(p_0_in),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[3]),
        .Q(m_axis_mm2s_cntrl_tdata[3]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[4]),
        .Q(m_axis_mm2s_cntrl_tdata[4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[5]),
        .Q(m_axis_mm2s_cntrl_tdata[5]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[6]),
        .Q(m_axis_mm2s_cntrl_tdata[6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[7]),
        .Q(m_axis_mm2s_cntrl_tdata[7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[8]),
        .Q(m_axis_mm2s_cntrl_tdata[8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(cntrl_fifo_rden),
        .D(cntrl_fifo_dout[9]),
        .Q(m_axis_mm2s_cntrl_tdata[9]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.mm2s_stop_d1_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_cntrl_strm_stop),
        .Q(\GEN_SYNC_FIFO.mm2s_stop_d1 ),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT5 #(
    .INIT(32'h557F554C)) 
    \GEN_SYNC_FIFO.xfer_in_progress_i_1 
       (.I0(m_axis_mm2s_cntrl_tready),
        .I1(follower_full_mm2s),
        .I2(p_0_in),
        .I3(m_axis_mm2s_cntrl_tlast_INST_0_i_1_n_0),
        .I4(\GEN_SYNC_FIFO.xfer_in_progress ),
        .O(\GEN_SYNC_FIFO.xfer_in_progress_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_SYNC_FIFO.xfer_in_progress_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_SYNC_FIFO.xfer_in_progress_i_1_n_0 ),
        .Q(\GEN_SYNC_FIFO.xfer_in_progress ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    m_axis_mm2s_cntrl_tlast_INST_0
       (.I0(m_axis_mm2s_cntrl_tlast_INST_0_i_1_n_0),
        .I1(p_0_in),
        .I2(follower_full_mm2s),
        .O(m_axis_mm2s_cntrl_tlast));
  LUT5 #(
    .INIT(32'h40404440)) 
    m_axis_mm2s_cntrl_tlast_INST_0_i_1
       (.I0(\GEN_SYNC_FIFO.mm2s_stop_d1 ),
        .I1(\GEN_SYNC_FIFO.xfer_in_progress ),
        .I2(m_axis_mm2s_cntrl_tvalid_0),
        .I3(soft_reset_d1),
        .I4(soft_reset_d2),
        .O(m_axis_mm2s_cntrl_tlast_INST_0_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF40404440)) 
    m_axis_mm2s_cntrl_tvalid_INST_0
       (.I0(\GEN_SYNC_FIFO.mm2s_stop_d1 ),
        .I1(\GEN_SYNC_FIFO.xfer_in_progress ),
        .I2(m_axis_mm2s_cntrl_tvalid_0),
        .I3(soft_reset_d1),
        .I4(soft_reset_d2),
        .I5(follower_full_mm2s),
        .O(m_axis_mm2s_cntrl_tvalid));
endmodule

module Loopback_axi_dma_1_0_axi_sg_datamover
   (sig_cmd_stat_rst_user_reg_n_cdc_from_reg,
    m_axi_sg_arburst,
    m_axi_sg_arvalid,
    m_axi_sg_rready,
    m_axi_sg_awlen,
    m_axi_sg_awsize,
    m_axi_sg_awvalid,
    m_axi_sg_awaddr,
    m_axi_sg_arlen,
    s_axis_ftch_cmd_tready,
    s_axis_updt_cmd_tready,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ,
    ftch_decerr_i,
    ftch_slverr_i,
    updt_decerr_i,
    updt_interr_i,
    updt_slverr_i,
    m_axi_sg_bready,
    follower_full_mm2s0,
    \GEN_CH1_UPDATE.ch1_active_i_reg ,
    m_axi_sg_wvalid,
    m_axi_sg_wlast,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    m_axi_sg_araddr,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0,
    m_axi_sg_aclk,
    m_axi_sg_rvalid,
    s_axis_ftch_cmd_tvalid,
    m_axis_updt_sts_tready,
    s_axis_updt_cmd_tvalid,
    m_axi_sg_bvalid,
    m_axi_sg_wready,
    follower_full_mm2s,
    ch1_updt_active,
    out,
    Q,
    m_axi_sg_rlast,
    m_axi_sg_arready,
    m_axi_sg_awready,
    m_axi_sg_bresp,
    ftch_cmnd_data,
    D,
    m_axi_sg_rresp);
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  output [0:0]m_axi_sg_arburst;
  output m_axi_sg_arvalid;
  output m_axi_sg_rready;
  output [0:0]m_axi_sg_awlen;
  output [0:0]m_axi_sg_awsize;
  output m_axi_sg_awvalid;
  output [27:0]m_axi_sg_awaddr;
  output [2:0]m_axi_sg_arlen;
  output s_axis_ftch_cmd_tready;
  output s_axis_updt_cmd_tready;
  output \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ;
  output ftch_decerr_i;
  output ftch_slverr_i;
  output updt_decerr_i;
  output updt_interr_i;
  output updt_slverr_i;
  output m_axi_sg_bready;
  output follower_full_mm2s0;
  output \GEN_CH1_UPDATE.ch1_active_i_reg ;
  output m_axi_sg_wvalid;
  output m_axi_sg_wlast;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  output [25:0]m_axi_sg_araddr;
  input sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  input m_axi_sg_aclk;
  input m_axi_sg_rvalid;
  input s_axis_ftch_cmd_tvalid;
  input m_axis_updt_sts_tready;
  input s_axis_updt_cmd_tvalid;
  input m_axi_sg_bvalid;
  input m_axi_sg_wready;
  input follower_full_mm2s;
  input ch1_updt_active;
  input out;
  input [0:0]Q;
  input m_axi_sg_rlast;
  input m_axi_sg_arready;
  input m_axi_sg_awready;
  input [1:0]m_axi_sg_bresp;
  input [26:0]ftch_cmnd_data;
  input [27:0]D;
  input [1:0]m_axi_sg_rresp;

  wire [27:0]D;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \GEN_CH1_UPDATE.ch1_active_i_reg ;
  wire \GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_12 ;
  wire \GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_13 ;
  wire \GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_14 ;
  wire \GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_15 ;
  wire \I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done ;
  wire \I_CMD_STATUS/I_CMD_FIFO/sig_init_done ;
  wire \I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_done ;
  wire \I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_done ;
  wire [0:0]Q;
  wire \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ;
  wire ch1_updt_active;
  wire follower_full_mm2s;
  wire follower_full_mm2s0;
  wire [26:0]ftch_cmnd_data;
  wire ftch_decerr_i;
  wire ftch_slverr_i;
  wire m_axi_sg_aclk;
  wire [25:0]m_axi_sg_araddr;
  wire [0:0]m_axi_sg_arburst;
  wire [2:0]m_axi_sg_arlen;
  wire m_axi_sg_arready;
  wire m_axi_sg_arvalid;
  wire [27:0]m_axi_sg_awaddr;
  wire [0:0]m_axi_sg_awlen;
  wire m_axi_sg_awready;
  wire [0:0]m_axi_sg_awsize;
  wire m_axi_sg_awvalid;
  wire m_axi_sg_bready;
  wire [1:0]m_axi_sg_bresp;
  wire m_axi_sg_bvalid;
  wire m_axi_sg_rlast;
  wire m_axi_sg_rready;
  wire [1:0]m_axi_sg_rresp;
  wire m_axi_sg_rvalid;
  wire m_axi_sg_wlast;
  wire m_axi_sg_wready;
  wire m_axi_sg_wvalid;
  wire m_axis_updt_sts_tready;
  wire out;
  wire s_axis_ftch_cmd_tready;
  wire s_axis_ftch_cmd_tvalid;
  wire s_axis_updt_cmd_tready;
  wire s_axis_updt_cmd_tvalid;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  wire sig_stream_rst;
  wire updt_decerr_i;
  wire updt_interr_i;
  wire updt_slverr_i;

  Loopback_axi_dma_1_0_axi_sg_mm2s_basic_wrap \GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER 
       (.\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] (\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ),
        .\USE_SINGLE_REG.sig_regfifo_empty_reg_reg (s_axis_ftch_cmd_tready),
        .ftch_cmnd_data(ftch_cmnd_data),
        .ftch_decerr_i(ftch_decerr_i),
        .ftch_slverr_i(ftch_slverr_i),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_araddr(m_axi_sg_araddr),
        .m_axi_sg_arburst(m_axi_sg_arburst),
        .m_axi_sg_arlen(m_axi_sg_arlen),
        .m_axi_sg_arready(m_axi_sg_arready),
        .m_axi_sg_arvalid(m_axi_sg_arvalid),
        .m_axi_sg_rlast(m_axi_sg_rlast),
        .m_axi_sg_rready(m_axi_sg_rready),
        .m_axi_sg_rresp(m_axi_sg_rresp),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .m_axis_updt_sts_tready(m_axis_updt_sts_tready),
        .s_axis_ftch_cmd_tvalid(s_axis_ftch_cmd_tvalid),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0(\GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_12 ),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1(\GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_13 ),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2(\GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_14 ),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_3(\GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_15 ),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_4(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0),
        .sig_init_done(\I_CMD_STATUS/I_CMD_FIFO/sig_init_done ),
        .sig_init_done_0(\I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done ),
        .sig_init_done_1(\I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_done ),
        .sig_init_done_2(\I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_done ),
        .sig_stream_rst(sig_stream_rst));
  Loopback_axi_dma_1_0_axi_sg_s2mm_basic_wrap \GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER 
       (.D({D,ch1_updt_active}),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\GEN_ASYNC_RESET.scndry_resetn_reg ),
        .\GEN_CH1_UPDATE.ch1_active_i_reg (\GEN_CH1_UPDATE.ch1_active_i_reg ),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg (sig_cmd_stat_rst_user_reg_n_cdc_from_reg),
        .Q(Q),
        .follower_full_mm2s(follower_full_mm2s),
        .follower_full_mm2s0(follower_full_mm2s0),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_awaddr(m_axi_sg_awaddr),
        .m_axi_sg_awlen(m_axi_sg_awlen),
        .m_axi_sg_awready(m_axi_sg_awready),
        .m_axi_sg_awsize(m_axi_sg_awsize),
        .m_axi_sg_awvalid(m_axi_sg_awvalid),
        .m_axi_sg_bready(m_axi_sg_bready),
        .m_axi_sg_bresp(m_axi_sg_bresp),
        .m_axi_sg_bvalid(m_axi_sg_bvalid),
        .m_axi_sg_wlast(m_axi_sg_wlast),
        .m_axi_sg_wready(m_axi_sg_wready),
        .m_axi_sg_wvalid(m_axi_sg_wvalid),
        .m_axis_updt_sts_tready(m_axis_updt_sts_tready),
        .out(out),
        .s_axis_updt_cmd_tready(s_axis_updt_cmd_tready),
        .s_axis_updt_cmd_tvalid(s_axis_updt_cmd_tvalid),
        .sig_init_done(\I_CMD_STATUS/I_CMD_FIFO/sig_init_done ),
        .sig_init_done_0(\I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done ),
        .sig_init_done_1(\I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_done ),
        .sig_init_done_2(\I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_done ),
        .sig_init_done_reg(\GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_12 ),
        .sig_init_done_reg_0(\GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_13 ),
        .sig_init_done_reg_1(\GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_14 ),
        .sig_init_done_reg_2(\GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER_n_15 ),
        .sig_stream_rst(sig_stream_rst),
        .updt_decerr_i(updt_decerr_i),
        .updt_interr_i(updt_interr_i),
        .updt_slverr_i(updt_slverr_i));
endmodule

module Loopback_axi_dma_1_0_axi_sg_fifo
   (sig_init_done,
    s_axis_updt_cmd_tready,
    sig_load_input_cmd,
    Q,
    sig_init_done_reg_0,
    m_axi_sg_aclk,
    sig_stream_rst,
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ,
    sig_data2all_tlast_error,
    sig_addr2wsc_cmd_fifo_empty,
    sig_cmd_reg_empty,
    s_axis_updt_cmd_tvalid,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 );
  output sig_init_done;
  output s_axis_updt_cmd_tready;
  output sig_load_input_cmd;
  output [29:0]Q;
  input sig_init_done_reg_0;
  input m_axi_sg_aclk;
  input sig_stream_rst;
  input \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  input sig_data2all_tlast_error;
  input sig_addr2wsc_cmd_fifo_empty;
  input sig_cmd_reg_empty;
  input s_axis_updt_cmd_tvalid;
  input [28:0]\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 ;

  wire [29:0]Q;
  wire \USE_SINGLE_REG.sig_push_regfifo ;
  wire [28:0]\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__1_n_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_i_1__1_n_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  wire m_axi_sg_aclk;
  wire s_axis_updt_cmd_tready;
  wire s_axis_updt_cmd_tvalid;
  wire sig_addr2wsc_cmd_fifo_empty;
  wire sig_cmd2mstr_cmd_valid;
  wire sig_cmd_reg_empty;
  wire sig_data2all_tlast_error;
  wire sig_init_done;
  wire sig_init_done_reg_0;
  wire sig_load_input_cmd;
  wire sig_stream_rst;

  LUT2 #(
    .INIT(4'h8)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg[63]_i_1 
       (.I0(s_axis_updt_cmd_tready),
        .I1(s_axis_updt_cmd_tvalid),
        .O(\USE_SINGLE_REG.sig_push_regfifo ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [0]),
        .Q(Q[0]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[35] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(1'b1),
        .Q(Q[2]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[36] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [2]),
        .Q(Q[3]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[38] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [3]),
        .Q(Q[4]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[39] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [4]),
        .Q(Q[5]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [1]),
        .Q(Q[1]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[40] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [5]),
        .Q(Q[6]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[41] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [6]),
        .Q(Q[7]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[42] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [7]),
        .Q(Q[8]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[43] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [8]),
        .Q(Q[9]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[44] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [9]),
        .Q(Q[10]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[45] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [10]),
        .Q(Q[11]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[46] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [11]),
        .Q(Q[12]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[47] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [12]),
        .Q(Q[13]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[48] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [13]),
        .Q(Q[14]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[49] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [14]),
        .Q(Q[15]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[50] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [15]),
        .Q(Q[16]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[51] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [16]),
        .Q(Q[17]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[52] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [17]),
        .Q(Q[18]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[53] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [18]),
        .Q(Q[19]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[54] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [19]),
        .Q(Q[20]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[55] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [20]),
        .Q(Q[21]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[56] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [21]),
        .Q(Q[22]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[57] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [22]),
        .Q(Q[23]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[58] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [23]),
        .Q(Q[24]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[59] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [24]),
        .Q(Q[25]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[60] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [25]),
        .Q(Q[26]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[61] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [26]),
        .Q(Q[27]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[62] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [27]),
        .Q(Q[28]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0 [28]),
        .Q(Q[29]),
        .R(sig_stream_rst));
  LUT6 #(
    .INIT(64'hFF08FFFFFF08FF08)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__1 
       (.I0(sig_load_input_cmd),
        .I1(sig_addr2wsc_cmd_fifo_empty),
        .I2(sig_data2all_tlast_error),
        .I3(sig_init_done),
        .I4(s_axis_updt_cmd_tvalid),
        .I5(s_axis_updt_cmd_tready),
        .O(\USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__1_n_0 ),
        .Q(s_axis_updt_cmd_tready),
        .R(sig_stream_rst));
  LUT6 #(
    .INIT(64'hA0AA8888AAAA8888)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_i_1__1 
       (.I0(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .I1(\USE_SINGLE_REG.sig_push_regfifo ),
        .I2(sig_data2all_tlast_error),
        .I3(sig_addr2wsc_cmd_fifo_empty),
        .I4(sig_cmd2mstr_cmd_valid),
        .I5(sig_cmd_reg_empty),
        .O(\USE_SINGLE_REG.sig_regfifo_full_reg_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_full_reg_i_1__1_n_0 ),
        .Q(sig_cmd2mstr_cmd_valid),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    sig_cmd_reg_empty_i_2__0
       (.I0(sig_cmd2mstr_cmd_valid),
        .I1(sig_cmd_reg_empty),
        .O(sig_load_input_cmd));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_done_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_init_done_reg_0),
        .Q(sig_init_done),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "axi_sg_fifo" *) 
module Loopback_axi_dma_1_0_axi_sg_fifo_23
   (\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ,
    sig_load_input_cmd,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_3,
    Q,
    sig_init_reg_reg_0,
    m_axi_sg_aclk,
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ,
    s_axis_ftch_cmd_tvalid,
    sig_addr2rsc_cmd_fifo_empty,
    sig_cmd_reg_empty,
    sig_init_done_3,
    sig_init_done,
    sig_init_done_0,
    sig_init_done_1,
    sig_init_done_2,
    ftch_cmnd_data);
  output \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ;
  output sig_load_input_cmd;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_3;
  output [27:0]Q;
  input sig_init_reg_reg_0;
  input m_axi_sg_aclk;
  input \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  input s_axis_ftch_cmd_tvalid;
  input sig_addr2rsc_cmd_fifo_empty;
  input sig_cmd_reg_empty;
  input sig_init_done_3;
  input sig_init_done;
  input sig_init_done_0;
  input sig_init_done_1;
  input sig_init_done_2;
  input [26:0]ftch_cmnd_data;

  wire \GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg ;
  wire \GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg2 ;
  wire [27:0]Q;
  wire \USE_SINGLE_REG.sig_push_regfifo ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_i_1_n_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_i_1_n_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  wire [26:0]ftch_cmnd_data;
  wire m_axi_sg_aclk;
  wire s_axis_ftch_cmd_tvalid;
  wire sig_addr2rsc_cmd_fifo_empty;
  wire sig_cmd2mstr_cmd_valid;
  wire sig_cmd_reg_empty;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_3;
  wire sig_init_done;
  wire sig_init_done_0;
  wire sig_init_done_1;
  wire sig_init_done_2;
  wire sig_init_done_3;
  wire sig_init_done_4;
  wire sig_init_done_i_1_n_0;
  wire sig_init_reg_reg_0;
  wire sig_load_input_cmd;

  LUT2 #(
    .INIT(4'h8)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg[64]_i_1 
       (.I0(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .I1(s_axis_ftch_cmd_tvalid),
        .O(\USE_SINGLE_REG.sig_push_regfifo ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(1'b1),
        .Q(Q[0]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[38] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[1]),
        .Q(Q[1]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[39] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[2]),
        .Q(Q[2]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[40] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[3]),
        .Q(Q[3]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[41] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[4]),
        .Q(Q[4]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[42] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[5]),
        .Q(Q[5]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[43] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[6]),
        .Q(Q[6]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[44] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[7]),
        .Q(Q[7]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[45] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[8]),
        .Q(Q[8]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[46] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[9]),
        .Q(Q[9]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[47] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[10]),
        .Q(Q[10]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[48] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[11]),
        .Q(Q[11]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[49] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[12]),
        .Q(Q[12]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[50] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[13]),
        .Q(Q[13]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[51] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[14]),
        .Q(Q[14]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[52] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[15]),
        .Q(Q[15]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[53] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[16]),
        .Q(Q[16]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[54] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[17]),
        .Q(Q[17]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[55] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[18]),
        .Q(Q[18]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[56] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[19]),
        .Q(Q[19]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[57] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[20]),
        .Q(Q[20]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[58] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[21]),
        .Q(Q[21]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[59] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[22]),
        .Q(Q[22]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[60] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[23]),
        .Q(Q[23]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[61] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[24]),
        .Q(Q[24]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[62] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[25]),
        .Q(Q[25]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[26]),
        .Q(Q[26]),
        .R(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[64] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(ftch_cmnd_data[0]),
        .Q(Q[27]),
        .R(sig_init_reg_reg_0));
  LUT6 #(
    .INIT(64'hFF80FFFFFF80FF80)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_i_1 
       (.I0(sig_cmd_reg_empty),
        .I1(sig_cmd2mstr_cmd_valid),
        .I2(sig_addr2rsc_cmd_fifo_empty),
        .I3(sig_init_done_4),
        .I4(s_axis_ftch_cmd_tvalid),
        .I5(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .O(\USE_SINGLE_REG.sig_regfifo_empty_reg_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_empty_reg_i_1_n_0 ),
        .Q(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .R(sig_init_reg_reg_0));
  LUT6 #(
    .INIT(64'h00AA8080AAAA8080)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_i_1 
       (.I0(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .I1(s_axis_ftch_cmd_tvalid),
        .I2(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .I3(sig_addr2rsc_cmd_fifo_empty),
        .I4(sig_cmd2mstr_cmd_valid),
        .I5(sig_cmd_reg_empty),
        .O(\USE_SINGLE_REG.sig_regfifo_full_reg_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_full_reg_i_1_n_0 ),
        .Q(sig_cmd2mstr_cmd_valid),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    sig_cmd_reg_empty_i_2
       (.I0(sig_cmd2mstr_cmd_valid),
        .I1(sig_cmd_reg_empty),
        .O(sig_load_input_cmd));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    sig_init_done_i_1
       (.I0(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .I1(sig_init_done_4),
        .I2(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg ),
        .I3(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg2 ),
        .O(sig_init_done_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    sig_init_done_i_1__0
       (.I0(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .I1(sig_init_done_3),
        .I2(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg ),
        .I3(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg2 ),
        .O(sig_cmd_stat_rst_user_reg_n_cdc_from_reg));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    sig_init_done_i_1__1
       (.I0(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .I1(sig_init_done),
        .I2(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg ),
        .I3(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg2 ),
        .O(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    sig_init_done_i_1__2
       (.I0(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .I1(sig_init_done_0),
        .I2(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg ),
        .I3(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg2 ),
        .O(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    sig_init_done_i_1__3
       (.I0(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .I1(sig_init_done_1),
        .I2(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg ),
        .I3(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg2 ),
        .O(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    sig_init_done_i_1__4
       (.I0(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .I1(sig_init_done_2),
        .I2(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg ),
        .I3(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg2 ),
        .O(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_3));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_done_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_init_done_i_1_n_0),
        .Q(sig_init_done_4),
        .R(1'b0));
  FDSE #(
    .INIT(1'b0)) 
    sig_init_reg2_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg ),
        .Q(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg2 ),
        .S(sig_init_reg_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_init_reg_reg_0),
        .Q(\GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_init_reg ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "axi_sg_fifo" *) 
module Loopback_axi_dma_1_0_axi_sg_fifo__parameterized0
   (sig_init_done_0,
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ,
    updt_decerr_i,
    updt_interr_i,
    updt_slverr_i,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    m_axi_sg_aclk,
    sig_init_done_reg_0,
    sig_stream_rst,
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ,
    sig_wsc2stat_status_valid,
    m_axis_updt_sts_tready,
    out,
    D);
  output sig_init_done_0;
  output \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ;
  output updt_decerr_i;
  output updt_interr_i;
  output updt_slverr_i;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  input m_axi_sg_aclk;
  input sig_init_done_reg_0;
  input sig_stream_rst;
  input \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  input sig_wsc2stat_status_valid;
  input m_axis_updt_sts_tready;
  input out;
  input [3:0]D;

  wire [3:0]D;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \USE_SINGLE_REG.sig_push_regfifo ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__2_n_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_i_1__2_n_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  wire m_axi_sg_aclk;
  wire [7:4]m_axis_updt_sts_tdata;
  wire m_axis_updt_sts_tready;
  wire m_axis_updt_sts_tvalid;
  wire out;
  wire sig_init_done_0;
  wire sig_init_done_reg_0;
  wire sig_stream_rst;
  wire sig_wsc2stat_status_valid;
  wire updt_decerr_i;
  wire updt_interr_i;
  wire updt_slverr_i;

  LUT2 #(
    .INIT(4'h8)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg[7]_i_1__0 
       (.I0(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .I1(sig_wsc2stat_status_valid),
        .O(\USE_SINGLE_REG.sig_push_regfifo ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(D[0]),
        .Q(m_axis_updt_sts_tdata[4]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(D[1]),
        .Q(m_axis_updt_sts_tdata[5]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(D[2]),
        .Q(m_axis_updt_sts_tdata[6]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(D[3]),
        .Q(m_axis_updt_sts_tdata[7]),
        .R(sig_stream_rst));
  LUT5 #(
    .INIT(32'hF8FFF8F8)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__2 
       (.I0(m_axis_updt_sts_tvalid),
        .I1(m_axis_updt_sts_tready),
        .I2(sig_init_done_0),
        .I3(sig_wsc2stat_status_valid),
        .I4(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .O(\USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__2_n_0 ),
        .Q(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .R(sig_stream_rst));
  LUT5 #(
    .INIT(32'h00AA8080)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_i_1__2 
       (.I0(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .I1(sig_wsc2stat_status_valid),
        .I2(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .I3(m_axis_updt_sts_tready),
        .I4(m_axis_updt_sts_tvalid),
        .O(\USE_SINGLE_REG.sig_regfifo_full_reg_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_full_reg_i_1__2_n_0 ),
        .Q(m_axis_updt_sts_tvalid),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_done_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_init_done_reg_0),
        .Q(sig_init_done_0),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    updt_decerr_i_i_1
       (.I0(m_axis_updt_sts_tdata[5]),
        .I1(m_axis_updt_sts_tvalid),
        .O(updt_decerr_i));
  LUT6 #(
    .INIT(64'h8888888888888880)) 
    updt_done_i_1
       (.I0(out),
        .I1(m_axis_updt_sts_tvalid),
        .I2(m_axis_updt_sts_tdata[6]),
        .I3(m_axis_updt_sts_tdata[7]),
        .I4(m_axis_updt_sts_tdata[5]),
        .I5(m_axis_updt_sts_tdata[4]),
        .O(\GEN_ASYNC_RESET.scndry_resetn_reg ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT2 #(
    .INIT(4'h8)) 
    updt_interr_i_i_1
       (.I0(m_axis_updt_sts_tvalid),
        .I1(m_axis_updt_sts_tdata[4]),
        .O(updt_interr_i));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT2 #(
    .INIT(4'h8)) 
    updt_slverr_i_i_1
       (.I0(m_axis_updt_sts_tvalid),
        .I1(m_axis_updt_sts_tdata[6]),
        .O(updt_slverr_i));
endmodule

(* ORIG_REF_NAME = "axi_sg_fifo" *) 
module Loopback_axi_dma_1_0_axi_sg_fifo__parameterized0_22
   (sig_init_done,
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7]_0 ,
    ftch_decerr_i,
    ftch_slverr_i,
    sig_init_done_reg_0,
    m_axi_sg_aclk,
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_1 ,
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ,
    sig_rsc2stat_status_valid,
    m_axis_updt_sts_tready,
    D);
  output sig_init_done;
  output \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ;
  output \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7]_0 ;
  output ftch_decerr_i;
  output ftch_slverr_i;
  input sig_init_done_reg_0;
  input m_axi_sg_aclk;
  input \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_1 ;
  input \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  input sig_rsc2stat_status_valid;
  input m_axis_updt_sts_tready;
  input [2:0]D;

  wire [2:0]D;
  wire \USE_SINGLE_REG.sig_push_regfifo ;
  wire \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7]_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__0_n_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_reg_1 ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_i_1__0_n_0 ;
  wire \USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ;
  wire ftch_decerr_i;
  wire ftch_slverr_i;
  wire m_axi_sg_aclk;
  wire [7:5]m_axis_ftch_sts_tdata;
  wire m_axis_ftch_sts_tvalid;
  wire m_axis_updt_sts_tready;
  wire sig_init_done;
  wire sig_init_done_reg_0;
  wire sig_rsc2stat_status_valid;

  LUT2 #(
    .INIT(4'h8)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg[7]_i_1 
       (.I0(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .I1(sig_rsc2stat_status_valid),
        .O(\USE_SINGLE_REG.sig_push_regfifo ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(D[0]),
        .Q(m_axis_ftch_sts_tdata[5]),
        .R(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(D[1]),
        .Q(m_axis_ftch_sts_tdata[6]),
        .R(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(\USE_SINGLE_REG.sig_push_regfifo ),
        .D(D[2]),
        .Q(m_axis_ftch_sts_tdata[7]),
        .R(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_1 ));
  LUT5 #(
    .INIT(32'hF8FFF8F8)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__0 
       (.I0(m_axis_ftch_sts_tvalid),
        .I1(m_axis_updt_sts_tready),
        .I2(sig_init_done),
        .I3(sig_rsc2stat_status_valid),
        .I4(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .O(\USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_empty_reg_i_1__0_n_0 ),
        .Q(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .R(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_1 ));
  LUT5 #(
    .INIT(32'h00AA8080)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_i_1__0 
       (.I0(\USE_SINGLE_REG.sig_regfifo_full_reg_reg_0 ),
        .I1(sig_rsc2stat_status_valid),
        .I2(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg_0 ),
        .I3(m_axis_updt_sts_tready),
        .I4(m_axis_ftch_sts_tvalid),
        .O(\USE_SINGLE_REG.sig_regfifo_full_reg_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \USE_SINGLE_REG.sig_regfifo_full_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\USE_SINGLE_REG.sig_regfifo_full_reg_i_1__0_n_0 ),
        .Q(m_axis_ftch_sts_tvalid),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT2 #(
    .INIT(4'h8)) 
    ftch_decerr_i_i_1
       (.I0(m_axis_ftch_sts_tvalid),
        .I1(m_axis_ftch_sts_tdata[5]),
        .O(ftch_decerr_i));
  LUT2 #(
    .INIT(4'h8)) 
    ftch_done_i_1
       (.I0(m_axis_ftch_sts_tdata[7]),
        .I1(m_axis_ftch_sts_tvalid),
        .O(\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT2 #(
    .INIT(4'h8)) 
    ftch_slverr_i_i_1
       (.I0(m_axis_ftch_sts_tvalid),
        .I1(m_axis_ftch_sts_tdata[6]),
        .O(ftch_slverr_i));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_done_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_init_done_reg_0),
        .Q(sig_init_done),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "axi_sg_fifo" *) 
module Loopback_axi_dma_1_0_axi_sg_fifo__parameterized1
   (sig_init_done_1,
    Q,
    m_axi_sg_bready,
    sig_coelsc_decerr_reg0,
    out,
    sig_coelsc_slverr_reg0,
    sig_stream_rst,
    m_axi_sg_aclk,
    sig_init_done_reg_0,
    \INFERRED_GEN.cnt_i_reg[0] ,
    m_axi_sg_bvalid,
    \INFERRED_GEN.cnt_i_reg[1] ,
    D,
    \GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ,
    m_axi_sg_bresp);
  output sig_init_done_1;
  output [0:0]Q;
  output m_axi_sg_bready;
  output sig_coelsc_decerr_reg0;
  output [0:0]out;
  output sig_coelsc_slverr_reg0;
  input sig_stream_rst;
  input m_axi_sg_aclk;
  input sig_init_done_reg_0;
  input \INFERRED_GEN.cnt_i_reg[0] ;
  input m_axi_sg_bvalid;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input [1:0]D;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ;
  input [1:0]m_axi_sg_bresp;

  wire [1:0]D;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ;
  wire \INFERRED_GEN.cnt_i_reg[0] ;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire [0:0]Q;
  wire m_axi_sg_aclk;
  wire m_axi_sg_bready;
  wire [1:0]m_axi_sg_bresp;
  wire m_axi_sg_bvalid;
  wire [0:0]out;
  wire sig_coelsc_decerr_reg0;
  wire sig_coelsc_slverr_reg0;
  wire sig_inhibit_rdy_n;
  wire sig_inhibit_rdy_n_i_1_n_0;
  wire sig_init_done_1;
  wire sig_init_done_reg_0;
  wire sig_stream_rst;

  Loopback_axi_dma_1_0_srl_fifo_f \USE_SRL_FIFO.I_SYNC_FIFO 
       (.D(D),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ),
        .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ),
        .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ),
        .Q(Q),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_bready(m_axi_sg_bready),
        .m_axi_sg_bresp(m_axi_sg_bresp),
        .m_axi_sg_bvalid(m_axi_sg_bvalid),
        .out(out),
        .sig_coelsc_decerr_reg0(sig_coelsc_decerr_reg0),
        .sig_coelsc_slverr_reg0(sig_coelsc_slverr_reg0),
        .sig_inhibit_rdy_n(sig_inhibit_rdy_n),
        .sig_stream_rst(sig_stream_rst));
  LUT2 #(
    .INIT(4'hE)) 
    sig_inhibit_rdy_n_i_1
       (.I0(sig_init_done_1),
        .I1(sig_inhibit_rdy_n),
        .O(sig_inhibit_rdy_n_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_inhibit_rdy_n_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_inhibit_rdy_n_i_1_n_0),
        .Q(sig_inhibit_rdy_n),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_done_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_init_done_reg_0),
        .Q(sig_init_done_1),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "axi_sg_fifo" *) 
module Loopback_axi_dma_1_0_axi_sg_fifo__parameterized2
   (FIFO_Full_reg,
    sig_init_done_2,
    sig_coelsc_interr_reg0,
    out,
    \INFERRED_GEN.cnt_i_reg[2] ,
    sig_inhibit_rdy_n_reg_0,
    E,
    \sig_wdc_statcnt_reg[2] ,
    sig_push_coelsc_reg,
    FIFO_Full_reg_0,
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ,
    sig_data2wsc_cmd_cmplt_reg,
    \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ,
    sig_stream_rst,
    m_axi_sg_aclk,
    sig_init_done_reg_0,
    D,
    \USE_SRL_FIFO.sig_wr_fifo ,
    sig_push_to_wsc,
    sig_tlast_err_stop,
    Q,
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ,
    sig_coelsc_reg_empty,
    \GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ,
    in);
  output FIFO_Full_reg;
  output sig_init_done_2;
  output sig_coelsc_interr_reg0;
  output [1:0]out;
  output \INFERRED_GEN.cnt_i_reg[2] ;
  output sig_inhibit_rdy_n_reg_0;
  output [0:0]E;
  output [1:0]\sig_wdc_statcnt_reg[2] ;
  output sig_push_coelsc_reg;
  output FIFO_Full_reg_0;
  output \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ;
  output sig_data2wsc_cmd_cmplt_reg;
  output \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ;
  input sig_stream_rst;
  input m_axi_sg_aclk;
  input sig_init_done_reg_0;
  input [2:0]D;
  input \USE_SRL_FIFO.sig_wr_fifo ;
  input sig_push_to_wsc;
  input sig_tlast_err_stop;
  input [2:0]Q;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ;
  input sig_coelsc_reg_empty;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ;
  input [2:0]in;

  wire [2:0]D;
  wire [0:0]E;
  wire FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ;
  wire \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ;
  wire \INFERRED_GEN.cnt_i_reg[2] ;
  wire [2:0]Q;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire [2:0]in;
  wire m_axi_sg_aclk;
  wire [1:0]out;
  wire sig_coelsc_interr_reg0;
  wire sig_coelsc_reg_empty;
  wire sig_data2wsc_cmd_cmplt_reg;
  wire sig_inhibit_rdy_n_i_1_n_0;
  wire sig_inhibit_rdy_n_reg_0;
  wire sig_init_done_2;
  wire sig_init_done_reg_0;
  wire sig_push_coelsc_reg;
  wire sig_push_to_wsc;
  wire sig_stream_rst;
  wire sig_tlast_err_stop;
  wire [1:0]\sig_wdc_statcnt_reg[2] ;

  Loopback_axi_dma_1_0_srl_fifo_f__parameterized0 \USE_SRL_FIFO.I_SYNC_FIFO 
       (.D(D),
        .E(E),
        .FIFO_Full_reg(FIFO_Full_reg),
        .FIFO_Full_reg_0(FIFO_Full_reg_0),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .\INFERRED_GEN.cnt_i_reg[0] (sig_inhibit_rdy_n_reg_0),
        .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ),
        .Q(Q),
        .\USE_SRL_FIFO.sig_wr_fifo (\USE_SRL_FIFO.sig_wr_fifo ),
        .in(in),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .out(out),
        .sig_coelsc_interr_reg0(sig_coelsc_interr_reg0),
        .sig_coelsc_reg_empty(sig_coelsc_reg_empty),
        .sig_data2wsc_cmd_cmplt_reg(sig_data2wsc_cmd_cmplt_reg),
        .sig_push_coelsc_reg(sig_push_coelsc_reg),
        .sig_push_to_wsc(sig_push_to_wsc),
        .sig_stream_rst(sig_stream_rst),
        .sig_tlast_err_stop(sig_tlast_err_stop),
        .\sig_wdc_statcnt_reg[2] (\sig_wdc_statcnt_reg[2] ));
  LUT2 #(
    .INIT(4'hE)) 
    sig_inhibit_rdy_n_i_1
       (.I0(sig_init_done_2),
        .I1(sig_inhibit_rdy_n_reg_0),
        .O(sig_inhibit_rdy_n_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_inhibit_rdy_n_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_inhibit_rdy_n_i_1_n_0),
        .Q(sig_inhibit_rdy_n_reg_0),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    sig_init_done_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_init_done_reg_0),
        .Q(sig_init_done_2),
        .R(1'b0));
endmodule

module Loopback_axi_dma_1_0_axi_sg_ftch_cmdsts_if
   (m_axis_updt_sts_tready,
    ftch_done,
    ftch_decerr,
    ftch_slverr,
    s_axis_ftch_cmd_tvalid,
    ftch_error_reg_0,
    ftch_error_early,
    out,
    m_axi_sg_aclk,
    sinit,
    ftch_done_reg_0,
    ftch_decerr_i,
    ftch_slverr_i,
    m_axi_sg_rresp,
    m_axi_sg_rvalid,
    s_axis_ftch_cmd_tvalid_reg_0);
  output m_axis_updt_sts_tready;
  output ftch_done;
  output ftch_decerr;
  output ftch_slverr;
  output s_axis_ftch_cmd_tvalid;
  output ftch_error_reg_0;
  output ftch_error_early;
  input out;
  input m_axi_sg_aclk;
  input sinit;
  input ftch_done_reg_0;
  input ftch_decerr_i;
  input ftch_slverr_i;
  input [0:0]m_axi_sg_rresp;
  input m_axi_sg_rvalid;
  input s_axis_ftch_cmd_tvalid_reg_0;

  wire ftch_decerr;
  wire ftch_decerr_i;
  wire ftch_done;
  wire ftch_done_reg_0;
  wire ftch_error_early;
  wire ftch_error_early_i_1_n_0;
  wire ftch_error_i_1_n_0;
  wire ftch_error_reg_0;
  wire ftch_slverr;
  wire ftch_slverr_i;
  wire m_axi_sg_aclk;
  wire [0:0]m_axi_sg_rresp;
  wire m_axi_sg_rvalid;
  wire m_axis_updt_sts_tready;
  wire out;
  wire s_axis_ftch_cmd_tvalid;
  wire s_axis_ftch_cmd_tvalid_reg_0;
  wire [1:1]sg_rresp;
  wire sg_rvalid;
  wire sinit;

  FDRE #(
    .INIT(1'b0)) 
    ftch_decerr_i_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ftch_decerr_i),
        .Q(ftch_decerr),
        .R(sinit));
  FDRE ftch_done_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ftch_done_reg_0),
        .Q(ftch_done),
        .R(sinit));
  LUT3 #(
    .INIT(8'hF8)) 
    ftch_error_early_i_1
       (.I0(sg_rresp),
        .I1(sg_rvalid),
        .I2(ftch_error_early),
        .O(ftch_error_early_i_1_n_0));
  FDRE ftch_error_early_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ftch_error_early_i_1_n_0),
        .Q(ftch_error_early),
        .R(sinit));
  LUT3 #(
    .INIT(8'hFE)) 
    ftch_error_i_1
       (.I0(ftch_decerr),
        .I1(ftch_slverr),
        .I2(ftch_error_reg_0),
        .O(ftch_error_i_1_n_0));
  FDRE ftch_error_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ftch_error_i_1_n_0),
        .Q(ftch_error_reg_0),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    ftch_slverr_i_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ftch_slverr_i),
        .Q(ftch_slverr),
        .R(sinit));
  FDRE m_axis_ftch_sts_tready_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(out),
        .Q(m_axis_updt_sts_tready),
        .R(1'b0));
  FDRE s_axis_ftch_cmd_tvalid_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axis_ftch_cmd_tvalid_reg_0),
        .Q(s_axis_ftch_cmd_tvalid),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \sg_rresp_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(m_axi_sg_rresp),
        .Q(sg_rresp),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    sg_rvalid_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(m_axi_sg_rvalid),
        .Q(sg_rvalid),
        .R(sinit));
endmodule

module Loopback_axi_dma_1_0_axi_sg_ftch_mngr
   (m_axis_updt_sts_tready,
    CO,
    mm2s_ftch_idle,
    ch1_use_crntdesc,
    \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg ,
    s_axis_ftch_cmd_tvalid,
    ftch_error,
    SR,
    \GEN_CH1_FETCH.ch1_active_i_reg ,
    ftch_cmnd_data,
    E,
    m_axi_sg_rvalid_0,
    \GEN_CH1_FETCH.ch1_active_i_reg_0 ,
    \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ,
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ,
    D,
    sg_ftch_error0,
    \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg ,
    \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_0 ,
    \GEN_CH1_FETCH.ch1_ftch_slverr_set_reg ,
    \GEN_CH1_FETCH.ch1_ftch_decerr_set_reg ,
    sinit,
    mm2s_dmacr,
    m_axi_sg_aclk,
    out,
    ftch_done_reg,
    ftch_decerr_i,
    ftch_slverr_i,
    m_axi_sg_rresp,
    m_axi_sg_rvalid,
    S,
    \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_0 ,
    soft_reset,
    ch1_ftch_queue_empty,
    mm2s_stop_i,
    updt_error,
    ch1_ftch_pause,
    dma_mm2s_error,
    \GEN_PNTR_FOR_CH1.ch1_use_crntdesc_reg ,
    Q,
    m_axi_sg_rdata,
    \ch1_sg_idle1_inferred__0/i__carry ,
    \ftch_error_addr_reg[31] ,
    s_axis_ftch_cmd_tready,
    mm2s_updt_interr_set,
    sg_interr_reg,
    mm2s_updt_slverr_set,
    sg_slverr_reg,
    mm2s_updt_decerr_set,
    sg_decerr_reg,
    ftch_stale_desc,
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6] ,
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 );
  output m_axis_updt_sts_tready;
  output [0:0]CO;
  output mm2s_ftch_idle;
  output ch1_use_crntdesc;
  output \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg ;
  output s_axis_ftch_cmd_tvalid;
  output ftch_error;
  output [0:0]SR;
  output \GEN_CH1_FETCH.ch1_active_i_reg ;
  output [26:0]ftch_cmnd_data;
  output [0:0]E;
  output m_axi_sg_rvalid_0;
  output \GEN_CH1_FETCH.ch1_active_i_reg_0 ;
  output \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  output [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ;
  output [25:0]D;
  output sg_ftch_error0;
  output \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg ;
  output \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_0 ;
  output \GEN_CH1_FETCH.ch1_ftch_slverr_set_reg ;
  output \GEN_CH1_FETCH.ch1_ftch_decerr_set_reg ;
  input sinit;
  input [1:0]mm2s_dmacr;
  input m_axi_sg_aclk;
  input out;
  input ftch_done_reg;
  input ftch_decerr_i;
  input ftch_slverr_i;
  input [0:0]m_axi_sg_rresp;
  input m_axi_sg_rvalid;
  input [6:0]S;
  input \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_0 ;
  input soft_reset;
  input ch1_ftch_queue_empty;
  input mm2s_stop_i;
  input updt_error;
  input ch1_ftch_pause;
  input dma_mm2s_error;
  input \GEN_PNTR_FOR_CH1.ch1_use_crntdesc_reg ;
  input [1:0]Q;
  input [0:0]m_axi_sg_rdata;
  input [5:0]\ch1_sg_idle1_inferred__0/i__carry ;
  input [25:0]\ftch_error_addr_reg[31] ;
  input s_axis_ftch_cmd_tready;
  input mm2s_updt_interr_set;
  input sg_interr_reg;
  input mm2s_updt_slverr_set;
  input sg_slverr_reg;
  input mm2s_updt_decerr_set;
  input sg_decerr_reg;
  input ftch_stale_desc;
  input [0:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6] ;
  input [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 ;

  wire [0:0]CO;
  wire [25:0]D;
  wire [0:0]E;
  wire \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  wire \GEN_CH1_FETCH.ch1_active_i_reg ;
  wire \GEN_CH1_FETCH.ch1_active_i_reg_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_decerr_set_reg ;
  wire \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg ;
  wire \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_slverr_set_reg ;
  wire [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ;
  wire [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 ;
  wire [0:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6] ;
  wire \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg ;
  wire \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_0 ;
  wire \GEN_PNTR_FOR_CH1.ch1_use_crntdesc_reg ;
  wire I_FTCH_PNTR_MNGR_n_3;
  wire I_FTCH_SG_n_63;
  wire [1:0]Q;
  wire [6:0]S;
  wire [0:0]SR;
  wire ch1_ftch_pause;
  wire ch1_ftch_queue_empty;
  wire [5:0]\ch1_sg_idle1_inferred__0/i__carry ;
  wire ch1_use_crntdesc;
  wire dma_mm2s_error;
  wire [26:0]ftch_cmnd_data;
  wire ftch_decerr;
  wire ftch_decerr_i;
  wire ftch_done;
  wire ftch_done_reg;
  wire ftch_error;
  wire [25:0]\ftch_error_addr_reg[31] ;
  wire ftch_error_early;
  wire ftch_slverr;
  wire ftch_slverr_i;
  wire ftch_stale_desc;
  wire m_axi_sg_aclk;
  wire [0:0]m_axi_sg_rdata;
  wire [0:0]m_axi_sg_rresp;
  wire m_axi_sg_rvalid;
  wire m_axi_sg_rvalid_0;
  wire m_axis_updt_sts_tready;
  wire [1:0]mm2s_dmacr;
  wire mm2s_ftch_idle;
  wire mm2s_ftch_stale_desc;
  wire mm2s_stop_i;
  wire mm2s_updt_decerr_set;
  wire mm2s_updt_interr_set;
  wire mm2s_updt_slverr_set;
  wire out;
  wire s_axis_ftch_cmd_tready;
  wire s_axis_ftch_cmd_tvalid;
  wire sg_decerr_reg;
  wire sg_ftch_error0;
  wire sg_interr_reg;
  wire sg_slverr_reg;
  wire sinit;
  wire soft_reset;
  wire updt_error;

  Loopback_axi_dma_1_0_axi_sg_ftch_cmdsts_if I_FTCH_CMDSTS_IF
       (.ftch_decerr(ftch_decerr),
        .ftch_decerr_i(ftch_decerr_i),
        .ftch_done(ftch_done),
        .ftch_done_reg_0(ftch_done_reg),
        .ftch_error_early(ftch_error_early),
        .ftch_error_reg_0(ftch_error),
        .ftch_slverr(ftch_slverr),
        .ftch_slverr_i(ftch_slverr_i),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_rresp(m_axi_sg_rresp),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .m_axis_updt_sts_tready(m_axis_updt_sts_tready),
        .out(out),
        .s_axis_ftch_cmd_tvalid(s_axis_ftch_cmd_tvalid),
        .s_axis_ftch_cmd_tvalid_reg_0(I_FTCH_SG_n_63),
        .sinit(sinit));
  Loopback_axi_dma_1_0_axi_sg_ftch_pntr I_FTCH_PNTR_MNGR
       (.CO(CO),
        .\GEN_MM2S.queue_full_new_reg (I_FTCH_PNTR_MNGR_n_3),
        .\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 (\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ),
        .\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 (\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 ),
        .\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 (\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6] ),
        .\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_0 (\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg ),
        .\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_1 (\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_0 ),
        .\GEN_PNTR_FOR_CH1.ch1_use_crntdesc_reg_0 (\GEN_PNTR_FOR_CH1.ch1_use_crntdesc_reg ),
        .S(S),
        .ch1_ftch_pause(ch1_ftch_pause),
        .\ch1_sg_idle1_inferred__0/i__carry_0 (\ch1_sg_idle1_inferred__0/i__carry ),
        .ch1_use_crntdesc(ch1_use_crntdesc),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .mm2s_dmacr(mm2s_dmacr[0]),
        .mm2s_ftch_stale_desc(mm2s_ftch_stale_desc),
        .out(out),
        .sinit(sinit),
        .updt_error(updt_error));
  Loopback_axi_dma_1_0_axi_sg_ftch_sm I_FTCH_SG
       (.D(D),
        .E(E),
        .\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 (\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ),
        .\FSM_sequential_ftch_cs_reg[1]_0 (ftch_error),
        .\GEN_CH1_FETCH.ch1_active_i_reg_0 (\GEN_CH1_FETCH.ch1_active_i_reg ),
        .\GEN_CH1_FETCH.ch1_active_i_reg_1 (ftch_cmnd_data[0]),
        .\GEN_CH1_FETCH.ch1_active_i_reg_2 (\GEN_CH1_FETCH.ch1_active_i_reg_0 ),
        .\GEN_CH1_FETCH.ch1_ftch_decerr_set_reg_0 (\GEN_CH1_FETCH.ch1_ftch_decerr_set_reg ),
        .\GEN_CH1_FETCH.ch1_ftch_idle_reg_0 (\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg ),
        .\GEN_CH1_FETCH.ch1_ftch_idle_reg_1 (I_FTCH_PNTR_MNGR_n_3),
        .\GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_0 (\GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg ),
        .\GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_1 (\GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_0 ),
        .\GEN_CH1_FETCH.ch1_ftch_slverr_set_reg_0 (\GEN_CH1_FETCH.ch1_ftch_slverr_set_reg ),
        .Q(Q),
        .SR(SR),
        .\USE_SINGLE_REG.sig_regfifo_empty_reg_reg (I_FTCH_SG_n_63),
        .ch1_ftch_pause(ch1_ftch_pause),
        .ch1_ftch_queue_empty(ch1_ftch_queue_empty),
        .dma_mm2s_error(dma_mm2s_error),
        .ftch_cmnd_data(ftch_cmnd_data[26:1]),
        .ftch_decerr(ftch_decerr),
        .ftch_done(ftch_done),
        .\ftch_error_addr_reg[31]_0 (\ftch_error_addr_reg[31] ),
        .\ftch_error_addr_reg[31]_1 (\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ),
        .ftch_error_early(ftch_error_early),
        .ftch_slverr(ftch_slverr),
        .ftch_stale_desc(ftch_stale_desc),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_rdata(m_axi_sg_rdata),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .m_axi_sg_rvalid_0(m_axi_sg_rvalid_0),
        .mm2s_dmacr(mm2s_dmacr),
        .mm2s_ftch_idle(mm2s_ftch_idle),
        .mm2s_ftch_stale_desc(mm2s_ftch_stale_desc),
        .mm2s_stop_i(mm2s_stop_i),
        .mm2s_updt_decerr_set(mm2s_updt_decerr_set),
        .mm2s_updt_interr_set(mm2s_updt_interr_set),
        .mm2s_updt_slverr_set(mm2s_updt_slverr_set),
        .out(out),
        .s_axis_ftch_cmd_tready(s_axis_ftch_cmd_tready),
        .s_axis_ftch_cmd_tvalid(s_axis_ftch_cmd_tvalid),
        .sg_decerr_reg(sg_decerr_reg),
        .sg_ftch_error0(sg_ftch_error0),
        .sg_interr_reg(sg_interr_reg),
        .sg_slverr_reg(sg_slverr_reg),
        .sinit(sinit),
        .soft_reset(soft_reset),
        .updt_error(updt_error));
endmodule

module Loopback_axi_dma_1_0_axi_sg_ftch_pntr
   (CO,
    ch1_use_crntdesc,
    \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_0 ,
    \GEN_MM2S.queue_full_new_reg ,
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 ,
    sinit,
    mm2s_dmacr,
    m_axi_sg_aclk,
    S,
    \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_1 ,
    ch1_ftch_pause,
    updt_error,
    mm2s_ftch_stale_desc,
    \GEN_PNTR_FOR_CH1.ch1_use_crntdesc_reg_0 ,
    out,
    \ch1_sg_idle1_inferred__0/i__carry_0 ,
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ,
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 );
  output [0:0]CO;
  output ch1_use_crntdesc;
  output \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_0 ;
  output \GEN_MM2S.queue_full_new_reg ;
  output [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 ;
  input sinit;
  input [0:0]mm2s_dmacr;
  input m_axi_sg_aclk;
  input [6:0]S;
  input \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_1 ;
  input ch1_ftch_pause;
  input updt_error;
  input mm2s_ftch_stale_desc;
  input \GEN_PNTR_FOR_CH1.ch1_use_crntdesc_reg_0 ;
  input out;
  input [5:0]\ch1_sg_idle1_inferred__0/i__carry_0 ;
  input [0:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ;
  input [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 ;

  wire [0:0]CO;
  wire \GEN_MM2S.queue_full_new_reg ;
  wire [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 ;
  wire [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 ;
  wire [0:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ;
  wire \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_0 ;
  wire \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_1 ;
  wire \GEN_PNTR_FOR_CH1.ch1_use_crntdesc_i_1_n_0 ;
  wire \GEN_PNTR_FOR_CH1.ch1_use_crntdesc_reg_0 ;
  wire [6:0]S;
  wire ch1_ftch_pause;
  wire ch1_run_stop_d1;
  wire [5:0]\ch1_sg_idle1_inferred__0/i__carry_0 ;
  wire \ch1_sg_idle1_inferred__0/i__carry_n_1 ;
  wire \ch1_sg_idle1_inferred__0/i__carry_n_2 ;
  wire \ch1_sg_idle1_inferred__0/i__carry_n_3 ;
  wire \ch1_sg_idle1_inferred__0/i__carry_n_4 ;
  wire \ch1_sg_idle1_inferred__0/i__carry_n_5 ;
  wire \ch1_sg_idle1_inferred__0/i__carry_n_6 ;
  wire \ch1_sg_idle1_inferred__0/i__carry_n_7 ;
  wire ch1_use_crntdesc;
  wire i__carry_i_1_n_0;
  wire i__carry_i_9_n_0;
  wire m_axi_sg_aclk;
  wire [0:0]mm2s_dmacr;
  wire mm2s_ftch_stale_desc;
  wire out;
  wire sinit;
  wire updt_error;
  wire [7:0]\NLW_ch1_sg_idle1_inferred__0/i__carry_O_UNCONNECTED ;

  LUT5 #(
    .INIT(32'h00010000)) 
    \GEN_CH1_FETCH.ch1_ftch_idle_i_5 
       (.I0(ch1_ftch_pause),
        .I1(\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_0 ),
        .I2(updt_error),
        .I3(mm2s_ftch_stale_desc),
        .I4(mm2s_dmacr),
        .O(\GEN_MM2S.queue_full_new_reg ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [4]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [5]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [5]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [6]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [7]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [8]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [9]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [9]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [10]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [11]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [12]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [13]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [14]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [15]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [16]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [17]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [18]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [19]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [20]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [21]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [22]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [23]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [24]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [25]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [0]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [0]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [1]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [2]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [2]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[6]_0 ),
        .D(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_1 [3]),
        .Q(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [3]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_run_stop_d1_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_dmacr),
        .Q(ch1_run_stop_d1),
        .R(sinit));
  FDRE \GEN_PNTR_FOR_CH1.ch1_sg_idle_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_1 ),
        .Q(\GEN_PNTR_FOR_CH1.ch1_sg_idle_reg_0 ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h40404440)) 
    \GEN_PNTR_FOR_CH1.ch1_use_crntdesc_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_use_crntdesc_reg_0 ),
        .I1(out),
        .I2(ch1_use_crntdesc),
        .I3(mm2s_dmacr),
        .I4(ch1_run_stop_d1),
        .O(\GEN_PNTR_FOR_CH1.ch1_use_crntdesc_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_PNTR_FOR_CH1.ch1_use_crntdesc_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_PNTR_FOR_CH1.ch1_use_crntdesc_i_1_n_0 ),
        .Q(ch1_use_crntdesc),
        .R(1'b0));
  CARRY8 \ch1_sg_idle1_inferred__0/i__carry 
       (.CI(i__carry_i_1_n_0),
        .CI_TOP(1'b0),
        .CO({CO,\ch1_sg_idle1_inferred__0/i__carry_n_1 ,\ch1_sg_idle1_inferred__0/i__carry_n_2 ,\ch1_sg_idle1_inferred__0/i__carry_n_3 ,\ch1_sg_idle1_inferred__0/i__carry_n_4 ,\ch1_sg_idle1_inferred__0/i__carry_n_5 ,\ch1_sg_idle1_inferred__0/i__carry_n_6 ,\ch1_sg_idle1_inferred__0/i__carry_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O(\NLW_ch1_sg_idle1_inferred__0/i__carry_O_UNCONNECTED [7:0]),
        .S({S,i__carry_i_9_n_0}));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    i__carry_i_1
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [2]),
        .I1(\ch1_sg_idle1_inferred__0/i__carry_0 [2]),
        .I2(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [0]),
        .I3(\ch1_sg_idle1_inferred__0/i__carry_0 [0]),
        .I4(\ch1_sg_idle1_inferred__0/i__carry_0 [1]),
        .I5(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [1]),
        .O(i__carry_i_1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    i__carry_i_9
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [3]),
        .I1(\ch1_sg_idle1_inferred__0/i__carry_0 [3]),
        .I2(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [4]),
        .I3(\ch1_sg_idle1_inferred__0/i__carry_0 [4]),
        .I4(\ch1_sg_idle1_inferred__0/i__carry_0 [5]),
        .I5(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_0 [5]),
        .O(i__carry_i_9_n_0));
endmodule

module Loopback_axi_dma_1_0_axi_sg_ftch_q_mngr
   (ch1_ftch_queue_empty,
    ch1_ftch_pause,
    \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ,
    \GEN_MM2S.queue_dout_valid_reg ,
    ftch_stale_desc,
    m_axis_mm2s_cntrl_tlast,
    m_axis_mm2s_cntrl_tvalid,
    Q,
    \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_1 ,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    \GEN_ASYNC_RESET.scndry_resetn_reg_0 ,
    \GEN_MM2S.queue_dout_new_reg[90] ,
    \GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] ,
    \GEN_MM2S.queue_dout_new_reg[64] ,
    m_axis_mm2s_cntrl_tdata,
    rst,
    m_axi_sg_aclk,
    m_axi_sg_rlast,
    sinit,
    mm2s_cntrl_strm_stop,
    queue_empty_new0,
    \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_2 ,
    out,
    m_axi_sg_rvalid,
    \GEN_MM2S.queue_dout_new_reg[90]_0 ,
    \GEN_MM2S.reg1_reg[90] ,
    m_axis_mm2s_cntrl_tready,
    m_axis_mm2s_cntrl_tvalid_0,
    soft_reset_d1,
    soft_reset_d2,
    \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ,
    \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ,
    \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_1 ,
    ftch_cmnd_data,
    ch1_use_crntdesc,
    ptr_queue_full,
    s_axis_mm2s_updtptr_tlast,
    packet_in_progress,
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ,
    m_axi_sg_rdata,
    mm2s_dmacr,
    s_axis_mm2s_cmd_tready,
    s_axis_mm2s_cmd_tvalid_split,
    E,
    D,
    \counter_reg[1]_0 );
  output ch1_ftch_queue_empty;
  output ch1_ftch_pause;
  output \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ;
  output \GEN_MM2S.queue_dout_valid_reg ;
  output ftch_stale_desc;
  output m_axis_mm2s_cntrl_tlast;
  output m_axis_mm2s_cntrl_tvalid;
  output [1:0]Q;
  output [0:0]\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_1 ;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  output \GEN_ASYNC_RESET.scndry_resetn_reg_0 ;
  output [85:0]\GEN_MM2S.queue_dout_new_reg[90] ;
  output [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] ;
  output \GEN_MM2S.queue_dout_new_reg[64] ;
  output [31:0]m_axis_mm2s_cntrl_tdata;
  input rst;
  input m_axi_sg_aclk;
  input m_axi_sg_rlast;
  input sinit;
  input mm2s_cntrl_strm_stop;
  input queue_empty_new0;
  input \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_2 ;
  input out;
  input m_axi_sg_rvalid;
  input [0:0]\GEN_MM2S.queue_dout_new_reg[90]_0 ;
  input [0:0]\GEN_MM2S.reg1_reg[90] ;
  input m_axis_mm2s_cntrl_tready;
  input m_axis_mm2s_cntrl_tvalid_0;
  input soft_reset_d1;
  input soft_reset_d2;
  input \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  input \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ;
  input \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_1 ;
  input [0:0]ftch_cmnd_data;
  input ch1_use_crntdesc;
  input ptr_queue_full;
  input s_axis_mm2s_updtptr_tlast;
  input packet_in_progress;
  input [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ;
  input [31:0]m_axi_sg_rdata;
  input [0:0]mm2s_dmacr;
  input s_axis_mm2s_cmd_tready;
  input s_axis_mm2s_cmd_tvalid_split;
  input [0:0]E;
  input [25:0]D;
  input [0:0]\counter_reg[1]_0 ;

  wire [25:0]D;
  wire [0:0]E;
  wire \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat[95]_i_1_n_0 ;
  wire \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg_0 ;
  wire [25:0]\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] ;
  wire \GEN_MM2S.queue_dout_new_reg[64] ;
  wire [85:0]\GEN_MM2S.queue_dout_new_reg[90] ;
  wire [0:0]\GEN_MM2S.queue_dout_new_reg[90]_0 ;
  wire \GEN_MM2S.queue_dout_valid_reg ;
  wire [0:0]\GEN_MM2S.reg1_reg[90] ;
  wire \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ;
  wire [0:0]\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_1 ;
  wire \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_2 ;
  wire [25:0]\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] ;
  wire \GEN_QUEUE.FTCH_QUEUE_I_n_5 ;
  wire \GEN_QUEUE.FTCH_QUEUE_I_n_6 ;
  wire \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ;
  wire \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_1 ;
  wire [1:0]Q;
  wire \TLAST_GEN.sof_ftch_desc_i_1_n_0 ;
  wire ch1_ftch_pause;
  wire ch1_ftch_queue_empty;
  wire ch1_use_crntdesc;
  wire [0:0]\counter_reg[1]_0 ;
  wire \counter_reg_n_0_[3] ;
  wire \counter_reg_n_0_[4] ;
  wire \counter_reg_n_0_[5] ;
  wire [95:0]data_concat;
  wire data_concat_valid;
  wire [0:0]ftch_cmnd_data;
  wire ftch_stale_desc;
  wire lsbnxtdesc_tready;
  wire m_axi_sg_aclk;
  wire [31:0]m_axi_sg_rdata;
  wire m_axi_sg_rlast;
  wire m_axi_sg_rvalid;
  wire [31:0]m_axis_mm2s_cntrl_tdata;
  wire m_axis_mm2s_cntrl_tlast;
  wire m_axis_mm2s_cntrl_tready;
  wire m_axis_mm2s_cntrl_tvalid;
  wire m_axis_mm2s_cntrl_tvalid_0;
  wire mm2s_cntrl_strm_stop;
  wire [0:0]mm2s_dmacr;
  wire \nxtdesc_int_reg_n_0_[10] ;
  wire \nxtdesc_int_reg_n_0_[11] ;
  wire \nxtdesc_int_reg_n_0_[12] ;
  wire \nxtdesc_int_reg_n_0_[13] ;
  wire \nxtdesc_int_reg_n_0_[14] ;
  wire \nxtdesc_int_reg_n_0_[15] ;
  wire \nxtdesc_int_reg_n_0_[16] ;
  wire \nxtdesc_int_reg_n_0_[17] ;
  wire \nxtdesc_int_reg_n_0_[18] ;
  wire \nxtdesc_int_reg_n_0_[19] ;
  wire \nxtdesc_int_reg_n_0_[20] ;
  wire \nxtdesc_int_reg_n_0_[21] ;
  wire \nxtdesc_int_reg_n_0_[22] ;
  wire \nxtdesc_int_reg_n_0_[23] ;
  wire \nxtdesc_int_reg_n_0_[24] ;
  wire \nxtdesc_int_reg_n_0_[25] ;
  wire \nxtdesc_int_reg_n_0_[26] ;
  wire \nxtdesc_int_reg_n_0_[27] ;
  wire \nxtdesc_int_reg_n_0_[28] ;
  wire \nxtdesc_int_reg_n_0_[29] ;
  wire \nxtdesc_int_reg_n_0_[30] ;
  wire \nxtdesc_int_reg_n_0_[31] ;
  wire \nxtdesc_int_reg_n_0_[6] ;
  wire \nxtdesc_int_reg_n_0_[7] ;
  wire \nxtdesc_int_reg_n_0_[8] ;
  wire \nxtdesc_int_reg_n_0_[9] ;
  wire out;
  wire p_0_in;
  wire p_0_in6_in;
  wire p_0_in8_in;
  wire packet_in_progress;
  wire ptr_queue_full;
  wire queue_empty_new0;
  wire rst;
  wire s_axis_mm2s_cmd_tready;
  wire s_axis_mm2s_cmd_tvalid_split;
  wire s_axis_mm2s_updtptr_tlast;
  wire sinit;
  wire sof_ftch_desc;
  wire soft_reset_d1;
  wire soft_reset_d2;
  wire tlast_new;

  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[32] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[0]),
        .Q(data_concat[32]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[33] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[1]),
        .Q(data_concat[33]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[34] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[2]),
        .Q(data_concat[34]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[35] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[3]),
        .Q(data_concat[35]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[36] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[4]),
        .Q(data_concat[36]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[37] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[5]),
        .Q(data_concat[37]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[38] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[6]),
        .Q(data_concat[38]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[39] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[7]),
        .Q(data_concat[39]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[40] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[8]),
        .Q(data_concat[40]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[41] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[9]),
        .Q(data_concat[41]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[42] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[10]),
        .Q(data_concat[42]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[43] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[11]),
        .Q(data_concat[43]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[44] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[12]),
        .Q(data_concat[44]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[45] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[13]),
        .Q(data_concat[45]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[46] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[14]),
        .Q(data_concat[46]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[47] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[15]),
        .Q(data_concat[47]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[48] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[16]),
        .Q(data_concat[48]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[49] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[17]),
        .Q(data_concat[49]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[50] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[18]),
        .Q(data_concat[50]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[51] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[19]),
        .Q(data_concat[51]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[52] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[20]),
        .Q(data_concat[52]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[53] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[21]),
        .Q(data_concat[53]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[54] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[22]),
        .Q(data_concat[54]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[55] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[23]),
        .Q(data_concat[55]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[56] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[24]),
        .Q(data_concat[56]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[57] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[25]),
        .Q(data_concat[57]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[58] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[26]),
        .Q(data_concat[58]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \DMA_REG2.data_concat_reg[59] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in8_in),
        .D(m_axi_sg_rdata[27]),
        .Q(data_concat[59]),
        .R(sinit));
  LUT5 #(
    .INIT(32'h70FF7000)) 
    \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat[95]_i_1 
       (.I0(ftch_cmnd_data),
        .I1(mm2s_dmacr),
        .I2(m_axi_sg_rdata[31]),
        .I3(p_0_in6_in),
        .I4(data_concat[95]),
        .O(\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat[95]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg[95] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat[95]_i_1_n_0 ),
        .Q(data_concat[95]),
        .R(sinit));
  LUT2 #(
    .INIT(4'h8)) 
    \FLOP_FOR_NOQUEUE.data_concat_valid_i_1 
       (.I0(m_axi_sg_rvalid),
        .I1(p_0_in6_in),
        .O(tlast_new));
  FDRE \FLOP_FOR_NOQUEUE.data_concat_valid_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(tlast_new),
        .Q(data_concat_valid),
        .R(sinit));
  FDRE \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_2 ),
        .Q(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .R(sinit));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[10]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [4]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[10] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [4]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[11]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [5]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[11] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [5]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[12]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [6]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[12] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [6]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[13]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [7]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[13] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [7]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[14]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [8]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[14] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [8]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[15]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [9]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[15] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [9]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[16]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [10]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[16] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [10]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[17]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [11]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[17] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [11]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[18]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [12]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[18] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [12]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[19]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [13]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[19] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [13]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[20]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [14]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[20] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [14]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[21]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [15]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[21] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [15]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[22]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [16]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[22] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [16]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[23]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [17]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[23] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [17]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[24]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [18]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[24] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [18]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[25]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [19]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[25] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [19]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[26]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [20]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[26] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [20]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[27]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [21]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[27] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [21]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[28]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [22]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[28] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [22]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[29]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [23]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[29] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [23]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[30]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [24]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[30] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [24]));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[31]_i_1 
       (.I0(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I1(ch1_use_crntdesc),
        .O(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_1 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[31]_i_2 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [25]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[31] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [25]));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[6]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [0]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[6] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [0]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[7]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [1]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[7] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [1]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[8]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [2]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[8] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [2]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \GEN_PNTR_FOR_CH1.ch1_fetch_address_i[9]_i_1 
       (.I0(\GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31] [3]),
        .I1(ch1_use_crntdesc),
        .I2(\GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_reg_0 ),
        .I3(\nxtdesc_int_reg_n_0_[9] ),
        .O(\GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[31] [3]));
  Loopback_axi_dma_1_0_axi_sg_ftch_queue \GEN_QUEUE.FTCH_QUEUE_I 
       (.D(D),
        .E(E),
        .\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 (\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\GEN_QUEUE.FTCH_QUEUE_I_n_5 ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg_0 (\GEN_ASYNC_RESET.scndry_resetn_reg ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg_1 (\GEN_ASYNC_RESET.scndry_resetn_reg_0 ),
        .\GEN_MM2S.queue_dout_new_reg[64]_0 (\GEN_MM2S.queue_dout_new_reg[64] ),
        .\GEN_MM2S.queue_dout_new_reg[90]_0 (\GEN_MM2S.queue_dout_new_reg[90] ),
        .\GEN_MM2S.queue_dout_new_reg[90]_1 (\GEN_MM2S.queue_dout_new_reg[90]_0 ),
        .\GEN_MM2S.queue_dout_valid_reg_0 (\GEN_MM2S.queue_dout_valid_reg ),
        .\GEN_MM2S.reg1_reg[64]_0 ({data_concat[95],data_concat[59:0]}),
        .\GEN_MM2S.reg1_reg[90]_0 (\GEN_MM2S.reg1_reg[90] ),
        .\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg (\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ),
        .\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 (\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_1 ),
        .Q({p_0_in6_in,Q}),
        .ch1_ftch_pause(ch1_ftch_pause),
        .ch1_ftch_queue_empty(ch1_ftch_queue_empty),
        .\counter_reg[0] (\GEN_QUEUE.FTCH_QUEUE_I_n_6 ),
        .data_concat_valid(data_concat_valid),
        .ftch_cmnd_data(ftch_cmnd_data),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_rdata(m_axi_sg_rdata),
        .m_axi_sg_rlast(m_axi_sg_rlast),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .m_axis_mm2s_cntrl_tdata(m_axis_mm2s_cntrl_tdata),
        .m_axis_mm2s_cntrl_tlast(m_axis_mm2s_cntrl_tlast),
        .m_axis_mm2s_cntrl_tready(m_axis_mm2s_cntrl_tready),
        .m_axis_mm2s_cntrl_tvalid(m_axis_mm2s_cntrl_tvalid),
        .m_axis_mm2s_cntrl_tvalid_0(m_axis_mm2s_cntrl_tvalid_0),
        .mm2s_cntrl_strm_stop(mm2s_cntrl_strm_stop),
        .out(out),
        .packet_in_progress(packet_in_progress),
        .ptr_queue_full(ptr_queue_full),
        .queue_empty_new0(queue_empty_new0),
        .rst(rst),
        .s_axis_mm2s_cmd_tready(s_axis_mm2s_cmd_tready),
        .s_axis_mm2s_cmd_tvalid_split(s_axis_mm2s_cmd_tvalid_split),
        .s_axis_mm2s_updtptr_tlast(s_axis_mm2s_updtptr_tlast),
        .sinit(sinit),
        .sof_ftch_desc(sof_ftch_desc),
        .soft_reset_d1(soft_reset_d1),
        .soft_reset_d2(soft_reset_d2));
  FDRE \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_QUEUE.FTCH_QUEUE_I_n_5 ),
        .Q(ftch_stale_desc),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000EAAAAAAA)) 
    \TLAST_GEN.sof_ftch_desc_i_1 
       (.I0(sof_ftch_desc),
        .I1(m_axi_sg_rdata[27]),
        .I2(p_0_in8_in),
        .I3(m_axi_sg_rvalid),
        .I4(\GEN_QUEUE.FTCH_QUEUE_I_n_6 ),
        .I5(\counter_reg[1]_0 ),
        .O(\TLAST_GEN.sof_ftch_desc_i_1_n_0 ));
  FDRE \TLAST_GEN.sof_ftch_desc_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\TLAST_GEN.sof_ftch_desc_i_1_n_0 ),
        .Q(sof_ftch_desc),
        .R(1'b0));
  FDSE \counter_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(m_axi_sg_rvalid),
        .D(1'b0),
        .Q(Q[0]),
        .S(\counter_reg[1]_0 ));
  FDRE \counter_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(m_axi_sg_rvalid),
        .D(Q[0]),
        .Q(Q[1]),
        .R(\counter_reg[1]_0 ));
  FDRE \counter_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(m_axi_sg_rvalid),
        .D(Q[1]),
        .Q(p_0_in),
        .R(\counter_reg[1]_0 ));
  FDRE \counter_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(m_axi_sg_rvalid),
        .D(p_0_in),
        .Q(\counter_reg_n_0_[3] ),
        .R(\counter_reg[1]_0 ));
  FDRE \counter_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(m_axi_sg_rvalid),
        .D(\counter_reg_n_0_[3] ),
        .Q(\counter_reg_n_0_[4] ),
        .R(\counter_reg[1]_0 ));
  FDRE \counter_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(m_axi_sg_rvalid),
        .D(\counter_reg_n_0_[4] ),
        .Q(\counter_reg_n_0_[5] ),
        .R(\counter_reg[1]_0 ));
  FDRE \counter_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(m_axi_sg_rvalid),
        .D(\counter_reg_n_0_[5] ),
        .Q(p_0_in8_in),
        .R(\counter_reg[1]_0 ));
  FDRE \counter_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(m_axi_sg_rvalid),
        .D(p_0_in8_in),
        .Q(p_0_in6_in),
        .R(\counter_reg[1]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[0]),
        .Q(data_concat[0]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[10]),
        .Q(data_concat[10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[11]),
        .Q(data_concat[11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[12]),
        .Q(data_concat[12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[13]),
        .Q(data_concat[13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[14]),
        .Q(data_concat[14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[15]),
        .Q(data_concat[15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[16]),
        .Q(data_concat[16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[17]),
        .Q(data_concat[17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[18]),
        .Q(data_concat[18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[19]),
        .Q(data_concat[19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[1]),
        .Q(data_concat[1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[20]),
        .Q(data_concat[20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[21]),
        .Q(data_concat[21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[22]),
        .Q(data_concat[22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[23]),
        .Q(data_concat[23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[24]),
        .Q(data_concat[24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[25]),
        .Q(data_concat[25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[26]),
        .Q(data_concat[26]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[27]),
        .Q(data_concat[27]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[28]),
        .Q(data_concat[28]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[29]),
        .Q(data_concat[29]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[2]),
        .Q(data_concat[2]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[30]),
        .Q(data_concat[30]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[31]),
        .Q(data_concat[31]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[3]),
        .Q(data_concat[3]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[4]),
        .Q(data_concat[4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[5]),
        .Q(data_concat[5]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[6]),
        .Q(data_concat[6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[7]),
        .Q(data_concat[7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[8]),
        .Q(data_concat[8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \data_concat_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(p_0_in),
        .D(m_axi_sg_rdata[9]),
        .Q(data_concat[9]),
        .R(sinit));
  LUT2 #(
    .INIT(4'h8)) 
    \nxtdesc_int[31]_i_1 
       (.I0(m_axi_sg_rvalid),
        .I1(Q[0]),
        .O(lsbnxtdesc_tready));
  FDRE \nxtdesc_int_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[10]),
        .Q(\nxtdesc_int_reg_n_0_[10] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[11]),
        .Q(\nxtdesc_int_reg_n_0_[11] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[12]),
        .Q(\nxtdesc_int_reg_n_0_[12] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[13]),
        .Q(\nxtdesc_int_reg_n_0_[13] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[14]),
        .Q(\nxtdesc_int_reg_n_0_[14] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[15]),
        .Q(\nxtdesc_int_reg_n_0_[15] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[16]),
        .Q(\nxtdesc_int_reg_n_0_[16] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[17]),
        .Q(\nxtdesc_int_reg_n_0_[17] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[18]),
        .Q(\nxtdesc_int_reg_n_0_[18] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[19]),
        .Q(\nxtdesc_int_reg_n_0_[19] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[20]),
        .Q(\nxtdesc_int_reg_n_0_[20] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[21]),
        .Q(\nxtdesc_int_reg_n_0_[21] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[22]),
        .Q(\nxtdesc_int_reg_n_0_[22] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[23]),
        .Q(\nxtdesc_int_reg_n_0_[23] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[24]),
        .Q(\nxtdesc_int_reg_n_0_[24] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[25]),
        .Q(\nxtdesc_int_reg_n_0_[25] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[26]),
        .Q(\nxtdesc_int_reg_n_0_[26] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[27]),
        .Q(\nxtdesc_int_reg_n_0_[27] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[28]),
        .Q(\nxtdesc_int_reg_n_0_[28] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[29]),
        .Q(\nxtdesc_int_reg_n_0_[29] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[30]),
        .Q(\nxtdesc_int_reg_n_0_[30] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[31]),
        .Q(\nxtdesc_int_reg_n_0_[31] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[6]),
        .Q(\nxtdesc_int_reg_n_0_[6] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[7]),
        .Q(\nxtdesc_int_reg_n_0_[7] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[8]),
        .Q(\nxtdesc_int_reg_n_0_[8] ),
        .R(sinit));
  FDRE \nxtdesc_int_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(lsbnxtdesc_tready),
        .D(m_axi_sg_rdata[9]),
        .Q(\nxtdesc_int_reg_n_0_[9] ),
        .R(sinit));
endmodule

module Loopback_axi_dma_1_0_axi_sg_ftch_queue
   (ch1_ftch_queue_empty,
    ch1_ftch_pause,
    \GEN_MM2S.queue_dout_valid_reg_0 ,
    m_axis_mm2s_cntrl_tlast,
    m_axis_mm2s_cntrl_tvalid,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    \counter_reg[0] ,
    \GEN_ASYNC_RESET.scndry_resetn_reg_0 ,
    \GEN_ASYNC_RESET.scndry_resetn_reg_1 ,
    \GEN_MM2S.queue_dout_new_reg[90]_0 ,
    \GEN_MM2S.queue_dout_new_reg[64]_0 ,
    m_axis_mm2s_cntrl_tdata,
    rst,
    m_axi_sg_aclk,
    m_axi_sg_rlast,
    sinit,
    mm2s_cntrl_strm_stop,
    queue_empty_new0,
    sof_ftch_desc,
    out,
    m_axi_sg_rvalid,
    \GEN_MM2S.queue_dout_new_reg[90]_1 ,
    \GEN_MM2S.reg1_reg[90]_0 ,
    m_axis_mm2s_cntrl_tready,
    m_axis_mm2s_cntrl_tvalid_0,
    soft_reset_d1,
    soft_reset_d2,
    \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ,
    Q,
    \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ,
    \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ,
    ftch_cmnd_data,
    ptr_queue_full,
    s_axis_mm2s_updtptr_tlast,
    packet_in_progress,
    data_concat_valid,
    m_axi_sg_rdata,
    s_axis_mm2s_cmd_tready,
    s_axis_mm2s_cmd_tvalid_split,
    E,
    D,
    \GEN_MM2S.reg1_reg[64]_0 );
  output ch1_ftch_queue_empty;
  output ch1_ftch_pause;
  output \GEN_MM2S.queue_dout_valid_reg_0 ;
  output m_axis_mm2s_cntrl_tlast;
  output m_axis_mm2s_cntrl_tvalid;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  output \counter_reg[0] ;
  output \GEN_ASYNC_RESET.scndry_resetn_reg_0 ;
  output \GEN_ASYNC_RESET.scndry_resetn_reg_1 ;
  output [85:0]\GEN_MM2S.queue_dout_new_reg[90]_0 ;
  output \GEN_MM2S.queue_dout_new_reg[64]_0 ;
  output [31:0]m_axis_mm2s_cntrl_tdata;
  input rst;
  input m_axi_sg_aclk;
  input m_axi_sg_rlast;
  input sinit;
  input mm2s_cntrl_strm_stop;
  input queue_empty_new0;
  input sof_ftch_desc;
  input out;
  input m_axi_sg_rvalid;
  input [0:0]\GEN_MM2S.queue_dout_new_reg[90]_1 ;
  input [0:0]\GEN_MM2S.reg1_reg[90]_0 ;
  input m_axis_mm2s_cntrl_tready;
  input m_axis_mm2s_cntrl_tvalid_0;
  input soft_reset_d1;
  input soft_reset_d2;
  input \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  input [2:0]Q;
  input \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ;
  input \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ;
  input [0:0]ftch_cmnd_data;
  input ptr_queue_full;
  input s_axis_mm2s_updtptr_tlast;
  input packet_in_progress;
  input data_concat_valid;
  input [31:0]m_axi_sg_rdata;
  input s_axis_mm2s_cmd_tready;
  input s_axis_mm2s_cmd_tvalid_split;
  input [0:0]E;
  input [25:0]D;
  input [60:0]\GEN_MM2S.reg1_reg[64]_0 ;

  wire [25:0]D;
  wire [0:0]E;
  wire \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg_0 ;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg_1 ;
  wire \GEN_MM2S.queue_dout_new_reg[64]_0 ;
  wire [85:0]\GEN_MM2S.queue_dout_new_reg[90]_0 ;
  wire [0:0]\GEN_MM2S.queue_dout_new_reg[90]_1 ;
  wire \GEN_MM2S.queue_dout_valid_i_1_n_0 ;
  wire \GEN_MM2S.queue_dout_valid_reg_0 ;
  wire [60:0]\GEN_MM2S.reg1_reg[64]_0 ;
  wire [0:0]\GEN_MM2S.reg1_reg[90]_0 ;
  wire \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ;
  wire \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ;
  wire [2:0]Q;
  wire ch1_ftch_pause;
  wire ch1_ftch_queue_empty;
  wire \counter_reg[0] ;
  wire [31:6]current_bd;
  wire data_concat_valid;
  wire [0:0]ftch_cmnd_data;
  wire m_axi_sg_aclk;
  wire [31:0]m_axi_sg_rdata;
  wire m_axi_sg_rlast;
  wire m_axi_sg_rvalid;
  wire [31:0]m_axis_mm2s_cntrl_tdata;
  wire m_axis_mm2s_cntrl_tlast;
  wire m_axis_mm2s_cntrl_tready;
  wire m_axis_mm2s_cntrl_tvalid;
  wire m_axis_mm2s_cntrl_tvalid_0;
  wire [59:59]m_axis_mm2s_ftch_tdata_new;
  wire mm2s_cntrl_strm_stop;
  wire out;
  wire packet_in_progress;
  wire ptr_queue_full;
  wire queue_empty_new0;
  wire queue_wren_new;
  wire [90:0]reg1;
  wire rst;
  wire s_axis_mm2s_cmd_tready;
  wire s_axis_mm2s_cmd_tvalid_split;
  wire s_axis_mm2s_updtptr_tlast;
  wire sinit;
  wire sof_ftch_desc;
  wire sof_ftch_desc_del1;
  wire sof_ftch_desc_del1_i_1_n_0;
  wire soft_reset_d1;
  wire soft_reset_d2;

  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[4]),
        .Q(current_bd[10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[5]),
        .Q(current_bd[11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[6]),
        .Q(current_bd[12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[7]),
        .Q(current_bd[13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[8]),
        .Q(current_bd[14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[9]),
        .Q(current_bd[15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[10]),
        .Q(current_bd[16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[11]),
        .Q(current_bd[17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[12]),
        .Q(current_bd[18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[13]),
        .Q(current_bd[19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[14]),
        .Q(current_bd[20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[15]),
        .Q(current_bd[21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[16]),
        .Q(current_bd[22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[17]),
        .Q(current_bd[23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[18]),
        .Q(current_bd[24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[19]),
        .Q(current_bd[25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[20]),
        .Q(current_bd[26]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[21]),
        .Q(current_bd[27]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[22]),
        .Q(current_bd[28]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[23]),
        .Q(current_bd[29]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[24]),
        .Q(current_bd[30]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[25]),
        .Q(current_bd[31]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[0]),
        .Q(current_bd[6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[1]),
        .Q(current_bd[7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[2]),
        .Q(current_bd[8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \CURRENT_BD_32.current_bd_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(D[3]),
        .Q(current_bd[9]),
        .R(sinit));
  Loopback_axi_dma_1_0_axi_sg_cntrl_strm \GEN_MM2S.CONTROL_STREAM.I_MM2S_CNTRL_STREAM 
       (.\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 (\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\GEN_ASYNC_RESET.scndry_resetn_reg ),
        .\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg (\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ),
        .\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 (\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ),
        .Q(Q),
        .\counter_reg[0] (\counter_reg[0] ),
        .ftch_cmnd_data(ftch_cmnd_data),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_rdata(m_axi_sg_rdata),
        .m_axi_sg_rlast(m_axi_sg_rlast),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .m_axis_mm2s_cntrl_tdata(m_axis_mm2s_cntrl_tdata),
        .m_axis_mm2s_cntrl_tlast(m_axis_mm2s_cntrl_tlast),
        .m_axis_mm2s_cntrl_tready(m_axis_mm2s_cntrl_tready),
        .m_axis_mm2s_cntrl_tvalid(m_axis_mm2s_cntrl_tvalid),
        .m_axis_mm2s_cntrl_tvalid_0(m_axis_mm2s_cntrl_tvalid_0),
        .mm2s_cntrl_strm_stop(mm2s_cntrl_strm_stop),
        .out(out),
        .rst(rst),
        .sinit(sinit),
        .sof_ftch_desc(sof_ftch_desc),
        .sof_ftch_desc_del1(sof_ftch_desc_del1),
        .soft_reset_d1(soft_reset_d1),
        .soft_reset_d2(soft_reset_d2));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[0]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [0]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[10]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [10]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[11]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [11]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[12]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [12]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[13]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [13]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[14]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [14]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[15]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [15]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[16]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [16]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[17]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [17]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[18]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [18]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[19]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [19]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[1]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [1]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[20]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [20]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[21]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [21]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[22]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [22]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[23]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [23]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[24]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [24]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[25]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [25]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[26]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [26]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[27]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [27]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[28]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [28]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[29]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [29]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[2]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [2]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[30]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [30]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[31]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [31]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[32] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[32]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [32]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[33] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[33]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [33]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[34] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[34]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [34]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[35] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[35]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [35]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[36] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[36]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [36]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[37] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[37]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [37]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[38] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[38]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [38]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[39] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[39]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [39]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[3]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [3]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[40] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[40]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [40]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[41] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[41]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [41]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[42] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[42]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [42]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[43] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[43]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [43]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[44] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[44]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [44]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[45] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[45]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [45]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[46] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[46]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [46]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[47] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[47]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [47]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[48] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[48]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [48]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[49] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[49]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [49]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[4]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [4]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[50] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[50]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [50]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[51] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[51]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [51]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[52] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[52]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [52]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[53] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[53]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [53]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[54] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[54]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [54]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[55] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[55]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [55]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[56] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[56]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [56]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[57] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[57]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [57]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[58] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[58]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [58]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[59] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[59]),
        .Q(m_axis_mm2s_ftch_tdata_new),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[5]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [5]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[64] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[64]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [59]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[65] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[65]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [60]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[66] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[66]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [61]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[67] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[67]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [62]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[68] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[68]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [63]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[69] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[69]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [64]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[6]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [6]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[70] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[70]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [65]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[71] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[71]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [66]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[72] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[72]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [67]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[73] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[73]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [68]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[74] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[74]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [69]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[75] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[75]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [70]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[76] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[76]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [71]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[77] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[77]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [72]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[78] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[78]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [73]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[79] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[79]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [74]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[7]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [7]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[80] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[80]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [75]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[81] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[81]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [76]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[82] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[82]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [77]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[83] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[83]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [78]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[84] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[84]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [79]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[85] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[85]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [80]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[86] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[86]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [81]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[87] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[87]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [82]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[88] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[88]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [83]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[89] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[89]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [84]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[8]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [8]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[90] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[90]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [85]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_new_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .D(reg1[9]),
        .Q(\GEN_MM2S.queue_dout_new_reg[90]_0 [9]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \GEN_MM2S.queue_dout_valid_i_1 
       (.I0(\GEN_MM2S.queue_dout_valid_reg_0 ),
        .I1(\GEN_MM2S.queue_dout_new_reg[90]_1 ),
        .I2(\GEN_MM2S.reg1_reg[90]_0 ),
        .O(\GEN_MM2S.queue_dout_valid_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_dout_valid_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_MM2S.queue_dout_valid_i_1_n_0 ),
        .Q(\GEN_MM2S.queue_dout_valid_reg_0 ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h40)) 
    \GEN_MM2S.queue_empty_new_i_2 
       (.I0(ch1_ftch_pause),
        .I1(ftch_cmnd_data),
        .I2(data_concat_valid),
        .O(queue_wren_new));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_empty_new_reg 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(1'b0),
        .Q(ch1_ftch_queue_empty),
        .S(queue_empty_new0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.queue_full_new_reg 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(1'b1),
        .Q(ch1_ftch_pause),
        .R(queue_empty_new0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [0]),
        .Q(reg1[0]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [10]),
        .Q(reg1[10]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [11]),
        .Q(reg1[11]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [12]),
        .Q(reg1[12]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [13]),
        .Q(reg1[13]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [14]),
        .Q(reg1[14]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [15]),
        .Q(reg1[15]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [16]),
        .Q(reg1[16]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [17]),
        .Q(reg1[17]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [18]),
        .Q(reg1[18]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [19]),
        .Q(reg1[19]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [1]),
        .Q(reg1[1]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [20]),
        .Q(reg1[20]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [21]),
        .Q(reg1[21]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [22]),
        .Q(reg1[22]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [23]),
        .Q(reg1[23]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [24]),
        .Q(reg1[24]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [25]),
        .Q(reg1[25]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [26]),
        .Q(reg1[26]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [27]),
        .Q(reg1[27]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [28]),
        .Q(reg1[28]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [29]),
        .Q(reg1[29]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [2]),
        .Q(reg1[2]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [30]),
        .Q(reg1[30]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [31]),
        .Q(reg1[31]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[32] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [32]),
        .Q(reg1[32]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[33] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [33]),
        .Q(reg1[33]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[34] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [34]),
        .Q(reg1[34]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[35] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [35]),
        .Q(reg1[35]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[36] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [36]),
        .Q(reg1[36]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[37] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [37]),
        .Q(reg1[37]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[38] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [38]),
        .Q(reg1[38]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[39] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [39]),
        .Q(reg1[39]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [3]),
        .Q(reg1[3]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[40] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [40]),
        .Q(reg1[40]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[41] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [41]),
        .Q(reg1[41]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[42] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [42]),
        .Q(reg1[42]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[43] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [43]),
        .Q(reg1[43]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[44] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [44]),
        .Q(reg1[44]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[45] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [45]),
        .Q(reg1[45]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[46] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [46]),
        .Q(reg1[46]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[47] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [47]),
        .Q(reg1[47]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[48] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [48]),
        .Q(reg1[48]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[49] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [49]),
        .Q(reg1[49]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [4]),
        .Q(reg1[4]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[50] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [50]),
        .Q(reg1[50]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[51] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [51]),
        .Q(reg1[51]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[52] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [52]),
        .Q(reg1[52]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[53] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [53]),
        .Q(reg1[53]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[54] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [54]),
        .Q(reg1[54]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[55] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [55]),
        .Q(reg1[55]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[56] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [56]),
        .Q(reg1[56]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[57] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [57]),
        .Q(reg1[57]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[58] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [58]),
        .Q(reg1[58]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[59] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [59]),
        .Q(reg1[59]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [5]),
        .Q(reg1[5]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[64] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [60]),
        .Q(reg1[64]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[65] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[6]),
        .Q(reg1[65]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[66] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[7]),
        .Q(reg1[66]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[67] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[8]),
        .Q(reg1[67]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[68] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[9]),
        .Q(reg1[68]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[69] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[10]),
        .Q(reg1[69]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [6]),
        .Q(reg1[6]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[70] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[11]),
        .Q(reg1[70]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[71] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[12]),
        .Q(reg1[71]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[72] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[13]),
        .Q(reg1[72]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[73] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[14]),
        .Q(reg1[73]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[74] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[15]),
        .Q(reg1[74]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[75] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[16]),
        .Q(reg1[75]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[76] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[17]),
        .Q(reg1[76]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[77] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[18]),
        .Q(reg1[77]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[78] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[19]),
        .Q(reg1[78]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[79] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[20]),
        .Q(reg1[79]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [7]),
        .Q(reg1[7]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[80] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[21]),
        .Q(reg1[80]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[81] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[22]),
        .Q(reg1[81]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[82] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[23]),
        .Q(reg1[82]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[83] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[24]),
        .Q(reg1[83]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[84] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[25]),
        .Q(reg1[84]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[85] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[26]),
        .Q(reg1[85]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[86] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[27]),
        .Q(reg1[86]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[87] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[28]),
        .Q(reg1[87]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[88] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[29]),
        .Q(reg1[88]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[89] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[30]),
        .Q(reg1[89]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [8]),
        .Q(reg1[8]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[90] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(current_bd[31]),
        .Q(reg1[90]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_MM2S.reg1_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(queue_wren_new),
        .D(\GEN_MM2S.reg1_reg[64]_0 [9]),
        .Q(reg1[9]),
        .R(\GEN_MM2S.reg1_reg[90]_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \GEN_NO_HOLD_DATA.s_axis_mm2s_cmd_tvalid_i_1 
       (.I0(\GEN_MM2S.queue_dout_new_reg[90]_0 [59]),
        .I1(\GEN_MM2S.queue_dout_valid_reg_0 ),
        .I2(s_axis_mm2s_cmd_tready),
        .I3(s_axis_mm2s_cmd_tvalid_split),
        .O(\GEN_MM2S.queue_dout_new_reg[64]_0 ));
  LUT5 #(
    .INIT(32'h00A8A0A0)) 
    packet_in_progress_i_1
       (.I0(out),
        .I1(m_axis_mm2s_ftch_tdata_new),
        .I2(packet_in_progress),
        .I3(\GEN_MM2S.queue_dout_new_reg[90]_0 [58]),
        .I4(\GEN_MM2S.queue_dout_valid_reg_0 ),
        .O(\GEN_ASYNC_RESET.scndry_resetn_reg_1 ));
  LUT5 #(
    .INIT(32'h00A0C0A0)) 
    sof_ftch_desc_del1_i_1
       (.I0(sof_ftch_desc_del1),
        .I1(sof_ftch_desc),
        .I2(out),
        .I3(m_axi_sg_rvalid),
        .I4(m_axi_sg_rlast),
        .O(sof_ftch_desc_del1_i_1_n_0));
  FDRE sof_ftch_desc_del1_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sof_ftch_desc_del1_i_1_n_0),
        .Q(sof_ftch_desc_del1),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hA088)) 
    updt_data_i_1
       (.I0(out),
        .I1(\GEN_MM2S.queue_dout_valid_reg_0 ),
        .I2(ptr_queue_full),
        .I3(s_axis_mm2s_updtptr_tlast),
        .O(\GEN_ASYNC_RESET.scndry_resetn_reg_0 ));
endmodule

module Loopback_axi_dma_1_0_axi_sg_ftch_sm
   (mm2s_ftch_idle,
    SR,
    \GEN_CH1_FETCH.ch1_active_i_reg_0 ,
    \GEN_CH1_FETCH.ch1_active_i_reg_1 ,
    mm2s_ftch_stale_desc,
    E,
    m_axi_sg_rvalid_0,
    \GEN_CH1_FETCH.ch1_active_i_reg_2 ,
    \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ,
    D,
    sg_ftch_error0,
    \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_0 ,
    ftch_cmnd_data,
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ,
    \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_1 ,
    \GEN_CH1_FETCH.ch1_ftch_slverr_set_reg_0 ,
    \GEN_CH1_FETCH.ch1_ftch_decerr_set_reg_0 ,
    m_axi_sg_aclk,
    \GEN_CH1_FETCH.ch1_ftch_idle_reg_0 ,
    \FSM_sequential_ftch_cs_reg[1]_0 ,
    soft_reset,
    out,
    ftch_done,
    ch1_ftch_queue_empty,
    mm2s_stop_i,
    \GEN_CH1_FETCH.ch1_ftch_idle_reg_1 ,
    mm2s_dmacr,
    updt_error,
    ch1_ftch_pause,
    ftch_error_early,
    dma_mm2s_error,
    m_axi_sg_rvalid,
    Q,
    m_axi_sg_rdata,
    \ftch_error_addr_reg[31]_0 ,
    \ftch_error_addr_reg[31]_1 ,
    s_axis_ftch_cmd_tready,
    s_axis_ftch_cmd_tvalid,
    mm2s_updt_interr_set,
    sg_interr_reg,
    mm2s_updt_slverr_set,
    sg_slverr_reg,
    mm2s_updt_decerr_set,
    sg_decerr_reg,
    sinit,
    ftch_stale_desc,
    ftch_slverr,
    ftch_decerr);
  output mm2s_ftch_idle;
  output [0:0]SR;
  output \GEN_CH1_FETCH.ch1_active_i_reg_0 ;
  output \GEN_CH1_FETCH.ch1_active_i_reg_1 ;
  output mm2s_ftch_stale_desc;
  output [0:0]E;
  output m_axi_sg_rvalid_0;
  output \GEN_CH1_FETCH.ch1_active_i_reg_2 ;
  output \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  output [25:0]D;
  output sg_ftch_error0;
  output \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_0 ;
  output [25:0]ftch_cmnd_data;
  output \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ;
  output \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_1 ;
  output \GEN_CH1_FETCH.ch1_ftch_slverr_set_reg_0 ;
  output \GEN_CH1_FETCH.ch1_ftch_decerr_set_reg_0 ;
  input m_axi_sg_aclk;
  input \GEN_CH1_FETCH.ch1_ftch_idle_reg_0 ;
  input \FSM_sequential_ftch_cs_reg[1]_0 ;
  input soft_reset;
  input out;
  input ftch_done;
  input ch1_ftch_queue_empty;
  input mm2s_stop_i;
  input \GEN_CH1_FETCH.ch1_ftch_idle_reg_1 ;
  input [1:0]mm2s_dmacr;
  input updt_error;
  input ch1_ftch_pause;
  input ftch_error_early;
  input dma_mm2s_error;
  input m_axi_sg_rvalid;
  input [1:0]Q;
  input [0:0]m_axi_sg_rdata;
  input [25:0]\ftch_error_addr_reg[31]_0 ;
  input [25:0]\ftch_error_addr_reg[31]_1 ;
  input s_axis_ftch_cmd_tready;
  input s_axis_ftch_cmd_tvalid;
  input mm2s_updt_interr_set;
  input sg_interr_reg;
  input mm2s_updt_slverr_set;
  input sg_slverr_reg;
  input mm2s_updt_decerr_set;
  input sg_decerr_reg;
  input sinit;
  input ftch_stale_desc;
  input ftch_slverr;
  input ftch_decerr;

  wire [25:0]D;
  wire [0:0]E;
  wire \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  wire \FSM_sequential_ftch_cs[0]_i_2_n_0 ;
  wire \FSM_sequential_ftch_cs_reg[1]_0 ;
  wire \GEN_CH1_FETCH.GEN_CH1_STALE_CHECK.ch1_stale_descriptor_i_1_n_0 ;
  wire \GEN_CH1_FETCH.ch1_active_i_i_1_n_0 ;
  wire \GEN_CH1_FETCH.ch1_active_i_reg_0 ;
  wire \GEN_CH1_FETCH.ch1_active_i_reg_1 ;
  wire \GEN_CH1_FETCH.ch1_active_i_reg_2 ;
  wire \GEN_CH1_FETCH.ch1_ftch_decerr_set_i_1_n_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_decerr_set_reg_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_idle_i_1_n_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_idle_i_2_n_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_idle_i_3_n_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_idle_i_4_n_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_idle_i_6_n_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_idle_reg_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_idle_reg_1 ;
  wire \GEN_CH1_FETCH.ch1_ftch_interr_set_i_i_1_n_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_1 ;
  wire \GEN_CH1_FETCH.ch1_ftch_slverr_set_i_1_n_0 ;
  wire \GEN_CH1_FETCH.ch1_ftch_slverr_set_reg_0 ;
  wire [1:0]Q;
  wire [0:0]SR;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ;
  wire ch1_ftch_pause;
  wire ch1_ftch_queue_empty;
  wire dma_mm2s_error;
  wire [25:0]ftch_cmnd_data;
  wire ftch_cmnd_wr;
  wire [1:0]ftch_cs;
  wire ftch_decerr;
  wire ftch_done;
  wire [31:6]ftch_error_addr_1;
  wire [25:0]\ftch_error_addr_reg[31]_0 ;
  wire [25:0]\ftch_error_addr_reg[31]_1 ;
  wire ftch_error_early;
  wire [1:0]ftch_ns__0;
  wire ftch_slverr;
  wire ftch_stale_desc;
  wire m_axi_sg_aclk;
  wire [0:0]m_axi_sg_rdata;
  wire m_axi_sg_rvalid;
  wire m_axi_sg_rvalid_0;
  wire [1:0]mm2s_dmacr;
  wire mm2s_ftch_decerr_set;
  wire mm2s_ftch_idle;
  wire mm2s_ftch_interr_set;
  wire mm2s_ftch_slverr_set;
  wire mm2s_ftch_stale_desc;
  wire mm2s_stop_i;
  wire mm2s_updt_decerr_set;
  wire mm2s_updt_interr_set;
  wire mm2s_updt_slverr_set;
  wire out;
  wire s_axis_ftch_cmd_tready;
  wire s_axis_ftch_cmd_tvalid;
  wire sg_decerr_reg;
  wire sg_ftch_error0;
  wire sg_interr_reg;
  wire sg_slverr_reg;
  wire sinit;
  wire soft_reset;
  wire updt_error;

  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    \CURRENT_BD_32.current_bd[31]_i_1 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(ftch_cs[0]),
        .I2(\FSM_sequential_ftch_cs_reg[1]_0 ),
        .I3(ftch_cs[1]),
        .O(E));
  LUT6 #(
    .INIT(64'hFEDCEEDCEEDCEEDC)) 
    \FSM_sequential_ftch_cs[0]_i_1 
       (.I0(ftch_cs[0]),
        .I1(\FSM_sequential_ftch_cs_reg[1]_0 ),
        .I2(\FSM_sequential_ftch_cs[0]_i_2_n_0 ),
        .I3(ftch_cs[1]),
        .I4(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I5(ftch_done),
        .O(ftch_ns__0[0]));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \FSM_sequential_ftch_cs[0]_i_2 
       (.I0(mm2s_dmacr[0]),
        .I1(mm2s_ftch_stale_desc),
        .I2(updt_error),
        .I3(\GEN_CH1_FETCH.ch1_ftch_idle_reg_0 ),
        .I4(ch1_ftch_pause),
        .I5(mm2s_stop_i),
        .O(\FSM_sequential_ftch_cs[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hEFEE)) 
    \FSM_sequential_ftch_cs[1]_i_1 
       (.I0(ftch_cs[0]),
        .I1(\FSM_sequential_ftch_cs_reg[1]_0 ),
        .I2(ftch_done),
        .I3(ftch_cs[1]),
        .O(ftch_ns__0[1]));
  (* FSM_ENCODED_STATES = "fetch_error:11,fetch_status:10,idle:00,fetch_descriptor:01" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_ftch_cs_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ftch_ns__0[0]),
        .Q(ftch_cs[0]),
        .R(sinit));
  (* FSM_ENCODED_STATES = "fetch_error:11,fetch_status:10,idle:00,fetch_descriptor:01" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_ftch_cs_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ftch_ns__0[1]),
        .Q(ftch_cs[1]),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \GEN_CH1_FETCH.GEN_CH1_STALE_CHECK.ch1_stale_descriptor_i_1 
       (.I0(ftch_stale_desc),
        .I1(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I2(mm2s_ftch_stale_desc),
        .O(\GEN_CH1_FETCH.GEN_CH1_STALE_CHECK.ch1_stale_descriptor_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_CH1_FETCH.GEN_CH1_STALE_CHECK.ch1_stale_descriptor_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_FETCH.GEN_CH1_STALE_CHECK.ch1_stale_descriptor_i_1_n_0 ),
        .Q(mm2s_ftch_stale_desc),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT5 #(
    .INIT(32'hFFFF0002)) 
    \GEN_CH1_FETCH.ch1_active_i_i_1 
       (.I0(\FSM_sequential_ftch_cs[0]_i_2_n_0 ),
        .I1(ftch_cs[0]),
        .I2(ftch_cs[1]),
        .I3(\FSM_sequential_ftch_cs_reg[1]_0 ),
        .I4(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .O(\GEN_CH1_FETCH.ch1_active_i_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_CH1_FETCH.ch1_active_i_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_FETCH.ch1_active_i_i_1_n_0 ),
        .Q(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \GEN_CH1_FETCH.ch1_ftch_decerr_set_i_1 
       (.I0(ftch_decerr),
        .I1(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I2(mm2s_ftch_decerr_set),
        .O(\GEN_CH1_FETCH.ch1_ftch_decerr_set_i_1_n_0 ));
  FDRE \GEN_CH1_FETCH.ch1_ftch_decerr_set_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_FETCH.ch1_ftch_decerr_set_i_1_n_0 ),
        .Q(mm2s_ftch_decerr_set),
        .R(sinit));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF0E0)) 
    \GEN_CH1_FETCH.ch1_ftch_idle_i_1 
       (.I0(\GEN_CH1_FETCH.ch1_ftch_idle_i_2_n_0 ),
        .I1(\GEN_CH1_FETCH.ch1_ftch_idle_i_3_n_0 ),
        .I2(\GEN_CH1_FETCH.ch1_ftch_idle_reg_0 ),
        .I3(mm2s_ftch_idle),
        .I4(\FSM_sequential_ftch_cs_reg[1]_0 ),
        .I5(\GEN_CH1_FETCH.ch1_ftch_idle_i_4_n_0 ),
        .O(\GEN_CH1_FETCH.ch1_ftch_idle_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8080808088808888)) 
    \GEN_CH1_FETCH.ch1_ftch_idle_i_2 
       (.I0(ftch_cs[1]),
        .I1(ch1_ftch_queue_empty),
        .I2(ftch_cs[0]),
        .I3(mm2s_stop_i),
        .I4(\GEN_CH1_FETCH.ch1_ftch_idle_reg_1 ),
        .I5(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .O(\GEN_CH1_FETCH.ch1_ftch_idle_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h202A0000202A202A)) 
    \GEN_CH1_FETCH.ch1_ftch_idle_i_3 
       (.I0(ch1_ftch_queue_empty),
        .I1(\GEN_CH1_FETCH.ch1_ftch_idle_i_6_n_0 ),
        .I2(ftch_cs[0]),
        .I3(ftch_cs[1]),
        .I4(mm2s_stop_i),
        .I5(\GEN_CH1_FETCH.ch1_ftch_idle_reg_1 ),
        .O(\GEN_CH1_FETCH.ch1_ftch_idle_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \GEN_CH1_FETCH.ch1_ftch_idle_i_4 
       (.I0(mm2s_ftch_interr_set),
        .I1(out),
        .O(\GEN_CH1_FETCH.ch1_ftch_idle_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \GEN_CH1_FETCH.ch1_ftch_idle_i_6 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\FSM_sequential_ftch_cs_reg[1]_0 ),
        .O(\GEN_CH1_FETCH.ch1_ftch_idle_i_6_n_0 ));
  FDRE \GEN_CH1_FETCH.ch1_ftch_idle_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_FETCH.ch1_ftch_idle_i_1_n_0 ),
        .Q(mm2s_ftch_idle),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT4 #(
    .INIT(16'hFFE0)) 
    \GEN_CH1_FETCH.ch1_ftch_interr_set_i_i_1 
       (.I0(\FSM_sequential_ftch_cs_reg[1]_0 ),
        .I1(ftch_done),
        .I2(mm2s_ftch_stale_desc),
        .I3(mm2s_ftch_interr_set),
        .O(\GEN_CH1_FETCH.ch1_ftch_interr_set_i_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_FETCH.ch1_ftch_interr_set_i_i_1_n_0 ),
        .Q(mm2s_ftch_interr_set),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \GEN_CH1_FETCH.ch1_ftch_slverr_set_i_1 
       (.I0(ftch_slverr),
        .I1(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I2(mm2s_ftch_slverr_set),
        .O(\GEN_CH1_FETCH.ch1_ftch_slverr_set_i_1_n_0 ));
  FDRE \GEN_CH1_FETCH.ch1_ftch_slverr_set_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_FETCH.ch1_ftch_slverr_set_i_1_n_0 ),
        .Q(mm2s_ftch_slverr_set),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/sg_decerr_i_1 
       (.I0(mm2s_ftch_decerr_set),
        .I1(mm2s_updt_decerr_set),
        .I2(sg_decerr_reg),
        .O(\GEN_CH1_FETCH.ch1_ftch_decerr_set_reg_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/sg_interr_i_1 
       (.I0(mm2s_ftch_interr_set),
        .I1(mm2s_updt_interr_set),
        .I2(sg_interr_reg),
        .O(\GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_1 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/sg_slverr_i_1 
       (.I0(mm2s_ftch_slverr_set),
        .I1(mm2s_updt_slverr_set),
        .I2(sg_slverr_reg),
        .O(\GEN_CH1_FETCH.ch1_ftch_slverr_set_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \GEN_NO_UPR_MSB_NXTDESC.ch1_nxtdesc_wren_i_1 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(m_axi_sg_rvalid),
        .I2(Q[1]),
        .O(\GEN_CH1_FETCH.ch1_active_i_reg_2 ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \GEN_STALE_DESC_CHECK.ftch_stale_desc_i_2 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(mm2s_dmacr[1]),
        .I2(m_axi_sg_rdata),
        .O(\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \QUEUE_COUNT.cmnds_queued_shift[3]_i_1 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_0 ),
        .I1(soft_reset),
        .I2(out),
        .O(SR));
  LUT6 #(
    .INIT(64'h545454545454FF54)) 
    \TLAST_GEN.sof_ftch_desc_i_3 
       (.I0(m_axi_sg_rvalid),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(ftch_cs[0]),
        .I4(\FSM_sequential_ftch_cs_reg[1]_0 ),
        .I5(ftch_cs[1]),
        .O(m_axi_sg_rvalid_0));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[10]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [4]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[10]),
        .O(D[4]));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[10]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [4]),
        .O(ftch_cmnd_data[4]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[11]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [5]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[11]),
        .O(D[5]));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[11]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [5]),
        .O(ftch_cmnd_data[5]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[12]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [6]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[12]),
        .O(D[6]));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[12]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [6]),
        .O(ftch_cmnd_data[6]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[13]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [7]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[13]),
        .O(D[7]));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[13]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [7]),
        .O(ftch_cmnd_data[7]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[14]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [8]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[14]),
        .O(D[8]));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[14]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [8]),
        .O(ftch_cmnd_data[8]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[15]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [9]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[15]),
        .O(D[9]));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[15]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [9]),
        .O(ftch_cmnd_data[9]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[16]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [10]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[16]),
        .O(D[10]));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[16]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [10]),
        .O(ftch_cmnd_data[10]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[17]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [11]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[17]),
        .O(D[11]));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[17]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [11]),
        .O(ftch_cmnd_data[11]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[18]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [12]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[18]),
        .O(D[12]));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[18]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [12]),
        .O(ftch_cmnd_data[12]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[19]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [13]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[19]),
        .O(D[13]));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[19]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [13]),
        .O(ftch_cmnd_data[13]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[20]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [14]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[20]),
        .O(D[14]));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[20]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [14]),
        .O(ftch_cmnd_data[14]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[21]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [15]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[21]),
        .O(D[15]));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[21]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [15]),
        .O(ftch_cmnd_data[15]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[22]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [16]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[22]),
        .O(D[16]));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[22]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [16]),
        .O(ftch_cmnd_data[16]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[23]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [17]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[23]),
        .O(D[17]));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[23]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [17]),
        .O(ftch_cmnd_data[17]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[24]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [18]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[24]),
        .O(D[18]));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[24]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [18]),
        .O(ftch_cmnd_data[18]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[25]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [19]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[25]),
        .O(D[19]));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[25]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [19]),
        .O(ftch_cmnd_data[19]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[26]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [20]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[26]),
        .O(D[20]));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[26]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [20]),
        .O(ftch_cmnd_data[20]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[27]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [21]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[27]),
        .O(D[21]));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[27]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [21]),
        .O(ftch_cmnd_data[21]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[28]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [22]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[28]),
        .O(D[22]));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[28]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [22]),
        .O(ftch_cmnd_data[22]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[29]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [23]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[29]),
        .O(D[23]));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[29]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [23]),
        .O(ftch_cmnd_data[23]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[30]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [24]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[30]),
        .O(D[24]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[30]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [24]),
        .O(ftch_cmnd_data[24]));
  LUT3 #(
    .INIT(8'h10)) 
    \ftch_error_addr[31]_i_1 
       (.I0(ftch_cs[1]),
        .I1(\FSM_sequential_ftch_cs_reg[1]_0 ),
        .I2(ftch_cs[0]),
        .O(ftch_cmnd_wr));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[31]_i_2 
       (.I0(\ftch_error_addr_reg[31]_0 [25]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[31]),
        .O(D[25]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[31]_i_2__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [25]),
        .O(ftch_cmnd_data[25]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \ftch_error_addr[31]_i_4 
       (.I0(mm2s_ftch_interr_set),
        .I1(mm2s_ftch_slverr_set),
        .I2(mm2s_ftch_decerr_set),
        .O(\GEN_CH1_FETCH.ch1_ftch_interr_set_i_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[6]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [0]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[6]),
        .O(D[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[6]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [0]),
        .O(ftch_cmnd_data[0]));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[7]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [1]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[7]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[7]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [1]),
        .O(ftch_cmnd_data[1]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[8]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [2]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[8]),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[8]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [2]),
        .O(ftch_cmnd_data[2]));
  LUT5 #(
    .INIT(32'hFFFE0002)) 
    \ftch_error_addr[9]_i_1 
       (.I0(\ftch_error_addr_reg[31]_0 [3]),
        .I1(mm2s_ftch_interr_set),
        .I2(mm2s_ftch_slverr_set),
        .I3(mm2s_ftch_decerr_set),
        .I4(ftch_error_addr_1[9]),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ftch_error_addr[9]_i_1__0 
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(\ftch_error_addr_reg[31]_1 [3]),
        .O(ftch_cmnd_data[3]));
  FDRE \ftch_error_addr_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[4]),
        .Q(ftch_error_addr_1[10]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[5]),
        .Q(ftch_error_addr_1[11]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[6]),
        .Q(ftch_error_addr_1[12]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[7]),
        .Q(ftch_error_addr_1[13]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[8]),
        .Q(ftch_error_addr_1[14]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[9]),
        .Q(ftch_error_addr_1[15]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[10]),
        .Q(ftch_error_addr_1[16]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[11]),
        .Q(ftch_error_addr_1[17]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[12]),
        .Q(ftch_error_addr_1[18]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[13]),
        .Q(ftch_error_addr_1[19]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[14]),
        .Q(ftch_error_addr_1[20]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[15]),
        .Q(ftch_error_addr_1[21]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[16]),
        .Q(ftch_error_addr_1[22]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[17]),
        .Q(ftch_error_addr_1[23]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[18]),
        .Q(ftch_error_addr_1[24]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[19]),
        .Q(ftch_error_addr_1[25]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[20]),
        .Q(ftch_error_addr_1[26]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[21]),
        .Q(ftch_error_addr_1[27]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[22]),
        .Q(ftch_error_addr_1[28]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[23]),
        .Q(ftch_error_addr_1[29]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[24]),
        .Q(ftch_error_addr_1[30]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[25]),
        .Q(ftch_error_addr_1[31]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[0]),
        .Q(ftch_error_addr_1[6]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[1]),
        .Q(ftch_error_addr_1[7]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[2]),
        .Q(ftch_error_addr_1[8]),
        .R(sinit));
  FDRE \ftch_error_addr_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(ftch_cmnd_wr),
        .D(ftch_cmnd_data[3]),
        .Q(ftch_error_addr_1[9]),
        .R(sinit));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF8)) 
    m_axis_mm2s_cntrl_tvalid_INST_0_i_1
       (.I0(\GEN_CH1_FETCH.ch1_active_i_reg_1 ),
        .I1(ftch_error_early),
        .I2(\FSM_sequential_ftch_cs_reg[1]_0 ),
        .I3(updt_error),
        .I4(dma_mm2s_error),
        .I5(mm2s_ftch_stale_desc),
        .O(\GEN_CH1_FETCH.ch1_active_i_reg_0 ));
  LUT5 #(
    .INIT(32'h555D000C)) 
    s_axis_ftch_cmd_tvalid_i_1
       (.I0(s_axis_ftch_cmd_tready),
        .I1(ftch_cs[0]),
        .I2(\FSM_sequential_ftch_cs_reg[1]_0 ),
        .I3(ftch_cs[1]),
        .I4(s_axis_ftch_cmd_tvalid),
        .O(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    sg_ftch_error_i_1
       (.I0(mm2s_ftch_decerr_set),
        .I1(mm2s_ftch_slverr_set),
        .I2(mm2s_ftch_interr_set),
        .O(sg_ftch_error0));
endmodule

module Loopback_axi_dma_1_0_axi_sg_intrpt
   (E,
    mm2s_dly_irq_set,
    ch1_delay_cnt_en,
    mm2s_ioc_irq_set,
    Q,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2]_0 ,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 ,
    ch1_dly_fast_cnt0,
    m_axi_sg_aclk,
    ch1_delay_count0,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg_0 ,
    mm2s_dmacr,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_0 ,
    \GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg_0 ,
    mm2s_irqthresh_wren,
    \GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg_1 ,
    out,
    sinit,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 ,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 ,
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 );
  output [0:0]E;
  output mm2s_dly_irq_set;
  output ch1_delay_cnt_en;
  output mm2s_ioc_irq_set;
  output [7:0]Q;
  output \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2]_0 ;
  output \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ;
  output [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 ;
  input ch1_dly_fast_cnt0;
  input m_axi_sg_aclk;
  input ch1_delay_count0;
  input \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg_0 ;
  input [4:0]mm2s_dmacr;
  input \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_0 ;
  input [0:0]\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg_0 ;
  input mm2s_irqthresh_wren;
  input \GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg_1 ;
  input out;
  input sinit;
  input [0:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 ;
  input [2:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 ;
  input [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 ;

  wire [0:0]E;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1_n_0 ;
  wire [6:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_5_n_0 ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg_0 ;
  wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0 ;
  wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 ;
  wire [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_i_1_n_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_i_3_n_0 ;
  wire [0:0]\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg_1 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count[2]_i_1_n_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count[3]_i_1_n_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count[5]_i_1_n_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count[6]_i_1_n_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count[7]_i_2_n_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count[7]_i_3_n_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2]_0 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ;
  wire [2:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 ;
  wire \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_0 ;
  wire [0:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 ;
  wire [7:0]Q;
  wire ch1_delay_cnt_en;
  wire ch1_delay_count0;
  wire ch1_dly_fast_cnt0;
  wire ch1_dly_fast_incr;
  wire m_axi_sg_aclk;
  wire [6:0]minusOp;
  wire mm2s_dly_irq_set;
  wire [4:0]mm2s_dmacr;
  wire mm2s_ioc_irq_set;
  wire mm2s_irqthresh_wren;
  wire out;
  wire [7:0]plusOp;
  wire sinit;

  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[0]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [0]),
        .O(minusOp[0]));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [1]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [0]),
        .O(minusOp[1]));
  LUT3 #(
    .INIT(8'hA9)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[2]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [2]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [1]),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [0]),
        .O(minusOp[2]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[3]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [3]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [2]),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [0]),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [1]),
        .O(minusOp[3]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[4]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [4]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [3]),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [1]),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [0]),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [2]),
        .O(minusOp[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[5]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [5]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [4]),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [2]),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [0]),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [1]),
        .I5(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [3]),
        .O(minusOp[5]));
  LUT3 #(
    .INIT(8'hF4)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [6]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_5_n_0 ),
        .I2(ch1_dly_fast_cnt0),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_2 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [6]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_5_n_0 ),
        .O(minusOp[6]));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(minusOp[0]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [0]),
        .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(minusOp[1]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [1]),
        .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(minusOp[2]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [2]),
        .S(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(minusOp[3]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [3]),
        .S(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(minusOp[4]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [4]),
        .S(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(minusOp[5]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [5]),
        .S(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(minusOp[6]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [6]),
        .S(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_2 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_5_n_0 ),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [6]),
        .O(ch1_dly_fast_incr));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_5 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [4]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [2]),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [0]),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [1]),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [3]),
        .I5(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg [5]),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ch1_dly_fast_incr),
        .Q(E),
        .R(ch1_dly_fast_cnt0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg_0 ),
        .Q(ch1_delay_cnt_en),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[0]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [0]),
        .O(plusOp[0]));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[1]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [0]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [1]),
        .O(plusOp[1]));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[2]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [2]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [1]),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [0]),
        .O(plusOp[2]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[3]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [3]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [0]),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [1]),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [2]),
        .O(plusOp[3]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[4]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [4]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [2]),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [1]),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [0]),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [3]),
        .O(plusOp[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[5]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [5]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [3]),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [0]),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [1]),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [2]),
        .I5(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [4]),
        .O(plusOp[5]));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[6]_i_1 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [6]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0 ),
        .O(plusOp[6]));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_2 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [7]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0 ),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [6]),
        .O(plusOp[7]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3 
       (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [5]),
        .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [3]),
        .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [0]),
        .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [1]),
        .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [2]),
        .I5(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [4]),
        .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(plusOp[0]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [0]),
        .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(plusOp[1]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [1]),
        .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(plusOp[2]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [2]),
        .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(plusOp[3]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [3]),
        .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(plusOp[4]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [4]),
        .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(plusOp[5]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [5]),
        .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(plusOp[6]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [6]),
        .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(plusOp[7]),
        .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]_0 [7]),
        .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ch1_delay_count0),
        .Q(mm2s_dly_irq_set),
        .R(ch1_dly_fast_cnt0));
  LUT6 #(
    .INIT(64'h0700000000000000)) 
    \GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_i_1 
       (.I0(mm2s_dly_irq_set),
        .I1(\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg_0 ),
        .I2(mm2s_irqthresh_wren),
        .I3(\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg_1 ),
        .I4(out),
        .I5(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ),
        .O(\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00010000)) 
    \GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_i_2 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[6]),
        .I3(Q[7]),
        .I4(\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_i_3_n_0 ),
        .O(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_i_3 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[2]),
        .O(\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_INCLUDE_MM2S.ch1_ioc_irq_set_i_i_1_n_0 ),
        .Q(mm2s_ioc_irq_set),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hEEE2222E)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[2]_i_1 
       (.I0(mm2s_dmacr[0]),
        .I1(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_0 ),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\GEN_INCLUDE_MM2S.ch1_thresh_count[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEE22222222E)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[3]_i_1 
       (.I0(mm2s_dmacr[1]),
        .I1(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_0 ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[3]),
        .O(\GEN_INCLUDE_MM2S.ch1_thresh_count[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF3AA0CAA)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[5]_i_1 
       (.I0(mm2s_dmacr[2]),
        .I1(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2]_0 ),
        .I2(Q[4]),
        .I3(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_0 ),
        .I4(Q[5]),
        .O(\GEN_INCLUDE_MM2S.ch1_thresh_count[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCFAAAA0030AAAA)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[6]_i_1 
       (.I0(mm2s_dmacr[3]),
        .I1(Q[4]),
        .I2(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2]_0 ),
        .I3(Q[5]),
        .I4(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_0 ),
        .I5(Q[6]),
        .O(\GEN_INCLUDE_MM2S.ch1_thresh_count[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[6]_i_2 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .O(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2]_0 ));
  LUT5 #(
    .INIT(32'hF3AA0CAA)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[7]_i_2 
       (.I0(mm2s_dmacr[4]),
        .I1(\GEN_INCLUDE_MM2S.ch1_thresh_count[7]_i_3_n_0 ),
        .I2(Q[6]),
        .I3(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_0 ),
        .I4(Q[7]),
        .O(\GEN_INCLUDE_MM2S.ch1_thresh_count[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[7]_i_3 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .I5(Q[5]),
        .O(\GEN_INCLUDE_MM2S.ch1_thresh_count[7]_i_3_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 ),
        .D(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 [0]),
        .Q(Q[0]),
        .S(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 ),
        .D(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 [1]),
        .Q(Q[1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 ),
        .D(\GEN_INCLUDE_MM2S.ch1_thresh_count[2]_i_1_n_0 ),
        .Q(Q[2]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 ),
        .D(\GEN_INCLUDE_MM2S.ch1_thresh_count[3]_i_1_n_0 ),
        .Q(Q[3]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 ),
        .D(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[4]_1 [2]),
        .Q(Q[4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 ),
        .D(\GEN_INCLUDE_MM2S.ch1_thresh_count[5]_i_1_n_0 ),
        .Q(Q[5]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 ),
        .D(\GEN_INCLUDE_MM2S.ch1_thresh_count[6]_i_1_n_0 ),
        .Q(Q[6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7]_1 ),
        .D(\GEN_INCLUDE_MM2S.ch1_thresh_count[7]_i_2_n_0 ),
        .Q(Q[7]),
        .R(sinit));
endmodule

module Loopback_axi_dma_1_0_axi_sg_mm2s_basic_wrap
   (sig_cmd_stat_rst_user_reg_n_cdc_from_reg,
    sig_stream_rst,
    m_axi_sg_arburst,
    m_axi_sg_arvalid,
    m_axi_sg_rready,
    m_axi_sg_arlen,
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ,
    \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ,
    ftch_decerr_i,
    ftch_slverr_i,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_3,
    m_axi_sg_araddr,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_4,
    m_axi_sg_aclk,
    m_axi_sg_rvalid,
    s_axis_ftch_cmd_tvalid,
    m_axis_updt_sts_tready,
    sig_init_done,
    sig_init_done_0,
    sig_init_done_1,
    sig_init_done_2,
    m_axi_sg_rlast,
    m_axi_sg_arready,
    ftch_cmnd_data,
    m_axi_sg_rresp);
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  output sig_stream_rst;
  output [0:0]m_axi_sg_arburst;
  output m_axi_sg_arvalid;
  output m_axi_sg_rready;
  output [2:0]m_axi_sg_arlen;
  output \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ;
  output \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ;
  output ftch_decerr_i;
  output ftch_slverr_i;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_3;
  output [25:0]m_axi_sg_araddr;
  input sig_cmd_stat_rst_user_reg_n_cdc_from_reg_4;
  input m_axi_sg_aclk;
  input m_axi_sg_rvalid;
  input s_axis_ftch_cmd_tvalid;
  input m_axis_updt_sts_tready;
  input sig_init_done;
  input sig_init_done_0;
  input sig_init_done_1;
  input sig_init_done_2;
  input m_axi_sg_rlast;
  input m_axi_sg_arready;
  input [26:0]ftch_cmnd_data;
  input [1:0]m_axi_sg_rresp;

  wire I_ADDR_CNTL_n_6;
  wire I_CMD_STATUS_n_10;
  wire I_MSTR_SCC_n_5;
  wire I_MSTR_SCC_n_7;
  wire \USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ;
  wire [26:0]ftch_cmnd_data;
  wire ftch_decerr_i;
  wire ftch_slverr_i;
  wire m_axi_sg_aclk;
  wire [25:0]m_axi_sg_araddr;
  wire [0:0]m_axi_sg_arburst;
  wire [2:0]m_axi_sg_arlen;
  wire m_axi_sg_arready;
  wire m_axi_sg_arvalid;
  wire m_axi_sg_rlast;
  wire m_axi_sg_rready;
  wire [1:0]m_axi_sg_rresp;
  wire m_axi_sg_rvalid;
  wire m_axis_updt_sts_tready;
  wire [31:6]p_1_in;
  wire s_axis_ftch_cmd_tvalid;
  wire sig_addr2rsc_cmd_fifo_empty;
  wire [31:6]sig_cmd_addr_reg;
  wire [0:0]sig_cmd_burst_reg;
  wire sig_cmd_reg_empty;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_3;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_4;
  wire [0:0]sig_cmd_tag_reg;
  wire sig_coelsc_tag_reg1;
  wire sig_data2rsc_decerr;
  wire sig_data2rsc_okay;
  wire sig_data2rsc_slverr;
  wire sig_data2rsc_valid;
  wire sig_init_done;
  wire sig_init_done_0;
  wire sig_init_done_1;
  wire sig_init_done_2;
  wire sig_load_input_cmd;
  wire sig_mstr2addr_cmd_valid;
  wire [0:0]sig_mstr2data_len;
  wire sig_next_burst;
  wire sig_rd_sts_decerr_reg0;
  wire [7:7]sig_rsc2stat_status;
  wire [6:5]sig_rsc2stat_status_0;
  wire sig_rsc2stat_status_valid;
  wire sig_stat2rsc_status_ready;
  wire sig_stream_rst;
  wire sm_set_error;

  Loopback_axi_dma_1_0_axi_sg_addr_cntl I_ADDR_CNTL
       (.D({sig_cmd_tag_reg,sig_mstr2data_len}),
        .Q(sig_cmd_addr_reg),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_araddr(m_axi_sg_araddr),
        .m_axi_sg_arburst(m_axi_sg_arburst),
        .m_axi_sg_arlen(m_axi_sg_arlen),
        .m_axi_sg_arready(m_axi_sg_arready),
        .m_axi_sg_arvalid(m_axi_sg_arvalid),
        .sig_addr2rsc_cmd_fifo_empty(sig_addr2rsc_cmd_fifo_empty),
        .sig_addr_reg_empty_reg_0(I_ADDR_CNTL_n_6),
        .sig_addr_valid_reg_reg_0(I_MSTR_SCC_n_5),
        .sig_addr_valid_reg_reg_1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg),
        .sig_cmd_burst_reg(sig_cmd_burst_reg),
        .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid),
        .sig_posted_to_axi_reg_0(I_MSTR_SCC_n_7),
        .sm_set_error(sm_set_error));
  Loopback_axi_dma_1_0_axi_sg_cmd_status_21 I_CMD_STATUS
       (.D({sig_rsc2stat_status,sig_rsc2stat_status_0}),
        .Q({I_CMD_STATUS_n_10,p_1_in,sig_next_burst}),
        .\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] (\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[7] ),
        .\USE_SINGLE_REG.sig_regfifo_empty_reg_reg (\USE_SINGLE_REG.sig_regfifo_empty_reg_reg ),
        .\USE_SINGLE_REG.sig_regfifo_full_reg_reg (sig_cmd_stat_rst_user_reg_n_cdc_from_reg),
        .ftch_cmnd_data(ftch_cmnd_data),
        .ftch_decerr_i(ftch_decerr_i),
        .ftch_slverr_i(ftch_slverr_i),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_updt_sts_tready(m_axis_updt_sts_tready),
        .s_axis_ftch_cmd_tvalid(s_axis_ftch_cmd_tvalid),
        .sig_addr2rsc_cmd_fifo_empty(sig_addr2rsc_cmd_fifo_empty),
        .sig_cmd_reg_empty(sig_cmd_reg_empty),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_3),
        .sig_init_done(sig_init_done),
        .sig_init_done_0(sig_init_done_0),
        .sig_init_done_1(sig_init_done_1),
        .sig_init_done_2(sig_init_done_2),
        .sig_init_reg_reg(sig_stream_rst),
        .sig_load_input_cmd(sig_load_input_cmd),
        .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid),
        .sig_stat2rsc_status_ready(sig_stat2rsc_status_ready));
  Loopback_axi_dma_1_0_axi_sg_scc I_MSTR_SCC
       (.D({sig_cmd_tag_reg,sig_mstr2data_len}),
        .Q({I_CMD_STATUS_n_10,p_1_in,sig_next_burst}),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .sig_addr2rsc_cmd_fifo_empty(sig_addr2rsc_cmd_fifo_empty),
        .sig_cmd2addr_valid1_reg_0(I_MSTR_SCC_n_7),
        .\sig_cmd_addr_reg_reg[31]_0 (sig_cmd_addr_reg),
        .\sig_cmd_addr_reg_reg[6]_0 (I_ADDR_CNTL_n_6),
        .sig_cmd_burst_reg(sig_cmd_burst_reg),
        .sig_cmd_reg_empty(sig_cmd_reg_empty),
        .sig_load_input_cmd(sig_load_input_cmd),
        .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid),
        .sig_posted_to_axi_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg),
        .sm_set_error(sm_set_error),
        .sm_set_error_reg_0(I_MSTR_SCC_n_5),
        .sm_set_error_reg_1(sig_stream_rst));
  Loopback_axi_dma_1_0_axi_sg_rddata_cntl I_RD_DATA_CNTL
       (.D(sig_rsc2stat_status_0[5]),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_rlast(m_axi_sg_rlast),
        .m_axi_sg_rready(m_axi_sg_rready),
        .m_axi_sg_rresp(m_axi_sg_rresp),
        .m_axi_sg_rvalid(m_axi_sg_rvalid),
        .mm2s_rlast_del_reg_0(sig_stream_rst),
        .sig_coelsc_tag_reg1(sig_coelsc_tag_reg1),
        .sig_data2rsc_decerr(sig_data2rsc_decerr),
        .sig_data2rsc_okay(sig_data2rsc_okay),
        .sig_data2rsc_slverr(sig_data2rsc_slverr),
        .sig_data2rsc_valid(sig_data2rsc_valid),
        .sig_rd_sts_decerr_reg0(sig_rd_sts_decerr_reg0));
  Loopback_axi_dma_1_0_axi_sg_rd_status_cntl I_RD_STATUS_CNTLR
       (.D({sig_rsc2stat_status,sig_rsc2stat_status_0}),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .sig_coelsc_okay_reg_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg),
        .sig_coelsc_tag_reg1(sig_coelsc_tag_reg1),
        .sig_data2rsc_decerr(sig_data2rsc_decerr),
        .sig_data2rsc_okay(sig_data2rsc_okay),
        .sig_data2rsc_slverr(sig_data2rsc_slverr),
        .sig_data2rsc_valid(sig_data2rsc_valid),
        .sig_rd_sts_decerr_reg0(sig_rd_sts_decerr_reg0),
        .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid),
        .sig_stat2rsc_status_ready(sig_stat2rsc_status_ready));
  Loopback_axi_dma_1_0_axi_sg_reset I_RESET
       (.m_axi_sg_aclk(m_axi_sg_aclk),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1(sig_stream_rst),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_4));
endmodule

module Loopback_axi_dma_1_0_axi_sg_rd_status_cntl
   (D,
    sig_rsc2stat_status_valid,
    sig_coelsc_tag_reg1,
    sig_rd_sts_decerr_reg0,
    m_axi_sg_aclk,
    sig_data2rsc_valid,
    sig_data2rsc_okay,
    sig_data2rsc_decerr,
    sig_data2rsc_slverr,
    sig_stat2rsc_status_ready,
    sig_coelsc_okay_reg_reg);
  output [2:0]D;
  output sig_rsc2stat_status_valid;
  output sig_coelsc_tag_reg1;
  input sig_rd_sts_decerr_reg0;
  input m_axi_sg_aclk;
  input sig_data2rsc_valid;
  input sig_data2rsc_okay;
  input sig_data2rsc_decerr;
  input sig_data2rsc_slverr;
  input sig_stat2rsc_status_ready;
  input sig_coelsc_okay_reg_reg;

  wire [2:0]D;
  wire m_axi_sg_aclk;
  wire sig_coelsc_okay_reg_reg;
  wire sig_coelsc_tag_reg1;
  wire sig_data2rsc_decerr;
  wire sig_data2rsc_okay;
  wire sig_data2rsc_slverr;
  wire sig_data2rsc_valid;
  wire sig_push_rd_sts_reg;
  wire sig_rd_sts_decerr_reg0;
  wire sig_rd_sts_okay_reg0__0;
  wire sig_rd_sts_slverr_reg0;
  wire sig_rd_sts_tag_reg0;
  wire sig_rsc2data_ready;
  wire sig_rsc2stat_status_valid;
  wire sig_stat2rsc_status_ready;

  LUT2 #(
    .INIT(4'h7)) 
    sig_coelsc_okay_reg_i_1
       (.I0(sig_rsc2data_ready),
        .I1(sig_coelsc_okay_reg_reg),
        .O(sig_coelsc_tag_reg1));
  LUT3 #(
    .INIT(8'h8F)) 
    sig_rd_sts_decerr_reg_i_1
       (.I0(sig_rsc2stat_status_valid),
        .I1(sig_stat2rsc_status_ready),
        .I2(sig_coelsc_okay_reg_reg),
        .O(sig_rd_sts_tag_reg0));
  LUT2 #(
    .INIT(4'h8)) 
    sig_rd_sts_decerr_reg_i_2
       (.I0(sig_rsc2data_ready),
        .I1(sig_data2rsc_valid),
        .O(sig_push_rd_sts_reg));
  FDRE #(
    .INIT(1'b0)) 
    sig_rd_sts_decerr_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_rd_sts_reg),
        .D(sig_rd_sts_decerr_reg0),
        .Q(D[0]),
        .R(sig_rd_sts_tag_reg0));
  LUT5 #(
    .INIT(32'h00000002)) 
    sig_rd_sts_okay_reg0
       (.I0(sig_data2rsc_okay),
        .I1(sig_data2rsc_decerr),
        .I2(D[0]),
        .I3(D[1]),
        .I4(sig_data2rsc_slverr),
        .O(sig_rd_sts_okay_reg0__0));
  FDSE #(
    .INIT(1'b0)) 
    sig_rd_sts_okay_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_rd_sts_reg),
        .D(sig_rd_sts_okay_reg0__0),
        .Q(D[2]),
        .S(sig_rd_sts_tag_reg0));
  FDSE #(
    .INIT(1'b0)) 
    sig_rd_sts_reg_empty_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_rd_sts_reg),
        .D(1'b0),
        .Q(sig_rsc2data_ready),
        .S(sig_rd_sts_tag_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_rd_sts_reg_full_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_rd_sts_reg),
        .D(sig_data2rsc_valid),
        .Q(sig_rsc2stat_status_valid),
        .R(sig_rd_sts_tag_reg0));
  LUT2 #(
    .INIT(4'hE)) 
    sig_rd_sts_slverr_reg_i_1__0
       (.I0(D[1]),
        .I1(sig_data2rsc_slverr),
        .O(sig_rd_sts_slverr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_rd_sts_slverr_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_rd_sts_reg),
        .D(sig_rd_sts_slverr_reg0),
        .Q(D[1]),
        .R(sig_rd_sts_tag_reg0));
endmodule

module Loopback_axi_dma_1_0_axi_sg_rddata_cntl
   (m_axi_sg_rready,
    sig_data2rsc_okay,
    sig_data2rsc_decerr,
    sig_data2rsc_slverr,
    sig_data2rsc_valid,
    sig_rd_sts_decerr_reg0,
    mm2s_rlast_del_reg_0,
    m_axi_sg_aclk,
    sig_coelsc_tag_reg1,
    m_axi_sg_rvalid,
    m_axi_sg_rlast,
    D,
    m_axi_sg_rresp);
  output m_axi_sg_rready;
  output sig_data2rsc_okay;
  output sig_data2rsc_decerr;
  output sig_data2rsc_slverr;
  output sig_data2rsc_valid;
  output sig_rd_sts_decerr_reg0;
  input mm2s_rlast_del_reg_0;
  input m_axi_sg_aclk;
  input sig_coelsc_tag_reg1;
  input m_axi_sg_rvalid;
  input m_axi_sg_rlast;
  input [0:0]D;
  input [1:0]m_axi_sg_rresp;

  wire [0:0]D;
  wire m_axi_sg_aclk;
  wire m_axi_sg_rlast;
  wire m_axi_sg_rready;
  wire [1:0]m_axi_sg_rresp;
  wire m_axi_sg_rvalid;
  wire mm2s_rlast_del_i_1_n_0;
  wire mm2s_rlast_del_reg_0;
  wire sig_coelsc_decerr_reg0;
  wire sig_coelsc_okay_reg_i_2_n_0;
  wire sig_coelsc_slverr_reg0;
  wire sig_coelsc_tag_reg1;
  wire sig_data2rsc_decerr;
  wire sig_data2rsc_okay;
  wire sig_data2rsc_slverr;
  wire sig_data2rsc_valid;
  wire sig_rd_sts_decerr_reg0;

  LUT2 #(
    .INIT(4'h8)) 
    mm2s_rlast_del_i_1
       (.I0(m_axi_sg_rvalid),
        .I1(m_axi_sg_rlast),
        .O(mm2s_rlast_del_i_1_n_0));
  FDRE mm2s_rlast_del_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(mm2s_rlast_del_i_1_n_0),
        .Q(sig_data2rsc_valid),
        .R(mm2s_rlast_del_reg_0));
  FDRE mm2s_rready_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(1'b1),
        .Q(m_axi_sg_rready),
        .R(mm2s_rlast_del_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    sig_coelsc_decerr_reg_i_1__0
       (.I0(m_axi_sg_rresp[1]),
        .I1(m_axi_sg_rresp[0]),
        .I2(sig_data2rsc_decerr),
        .O(sig_coelsc_decerr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_coelsc_decerr_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(m_axi_sg_rvalid),
        .D(sig_coelsc_decerr_reg0),
        .Q(sig_data2rsc_decerr),
        .R(sig_coelsc_tag_reg1));
  LUT1 #(
    .INIT(2'h1)) 
    sig_coelsc_okay_reg_i_2
       (.I0(m_axi_sg_rresp[1]),
        .O(sig_coelsc_okay_reg_i_2_n_0));
  FDSE #(
    .INIT(1'b0)) 
    sig_coelsc_okay_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(m_axi_sg_rvalid),
        .D(sig_coelsc_okay_reg_i_2_n_0),
        .Q(sig_data2rsc_okay),
        .S(sig_coelsc_tag_reg1));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hF4)) 
    sig_coelsc_slverr_reg_i_1__0
       (.I0(m_axi_sg_rresp[0]),
        .I1(m_axi_sg_rresp[1]),
        .I2(sig_data2rsc_slverr),
        .O(sig_coelsc_slverr_reg0));
  FDRE #(
    .INIT(1'b0)) 
    sig_coelsc_slverr_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(m_axi_sg_rvalid),
        .D(sig_coelsc_slverr_reg0),
        .Q(sig_data2rsc_slverr),
        .R(sig_coelsc_tag_reg1));
  LUT2 #(
    .INIT(4'hE)) 
    sig_rd_sts_decerr_reg_i_3
       (.I0(sig_data2rsc_decerr),
        .I1(D),
        .O(sig_rd_sts_decerr_reg0));
endmodule

module Loopback_axi_dma_1_0_axi_sg_reset
   (sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2,
    m_axi_sg_aclk);
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1;
  input sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2;
  input m_axi_sg_aclk;

  wire m_axi_sg_aclk;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2;

  LUT1 #(
    .INIT(2'h1)) 
    mm2s_rready_i_1
       (.I0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0),
        .O(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_2),
        .Q(sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0),
        .R(1'b0));
endmodule

module Loopback_axi_dma_1_0_axi_sg_s2mm_basic_wrap
   (m_axi_sg_awlen,
    m_axi_sg_awsize,
    m_axi_sg_awvalid,
    m_axi_sg_awaddr,
    sig_init_done,
    s_axis_updt_cmd_tready,
    sig_init_done_0,
    sig_init_done_1,
    sig_init_done_2,
    updt_decerr_i,
    updt_interr_i,
    updt_slverr_i,
    m_axi_sg_bready,
    follower_full_mm2s0,
    \GEN_CH1_UPDATE.ch1_active_i_reg ,
    m_axi_sg_wvalid,
    m_axi_sg_wlast,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    m_axi_sg_aclk,
    sig_stream_rst,
    sig_init_done_reg,
    sig_init_done_reg_0,
    sig_init_done_reg_1,
    sig_init_done_reg_2,
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ,
    s_axis_updt_cmd_tvalid,
    m_axis_updt_sts_tready,
    m_axi_sg_bvalid,
    m_axi_sg_wready,
    follower_full_mm2s,
    D,
    out,
    Q,
    m_axi_sg_awready,
    m_axi_sg_bresp);
  output [0:0]m_axi_sg_awlen;
  output [0:0]m_axi_sg_awsize;
  output m_axi_sg_awvalid;
  output [27:0]m_axi_sg_awaddr;
  output sig_init_done;
  output s_axis_updt_cmd_tready;
  output sig_init_done_0;
  output sig_init_done_1;
  output sig_init_done_2;
  output updt_decerr_i;
  output updt_interr_i;
  output updt_slverr_i;
  output m_axi_sg_bready;
  output follower_full_mm2s0;
  output \GEN_CH1_UPDATE.ch1_active_i_reg ;
  output m_axi_sg_wvalid;
  output m_axi_sg_wlast;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  input m_axi_sg_aclk;
  input sig_stream_rst;
  input sig_init_done_reg;
  input sig_init_done_reg_0;
  input sig_init_done_reg_1;
  input sig_init_done_reg_2;
  input \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ;
  input s_axis_updt_cmd_tvalid;
  input m_axis_updt_sts_tready;
  input m_axi_sg_bvalid;
  input m_axi_sg_wready;
  input follower_full_mm2s;
  input [28:0]D;
  input out;
  input [0:0]Q;
  input m_axi_sg_awready;
  input [1:0]m_axi_sg_bresp;

  wire [28:0]D;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \GEN_CH1_UPDATE.ch1_active_i_reg ;
  wire \GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.sig_wr_fifo ;
  wire \GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_inhibit_rdy_n ;
  wire \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ;
  wire I_ADDR_CNTL_n_33;
  wire I_CMD_STATUS_n_10;
  wire I_CMD_STATUS_n_11;
  wire I_CMD_STATUS_n_12;
  wire I_CMD_STATUS_n_13;
  wire I_CMD_STATUS_n_14;
  wire I_CMD_STATUS_n_15;
  wire I_CMD_STATUS_n_16;
  wire I_CMD_STATUS_n_17;
  wire I_CMD_STATUS_n_18;
  wire I_CMD_STATUS_n_19;
  wire I_CMD_STATUS_n_20;
  wire I_CMD_STATUS_n_21;
  wire I_CMD_STATUS_n_22;
  wire I_CMD_STATUS_n_23;
  wire I_CMD_STATUS_n_24;
  wire I_CMD_STATUS_n_25;
  wire I_CMD_STATUS_n_26;
  wire I_CMD_STATUS_n_27;
  wire I_CMD_STATUS_n_28;
  wire I_CMD_STATUS_n_29;
  wire I_CMD_STATUS_n_30;
  wire I_CMD_STATUS_n_31;
  wire I_CMD_STATUS_n_32;
  wire I_CMD_STATUS_n_33;
  wire I_CMD_STATUS_n_34;
  wire I_CMD_STATUS_n_35;
  wire I_CMD_STATUS_n_36;
  wire I_CMD_STATUS_n_37;
  wire I_CMD_STATUS_n_38;
  wire I_CMD_STATUS_n_9;
  wire I_MSTR_SCC_n_10;
  wire I_MSTR_SCC_n_11;
  wire I_MSTR_SCC_n_12;
  wire I_MSTR_SCC_n_13;
  wire I_MSTR_SCC_n_14;
  wire I_MSTR_SCC_n_15;
  wire I_MSTR_SCC_n_16;
  wire I_MSTR_SCC_n_17;
  wire I_MSTR_SCC_n_18;
  wire I_MSTR_SCC_n_19;
  wire I_MSTR_SCC_n_2;
  wire I_MSTR_SCC_n_20;
  wire I_MSTR_SCC_n_21;
  wire I_MSTR_SCC_n_22;
  wire I_MSTR_SCC_n_23;
  wire I_MSTR_SCC_n_24;
  wire I_MSTR_SCC_n_25;
  wire I_MSTR_SCC_n_26;
  wire I_MSTR_SCC_n_27;
  wire I_MSTR_SCC_n_28;
  wire I_MSTR_SCC_n_29;
  wire I_MSTR_SCC_n_3;
  wire I_MSTR_SCC_n_30;
  wire I_MSTR_SCC_n_31;
  wire I_MSTR_SCC_n_32;
  wire I_MSTR_SCC_n_33;
  wire I_MSTR_SCC_n_34;
  wire I_MSTR_SCC_n_6;
  wire I_MSTR_SCC_n_8;
  wire I_MSTR_SCC_n_9;
  wire I_WR_STATUS_CNTLR_n_10;
  wire I_WR_STATUS_CNTLR_n_11;
  wire I_WR_STATUS_CNTLR_n_4;
  wire [0:0]Q;
  wire follower_full_mm2s;
  wire follower_full_mm2s0;
  wire m_axi_sg_aclk;
  wire [27:0]m_axi_sg_awaddr;
  wire [0:0]m_axi_sg_awlen;
  wire m_axi_sg_awready;
  wire [0:0]m_axi_sg_awsize;
  wire m_axi_sg_awvalid;
  wire m_axi_sg_bready;
  wire [1:0]m_axi_sg_bresp;
  wire m_axi_sg_bvalid;
  wire m_axi_sg_wlast;
  wire m_axi_sg_wready;
  wire m_axi_sg_wvalid;
  wire m_axis_updt_sts_tready;
  wire out;
  wire s_axis_updt_cmd_tready;
  wire s_axis_updt_cmd_tvalid;
  wire sig_addr2data_addr_posted;
  wire sig_addr2wsc_cmd_fifo_empty;
  wire sig_calc2dm_calc_err;
  wire sig_cmd_reg_empty;
  wire sig_coelsc_okay_reg;
  wire sig_data2all_tlast_error;
  wire sig_data2wsc_calc_err;
  wire sig_data2wsc_cmd_cmplt;
  wire sig_data2wsc_last_err;
  wire sig_dqual_reg_empty;
  wire sig_init_done;
  wire sig_init_done_0;
  wire sig_init_done_1;
  wire sig_init_done_2;
  wire sig_init_done_reg;
  wire sig_init_done_reg_0;
  wire sig_init_done_reg_1;
  wire sig_init_done_reg_2;
  wire sig_load_input_cmd;
  wire sig_mstr2data_cmd_valid;
  wire [0:0]sig_mstr2data_len;
  wire sig_next_calc_error_reg;
  wire sig_push_addr_reg1_out;
  wire sig_push_to_wsc;
  wire sig_stat2wsc_status_ready;
  wire sig_stream_rst;
  wire sig_tlast_err_stop;
  wire [6:4]sig_wsc2stat_status;
  wire sig_wsc2stat_status_valid;
  wire updt_decerr_i;
  wire updt_interr_i;
  wire updt_slverr_i;

  Loopback_axi_dma_1_0_axi_sg_addr_cntl__parameterized0 I_ADDR_CNTL
       (.Q({I_MSTR_SCC_n_8,I_MSTR_SCC_n_9,I_MSTR_SCC_n_10,I_MSTR_SCC_n_11,I_MSTR_SCC_n_12,I_MSTR_SCC_n_13,I_MSTR_SCC_n_14,I_MSTR_SCC_n_15,I_MSTR_SCC_n_16,I_MSTR_SCC_n_17,I_MSTR_SCC_n_18,I_MSTR_SCC_n_19,I_MSTR_SCC_n_20,I_MSTR_SCC_n_21,I_MSTR_SCC_n_22,I_MSTR_SCC_n_23,I_MSTR_SCC_n_24,I_MSTR_SCC_n_25,I_MSTR_SCC_n_26,I_MSTR_SCC_n_27,I_MSTR_SCC_n_28,I_MSTR_SCC_n_29,I_MSTR_SCC_n_30,I_MSTR_SCC_n_31,I_MSTR_SCC_n_32,I_MSTR_SCC_n_33,I_MSTR_SCC_n_34}),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_awaddr(m_axi_sg_awaddr),
        .m_axi_sg_awlen(m_axi_sg_awlen),
        .m_axi_sg_awready(m_axi_sg_awready),
        .m_axi_sg_awsize(m_axi_sg_awsize),
        .m_axi_sg_awvalid(m_axi_sg_awvalid),
        .out(sig_addr2data_addr_posted),
        .sig_addr2wsc_cmd_fifo_empty(sig_addr2wsc_cmd_fifo_empty),
        .sig_addr_reg_empty_reg_0(I_ADDR_CNTL_n_33),
        .sig_addr_valid_reg_reg_0(I_MSTR_SCC_n_6),
        .sig_addr_valid_reg_reg_1(\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .sig_calc2dm_calc_err(sig_calc2dm_calc_err),
        .sig_data2all_tlast_error(sig_data2all_tlast_error),
        .sig_mstr2data_len(sig_mstr2data_len),
        .\sig_next_addr_reg_reg[3]_0 (I_MSTR_SCC_n_2),
        .sig_posted_to_axi_2_reg_0(I_MSTR_SCC_n_3),
        .sig_push_addr_reg1_out(sig_push_addr_reg1_out));
  Loopback_axi_dma_1_0_axi_sg_cmd_status I_CMD_STATUS
       (.D({sig_coelsc_okay_reg,sig_wsc2stat_status}),
        .\GEN_ASYNC_RESET.scndry_resetn_reg (\GEN_ASYNC_RESET.scndry_resetn_reg ),
        .Q({I_CMD_STATUS_n_9,I_CMD_STATUS_n_10,I_CMD_STATUS_n_11,I_CMD_STATUS_n_12,I_CMD_STATUS_n_13,I_CMD_STATUS_n_14,I_CMD_STATUS_n_15,I_CMD_STATUS_n_16,I_CMD_STATUS_n_17,I_CMD_STATUS_n_18,I_CMD_STATUS_n_19,I_CMD_STATUS_n_20,I_CMD_STATUS_n_21,I_CMD_STATUS_n_22,I_CMD_STATUS_n_23,I_CMD_STATUS_n_24,I_CMD_STATUS_n_25,I_CMD_STATUS_n_26,I_CMD_STATUS_n_27,I_CMD_STATUS_n_28,I_CMD_STATUS_n_29,I_CMD_STATUS_n_30,I_CMD_STATUS_n_31,I_CMD_STATUS_n_32,I_CMD_STATUS_n_33,I_CMD_STATUS_n_34,I_CMD_STATUS_n_35,I_CMD_STATUS_n_36,I_CMD_STATUS_n_37,I_CMD_STATUS_n_38}),
        .\USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63] (D),
        .\USE_SINGLE_REG.sig_regfifo_full_reg_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_updt_sts_tready(m_axis_updt_sts_tready),
        .out(out),
        .s_axis_updt_cmd_tready(s_axis_updt_cmd_tready),
        .s_axis_updt_cmd_tvalid(s_axis_updt_cmd_tvalid),
        .sig_addr2wsc_cmd_fifo_empty(sig_addr2wsc_cmd_fifo_empty),
        .sig_cmd_reg_empty(sig_cmd_reg_empty),
        .sig_data2all_tlast_error(sig_data2all_tlast_error),
        .sig_init_done(sig_init_done),
        .sig_init_done_0(sig_init_done_0),
        .sig_init_done_reg(sig_init_done_reg),
        .sig_init_done_reg_0(sig_init_done_reg_0),
        .sig_load_input_cmd(sig_load_input_cmd),
        .sig_stat2wsc_status_ready(sig_stat2wsc_status_ready),
        .sig_stream_rst(sig_stream_rst),
        .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid),
        .updt_decerr_i(updt_decerr_i),
        .updt_interr_i(updt_interr_i),
        .updt_slverr_i(updt_slverr_i));
  Loopback_axi_dma_1_0_axi_sg_scc_wr I_MSTR_SCC
       (.Q({I_CMD_STATUS_n_9,I_CMD_STATUS_n_10,I_CMD_STATUS_n_11,I_CMD_STATUS_n_12,I_CMD_STATUS_n_13,I_CMD_STATUS_n_14,I_CMD_STATUS_n_15,I_CMD_STATUS_n_16,I_CMD_STATUS_n_17,I_CMD_STATUS_n_18,I_CMD_STATUS_n_19,I_CMD_STATUS_n_20,I_CMD_STATUS_n_21,I_CMD_STATUS_n_22,I_CMD_STATUS_n_23,I_CMD_STATUS_n_24,I_CMD_STATUS_n_25,I_CMD_STATUS_n_26,I_CMD_STATUS_n_27,I_CMD_STATUS_n_28,I_CMD_STATUS_n_29,I_CMD_STATUS_n_30,I_CMD_STATUS_n_31,I_CMD_STATUS_n_32,I_CMD_STATUS_n_33,I_CMD_STATUS_n_34,I_CMD_STATUS_n_35,I_CMD_STATUS_n_36,I_CMD_STATUS_n_37,I_CMD_STATUS_n_38}),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .sig_addr2wsc_cmd_fifo_empty(sig_addr2wsc_cmd_fifo_empty),
        .sig_calc2dm_calc_err(sig_calc2dm_calc_err),
        .\sig_cmd_addr_reg_reg[31]_0 ({I_MSTR_SCC_n_8,I_MSTR_SCC_n_9,I_MSTR_SCC_n_10,I_MSTR_SCC_n_11,I_MSTR_SCC_n_12,I_MSTR_SCC_n_13,I_MSTR_SCC_n_14,I_MSTR_SCC_n_15,I_MSTR_SCC_n_16,I_MSTR_SCC_n_17,I_MSTR_SCC_n_18,I_MSTR_SCC_n_19,I_MSTR_SCC_n_20,I_MSTR_SCC_n_21,I_MSTR_SCC_n_22,I_MSTR_SCC_n_23,I_MSTR_SCC_n_24,I_MSTR_SCC_n_25,I_MSTR_SCC_n_26,I_MSTR_SCC_n_27,I_MSTR_SCC_n_28,I_MSTR_SCC_n_29,I_MSTR_SCC_n_30,I_MSTR_SCC_n_31,I_MSTR_SCC_n_32,I_MSTR_SCC_n_33,I_MSTR_SCC_n_34}),
        .\sig_cmd_addr_reg_reg[3]_0 (I_MSTR_SCC_n_2),
        .\sig_cmd_addr_reg_reg[3]_1 (I_ADDR_CNTL_n_33),
        .sig_cmd_reg_empty(sig_cmd_reg_empty),
        .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(I_MSTR_SCC_n_3),
        .sig_data2all_tlast_error(sig_data2all_tlast_error),
        .sig_load_input_cmd(sig_load_input_cmd),
        .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid),
        .sig_mstr2data_len(sig_mstr2data_len),
        .sig_posted_to_axi_2_reg(\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .sig_push_addr_reg1_out(sig_push_addr_reg1_out),
        .sig_stream_rst(sig_stream_rst),
        .sm_set_error_reg_0(I_MSTR_SCC_n_6));
  Loopback_axi_dma_1_0_axi_sg_wrdata_cntl I_WR_DATA_CNTL
       (.D(D[0]),
        .\GEN_CH1_UPDATE.ch1_active_i_reg (\GEN_CH1_UPDATE.ch1_active_i_reg ),
        .\GEN_OMIT_INDET_BTT.sig_tlast_err_stop_reg_0 (I_WR_STATUS_CNTLR_n_4),
        .\GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg (out),
        .Q(Q),
        .\USE_SRL_FIFO.sig_wr_fifo (\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.sig_wr_fifo ),
        .follower_full_mm2s(follower_full_mm2s),
        .follower_full_mm2s0(follower_full_mm2s0),
        .in({sig_data2wsc_calc_err,sig_data2wsc_last_err,sig_data2wsc_cmd_cmplt}),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_wlast(m_axi_sg_wlast),
        .m_axi_sg_wready(m_axi_sg_wready),
        .m_axi_sg_wvalid(m_axi_sg_wvalid),
        .out(sig_addr2data_addr_posted),
        .sig_calc2dm_calc_err(sig_calc2dm_calc_err),
        .sig_data2all_tlast_error(sig_data2all_tlast_error),
        .sig_data2wsc_calc_err_reg_0(I_WR_STATUS_CNTLR_n_10),
        .\sig_dbeat_cntr_reg[0]_0 (I_MSTR_SCC_n_2),
        .sig_dqual_reg_empty(sig_dqual_reg_empty),
        .sig_dqual_reg_empty_reg_0(I_WR_STATUS_CNTLR_n_11),
        .sig_inhibit_rdy_n(\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_inhibit_rdy_n ),
        .sig_next_calc_error_reg(sig_next_calc_error_reg),
        .sig_push_err2wsc_reg_0(\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .sig_push_to_wsc(sig_push_to_wsc),
        .sig_stream_rst(sig_stream_rst),
        .sig_tlast_err_stop(sig_tlast_err_stop));
  Loopback_axi_dma_1_0_axi_sg_wr_status_cntl I_WR_STATUS_CNTLR
       (.D({sig_coelsc_okay_reg,sig_wsc2stat_status}),
        .FIFO_Full_reg(I_WR_STATUS_CNTLR_n_4),
        .FIFO_Full_reg_0(I_WR_STATUS_CNTLR_n_10),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_0 (I_WR_STATUS_CNTLR_n_11),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_1 (\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .\USE_SRL_FIFO.sig_wr_fifo (\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.sig_wr_fifo ),
        .in({sig_data2wsc_calc_err,sig_data2wsc_last_err,sig_data2wsc_cmd_cmplt}),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_bready(m_axi_sg_bready),
        .m_axi_sg_bresp(m_axi_sg_bresp),
        .m_axi_sg_bvalid(m_axi_sg_bvalid),
        .sig_dqual_reg_empty(sig_dqual_reg_empty),
        .sig_inhibit_rdy_n(\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/sig_inhibit_rdy_n ),
        .sig_init_done_1(sig_init_done_1),
        .sig_init_done_2(sig_init_done_2),
        .sig_init_done_reg(sig_init_done_reg_1),
        .sig_init_done_reg_0(sig_init_done_reg_2),
        .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid),
        .sig_next_calc_error_reg(sig_next_calc_error_reg),
        .sig_push_to_wsc(sig_push_to_wsc),
        .sig_stat2wsc_status_ready(sig_stat2wsc_status_ready),
        .sig_stream_rst(sig_stream_rst),
        .sig_tlast_err_stop(sig_tlast_err_stop),
        .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid));
endmodule

module Loopback_axi_dma_1_0_axi_sg_scc
   (sig_cmd_reg_empty,
    D,
    sig_mstr2addr_cmd_valid,
    sig_cmd_burst_reg,
    sm_set_error_reg_0,
    sm_set_error,
    sig_cmd2addr_valid1_reg_0,
    \sig_cmd_addr_reg_reg[31]_0 ,
    \sig_cmd_addr_reg_reg[6]_0 ,
    sig_load_input_cmd,
    m_axi_sg_aclk,
    Q,
    sig_posted_to_axi_reg,
    sig_addr2rsc_cmd_fifo_empty,
    sm_set_error_reg_1);
  output sig_cmd_reg_empty;
  output [1:0]D;
  output sig_mstr2addr_cmd_valid;
  output [0:0]sig_cmd_burst_reg;
  output sm_set_error_reg_0;
  output sm_set_error;
  output sig_cmd2addr_valid1_reg_0;
  output [25:0]\sig_cmd_addr_reg_reg[31]_0 ;
  input \sig_cmd_addr_reg_reg[6]_0 ;
  input sig_load_input_cmd;
  input m_axi_sg_aclk;
  input [27:0]Q;
  input sig_posted_to_axi_reg;
  input sig_addr2rsc_cmd_fifo_empty;
  input sm_set_error_reg_1;

  wire [1:0]D;
  wire [27:0]Q;
  wire m_axi_sg_aclk;
  wire sig_addr2rsc_cmd_fifo_empty;
  wire sig_btt_is_zero__0;
  wire sig_btt_is_zero_reg;
  wire sig_cmd2addr_valid1_reg_0;
  wire [25:0]\sig_cmd_addr_reg_reg[31]_0 ;
  wire \sig_cmd_addr_reg_reg[6]_0 ;
  wire [0:0]sig_cmd_burst_reg;
  wire sig_cmd_reg_empty;
  wire sig_load_input_cmd;
  wire sig_mstr2addr_cmd_valid;
  wire sig_posted_to_axi_reg;
  wire sm_set_error;
  wire sm_set_error_i_1_n_0;
  wire sm_set_error_reg_0;
  wire sm_set_error_reg_1;

  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT1 #(
    .INIT(2'h1)) 
    sig_addr_valid_reg_i_1
       (.I0(sm_set_error),
        .O(sm_set_error_reg_0));
  LUT2 #(
    .INIT(4'h1)) 
    sig_btt_is_zero
       (.I0(Q[0]),
        .I1(Q[27]),
        .O(sig_btt_is_zero__0));
  FDRE #(
    .INIT(1'b0)) 
    sig_btt_is_zero_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(sig_btt_is_zero__0),
        .Q(sig_btt_is_zero_reg),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE sig_cmd2addr_valid1_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(1'b1),
        .Q(sig_mstr2addr_cmd_valid),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[5]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [4]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[6]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [5]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[7]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [6]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[8]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [7]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[9]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [8]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[10]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [9]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[11]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [10]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[12]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [11]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[13]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [12]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[14]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [13]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[15]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [14]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[16]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [15]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[17]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [16]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[18]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [17]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[19]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [18]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[20]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [19]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[21]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [20]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[22]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [21]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[23]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [22]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[24]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [23]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[25]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [24]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[26]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [25]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[1]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [0]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[2]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [1]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[3]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [2]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[4]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [3]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_burst_reg_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[0]),
        .Q(sig_cmd_burst_reg),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  FDSE #(
    .INIT(1'b0)) 
    sig_cmd_reg_empty_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(1'b0),
        .Q(sig_cmd_reg_empty),
        .S(\sig_cmd_addr_reg_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_tag_reg_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[27]),
        .Q(D[1]),
        .R(\sig_cmd_addr_reg_reg[6]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \sig_next_len_reg[1]_i_1 
       (.I0(D[1]),
        .O(D[0]));
  LUT3 #(
    .INIT(8'h80)) 
    sig_posted_to_axi_2_i_1__1
       (.I0(sig_mstr2addr_cmd_valid),
        .I1(sig_posted_to_axi_reg),
        .I2(sig_addr2rsc_cmd_fifo_empty),
        .O(sig_cmd2addr_valid1_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT2 #(
    .INIT(4'hE)) 
    sm_set_error_i_1
       (.I0(sig_btt_is_zero_reg),
        .I1(sm_set_error),
        .O(sm_set_error_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sm_set_error_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sm_set_error_i_1_n_0),
        .Q(sm_set_error),
        .R(sm_set_error_reg_1));
endmodule

module Loopback_axi_dma_1_0_axi_sg_scc_wr
   (sig_cmd_reg_empty,
    sig_mstr2data_cmd_valid,
    \sig_cmd_addr_reg_reg[3]_0 ,
    sig_cmd_stat_rst_user_reg_n_cdc_from_reg,
    sig_push_addr_reg1_out,
    sig_mstr2data_len,
    sm_set_error_reg_0,
    sig_calc2dm_calc_err,
    \sig_cmd_addr_reg_reg[31]_0 ,
    \sig_cmd_addr_reg_reg[3]_1 ,
    sig_load_input_cmd,
    m_axi_sg_aclk,
    Q,
    sig_posted_to_axi_2_reg,
    sig_addr2wsc_cmd_fifo_empty,
    sig_data2all_tlast_error,
    sig_stream_rst);
  output sig_cmd_reg_empty;
  output sig_mstr2data_cmd_valid;
  output \sig_cmd_addr_reg_reg[3]_0 ;
  output sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  output sig_push_addr_reg1_out;
  output [0:0]sig_mstr2data_len;
  output sm_set_error_reg_0;
  output sig_calc2dm_calc_err;
  output [26:0]\sig_cmd_addr_reg_reg[31]_0 ;
  input \sig_cmd_addr_reg_reg[3]_1 ;
  input sig_load_input_cmd;
  input m_axi_sg_aclk;
  input [29:0]Q;
  input sig_posted_to_axi_2_reg;
  input sig_addr2wsc_cmd_fifo_empty;
  input sig_data2all_tlast_error;
  input sig_stream_rst;

  wire [29:0]Q;
  wire m_axi_sg_aclk;
  wire sig_addr2wsc_cmd_fifo_empty;
  wire sig_btt_is_zero__0;
  wire sig_btt_is_zero_reg_reg_n_0;
  wire sig_calc2dm_calc_err;
  wire [26:0]\sig_cmd_addr_reg_reg[31]_0 ;
  wire \sig_cmd_addr_reg_reg[3]_0 ;
  wire \sig_cmd_addr_reg_reg[3]_1 ;
  wire sig_cmd_reg_empty;
  wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg;
  wire sig_data2all_tlast_error;
  wire sig_load_input_cmd;
  wire sig_mstr2data_cmd_valid;
  wire [0:0]sig_mstr2data_len;
  wire sig_posted_to_axi_2_reg;
  wire sig_push_addr_reg1_out;
  wire sig_stream_rst;
  wire sm_set_error_i_1_n_0;
  wire sm_set_error_reg_0;

  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT1 #(
    .INIT(2'h1)) 
    sig_addr_valid_reg_i_1__0
       (.I0(sig_calc2dm_calc_err),
        .O(sm_set_error_reg_0));
  LUT2 #(
    .INIT(4'h1)) 
    sig_btt_is_zero
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(sig_btt_is_zero__0));
  FDRE #(
    .INIT(1'b0)) 
    sig_btt_is_zero_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(sig_btt_is_zero__0),
        .Q(sig_btt_is_zero_reg_reg_n_0),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    sig_cmd2addr_valid1_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(1'b1),
        .Q(sig_mstr2data_cmd_valid),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[8]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [5]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[9]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [6]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[10]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [7]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[11]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [8]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[12]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [9]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[13]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [10]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[14]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [11]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[15]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [12]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[16]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [13]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[17]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [14]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[18]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [15]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[19]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [16]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[20]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [17]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[21]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [18]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[22]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [19]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[23]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [20]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[24]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [21]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[25]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [22]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[26]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [23]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[27]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [24]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[28]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [25]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[29]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [26]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[2]),
        .Q(\sig_cmd_addr_reg_reg[3]_0 ),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[3]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [0]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[4]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [1]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[5]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [2]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[6]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [3]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_cmd_addr_reg_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(Q[7]),
        .Q(\sig_cmd_addr_reg_reg[31]_0 [4]),
        .R(\sig_cmd_addr_reg_reg[3]_1 ));
  FDSE #(
    .INIT(1'b0)) 
    sig_cmd_reg_empty_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_load_input_cmd),
        .D(1'b0),
        .Q(sig_cmd_reg_empty),
        .S(\sig_cmd_addr_reg_reg[3]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \sig_next_addr_reg[31]_i_2__0 
       (.I0(sig_mstr2data_cmd_valid),
        .I1(sig_addr2wsc_cmd_fifo_empty),
        .I2(sig_data2all_tlast_error),
        .O(sig_push_addr_reg1_out));
  LUT1 #(
    .INIT(2'h1)) 
    \sig_next_len_reg[2]_i_1 
       (.I0(\sig_cmd_addr_reg_reg[3]_0 ),
        .O(sig_mstr2data_len));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    sig_posted_to_axi_2_i_1
       (.I0(sig_posted_to_axi_2_reg),
        .I1(sig_mstr2data_cmd_valid),
        .I2(sig_addr2wsc_cmd_fifo_empty),
        .I3(sig_data2all_tlast_error),
        .O(sig_cmd_stat_rst_user_reg_n_cdc_from_reg));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT2 #(
    .INIT(4'hE)) 
    sm_set_error_i_1
       (.I0(sig_btt_is_zero_reg_reg_n_0),
        .I1(sig_calc2dm_calc_err),
        .O(sm_set_error_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sm_set_error_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sm_set_error_i_1_n_0),
        .Q(sig_calc2dm_calc_err),
        .R(sig_stream_rst));
endmodule

module Loopback_axi_dma_1_0_axi_sg_updt_cmdsts_if
   (updt_decerr,
    updt_interr,
    updt_slverr,
    s_axis_updt_cmd_tvalid,
    updt_done,
    ch1_updt_ioc_irq_set0,
    updt_error_reg_0,
    sinit,
    updt_decerr_i,
    m_axi_sg_aclk,
    updt_interr_i,
    updt_slverr_i,
    s_axis_updt_cmd_tvalid_reg_0,
    updt_done_reg_0,
    ch1_updt_ioc);
  output updt_decerr;
  output updt_interr;
  output updt_slverr;
  output s_axis_updt_cmd_tvalid;
  output updt_done;
  output ch1_updt_ioc_irq_set0;
  output updt_error_reg_0;
  input sinit;
  input updt_decerr_i;
  input m_axi_sg_aclk;
  input updt_interr_i;
  input updt_slverr_i;
  input s_axis_updt_cmd_tvalid_reg_0;
  input updt_done_reg_0;
  input ch1_updt_ioc;

  wire ch1_updt_ioc;
  wire ch1_updt_ioc_irq_set0;
  wire m_axi_sg_aclk;
  wire s_axis_updt_cmd_tvalid;
  wire s_axis_updt_cmd_tvalid_reg_0;
  wire sinit;
  wire updt_decerr;
  wire updt_decerr_i;
  wire updt_done;
  wire updt_done_reg_0;
  wire updt_error_i_1_n_0;
  wire updt_error_reg_0;
  wire updt_interr;
  wire updt_interr_i;
  wire updt_slverr;
  wire updt_slverr_i;

  LUT2 #(
    .INIT(4'h8)) 
    \GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_i_1 
       (.I0(updt_done),
        .I1(ch1_updt_ioc),
        .O(ch1_updt_ioc_irq_set0));
  FDRE s_axis_updt_cmd_tvalid_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axis_updt_cmd_tvalid_reg_0),
        .Q(s_axis_updt_cmd_tvalid),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    updt_decerr_i_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_decerr_i),
        .Q(updt_decerr),
        .R(sinit));
  FDRE updt_done_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_done_reg_0),
        .Q(updt_done),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    updt_error_i_1
       (.I0(updt_slverr),
        .I1(updt_interr),
        .I2(updt_decerr),
        .I3(updt_error_reg_0),
        .O(updt_error_i_1_n_0));
  FDRE updt_error_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_error_i_1_n_0),
        .Q(updt_error_reg_0),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    updt_interr_i_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_interr_i),
        .Q(updt_interr),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    updt_slverr_i_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_slverr_i),
        .Q(updt_slverr),
        .R(sinit));
endmodule

module Loopback_axi_dma_1_0_axi_sg_updt_mngr
   (\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg ,
    ch1_updt_active,
    mm2s_updt_idle,
    s_axis_updt_cmd_tvalid,
    updt_error,
    \GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_0 ,
    \GEN_CH1_UPDATE.ch1_dma_interr_set_reg ,
    mm2s_dma_interr_set,
    mm2s_dma_slverr_set,
    mm2s_dma_decerr_set,
    \GEN_CH1_UPDATE.ch1_updt_slverr_set_reg ,
    \GEN_CH1_UPDATE.ch1_updt_interr_set_reg ,
    \GEN_CH1_UPDATE.ch1_updt_decerr_set_reg ,
    D,
    m_axi_sg_wdata,
    \GEN_CH1_UPDATE.ch1_dma_interr_set_reg_0 ,
    \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg ,
    \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg ,
    \updt_error_addr_reg[31] ,
    sinit,
    m_axi_sg_aclk,
    updt_decerr_i,
    updt_interr_i,
    updt_slverr_i,
    updt_done_reg,
    ftch_error,
    out,
    \GEN_CH1_UPDATE.ch1_updt_idle_reg ,
    E,
    ptr_queue_empty,
    follower_empty_mm2s,
    ch1_updt_ioc,
    mm2s_irqthresh_wren,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ,
    mm2s_dly_irq_set,
    \ftch_error_addr_reg[8] ,
    Q,
    s_axis_updt_cmd_tready,
    dma_interr_reg,
    dma_slverr_reg,
    dma_decerr_reg,
    \update_address_reg[31] ,
    ch1_dma_interr,
    ch1_dma_slverr,
    ch1_dma_decerr);
  output \GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg ;
  output ch1_updt_active;
  output mm2s_updt_idle;
  output s_axis_updt_cmd_tvalid;
  output updt_error;
  output [0:0]\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_0 ;
  output [0:0]\GEN_CH1_UPDATE.ch1_dma_interr_set_reg ;
  output mm2s_dma_interr_set;
  output mm2s_dma_slverr_set;
  output mm2s_dma_decerr_set;
  output \GEN_CH1_UPDATE.ch1_updt_slverr_set_reg ;
  output \GEN_CH1_UPDATE.ch1_updt_interr_set_reg ;
  output \GEN_CH1_UPDATE.ch1_updt_decerr_set_reg ;
  output [27:0]D;
  output [29:0]m_axi_sg_wdata;
  output \GEN_CH1_UPDATE.ch1_dma_interr_set_reg_0 ;
  output \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg ;
  output \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg ;
  output [25:0]\updt_error_addr_reg[31] ;
  input sinit;
  input m_axi_sg_aclk;
  input updt_decerr_i;
  input updt_interr_i;
  input updt_slverr_i;
  input updt_done_reg;
  input ftch_error;
  input out;
  input \GEN_CH1_UPDATE.ch1_updt_idle_reg ;
  input [0:0]E;
  input ptr_queue_empty;
  input follower_empty_mm2s;
  input ch1_updt_ioc;
  input mm2s_irqthresh_wren;
  input [0:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ;
  input mm2s_dly_irq_set;
  input \ftch_error_addr_reg[8] ;
  input [29:0]Q;
  input s_axis_updt_cmd_tready;
  input dma_interr_reg;
  input dma_slverr_reg;
  input dma_decerr_reg;
  input [25:0]\update_address_reg[31] ;
  input ch1_dma_interr;
  input ch1_dma_slverr;
  input ch1_dma_decerr;

  wire [27:0]D;
  wire [0:0]E;
  wire \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg ;
  wire [0:0]\GEN_CH1_UPDATE.ch1_dma_interr_set_reg ;
  wire \GEN_CH1_UPDATE.ch1_dma_interr_set_reg_0 ;
  wire \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg ;
  wire \GEN_CH1_UPDATE.ch1_updt_decerr_set_reg ;
  wire \GEN_CH1_UPDATE.ch1_updt_idle_reg ;
  wire \GEN_CH1_UPDATE.ch1_updt_interr_set_reg ;
  wire \GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg ;
  wire [0:0]\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_0 ;
  wire \GEN_CH1_UPDATE.ch1_updt_slverr_set_reg ;
  wire [0:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ;
  wire I_UPDT_SG_n_69;
  wire [29:0]Q;
  wire ch1_dma_decerr;
  wire ch1_dma_interr;
  wire ch1_dma_slverr;
  wire ch1_updt_active;
  wire ch1_updt_ioc;
  wire ch1_updt_ioc_irq_set0;
  wire dma_decerr_reg;
  wire dma_interr_reg;
  wire dma_slverr_reg;
  wire follower_empty_mm2s;
  wire ftch_error;
  wire \ftch_error_addr_reg[8] ;
  wire m_axi_sg_aclk;
  wire [29:0]m_axi_sg_wdata;
  wire mm2s_dly_irq_set;
  wire mm2s_dma_decerr_set;
  wire mm2s_dma_interr_set;
  wire mm2s_dma_slverr_set;
  wire mm2s_irqthresh_wren;
  wire mm2s_updt_idle;
  wire out;
  wire ptr_queue_empty;
  wire s_axis_updt_cmd_tready;
  wire s_axis_updt_cmd_tvalid;
  wire sinit;
  wire [25:0]\update_address_reg[31] ;
  wire updt_decerr;
  wire updt_decerr_i;
  wire updt_done;
  wire updt_done_reg;
  wire updt_error;
  wire [25:0]\updt_error_addr_reg[31] ;
  wire updt_interr;
  wire updt_interr_i;
  wire updt_slverr;
  wire updt_slverr_i;

  Loopback_axi_dma_1_0_axi_sg_updt_cmdsts_if I_UPDT_CMDSTS_IF
       (.ch1_updt_ioc(ch1_updt_ioc),
        .ch1_updt_ioc_irq_set0(ch1_updt_ioc_irq_set0),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .s_axis_updt_cmd_tvalid(s_axis_updt_cmd_tvalid),
        .s_axis_updt_cmd_tvalid_reg_0(I_UPDT_SG_n_69),
        .sinit(sinit),
        .updt_decerr(updt_decerr),
        .updt_decerr_i(updt_decerr_i),
        .updt_done(updt_done),
        .updt_done_reg_0(updt_done_reg),
        .updt_error_reg_0(updt_error),
        .updt_interr(updt_interr),
        .updt_interr_i(updt_interr_i),
        .updt_slverr(updt_slverr),
        .updt_slverr_i(updt_slverr_i));
  Loopback_axi_dma_1_0_axi_sg_updt_sm I_UPDT_SG
       (.D(D),
        .E(E),
        .\FSM_sequential_updt_cs_reg[2]_0 (updt_error),
        .\GEN_CH1_UPDATE.ch1_active_i_reg_0 (ch1_updt_active),
        .\GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_0 (mm2s_dma_decerr_set),
        .\GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_1 (\GEN_CH1_UPDATE.ch1_dma_decerr_set_reg ),
        .\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_0 (\GEN_CH1_UPDATE.ch1_dma_interr_set_reg ),
        .\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_1 (mm2s_dma_interr_set),
        .\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_2 (\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_0 ),
        .\GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_0 (mm2s_dma_slverr_set),
        .\GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_1 (\GEN_CH1_UPDATE.ch1_dma_slverr_set_reg ),
        .\GEN_CH1_UPDATE.ch1_updt_decerr_set_reg_0 (\GEN_CH1_UPDATE.ch1_updt_decerr_set_reg ),
        .\GEN_CH1_UPDATE.ch1_updt_idle_reg_0 (\GEN_CH1_UPDATE.ch1_updt_idle_reg ),
        .\GEN_CH1_UPDATE.ch1_updt_interr_set_reg_0 (\GEN_CH1_UPDATE.ch1_updt_interr_set_reg ),
        .\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_0 (\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg ),
        .\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_1 (\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_0 ),
        .\GEN_CH1_UPDATE.ch1_updt_slverr_set_reg_0 (\GEN_CH1_UPDATE.ch1_updt_slverr_set_reg ),
        .\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] (\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ),
        .Q(Q),
        .\USE_SINGLE_REG.sig_regfifo_empty_reg_reg (I_UPDT_SG_n_69),
        .ch1_dma_decerr(ch1_dma_decerr),
        .ch1_dma_interr(ch1_dma_interr),
        .ch1_dma_slverr(ch1_dma_slverr),
        .ch1_updt_ioc_irq_set0(ch1_updt_ioc_irq_set0),
        .dma_decerr_reg(dma_decerr_reg),
        .dma_interr_reg(dma_interr_reg),
        .dma_slverr_reg(dma_slverr_reg),
        .follower_empty_mm2s(follower_empty_mm2s),
        .ftch_error(ftch_error),
        .\ftch_error_addr_reg[8] (\ftch_error_addr_reg[8] ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_wdata(m_axi_sg_wdata),
        .mm2s_dly_irq_set(mm2s_dly_irq_set),
        .mm2s_irqthresh_wren(mm2s_irqthresh_wren),
        .mm2s_updt_idle(mm2s_updt_idle),
        .out(out),
        .ptr_queue_empty(ptr_queue_empty),
        .s_axis_updt_cmd_tready(s_axis_updt_cmd_tready),
        .s_axis_updt_cmd_tvalid(s_axis_updt_cmd_tvalid),
        .sinit(sinit),
        .\update_address_reg[31]_0 (\update_address_reg[31] ),
        .updt_decerr(updt_decerr),
        .updt_done(updt_done),
        .\updt_error_addr_reg[31]_0 (\updt_error_addr_reg[31] ),
        .updt_interr(updt_interr),
        .updt_slverr(updt_slverr));
endmodule

module Loopback_axi_dma_1_0_axi_sg_updt_q_mngr
   (ptr_queue_full,
    ptr_queue_empty,
    sts_queue_full,
    follower_full_mm2s,
    follower_empty_mm2s,
    updt_curdesc_wren_reg,
    ch1_updt_ioc,
    ch1_dma_interr,
    ch1_dma_slverr,
    ch1_dma_decerr,
    Q,
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg ,
    \updt_curdesc_reg[31] ,
    E,
    m_axi_sg_aclk,
    sinit,
    ch1_updt_active,
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32] ,
    follower_full_mm2s0,
    updt_ioc_reg,
    out,
    mm2s_dma_interr_set,
    mm2s_dma_slverr_set,
    mm2s_dma_decerr_set,
    ftch_error,
    \FSM_sequential_pntr_cs_reg[1] ,
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31] ,
    D);
  output ptr_queue_full;
  output ptr_queue_empty;
  output sts_queue_full;
  output follower_full_mm2s;
  output follower_empty_mm2s;
  output [0:0]updt_curdesc_wren_reg;
  output ch1_updt_ioc;
  output ch1_dma_interr;
  output ch1_dma_slverr;
  output ch1_dma_decerr;
  output [29:0]Q;
  output \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg ;
  output [25:0]\updt_curdesc_reg[31] ;
  input [0:0]E;
  input m_axi_sg_aclk;
  input sinit;
  input ch1_updt_active;
  input [0:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32] ;
  input follower_full_mm2s0;
  input updt_ioc_reg;
  input out;
  input mm2s_dma_interr_set;
  input mm2s_dma_slverr_set;
  input mm2s_dma_decerr_set;
  input ftch_error;
  input \FSM_sequential_pntr_cs_reg[1] ;
  input [25:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31] ;
  input [30:0]D;

  wire [30:0]D;
  wire [0:0]E;
  wire \FSM_sequential_pntr_cs_reg[1] ;
  wire \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg ;
  wire [25:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31] ;
  wire [0:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32] ;
  wire [29:0]Q;
  wire ch1_dma_decerr;
  wire ch1_dma_interr;
  wire ch1_dma_slverr;
  wire ch1_updt_active;
  wire ch1_updt_ioc;
  wire follower_empty_mm2s;
  wire follower_full_mm2s;
  wire follower_full_mm2s0;
  wire ftch_error;
  wire m_axi_sg_aclk;
  wire mm2s_dma_decerr_set;
  wire mm2s_dma_interr_set;
  wire mm2s_dma_slverr_set;
  wire out;
  wire ptr_queue_empty;
  wire ptr_queue_full;
  wire sinit;
  wire sts_queue_full;
  wire [25:0]\updt_curdesc_reg[31] ;
  wire [0:0]updt_curdesc_wren_reg;
  wire updt_ioc_reg;

  Loopback_axi_dma_1_0_axi_sg_updt_queue \GEN_QUEUE.I_UPDT_DESC_QUEUE 
       (.D(D),
        .E(E),
        .\FSM_sequential_pntr_cs_reg[1]_0 (\FSM_sequential_pntr_cs_reg[1] ),
        .\GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_0 (follower_empty_mm2s),
        .\GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_1 (\GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg ),
        .\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 (\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31] ),
        .\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_empty_reg_0 (ptr_queue_empty),
        .\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 (\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32] ),
        .Q(Q),
        .ch1_dma_decerr(ch1_dma_decerr),
        .ch1_dma_interr(ch1_dma_interr),
        .ch1_dma_slverr(ch1_dma_slverr),
        .ch1_updt_active(ch1_updt_active),
        .ch1_updt_ioc(ch1_updt_ioc),
        .follower_full_mm2s(follower_full_mm2s),
        .follower_full_mm2s0(follower_full_mm2s0),
        .ftch_error(ftch_error),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .mm2s_dma_decerr_set(mm2s_dma_decerr_set),
        .mm2s_dma_interr_set(mm2s_dma_interr_set),
        .mm2s_dma_slverr_set(mm2s_dma_slverr_set),
        .out(out),
        .ptr_queue_full(ptr_queue_full),
        .sinit(sinit),
        .sts_queue_full(sts_queue_full),
        .\updt_curdesc_reg[31]_0 (\updt_curdesc_reg[31] ),
        .updt_curdesc_wren_reg_0(updt_curdesc_wren_reg),
        .updt_ioc_reg_0(updt_ioc_reg));
endmodule

module Loopback_axi_dma_1_0_axi_sg_updt_queue
   (ptr_queue_full,
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_empty_reg_0 ,
    sts_queue_full,
    follower_full_mm2s,
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_0 ,
    updt_curdesc_wren_reg_0,
    ch1_updt_ioc,
    ch1_dma_interr,
    ch1_dma_slverr,
    ch1_dma_decerr,
    Q,
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_1 ,
    \updt_curdesc_reg[31]_0 ,
    E,
    m_axi_sg_aclk,
    sinit,
    ch1_updt_active,
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ,
    follower_full_mm2s0,
    updt_ioc_reg_0,
    out,
    mm2s_dma_interr_set,
    mm2s_dma_slverr_set,
    mm2s_dma_decerr_set,
    ftch_error,
    \FSM_sequential_pntr_cs_reg[1]_0 ,
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 ,
    D);
  output ptr_queue_full;
  output \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_empty_reg_0 ;
  output sts_queue_full;
  output follower_full_mm2s;
  output \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_0 ;
  output [0:0]updt_curdesc_wren_reg_0;
  output ch1_updt_ioc;
  output ch1_dma_interr;
  output ch1_dma_slverr;
  output ch1_dma_decerr;
  output [29:0]Q;
  output \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_1 ;
  output [25:0]\updt_curdesc_reg[31]_0 ;
  input [0:0]E;
  input m_axi_sg_aclk;
  input sinit;
  input ch1_updt_active;
  input [0:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ;
  input follower_full_mm2s0;
  input updt_ioc_reg_0;
  input out;
  input mm2s_dma_interr_set;
  input mm2s_dma_slverr_set;
  input mm2s_dma_decerr_set;
  input ftch_error;
  input \FSM_sequential_pntr_cs_reg[1]_0 ;
  input [25:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 ;
  input [30:0]D;

  wire [30:0]D;
  wire [0:0]E;
  wire \FSM_sequential_pntr_cs_reg[1]_0 ;
  wire \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_0 ;
  wire \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_1 ;
  wire [25:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 ;
  wire \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_empty_reg_0 ;
  wire [0:0]\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ;
  wire [29:0]Q;
  wire ch1_dma_decerr;
  wire ch1_dma_interr;
  wire ch1_dma_slverr;
  wire ch1_updt_active;
  wire ch1_updt_ioc;
  wire dma_decerr_i_1_n_0;
  wire dma_interr_i_1_n_0;
  wire dma_slverr_i_1_n_0;
  wire follower_full_mm2s;
  wire follower_full_mm2s0;
  wire ftch_error;
  wire m_axi_sg_aclk;
  wire mm2s_dma_decerr_set;
  wire mm2s_dma_interr_set;
  wire mm2s_dma_slverr_set;
  wire out;
  wire p_0_in;
  wire [1:0]pntr_cs;
  wire [1:0]pntr_ns;
  wire [31:6]ptr_queue_dout;
  wire ptr_queue_empty0;
  wire ptr_queue_full;
  wire sinit;
  wire [32:0]sts_queue_dout;
  wire sts_queue_empty;
  wire sts_queue_empty0;
  wire sts_queue_full;
  wire sts_rden;
  wire updt_active_d1;
  wire updt_curdesc0;
  wire [25:0]\updt_curdesc_reg[31]_0 ;
  wire [0:0]updt_curdesc_wren_reg_0;
  wire updt_ioc_i_1_n_0;
  wire updt_ioc_reg_0;
  wire writing_status;
  wire writing_status_d1;
  wire writing_status_re_ch1;

  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'h0000B0BC)) 
    \FSM_sequential_pntr_cs[0]_i_1 
       (.I0(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_empty_reg_0 ),
        .I1(ch1_updt_active),
        .I2(pntr_cs[0]),
        .I3(updt_active_d1),
        .I4(pntr_cs[1]),
        .O(pntr_ns[0]));
  LUT6 #(
    .INIT(64'h000044443FFF0000)) 
    \FSM_sequential_pntr_cs[1]_i_1 
       (.I0(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_empty_reg_0 ),
        .I1(ch1_updt_active),
        .I2(Q[29]),
        .I3(\FSM_sequential_pntr_cs_reg[1]_0 ),
        .I4(pntr_cs[1]),
        .I5(pntr_cs[0]),
        .O(pntr_ns[1]));
  (* FSM_ENCODED_STATES = "read_curdesc_lsb:01,write_status:10,idle:00" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_pntr_cs_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(pntr_ns[0]),
        .Q(pntr_cs[0]),
        .R(sinit));
  (* FSM_ENCODED_STATES = "read_curdesc_lsb:01,write_status:10,idle:00" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_pntr_cs_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(pntr_ns[1]),
        .Q(pntr_cs[1]),
        .R(sinit));
  LUT3 #(
    .INIT(8'hFE)) 
    \GEN_CH1_UPDATE.ch1_updt_idle_i_2 
       (.I0(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_0 ),
        .I1(ftch_error),
        .I2(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_empty_reg_0 ),
        .O(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_1 ));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(1'b0),
        .Q(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_0 ),
        .S(follower_full_mm2s0));
  LUT2 #(
    .INIT(4'h2)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_full_mm2s_i_2 
       (.I0(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_0 ),
        .I1(sts_queue_empty),
        .O(sts_rden));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_full_mm2s_reg 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(1'b1),
        .Q(follower_full_mm2s),
        .R(follower_full_mm2s0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[0]),
        .Q(Q[0]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[10]),
        .Q(Q[10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[11]),
        .Q(Q[11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[12]),
        .Q(Q[12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[13]),
        .Q(Q[13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[14]),
        .Q(Q[14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[15]),
        .Q(Q[15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[16]),
        .Q(Q[16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[17]),
        .Q(Q[17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[18]),
        .Q(Q[18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[19]),
        .Q(Q[19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[1]),
        .Q(Q[1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[20]),
        .Q(Q[20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[21]),
        .Q(Q[21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[22]),
        .Q(Q[22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[23]),
        .Q(Q[23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[24]),
        .Q(Q[24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[25]),
        .Q(Q[25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[28]),
        .Q(Q[26]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[29]),
        .Q(Q[27]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[2]),
        .Q(Q[2]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[30]),
        .Q(Q[28]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[31]),
        .Q(Q[29]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[32] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[32]),
        .Q(p_0_in),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[3]),
        .Q(Q[3]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[4]),
        .Q(Q[4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[5]),
        .Q(Q[5]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[6]),
        .Q(Q[6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[7]),
        .Q(Q[7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[8]),
        .Q(Q[8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_reg_mm2s_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(sts_rden),
        .D(sts_queue_dout[9]),
        .Q(Q[9]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [4]),
        .Q(ptr_queue_dout[10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [5]),
        .Q(ptr_queue_dout[11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [6]),
        .Q(ptr_queue_dout[12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [7]),
        .Q(ptr_queue_dout[13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [8]),
        .Q(ptr_queue_dout[14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [9]),
        .Q(ptr_queue_dout[15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [10]),
        .Q(ptr_queue_dout[16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [11]),
        .Q(ptr_queue_dout[17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [12]),
        .Q(ptr_queue_dout[18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [13]),
        .Q(ptr_queue_dout[19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [14]),
        .Q(ptr_queue_dout[20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [15]),
        .Q(ptr_queue_dout[21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [16]),
        .Q(ptr_queue_dout[22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [17]),
        .Q(ptr_queue_dout[23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [18]),
        .Q(ptr_queue_dout[24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [19]),
        .Q(ptr_queue_dout[25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [20]),
        .Q(ptr_queue_dout[26]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [21]),
        .Q(ptr_queue_dout[27]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [22]),
        .Q(ptr_queue_dout[28]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [23]),
        .Q(ptr_queue_dout[29]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [24]),
        .Q(ptr_queue_dout[30]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [25]),
        .Q(ptr_queue_dout[31]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [0]),
        .Q(ptr_queue_dout[6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [1]),
        .Q(ptr_queue_dout[7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [2]),
        .Q(ptr_queue_dout[8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_dout_reg[31]_0 [3]),
        .Q(ptr_queue_dout[9]),
        .R(sinit));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_empty_reg 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(1'b0),
        .Q(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_empty_reg_0 ),
        .S(ptr_queue_empty0));
  LUT5 #(
    .INIT(32'h0020FFFF)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_full_i_1 
       (.I0(ch1_updt_active),
        .I1(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_empty_reg_0 ),
        .I2(pntr_cs[0]),
        .I3(pntr_cs[1]),
        .I4(out),
        .O(ptr_queue_empty0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_full_reg 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(1'b1),
        .Q(ptr_queue_full),
        .R(ptr_queue_empty0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[0]),
        .Q(sts_queue_dout[0]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[10]),
        .Q(sts_queue_dout[10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[11]),
        .Q(sts_queue_dout[11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[12]),
        .Q(sts_queue_dout[12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[13]),
        .Q(sts_queue_dout[13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[14]),
        .Q(sts_queue_dout[14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[15]),
        .Q(sts_queue_dout[15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[16]),
        .Q(sts_queue_dout[16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[17]),
        .Q(sts_queue_dout[17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[18]),
        .Q(sts_queue_dout[18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[19]),
        .Q(sts_queue_dout[19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[1]),
        .Q(sts_queue_dout[1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[20]),
        .Q(sts_queue_dout[20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[21]),
        .Q(sts_queue_dout[21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[22]),
        .Q(sts_queue_dout[22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[23]),
        .Q(sts_queue_dout[23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[24]),
        .Q(sts_queue_dout[24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[25]),
        .Q(sts_queue_dout[25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[26]),
        .Q(sts_queue_dout[28]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[27]),
        .Q(sts_queue_dout[29]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[2]),
        .Q(sts_queue_dout[2]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[28]),
        .Q(sts_queue_dout[30]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[29]),
        .Q(sts_queue_dout[31]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[30]),
        .Q(sts_queue_dout[32]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[3]),
        .Q(sts_queue_dout[3]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[4]),
        .Q(sts_queue_dout[4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[5]),
        .Q(sts_queue_dout[5]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[6]),
        .Q(sts_queue_dout[6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[7]),
        .Q(sts_queue_dout[7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[8]),
        .Q(sts_queue_dout[8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(D[9]),
        .Q(sts_queue_dout[9]),
        .R(sinit));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_empty_reg 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(1'b0),
        .Q(sts_queue_empty),
        .S(sts_queue_empty0));
  LUT3 #(
    .INIT(8'h4F)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_full_i_1 
       (.I0(sts_queue_empty),
        .I1(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg_0 ),
        .I2(out),
        .O(sts_queue_empty0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_full_reg 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.sts_queue_dout_reg[32]_0 ),
        .D(1'b1),
        .Q(sts_queue_full),
        .R(sts_queue_empty0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.updt_active_d1_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ch1_updt_active),
        .Q(updt_active_d1),
        .R(sinit));
  LUT5 #(
    .INIT(32'h44400040)) 
    dma_decerr_i_1
       (.I0(mm2s_dma_decerr_set),
        .I1(out),
        .I2(ch1_dma_decerr),
        .I3(writing_status_re_ch1),
        .I4(Q[28]),
        .O(dma_decerr_i_1_n_0));
  FDRE dma_decerr_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(dma_decerr_i_1_n_0),
        .Q(ch1_dma_decerr),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h44400040)) 
    dma_interr_i_1
       (.I0(mm2s_dma_interr_set),
        .I1(out),
        .I2(ch1_dma_interr),
        .I3(writing_status_re_ch1),
        .I4(Q[26]),
        .O(dma_interr_i_1_n_0));
  FDRE dma_interr_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(dma_interr_i_1_n_0),
        .Q(ch1_dma_interr),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h44400040)) 
    dma_slverr_i_1
       (.I0(mm2s_dma_slverr_set),
        .I1(out),
        .I2(ch1_dma_slverr),
        .I3(writing_status_re_ch1),
        .I4(Q[27]),
        .O(dma_slverr_i_1_n_0));
  FDRE dma_slverr_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(dma_slverr_i_1_n_0),
        .Q(ch1_dma_slverr),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0400)) 
    \updt_curdesc[31]_i_1 
       (.I0(pntr_cs[1]),
        .I1(pntr_cs[0]),
        .I2(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.ptr_queue_empty_reg_0 ),
        .I3(ch1_updt_active),
        .O(updt_curdesc0));
  FDRE \updt_curdesc_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[10]),
        .Q(\updt_curdesc_reg[31]_0 [4]),
        .R(sinit));
  FDRE \updt_curdesc_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[11]),
        .Q(\updt_curdesc_reg[31]_0 [5]),
        .R(sinit));
  FDRE \updt_curdesc_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[12]),
        .Q(\updt_curdesc_reg[31]_0 [6]),
        .R(sinit));
  FDRE \updt_curdesc_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[13]),
        .Q(\updt_curdesc_reg[31]_0 [7]),
        .R(sinit));
  FDRE \updt_curdesc_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[14]),
        .Q(\updt_curdesc_reg[31]_0 [8]),
        .R(sinit));
  FDRE \updt_curdesc_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[15]),
        .Q(\updt_curdesc_reg[31]_0 [9]),
        .R(sinit));
  FDRE \updt_curdesc_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[16]),
        .Q(\updt_curdesc_reg[31]_0 [10]),
        .R(sinit));
  FDRE \updt_curdesc_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[17]),
        .Q(\updt_curdesc_reg[31]_0 [11]),
        .R(sinit));
  FDRE \updt_curdesc_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[18]),
        .Q(\updt_curdesc_reg[31]_0 [12]),
        .R(sinit));
  FDRE \updt_curdesc_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[19]),
        .Q(\updt_curdesc_reg[31]_0 [13]),
        .R(sinit));
  FDRE \updt_curdesc_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[20]),
        .Q(\updt_curdesc_reg[31]_0 [14]),
        .R(sinit));
  FDRE \updt_curdesc_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[21]),
        .Q(\updt_curdesc_reg[31]_0 [15]),
        .R(sinit));
  FDRE \updt_curdesc_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[22]),
        .Q(\updt_curdesc_reg[31]_0 [16]),
        .R(sinit));
  FDRE \updt_curdesc_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[23]),
        .Q(\updt_curdesc_reg[31]_0 [17]),
        .R(sinit));
  FDRE \updt_curdesc_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[24]),
        .Q(\updt_curdesc_reg[31]_0 [18]),
        .R(sinit));
  FDRE \updt_curdesc_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[25]),
        .Q(\updt_curdesc_reg[31]_0 [19]),
        .R(sinit));
  FDRE \updt_curdesc_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[26]),
        .Q(\updt_curdesc_reg[31]_0 [20]),
        .R(sinit));
  FDRE \updt_curdesc_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[27]),
        .Q(\updt_curdesc_reg[31]_0 [21]),
        .R(sinit));
  FDRE \updt_curdesc_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[28]),
        .Q(\updt_curdesc_reg[31]_0 [22]),
        .R(sinit));
  FDRE \updt_curdesc_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[29]),
        .Q(\updt_curdesc_reg[31]_0 [23]),
        .R(sinit));
  FDRE \updt_curdesc_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[30]),
        .Q(\updt_curdesc_reg[31]_0 [24]),
        .R(sinit));
  FDRE \updt_curdesc_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[31]),
        .Q(\updt_curdesc_reg[31]_0 [25]),
        .R(sinit));
  FDRE \updt_curdesc_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[6]),
        .Q(\updt_curdesc_reg[31]_0 [0]),
        .R(sinit));
  FDRE \updt_curdesc_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[7]),
        .Q(\updt_curdesc_reg[31]_0 [1]),
        .R(sinit));
  FDRE \updt_curdesc_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[8]),
        .Q(\updt_curdesc_reg[31]_0 [2]),
        .R(sinit));
  FDRE \updt_curdesc_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(updt_curdesc0),
        .D(ptr_queue_dout[9]),
        .Q(\updt_curdesc_reg[31]_0 [3]),
        .R(sinit));
  FDRE updt_curdesc_wren_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_curdesc0),
        .Q(updt_curdesc_wren_reg_0),
        .R(sinit));
  LUT5 #(
    .INIT(32'h44400040)) 
    updt_ioc_i_1
       (.I0(updt_ioc_reg_0),
        .I1(out),
        .I2(ch1_updt_ioc),
        .I3(writing_status_re_ch1),
        .I4(p_0_in),
        .O(updt_ioc_i_1_n_0));
  LUT4 #(
    .INIT(16'h0400)) 
    updt_ioc_i_2
       (.I0(writing_status_d1),
        .I1(ch1_updt_active),
        .I2(pntr_cs[0]),
        .I3(pntr_cs[1]),
        .O(writing_status_re_ch1));
  FDRE updt_ioc_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_ioc_i_1_n_0),
        .Q(ch1_updt_ioc),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT2 #(
    .INIT(4'h2)) 
    writing_status_d1_i_1
       (.I0(pntr_cs[1]),
        .I1(pntr_cs[0]),
        .O(writing_status));
  FDRE #(
    .INIT(1'b0)) 
    writing_status_d1_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(writing_status),
        .Q(writing_status_d1),
        .R(sinit));
endmodule

module Loopback_axi_dma_1_0_axi_sg_updt_sm
   (\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_0 ,
    \GEN_CH1_UPDATE.ch1_active_i_reg_0 ,
    mm2s_updt_idle,
    \GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_1 ,
    \GEN_CH1_UPDATE.ch1_dma_interr_set_reg_0 ,
    \GEN_CH1_UPDATE.ch1_dma_interr_set_reg_1 ,
    \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_0 ,
    \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_0 ,
    \GEN_CH1_UPDATE.ch1_updt_slverr_set_reg_0 ,
    \GEN_CH1_UPDATE.ch1_updt_interr_set_reg_0 ,
    \GEN_CH1_UPDATE.ch1_updt_decerr_set_reg_0 ,
    D,
    m_axi_sg_wdata,
    \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ,
    \GEN_CH1_UPDATE.ch1_dma_interr_set_reg_2 ,
    \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_1 ,
    \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_1 ,
    \updt_error_addr_reg[31]_0 ,
    sinit,
    ch1_updt_ioc_irq_set0,
    m_axi_sg_aclk,
    \FSM_sequential_updt_cs_reg[2]_0 ,
    ftch_error,
    out,
    \GEN_CH1_UPDATE.ch1_updt_idle_reg_0 ,
    E,
    updt_done,
    ptr_queue_empty,
    follower_empty_mm2s,
    mm2s_irqthresh_wren,
    \GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ,
    mm2s_dly_irq_set,
    \ftch_error_addr_reg[8] ,
    Q,
    s_axis_updt_cmd_tready,
    s_axis_updt_cmd_tvalid,
    dma_interr_reg,
    dma_slverr_reg,
    dma_decerr_reg,
    \update_address_reg[31]_0 ,
    updt_interr,
    updt_slverr,
    updt_decerr,
    ch1_dma_interr,
    ch1_dma_slverr,
    ch1_dma_decerr);
  output \GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_0 ;
  output \GEN_CH1_UPDATE.ch1_active_i_reg_0 ;
  output mm2s_updt_idle;
  output [0:0]\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_1 ;
  output [0:0]\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_0 ;
  output \GEN_CH1_UPDATE.ch1_dma_interr_set_reg_1 ;
  output \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_0 ;
  output \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_0 ;
  output \GEN_CH1_UPDATE.ch1_updt_slverr_set_reg_0 ;
  output \GEN_CH1_UPDATE.ch1_updt_interr_set_reg_0 ;
  output \GEN_CH1_UPDATE.ch1_updt_decerr_set_reg_0 ;
  output [27:0]D;
  output [29:0]m_axi_sg_wdata;
  output \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ;
  output \GEN_CH1_UPDATE.ch1_dma_interr_set_reg_2 ;
  output \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_1 ;
  output \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_1 ;
  output [25:0]\updt_error_addr_reg[31]_0 ;
  input sinit;
  input ch1_updt_ioc_irq_set0;
  input m_axi_sg_aclk;
  input \FSM_sequential_updt_cs_reg[2]_0 ;
  input ftch_error;
  input out;
  input \GEN_CH1_UPDATE.ch1_updt_idle_reg_0 ;
  input [0:0]E;
  input updt_done;
  input ptr_queue_empty;
  input follower_empty_mm2s;
  input mm2s_irqthresh_wren;
  input [0:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ;
  input mm2s_dly_irq_set;
  input \ftch_error_addr_reg[8] ;
  input [29:0]Q;
  input s_axis_updt_cmd_tready;
  input s_axis_updt_cmd_tvalid;
  input dma_interr_reg;
  input dma_slverr_reg;
  input dma_decerr_reg;
  input [25:0]\update_address_reg[31]_0 ;
  input updt_interr;
  input updt_slverr;
  input updt_decerr;
  input ch1_dma_interr;
  input ch1_dma_slverr;
  input ch1_dma_decerr;

  wire [27:0]D;
  wire [0:0]E;
  wire \FSM_sequential_updt_cs[0]_i_2_n_0 ;
  wire \FSM_sequential_updt_cs[0]_i_3_n_0 ;
  wire \FSM_sequential_updt_cs_reg[2]_0 ;
  wire \GEN_CH1_UPDATE.ch1_active_i_i_1_n_0 ;
  wire \GEN_CH1_UPDATE.ch1_active_i_reg_0 ;
  wire \GEN_CH1_UPDATE.ch1_dma_decerr_set_i_1_n_0 ;
  wire \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_0 ;
  wire \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_1 ;
  wire \GEN_CH1_UPDATE.ch1_dma_interr_set_i_1_n_0 ;
  wire [0:0]\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_0 ;
  wire \GEN_CH1_UPDATE.ch1_dma_interr_set_reg_1 ;
  wire \GEN_CH1_UPDATE.ch1_dma_interr_set_reg_2 ;
  wire \GEN_CH1_UPDATE.ch1_dma_slverr_set_i_1_n_0 ;
  wire \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_0 ;
  wire \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_1 ;
  wire \GEN_CH1_UPDATE.ch1_updt_decerr_set_i_1_n_0 ;
  wire \GEN_CH1_UPDATE.ch1_updt_decerr_set_reg_0 ;
  wire \GEN_CH1_UPDATE.ch1_updt_idle_i_1_n_0 ;
  wire \GEN_CH1_UPDATE.ch1_updt_idle_i_3_n_0 ;
  wire \GEN_CH1_UPDATE.ch1_updt_idle_reg_0 ;
  wire \GEN_CH1_UPDATE.ch1_updt_interr_set_i_1_n_0 ;
  wire \GEN_CH1_UPDATE.ch1_updt_interr_set_reg_0 ;
  wire \GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_0 ;
  wire [0:0]\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_1 ;
  wire \GEN_CH1_UPDATE.ch1_updt_slverr_set_i_1_n_0 ;
  wire \GEN_CH1_UPDATE.ch1_updt_slverr_set_reg_0 ;
  wire [0:0]\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ;
  wire [29:0]Q;
  wire \USE_SINGLE_REG.sig_regfifo_empty_reg_reg ;
  wire ch1_dma_decerr;
  wire ch1_dma_interr;
  wire ch1_dma_slverr;
  wire ch1_updt_ioc_irq_set0;
  wire dma_decerr_reg;
  wire dma_interr_reg;
  wire dma_slverr_reg;
  wire follower_empty_mm2s;
  wire ftch_error;
  wire \ftch_error_addr[31]_i_3_n_0 ;
  wire \ftch_error_addr_reg[8] ;
  wire m_axi_sg_aclk;
  wire [29:0]m_axi_sg_wdata;
  wire mm2s_dly_irq_set;
  wire mm2s_irqthresh_wren;
  wire mm2s_updt_idle;
  wire out;
  wire ptr_queue_empty;
  wire s_axis_updt_cmd_tready;
  wire s_axis_updt_cmd_tvalid;
  wire sinit;
  wire [25:0]\update_address_reg[31]_0 ;
  wire updt_cmnd_wr;
  wire [2:0]updt_cs;
  wire updt_decerr;
  wire updt_done;
  wire [25:0]\updt_error_addr_reg[31]_0 ;
  wire updt_interr;
  wire [2:0]updt_ns;
  wire updt_slverr;

  LUT6 #(
    .INIT(64'hAAAAAAAAABAAFFFF)) 
    \FSM_sequential_updt_cs[0]_i_1 
       (.I0(\FSM_sequential_updt_cs[0]_i_2_n_0 ),
        .I1(E),
        .I2(updt_cs[1]),
        .I3(updt_cs[0]),
        .I4(\FSM_sequential_updt_cs[0]_i_3_n_0 ),
        .I5(updt_cs[2]),
        .O(updt_ns[0]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h00000070)) 
    \FSM_sequential_updt_cs[0]_i_2 
       (.I0(updt_done),
        .I1(updt_cs[0]),
        .I2(updt_cs[1]),
        .I3(\FSM_sequential_updt_cs_reg[2]_0 ),
        .I4(updt_cs[2]),
        .O(\FSM_sequential_updt_cs[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_sequential_updt_cs[0]_i_3 
       (.I0(updt_cs[0]),
        .I1(updt_cs[1]),
        .I2(\FSM_sequential_updt_cs_reg[2]_0 ),
        .I3(ptr_queue_empty),
        .I4(ftch_error),
        .I5(follower_empty_mm2s),
        .O(\FSM_sequential_updt_cs[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0022030003220300)) 
    \FSM_sequential_updt_cs[1]_i_1 
       (.I0(E),
        .I1(updt_cs[2]),
        .I2(\FSM_sequential_updt_cs_reg[2]_0 ),
        .I3(updt_cs[1]),
        .I4(updt_cs[0]),
        .I5(updt_done),
        .O(updt_ns[1]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'hFFD0)) 
    \FSM_sequential_updt_cs[2]_i_1 
       (.I0(updt_cs[0]),
        .I1(updt_cs[1]),
        .I2(\FSM_sequential_updt_cs_reg[2]_0 ),
        .I3(updt_cs[2]),
        .O(updt_ns[2]));
  (* FSM_ENCODED_STATES = "get_update_pntr:001,update_descriptor:010,update_error:100,update_status:011,idle:000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_updt_cs_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_ns[0]),
        .Q(updt_cs[0]),
        .R(sinit));
  (* FSM_ENCODED_STATES = "get_update_pntr:001,update_descriptor:010,update_error:100,update_status:011,idle:000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_updt_cs_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_ns[1]),
        .Q(updt_cs[1]),
        .R(sinit));
  (* FSM_ENCODED_STATES = "get_update_pntr:001,update_descriptor:010,update_error:100,update_status:011,idle:000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_updt_cs_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(updt_ns[2]),
        .Q(updt_cs[2]),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h00AA0202)) 
    \GEN_CH1_UPDATE.ch1_active_i_i_1 
       (.I0(out),
        .I1(updt_cs[2]),
        .I2(\FSM_sequential_updt_cs[0]_i_3_n_0 ),
        .I3(updt_done),
        .I4(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .O(\GEN_CH1_UPDATE.ch1_active_i_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_CH1_UPDATE.ch1_active_i_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_UPDATE.ch1_active_i_i_1_n_0 ),
        .Q(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \GEN_CH1_UPDATE.ch1_dma_decerr_set_i_1 
       (.I0(ch1_dma_decerr),
        .I1(updt_done),
        .I2(\GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_0 ),
        .O(\GEN_CH1_UPDATE.ch1_dma_decerr_set_i_1_n_0 ));
  FDRE \GEN_CH1_UPDATE.ch1_dma_decerr_set_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_UPDATE.ch1_dma_decerr_set_i_1_n_0 ),
        .Q(\GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_0 ),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \GEN_CH1_UPDATE.ch1_dma_interr_set_i_1 
       (.I0(ch1_dma_interr),
        .I1(updt_done),
        .I2(\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_1 ),
        .O(\GEN_CH1_UPDATE.ch1_dma_interr_set_i_1_n_0 ));
  FDRE \GEN_CH1_UPDATE.ch1_dma_interr_set_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_UPDATE.ch1_dma_interr_set_i_1_n_0 ),
        .Q(\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_1 ),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \GEN_CH1_UPDATE.ch1_dma_slverr_set_i_1 
       (.I0(ch1_dma_slverr),
        .I1(updt_done),
        .I2(\GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_0 ),
        .O(\GEN_CH1_UPDATE.ch1_dma_slverr_set_i_1_n_0 ));
  FDRE \GEN_CH1_UPDATE.ch1_dma_slverr_set_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_UPDATE.ch1_dma_slverr_set_i_1_n_0 ),
        .Q(\GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_0 ),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \GEN_CH1_UPDATE.ch1_updt_decerr_set_i_1 
       (.I0(updt_decerr),
        .I1(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I2(\GEN_CH1_UPDATE.ch1_updt_decerr_set_reg_0 ),
        .O(\GEN_CH1_UPDATE.ch1_updt_decerr_set_i_1_n_0 ));
  FDRE \GEN_CH1_UPDATE.ch1_updt_decerr_set_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_UPDATE.ch1_updt_decerr_set_i_1_n_0 ),
        .Q(\GEN_CH1_UPDATE.ch1_updt_decerr_set_reg_0 ),
        .R(sinit));
  LUT6 #(
    .INIT(64'hFFEFFFEFEFEFFFEF)) 
    \GEN_CH1_UPDATE.ch1_updt_idle_i_1 
       (.I0(\FSM_sequential_updt_cs_reg[2]_0 ),
        .I1(ftch_error),
        .I2(out),
        .I3(\GEN_CH1_UPDATE.ch1_updt_idle_reg_0 ),
        .I4(\GEN_CH1_UPDATE.ch1_updt_idle_i_3_n_0 ),
        .I5(mm2s_updt_idle),
        .O(\GEN_CH1_UPDATE.ch1_updt_idle_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFAAF4AA)) 
    \GEN_CH1_UPDATE.ch1_updt_idle_i_3 
       (.I0(updt_cs[0]),
        .I1(\FSM_sequential_updt_cs_reg[2]_0 ),
        .I2(updt_cs[2]),
        .I3(updt_cs[1]),
        .I4(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .O(\GEN_CH1_UPDATE.ch1_updt_idle_i_3_n_0 ));
  FDRE \GEN_CH1_UPDATE.ch1_updt_idle_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_UPDATE.ch1_updt_idle_i_1_n_0 ),
        .Q(mm2s_updt_idle),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \GEN_CH1_UPDATE.ch1_updt_interr_set_i_1 
       (.I0(updt_interr),
        .I1(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I2(\GEN_CH1_UPDATE.ch1_updt_interr_set_reg_0 ),
        .O(\GEN_CH1_UPDATE.ch1_updt_interr_set_i_1_n_0 ));
  FDRE \GEN_CH1_UPDATE.ch1_updt_interr_set_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_UPDATE.ch1_updt_interr_set_i_1_n_0 ),
        .Q(\GEN_CH1_UPDATE.ch1_updt_interr_set_reg_0 ),
        .R(sinit));
  FDRE \GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(ch1_updt_ioc_irq_set0),
        .Q(\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_0 ),
        .R(sinit));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \GEN_CH1_UPDATE.ch1_updt_slverr_set_i_1 
       (.I0(updt_slverr),
        .I1(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I2(\GEN_CH1_UPDATE.ch1_updt_slverr_set_reg_0 ),
        .O(\GEN_CH1_UPDATE.ch1_updt_slverr_set_i_1_n_0 ));
  FDRE \GEN_CH1_UPDATE.ch1_updt_slverr_set_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_CH1_UPDATE.ch1_updt_slverr_set_i_1_n_0 ),
        .Q(\GEN_CH1_UPDATE.ch1_updt_slverr_set_reg_0 ),
        .R(sinit));
  LUT4 #(
    .INIT(16'hFEEE)) 
    \GEN_INCLUDE_MM2S.ch1_thresh_count[7]_i_1 
       (.I0(\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_0 ),
        .I1(mm2s_irqthresh_wren),
        .I2(\GEN_INCLUDE_MM2S.ch1_thresh_count_reg[7] ),
        .I3(mm2s_dly_irq_set),
        .O(\GEN_CH1_UPDATE.ch1_updt_ioc_irq_set_reg_1 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/dma_decerr_i_1 
       (.I0(\GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_0 ),
        .I1(dma_decerr_reg),
        .O(\GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_1 ));
  LUT2 #(
    .INIT(4'hE)) 
    \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/dma_interr_i_1 
       (.I0(\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_1 ),
        .I1(dma_interr_reg),
        .O(\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_2 ));
  LUT2 #(
    .INIT(4'hE)) 
    \GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/dma_slverr_i_1 
       (.I0(\GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_0 ),
        .I1(dma_slverr_reg),
        .O(\GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \USE_SINGLE_REG.sig_regfifo_dout_reg[3]_i_1 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .O(D[0]));
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    \ftch_error_addr[31]_i_1__0 
       (.I0(\ftch_error_addr[31]_i_3_n_0 ),
        .I1(\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_1 ),
        .I2(\GEN_CH1_UPDATE.ch1_dma_slverr_set_reg_0 ),
        .I3(\ftch_error_addr_reg[8] ),
        .I4(\GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_0 ),
        .O(\GEN_CH1_UPDATE.ch1_dma_interr_set_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \ftch_error_addr[31]_i_3 
       (.I0(\GEN_CH1_UPDATE.ch1_updt_slverr_set_reg_0 ),
        .I1(\GEN_CH1_UPDATE.ch1_updt_interr_set_reg_0 ),
        .I2(\GEN_CH1_UPDATE.ch1_updt_decerr_set_reg_0 ),
        .O(\ftch_error_addr[31]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[0]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[0]),
        .O(m_axi_sg_wdata[0]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[10]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[10]),
        .O(m_axi_sg_wdata[10]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[11]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[11]),
        .O(m_axi_sg_wdata[11]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[12]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[12]),
        .O(m_axi_sg_wdata[12]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[13]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[13]),
        .O(m_axi_sg_wdata[13]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[14]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[14]),
        .O(m_axi_sg_wdata[14]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[15]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[15]),
        .O(m_axi_sg_wdata[15]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[16]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[16]),
        .O(m_axi_sg_wdata[16]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[17]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[17]),
        .O(m_axi_sg_wdata[17]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[18]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[18]),
        .O(m_axi_sg_wdata[18]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[19]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[19]),
        .O(m_axi_sg_wdata[19]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[1]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[1]),
        .O(m_axi_sg_wdata[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[20]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[20]),
        .O(m_axi_sg_wdata[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[21]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[21]),
        .O(m_axi_sg_wdata[21]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[22]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[22]),
        .O(m_axi_sg_wdata[22]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[23]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[23]),
        .O(m_axi_sg_wdata[23]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[24]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[24]),
        .O(m_axi_sg_wdata[24]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[25]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[25]),
        .O(m_axi_sg_wdata[25]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[28]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[26]),
        .O(m_axi_sg_wdata[26]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[29]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[27]),
        .O(m_axi_sg_wdata[27]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[2]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[2]),
        .O(m_axi_sg_wdata[2]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[30]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[28]),
        .O(m_axi_sg_wdata[28]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[31]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[29]),
        .O(m_axi_sg_wdata[29]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[3]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[3]),
        .O(m_axi_sg_wdata[3]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[4]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[4]),
        .O(m_axi_sg_wdata[4]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[5]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[5]),
        .O(m_axi_sg_wdata[5]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[6]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[6]),
        .O(m_axi_sg_wdata[6]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[7]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[7]),
        .O(m_axi_sg_wdata[7]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[8]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[8]),
        .O(m_axi_sg_wdata[8]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_sg_wdata[9]_INST_0 
       (.I0(\GEN_CH1_UPDATE.ch1_active_i_reg_0 ),
        .I1(Q[9]),
        .O(m_axi_sg_wdata[9]));
  LUT6 #(
    .INIT(64'h5555575500000300)) 
    s_axis_updt_cmd_tvalid_i_1
       (.I0(s_axis_updt_cmd_tready),
        .I1(updt_cs[2]),
        .I2(\FSM_sequential_updt_cs_reg[2]_0 ),
        .I3(updt_cs[1]),
        .I4(updt_cs[0]),
        .I5(s_axis_updt_cmd_tvalid),
        .O(\USE_SINGLE_REG.sig_regfifo_empty_reg_reg ));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [4]),
        .Q(D[6]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [5]),
        .Q(D[7]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [6]),
        .Q(D[8]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [7]),
        .Q(D[9]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [8]),
        .Q(D[10]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [9]),
        .Q(D[11]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [10]),
        .Q(D[12]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [11]),
        .Q(D[13]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [12]),
        .Q(D[14]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [13]),
        .Q(D[15]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [14]),
        .Q(D[16]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [15]),
        .Q(D[17]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [16]),
        .Q(D[18]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [17]),
        .Q(D[19]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [18]),
        .Q(D[20]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [19]),
        .Q(D[21]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [20]),
        .Q(D[22]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [21]),
        .Q(D[23]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [22]),
        .Q(D[24]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [23]),
        .Q(D[25]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [24]),
        .Q(D[26]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [25]),
        .Q(D[27]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(1'b1),
        .Q(D[1]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [0]),
        .Q(D[2]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [1]),
        .Q(D[3]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [2]),
        .Q(D[4]),
        .R(sinit));
  FDRE #(
    .INIT(1'b0)) 
    \update_address_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(E),
        .D(\update_address_reg[31]_0 [3]),
        .Q(D[5]),
        .R(sinit));
  LUT4 #(
    .INIT(16'h0004)) 
    \updt_error_addr[31]_i_1 
       (.I0(updt_cs[0]),
        .I1(updt_cs[1]),
        .I2(\FSM_sequential_updt_cs_reg[2]_0 ),
        .I3(updt_cs[2]),
        .O(updt_cmnd_wr));
  FDRE \updt_error_addr_reg[10] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[6]),
        .Q(\updt_error_addr_reg[31]_0 [4]),
        .R(sinit));
  FDRE \updt_error_addr_reg[11] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[7]),
        .Q(\updt_error_addr_reg[31]_0 [5]),
        .R(sinit));
  FDRE \updt_error_addr_reg[12] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[8]),
        .Q(\updt_error_addr_reg[31]_0 [6]),
        .R(sinit));
  FDRE \updt_error_addr_reg[13] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[9]),
        .Q(\updt_error_addr_reg[31]_0 [7]),
        .R(sinit));
  FDRE \updt_error_addr_reg[14] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[10]),
        .Q(\updt_error_addr_reg[31]_0 [8]),
        .R(sinit));
  FDRE \updt_error_addr_reg[15] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[11]),
        .Q(\updt_error_addr_reg[31]_0 [9]),
        .R(sinit));
  FDRE \updt_error_addr_reg[16] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[12]),
        .Q(\updt_error_addr_reg[31]_0 [10]),
        .R(sinit));
  FDRE \updt_error_addr_reg[17] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[13]),
        .Q(\updt_error_addr_reg[31]_0 [11]),
        .R(sinit));
  FDRE \updt_error_addr_reg[18] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[14]),
        .Q(\updt_error_addr_reg[31]_0 [12]),
        .R(sinit));
  FDRE \updt_error_addr_reg[19] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[15]),
        .Q(\updt_error_addr_reg[31]_0 [13]),
        .R(sinit));
  FDRE \updt_error_addr_reg[20] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[16]),
        .Q(\updt_error_addr_reg[31]_0 [14]),
        .R(sinit));
  FDRE \updt_error_addr_reg[21] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[17]),
        .Q(\updt_error_addr_reg[31]_0 [15]),
        .R(sinit));
  FDRE \updt_error_addr_reg[22] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[18]),
        .Q(\updt_error_addr_reg[31]_0 [16]),
        .R(sinit));
  FDRE \updt_error_addr_reg[23] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[19]),
        .Q(\updt_error_addr_reg[31]_0 [17]),
        .R(sinit));
  FDRE \updt_error_addr_reg[24] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[20]),
        .Q(\updt_error_addr_reg[31]_0 [18]),
        .R(sinit));
  FDRE \updt_error_addr_reg[25] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[21]),
        .Q(\updt_error_addr_reg[31]_0 [19]),
        .R(sinit));
  FDRE \updt_error_addr_reg[26] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[22]),
        .Q(\updt_error_addr_reg[31]_0 [20]),
        .R(sinit));
  FDRE \updt_error_addr_reg[27] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[23]),
        .Q(\updt_error_addr_reg[31]_0 [21]),
        .R(sinit));
  FDRE \updt_error_addr_reg[28] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[24]),
        .Q(\updt_error_addr_reg[31]_0 [22]),
        .R(sinit));
  FDRE \updt_error_addr_reg[29] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[25]),
        .Q(\updt_error_addr_reg[31]_0 [23]),
        .R(sinit));
  FDRE \updt_error_addr_reg[30] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[26]),
        .Q(\updt_error_addr_reg[31]_0 [24]),
        .R(sinit));
  FDRE \updt_error_addr_reg[31] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[27]),
        .Q(\updt_error_addr_reg[31]_0 [25]),
        .R(sinit));
  FDRE \updt_error_addr_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[2]),
        .Q(\updt_error_addr_reg[31]_0 [0]),
        .R(sinit));
  FDRE \updt_error_addr_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[3]),
        .Q(\updt_error_addr_reg[31]_0 [1]),
        .R(sinit));
  FDRE \updt_error_addr_reg[8] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[4]),
        .Q(\updt_error_addr_reg[31]_0 [2]),
        .R(sinit));
  FDRE \updt_error_addr_reg[9] 
       (.C(m_axi_sg_aclk),
        .CE(updt_cmnd_wr),
        .D(D[5]),
        .Q(\updt_error_addr_reg[31]_0 [3]),
        .R(sinit));
endmodule

module Loopback_axi_dma_1_0_axi_sg_wr_status_cntl
   (D,
    FIFO_Full_reg,
    sig_wsc2stat_status_valid,
    sig_init_done_1,
    sig_init_done_2,
    m_axi_sg_bready,
    sig_inhibit_rdy_n,
    FIFO_Full_reg_0,
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_0 ,
    m_axi_sg_aclk,
    sig_stream_rst,
    sig_init_done_reg,
    sig_init_done_reg_0,
    sig_stat2wsc_status_ready,
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_1 ,
    m_axi_sg_bvalid,
    \USE_SRL_FIFO.sig_wr_fifo ,
    sig_push_to_wsc,
    sig_tlast_err_stop,
    sig_next_calc_error_reg,
    sig_dqual_reg_empty,
    sig_mstr2data_cmd_valid,
    m_axi_sg_bresp,
    in);
  output [3:0]D;
  output FIFO_Full_reg;
  output sig_wsc2stat_status_valid;
  output sig_init_done_1;
  output sig_init_done_2;
  output m_axi_sg_bready;
  output sig_inhibit_rdy_n;
  output FIFO_Full_reg_0;
  output \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_0 ;
  input m_axi_sg_aclk;
  input sig_stream_rst;
  input sig_init_done_reg;
  input sig_init_done_reg_0;
  input sig_stat2wsc_status_ready;
  input \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_1 ;
  input m_axi_sg_bvalid;
  input \USE_SRL_FIFO.sig_wr_fifo ;
  input sig_push_to_wsc;
  input sig_tlast_err_stop;
  input sig_next_calc_error_reg;
  input sig_dqual_reg_empty;
  input sig_mstr2data_cmd_valid;
  input [1:0]m_axi_sg_bresp;
  input [2:0]in;

  wire [3:0]D;
  wire FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire \GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_12 ;
  wire \GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_13 ;
  wire \GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_14 ;
  wire \GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_5 ;
  wire \GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_7 ;
  wire \GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_8 ;
  wire \GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_9 ;
  wire \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_0 ;
  wire \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_1 ;
  wire [2:0]\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out ;
  wire \USE_SRL_FIFO.sig_rd_empty ;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire [2:0]in;
  wire m_axi_sg_aclk;
  wire m_axi_sg_bready;
  wire [1:0]m_axi_sg_bresp;
  wire m_axi_sg_bvalid;
  wire sig_coelsc_decerr_reg0;
  wire sig_coelsc_interr_reg0;
  wire sig_coelsc_reg_empty;
  wire sig_coelsc_slverr_reg0;
  wire sig_coelsc_tag_reg0;
  wire sig_dqual_reg_empty;
  wire sig_inhibit_rdy_n;
  wire sig_init_done_1;
  wire sig_init_done_2;
  wire sig_init_done_reg;
  wire sig_init_done_reg_0;
  wire sig_mstr2data_cmd_valid;
  wire sig_next_calc_error_reg;
  wire sig_push_coelsc_reg;
  wire sig_push_to_wsc;
  wire sig_stat2wsc_status_ready;
  wire sig_statcnt_gt_eq_thres;
  wire sig_stream_rst;
  wire sig_tlast_err_stop;
  wire [2:0]sig_wdc_statcnt;
  wire \sig_wdc_statcnt[0]_i_1_n_0 ;
  wire sig_wdc_status_going_full;
  wire [1:1]sig_wresp_sfifo_out;
  wire sig_wsc2stat_status_valid;

  Loopback_axi_dma_1_0_axi_sg_fifo__parameterized2 \GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO 
       (.D(D[2:0]),
        .E(\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_7 ),
        .FIFO_Full_reg(FIFO_Full_reg),
        .FIFO_Full_reg_0(FIFO_Full_reg_0),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg (\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_14 ),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg (sig_wresp_sfifo_out),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg (\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_12 ),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg (\USE_SRL_FIFO.sig_rd_empty ),
        .\INFERRED_GEN.cnt_i_reg[2] (\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_5 ),
        .Q(sig_wdc_statcnt),
        .\USE_SRL_FIFO.sig_wr_fifo (\USE_SRL_FIFO.sig_wr_fifo ),
        .in(in),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .out({\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out [2],\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out [0]}),
        .sig_coelsc_interr_reg0(sig_coelsc_interr_reg0),
        .sig_coelsc_reg_empty(sig_coelsc_reg_empty),
        .sig_data2wsc_cmd_cmplt_reg(\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_13 ),
        .sig_inhibit_rdy_n_reg_0(sig_inhibit_rdy_n),
        .sig_init_done_2(sig_init_done_2),
        .sig_init_done_reg_0(sig_init_done_reg_0),
        .sig_push_coelsc_reg(sig_push_coelsc_reg),
        .sig_push_to_wsc(sig_push_to_wsc),
        .sig_stream_rst(sig_stream_rst),
        .sig_tlast_err_stop(sig_tlast_err_stop),
        .\sig_wdc_statcnt_reg[2] ({\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_8 ,\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_9 }));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_decerr_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_coelsc_reg),
        .D(sig_coelsc_decerr_reg0),
        .Q(D[1]),
        .R(sig_coelsc_tag_reg0));
  LUT3 #(
    .INIT(8'h8F)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_i_1 
       (.I0(sig_wsc2stat_status_valid),
        .I1(sig_stat2wsc_status_ready),
        .I2(\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_1 ),
        .O(sig_coelsc_tag_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_coelsc_reg),
        .D(sig_coelsc_interr_reg0),
        .Q(D[0]),
        .R(sig_coelsc_tag_reg0));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_coelsc_reg),
        .D(\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_14 ),
        .Q(D[3]),
        .S(sig_coelsc_tag_reg0));
  FDSE #(
    .INIT(1'b0)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_coelsc_reg),
        .D(\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_13 ),
        .Q(sig_coelsc_reg_empty),
        .S(sig_coelsc_tag_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_coelsc_reg),
        .D(\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out [0]),
        .Q(sig_wsc2stat_status_valid),
        .R(sig_coelsc_tag_reg0));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(sig_push_coelsc_reg),
        .D(sig_coelsc_slverr_reg0),
        .Q(D[2]),
        .R(sig_coelsc_tag_reg0));
  Loopback_axi_dma_1_0_axi_sg_fifo__parameterized1 I_WRESP_STATUS_FIFO
       (.D(D[2:1]),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg (\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out [2]),
        .\INFERRED_GEN.cnt_i_reg[0] (\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_5 ),
        .\INFERRED_GEN.cnt_i_reg[1] (\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_12 ),
        .Q(\USE_SRL_FIFO.sig_rd_empty ),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_bready(m_axi_sg_bready),
        .m_axi_sg_bresp(m_axi_sg_bresp),
        .m_axi_sg_bvalid(m_axi_sg_bvalid),
        .out(sig_wresp_sfifo_out),
        .sig_coelsc_decerr_reg0(sig_coelsc_decerr_reg0),
        .sig_coelsc_slverr_reg0(sig_coelsc_slverr_reg0),
        .sig_init_done_1(sig_init_done_1),
        .sig_init_done_reg_0(sig_init_done_reg),
        .sig_stream_rst(sig_stream_rst));
  LUT6 #(
    .INIT(64'hFFFFFFFFF2FFFFFF)) 
    sig_dqual_reg_full_i_3
       (.I0(sig_wsc2stat_status_valid),
        .I1(sig_stat2wsc_status_ready),
        .I2(sig_next_calc_error_reg),
        .I3(sig_dqual_reg_empty),
        .I4(sig_mstr2data_cmd_valid),
        .I5(sig_wdc_status_going_full),
        .O(\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \sig_wdc_statcnt[0]_i_1 
       (.I0(sig_wdc_statcnt[0]),
        .O(\sig_wdc_statcnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_wdc_statcnt_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_7 ),
        .D(\sig_wdc_statcnt[0]_i_1_n_0 ),
        .Q(sig_wdc_statcnt[0]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sig_wdc_statcnt_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_7 ),
        .D(\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_9 ),
        .Q(sig_wdc_statcnt[1]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sig_wdc_statcnt_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_7 ),
        .D(\GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO_n_8 ),
        .Q(sig_wdc_statcnt[2]),
        .R(sig_stream_rst));
  LUT3 #(
    .INIT(8'hFE)) 
    sig_wdc_status_going_full_i_1
       (.I0(sig_wdc_statcnt[2]),
        .I1(sig_wdc_statcnt[1]),
        .I2(sig_wdc_statcnt[0]),
        .O(sig_statcnt_gt_eq_thres));
  FDRE #(
    .INIT(1'b0)) 
    sig_wdc_status_going_full_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_statcnt_gt_eq_thres),
        .Q(sig_wdc_status_going_full),
        .R(sig_stream_rst));
endmodule

module Loopback_axi_dma_1_0_axi_sg_wrdata_cntl
   (sig_next_calc_error_reg,
    sig_dqual_reg_empty,
    sig_push_to_wsc,
    in,
    \USE_SRL_FIFO.sig_wr_fifo ,
    sig_tlast_err_stop,
    follower_full_mm2s0,
    sig_data2all_tlast_error,
    \GEN_CH1_UPDATE.ch1_active_i_reg ,
    m_axi_sg_wvalid,
    m_axi_sg_wlast,
    m_axi_sg_aclk,
    sig_calc2dm_calc_err,
    sig_stream_rst,
    sig_data2wsc_calc_err_reg_0,
    sig_push_err2wsc_reg_0,
    sig_inhibit_rdy_n,
    \GEN_OMIT_INDET_BTT.sig_tlast_err_stop_reg_0 ,
    \sig_dbeat_cntr_reg[0]_0 ,
    out,
    sig_dqual_reg_empty_reg_0,
    m_axi_sg_wready,
    follower_full_mm2s,
    D,
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg ,
    Q);
  output sig_next_calc_error_reg;
  output sig_dqual_reg_empty;
  output sig_push_to_wsc;
  output [2:0]in;
  output \USE_SRL_FIFO.sig_wr_fifo ;
  output sig_tlast_err_stop;
  output follower_full_mm2s0;
  output sig_data2all_tlast_error;
  output \GEN_CH1_UPDATE.ch1_active_i_reg ;
  output m_axi_sg_wvalid;
  output m_axi_sg_wlast;
  input m_axi_sg_aclk;
  input sig_calc2dm_calc_err;
  input sig_stream_rst;
  input sig_data2wsc_calc_err_reg_0;
  input sig_push_err2wsc_reg_0;
  input sig_inhibit_rdy_n;
  input \GEN_OMIT_INDET_BTT.sig_tlast_err_stop_reg_0 ;
  input \sig_dbeat_cntr_reg[0]_0 ;
  input out;
  input sig_dqual_reg_empty_reg_0;
  input m_axi_sg_wready;
  input follower_full_mm2s;
  input [0:0]D;
  input \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg ;
  input [0:0]Q;

  wire [0:0]D;
  wire \GEN_CH1_UPDATE.ch1_active_i_reg ;
  wire \GEN_OMIT_INDET_BTT.sig_tlast_err_stop_i_1_n_0 ;
  wire \GEN_OMIT_INDET_BTT.sig_tlast_err_stop_reg_0 ;
  wire \GEN_OMIT_INDET_BTT.sig_tlast_error_reg_i_1_n_0 ;
  wire \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg ;
  wire [0:0]Q;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire follower_full_mm2s;
  wire follower_full_mm2s0;
  wire [2:0]in;
  wire m_axi_sg_aclk;
  wire m_axi_sg_wlast;
  wire m_axi_sg_wlast_INST_0_i_1_n_0;
  wire m_axi_sg_wready;
  wire m_axi_sg_wvalid;
  wire m_axi_sg_wvalid_INST_0_i_1_n_0;
  wire m_axi_sg_wvalid_INST_0_i_2_n_0;
  wire out;
  wire [2:0]sig_addr_posted_cntr;
  wire \sig_addr_posted_cntr[0]_i_1_n_0 ;
  wire \sig_addr_posted_cntr[1]_i_1_n_0 ;
  wire \sig_addr_posted_cntr[2]_i_1_n_0 ;
  wire \sig_addr_posted_cntr[2]_i_2_n_0 ;
  wire sig_calc2dm_calc_err;
  wire sig_clr_dqual_reg;
  wire sig_data2all_tlast_error;
  wire sig_data2mstr_cmd_ready;
  wire sig_data2wsc_calc_err_reg_0;
  wire sig_data2wsc_cmd_cmplt0;
  wire sig_data2wsc_last_err0;
  wire [7:0]sig_dbeat_cntr;
  wire \sig_dbeat_cntr[0]_i_1_n_0 ;
  wire \sig_dbeat_cntr[1]_i_1_n_0 ;
  wire \sig_dbeat_cntr[2]_i_1_n_0 ;
  wire \sig_dbeat_cntr[3]_i_1_n_0 ;
  wire \sig_dbeat_cntr[4]_i_1_n_0 ;
  wire \sig_dbeat_cntr[5]_i_1_n_0 ;
  wire \sig_dbeat_cntr[6]_i_1_n_0 ;
  wire \sig_dbeat_cntr[7]_i_1_n_0 ;
  wire \sig_dbeat_cntr[7]_i_2_n_0 ;
  wire \sig_dbeat_cntr[7]_i_3_n_0 ;
  wire \sig_dbeat_cntr[7]_i_4_n_0 ;
  wire \sig_dbeat_cntr_reg[0]_0 ;
  wire sig_dqual_reg_empty;
  wire sig_dqual_reg_empty_reg_0;
  wire sig_dqual_reg_full;
  wire sig_inhibit_rdy_n;
  wire sig_last_mmap_dbeat;
  wire sig_last_mmap_dbeat_reg;
  wire sig_ld_new_cmd_reg;
  wire sig_ld_new_cmd_reg_i_1_n_0;
  wire sig_next_calc_error_reg;
  wire sig_push_err2wsc;
  wire sig_push_err2wsc_i_1_n_0;
  wire sig_push_err2wsc_reg_0;
  wire sig_push_to_wsc;
  wire sig_push_to_wsc0;
  wire sig_push_to_wsc_i_2_n_0;
  wire sig_stream_rst;
  wire sig_tlast_err_stop;

  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT5 #(
    .INIT(32'h00000080)) 
    \FSM_sequential_pntr_cs[1]_i_2 
       (.I0(D),
        .I1(follower_full_mm2s),
        .I2(m_axi_sg_wready),
        .I3(sig_data2all_tlast_error),
        .I4(m_axi_sg_wvalid_INST_0_i_1_n_0),
        .O(\GEN_CH1_UPDATE.ch1_active_i_reg ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT5 #(
    .INIT(32'hFFFF4000)) 
    \GEN_OMIT_INDET_BTT.sig_tlast_err_stop_i_1 
       (.I0(\GEN_OMIT_INDET_BTT.sig_tlast_err_stop_reg_0 ),
        .I1(sig_inhibit_rdy_n),
        .I2(sig_push_to_wsc),
        .I3(sig_data2all_tlast_error),
        .I4(sig_tlast_err_stop),
        .O(\GEN_OMIT_INDET_BTT.sig_tlast_err_stop_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_OMIT_INDET_BTT.sig_tlast_err_stop_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_OMIT_INDET_BTT.sig_tlast_err_stop_i_1_n_0 ),
        .Q(sig_tlast_err_stop),
        .R(sig_stream_rst));
  LUT6 #(
    .INIT(64'hFFFFFFFF08080708)) 
    \GEN_OMIT_INDET_BTT.sig_tlast_error_reg_i_1 
       (.I0(D),
        .I1(Q),
        .I2(\sig_dbeat_cntr[7]_i_3_n_0 ),
        .I3(sig_dqual_reg_full),
        .I4(\sig_dbeat_cntr[7]_i_4_n_0 ),
        .I5(sig_data2all_tlast_error),
        .O(\GEN_OMIT_INDET_BTT.sig_tlast_error_reg_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \GEN_OMIT_INDET_BTT.sig_tlast_error_reg_reg 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GEN_OMIT_INDET_BTT.sig_tlast_error_reg_i_1_n_0 ),
        .Q(sig_data2all_tlast_error),
        .R(sig_stream_rst));
  LUT6 #(
    .INIT(64'h10000000FFFFFFFF)) 
    \GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_full_mm2s_i_1 
       (.I0(m_axi_sg_wvalid_INST_0_i_1_n_0),
        .I1(sig_data2all_tlast_error),
        .I2(m_axi_sg_wready),
        .I3(follower_full_mm2s),
        .I4(D),
        .I5(\GEN_Q_FOR_SYNC.MM2S_CHANNEL.follower_empty_mm2s_reg ),
        .O(follower_full_mm2s0));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    \INFERRED_GEN.data_reg[2][6]_srl3_i_1 
       (.I0(sig_push_to_wsc),
        .I1(sig_inhibit_rdy_n),
        .I2(\GEN_OMIT_INDET_BTT.sig_tlast_err_stop_reg_0 ),
        .I3(sig_tlast_err_stop),
        .O(\USE_SRL_FIFO.sig_wr_fifo ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    m_axi_sg_wlast_INST_0
       (.I0(sig_dqual_reg_full),
        .I1(sig_dbeat_cntr[5]),
        .I2(sig_dbeat_cntr[4]),
        .I3(m_axi_sg_wlast_INST_0_i_1_n_0),
        .I4(sig_dbeat_cntr[6]),
        .I5(sig_dbeat_cntr[7]),
        .O(m_axi_sg_wlast));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    m_axi_sg_wlast_INST_0_i_1
       (.I0(sig_dbeat_cntr[3]),
        .I1(sig_dbeat_cntr[2]),
        .I2(sig_dbeat_cntr[0]),
        .I3(sig_dbeat_cntr[1]),
        .O(m_axi_sg_wlast_INST_0_i_1_n_0));
  LUT4 #(
    .INIT(16'h00F8)) 
    m_axi_sg_wvalid_INST_0
       (.I0(D),
        .I1(follower_full_mm2s),
        .I2(sig_data2all_tlast_error),
        .I3(m_axi_sg_wvalid_INST_0_i_1_n_0),
        .O(m_axi_sg_wvalid));
  LUT6 #(
    .INIT(64'hFFFFFFFF01110101)) 
    m_axi_sg_wvalid_INST_0_i_1
       (.I0(sig_addr_posted_cntr[2]),
        .I1(sig_addr_posted_cntr[1]),
        .I2(sig_addr_posted_cntr[0]),
        .I3(out),
        .I4(sig_last_mmap_dbeat_reg),
        .I5(m_axi_sg_wvalid_INST_0_i_2_n_0),
        .O(m_axi_sg_wvalid_INST_0_i_1_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    m_axi_sg_wvalid_INST_0_i_2
       (.I0(sig_next_calc_error_reg),
        .I1(sig_dqual_reg_full),
        .O(m_axi_sg_wvalid_INST_0_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \sig_addr_posted_cntr[0]_i_1 
       (.I0(sig_addr_posted_cntr[0]),
        .O(\sig_addr_posted_cntr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT5 #(
    .INIT(32'hCCBC33C3)) 
    \sig_addr_posted_cntr[1]_i_1 
       (.I0(sig_addr_posted_cntr[2]),
        .I1(sig_addr_posted_cntr[1]),
        .I2(out),
        .I3(sig_last_mmap_dbeat_reg),
        .I4(sig_addr_posted_cntr[0]),
        .O(\sig_addr_posted_cntr[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h26666664)) 
    \sig_addr_posted_cntr[2]_i_1 
       (.I0(sig_last_mmap_dbeat_reg),
        .I1(out),
        .I2(sig_addr_posted_cntr[1]),
        .I3(sig_addr_posted_cntr[0]),
        .I4(sig_addr_posted_cntr[2]),
        .O(\sig_addr_posted_cntr[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT5 #(
    .INIT(32'hEEFE1181)) 
    \sig_addr_posted_cntr[2]_i_2 
       (.I0(sig_addr_posted_cntr[1]),
        .I1(sig_addr_posted_cntr[0]),
        .I2(out),
        .I3(sig_last_mmap_dbeat_reg),
        .I4(sig_addr_posted_cntr[2]),
        .O(\sig_addr_posted_cntr[2]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_posted_cntr_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(\sig_addr_posted_cntr[2]_i_1_n_0 ),
        .D(\sig_addr_posted_cntr[0]_i_1_n_0 ),
        .Q(sig_addr_posted_cntr[0]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_posted_cntr_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(\sig_addr_posted_cntr[2]_i_1_n_0 ),
        .D(\sig_addr_posted_cntr[1]_i_1_n_0 ),
        .Q(sig_addr_posted_cntr[1]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sig_addr_posted_cntr_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(\sig_addr_posted_cntr[2]_i_1_n_0 ),
        .D(\sig_addr_posted_cntr[2]_i_2_n_0 ),
        .Q(sig_addr_posted_cntr[2]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    sig_data2wsc_calc_err_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_to_wsc_i_2_n_0),
        .D(sig_next_calc_error_reg),
        .Q(in[2]),
        .R(sig_push_to_wsc0));
  LUT5 #(
    .INIT(32'hFFFFFF40)) 
    sig_data2wsc_cmd_cmplt_i_1
       (.I0(\sig_dbeat_cntr[7]_i_3_n_0 ),
        .I1(Q),
        .I2(D),
        .I3(sig_data2all_tlast_error),
        .I4(sig_dqual_reg_full),
        .O(sig_data2wsc_cmd_cmplt0));
  FDRE #(
    .INIT(1'b0)) 
    sig_data2wsc_cmd_cmplt_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_to_wsc_i_2_n_0),
        .D(sig_data2wsc_cmd_cmplt0),
        .Q(in[0]),
        .R(sig_push_to_wsc0));
  LUT6 #(
    .INIT(64'hAAEAAAEAAABFAAEA)) 
    sig_data2wsc_last_err_i_1
       (.I0(sig_data2all_tlast_error),
        .I1(D),
        .I2(Q),
        .I3(\sig_dbeat_cntr[7]_i_3_n_0 ),
        .I4(sig_dqual_reg_full),
        .I5(\sig_dbeat_cntr[7]_i_4_n_0 ),
        .O(sig_data2wsc_last_err0));
  FDRE #(
    .INIT(1'b0)) 
    sig_data2wsc_last_err_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_to_wsc_i_2_n_0),
        .D(sig_data2wsc_last_err0),
        .Q(in[1]),
        .R(sig_push_to_wsc0));
  LUT3 #(
    .INIT(8'h47)) 
    \sig_dbeat_cntr[0]_i_1 
       (.I0(\sig_dbeat_cntr_reg[0]_0 ),
        .I1(sig_data2mstr_cmd_ready),
        .I2(sig_dbeat_cntr[0]),
        .O(\sig_dbeat_cntr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT3 #(
    .INIT(8'h41)) 
    \sig_dbeat_cntr[1]_i_1 
       (.I0(sig_data2mstr_cmd_ready),
        .I1(sig_dbeat_cntr[0]),
        .I2(sig_dbeat_cntr[1]),
        .O(\sig_dbeat_cntr[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT5 #(
    .INIT(32'h00FFE1E1)) 
    \sig_dbeat_cntr[2]_i_1 
       (.I0(sig_dbeat_cntr[0]),
        .I1(sig_dbeat_cntr[1]),
        .I2(sig_dbeat_cntr[2]),
        .I3(\sig_dbeat_cntr_reg[0]_0 ),
        .I4(sig_data2mstr_cmd_ready),
        .O(\sig_dbeat_cntr[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT5 #(
    .INIT(32'h44444441)) 
    \sig_dbeat_cntr[3]_i_1 
       (.I0(sig_data2mstr_cmd_ready),
        .I1(sig_dbeat_cntr[3]),
        .I2(sig_dbeat_cntr[2]),
        .I3(sig_dbeat_cntr[0]),
        .I4(sig_dbeat_cntr[1]),
        .O(\sig_dbeat_cntr[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000FFFE00000001)) 
    \sig_dbeat_cntr[4]_i_1 
       (.I0(sig_dbeat_cntr[3]),
        .I1(sig_dbeat_cntr[2]),
        .I2(sig_dbeat_cntr[0]),
        .I3(sig_dbeat_cntr[1]),
        .I4(sig_data2mstr_cmd_ready),
        .I5(sig_dbeat_cntr[4]),
        .O(\sig_dbeat_cntr[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'h00E1)) 
    \sig_dbeat_cntr[5]_i_1 
       (.I0(sig_dbeat_cntr[4]),
        .I1(m_axi_sg_wlast_INST_0_i_1_n_0),
        .I2(sig_dbeat_cntr[5]),
        .I3(sig_data2mstr_cmd_ready),
        .O(\sig_dbeat_cntr[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT5 #(
    .INIT(32'h0000FE01)) 
    \sig_dbeat_cntr[6]_i_1 
       (.I0(m_axi_sg_wlast_INST_0_i_1_n_0),
        .I1(sig_dbeat_cntr[4]),
        .I2(sig_dbeat_cntr[5]),
        .I3(sig_dbeat_cntr[6]),
        .I4(sig_data2mstr_cmd_ready),
        .O(\sig_dbeat_cntr[6]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hF4)) 
    \sig_dbeat_cntr[7]_i_1 
       (.I0(\sig_dbeat_cntr[7]_i_3_n_0 ),
        .I1(\sig_dbeat_cntr[7]_i_4_n_0 ),
        .I2(sig_data2mstr_cmd_ready),
        .O(\sig_dbeat_cntr[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0001)) 
    \sig_dbeat_cntr[7]_i_2 
       (.I0(sig_dbeat_cntr[5]),
        .I1(sig_dbeat_cntr[4]),
        .I2(m_axi_sg_wlast_INST_0_i_1_n_0),
        .I3(sig_dbeat_cntr[6]),
        .I4(sig_dbeat_cntr[7]),
        .I5(sig_data2mstr_cmd_ready),
        .O(\sig_dbeat_cntr[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT5 #(
    .INIT(32'hDDDDDFFF)) 
    \sig_dbeat_cntr[7]_i_3 
       (.I0(m_axi_sg_wready),
        .I1(m_axi_sg_wvalid_INST_0_i_1_n_0),
        .I2(D),
        .I3(follower_full_mm2s),
        .I4(sig_data2all_tlast_error),
        .O(\sig_dbeat_cntr[7]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \sig_dbeat_cntr[7]_i_4 
       (.I0(sig_dbeat_cntr[7]),
        .I1(sig_dbeat_cntr[6]),
        .I2(m_axi_sg_wlast_INST_0_i_1_n_0),
        .I3(sig_dbeat_cntr[4]),
        .I4(sig_dbeat_cntr[5]),
        .O(\sig_dbeat_cntr[7]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(\sig_dbeat_cntr[7]_i_1_n_0 ),
        .D(\sig_dbeat_cntr[0]_i_1_n_0 ),
        .Q(sig_dbeat_cntr[0]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(\sig_dbeat_cntr[7]_i_1_n_0 ),
        .D(\sig_dbeat_cntr[1]_i_1_n_0 ),
        .Q(sig_dbeat_cntr[1]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(\sig_dbeat_cntr[7]_i_1_n_0 ),
        .D(\sig_dbeat_cntr[2]_i_1_n_0 ),
        .Q(sig_dbeat_cntr[2]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(\sig_dbeat_cntr[7]_i_1_n_0 ),
        .D(\sig_dbeat_cntr[3]_i_1_n_0 ),
        .Q(sig_dbeat_cntr[3]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(\sig_dbeat_cntr[7]_i_1_n_0 ),
        .D(\sig_dbeat_cntr[4]_i_1_n_0 ),
        .Q(sig_dbeat_cntr[4]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[5] 
       (.C(m_axi_sg_aclk),
        .CE(\sig_dbeat_cntr[7]_i_1_n_0 ),
        .D(\sig_dbeat_cntr[5]_i_1_n_0 ),
        .Q(sig_dbeat_cntr[5]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[6] 
       (.C(m_axi_sg_aclk),
        .CE(\sig_dbeat_cntr[7]_i_1_n_0 ),
        .D(\sig_dbeat_cntr[6]_i_1_n_0 ),
        .Q(sig_dbeat_cntr[6]),
        .R(sig_stream_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sig_dbeat_cntr_reg[7] 
       (.C(m_axi_sg_aclk),
        .CE(\sig_dbeat_cntr[7]_i_1_n_0 ),
        .D(\sig_dbeat_cntr[7]_i_2_n_0 ),
        .Q(sig_dbeat_cntr[7]),
        .R(sig_stream_rst));
  FDSE #(
    .INIT(1'b0)) 
    sig_dqual_reg_empty_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_data2mstr_cmd_ready),
        .D(1'b0),
        .Q(sig_dqual_reg_empty),
        .S(sig_clr_dqual_reg));
  LUT6 #(
    .INIT(64'h00000010FFFFFFFF)) 
    sig_dqual_reg_full_i_1
       (.I0(\sig_dbeat_cntr[7]_i_4_n_0 ),
        .I1(\sig_dbeat_cntr[7]_i_3_n_0 ),
        .I2(sig_dqual_reg_full),
        .I3(sig_next_calc_error_reg),
        .I4(sig_data2mstr_cmd_ready),
        .I5(sig_push_err2wsc_reg_0),
        .O(sig_clr_dqual_reg));
  LUT4 #(
    .INIT(16'h007F)) 
    sig_dqual_reg_full_i_2
       (.I0(sig_addr_posted_cntr[2]),
        .I1(sig_addr_posted_cntr[0]),
        .I2(sig_addr_posted_cntr[1]),
        .I3(sig_dqual_reg_empty_reg_0),
        .O(sig_data2mstr_cmd_ready));
  FDRE #(
    .INIT(1'b0)) 
    sig_dqual_reg_full_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_data2mstr_cmd_ready),
        .D(1'b1),
        .Q(sig_dqual_reg_full),
        .R(sig_clr_dqual_reg));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    sig_last_mmap_dbeat_reg_i_1
       (.I0(sig_dbeat_cntr[5]),
        .I1(sig_dbeat_cntr[4]),
        .I2(m_axi_sg_wlast_INST_0_i_1_n_0),
        .I3(sig_dbeat_cntr[6]),
        .I4(sig_dbeat_cntr[7]),
        .I5(\sig_dbeat_cntr[7]_i_3_n_0 ),
        .O(sig_last_mmap_dbeat));
  FDRE #(
    .INIT(1'b0)) 
    sig_last_mmap_dbeat_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_last_mmap_dbeat),
        .Q(sig_last_mmap_dbeat_reg),
        .R(sig_stream_rst));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT3 #(
    .INIT(8'h40)) 
    sig_ld_new_cmd_reg_i_1
       (.I0(sig_ld_new_cmd_reg),
        .I1(sig_push_err2wsc_reg_0),
        .I2(sig_data2mstr_cmd_ready),
        .O(sig_ld_new_cmd_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_ld_new_cmd_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_ld_new_cmd_reg_i_1_n_0),
        .Q(sig_ld_new_cmd_reg),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    sig_next_calc_error_reg_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_data2mstr_cmd_ready),
        .D(sig_calc2dm_calc_err),
        .Q(sig_next_calc_error_reg),
        .R(sig_clr_dqual_reg));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    sig_push_err2wsc_i_1
       (.I0(sig_push_err2wsc_reg_0),
        .I1(sig_push_err2wsc),
        .I2(sig_ld_new_cmd_reg),
        .I3(sig_next_calc_error_reg),
        .O(sig_push_err2wsc_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_push_err2wsc_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(sig_push_err2wsc_i_1_n_0),
        .Q(sig_push_err2wsc),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h5400FFFF)) 
    sig_push_to_wsc_i_1
       (.I0(sig_push_err2wsc),
        .I1(\sig_dbeat_cntr[7]_i_3_n_0 ),
        .I2(\sig_dbeat_cntr[7]_i_4_n_0 ),
        .I3(sig_data2wsc_calc_err_reg_0),
        .I4(sig_push_err2wsc_reg_0),
        .O(sig_push_to_wsc0));
  LUT4 #(
    .INIT(16'h5501)) 
    sig_push_to_wsc_i_2
       (.I0(sig_tlast_err_stop),
        .I1(\sig_dbeat_cntr[7]_i_4_n_0 ),
        .I2(\sig_dbeat_cntr[7]_i_3_n_0 ),
        .I3(sig_push_err2wsc),
        .O(sig_push_to_wsc_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    sig_push_to_wsc_reg
       (.C(m_axi_sg_aclk),
        .CE(sig_push_to_wsc_i_2_n_0),
        .D(1'b1),
        .Q(sig_push_to_wsc),
        .R(sig_push_to_wsc0));
endmodule

module Loopback_axi_dma_1_0_cdc_sync
   (scndry_out,
    axi_resetn,
    m_axi_sg_aclk);
  output scndry_out;
  input axi_resetn;
  input m_axi_sg_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire Q;
  wire axi_resetn;
  wire m_axi_sg_aclk;
  wire scndry_out;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(axi_resetn),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(scndry_out),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync_0
   (scndry_out,
    axi_resetn,
    s_axi_lite_aclk);
  output scndry_out;
  input axi_resetn;
  input s_axi_lite_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire Q;
  wire axi_resetn;
  wire s_axi_lite_aclk;
  wire scndry_out;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(axi_resetn),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(scndry_out),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync_1
   (scndry_out,
    prmry_in,
    m_axi_mm2s_aclk);
  output scndry_out;
  input prmry_in;
  input m_axi_mm2s_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire Q;
  wire m_axi_mm2s_aclk;
  wire prmry_in;
  wire scndry_out;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(prmry_in),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(scndry_out),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync_10
   (\GEN_ASYNC_WRITE.rdy_to2_reg ,
    scndry_out,
    s_axi_lite_wready,
    \GEN_ASYNC_WRITE.bvalid_i_reg ,
    \GEN_ASYNC_WRITE.bvalid_i_reg_0 ,
    s_axi_lite_bvalid,
    s_axi_lite_bready,
    prmry_in,
    s_axi_lite_aclk);
  output \GEN_ASYNC_WRITE.rdy_to2_reg ;
  output scndry_out;
  output s_axi_lite_wready;
  input \GEN_ASYNC_WRITE.bvalid_i_reg ;
  input \GEN_ASYNC_WRITE.bvalid_i_reg_0 ;
  input s_axi_lite_bvalid;
  input s_axi_lite_bready;
  input prmry_in;
  input s_axi_lite_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire \GEN_ASYNC_WRITE.bvalid_i_reg ;
  wire \GEN_ASYNC_WRITE.bvalid_i_reg_0 ;
  wire \GEN_ASYNC_WRITE.rdy_to2_reg ;
  wire Q;
  wire prmry_in;
  wire s_axi_lite_aclk;
  wire s_axi_lite_bready;
  wire s_axi_lite_bvalid;
  wire s_axi_lite_wready;
  wire scndry_out;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_in),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(scndry_out),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT5 #(
    .INIT(32'h0020F020)) 
    \GEN_ASYNC_WRITE.bvalid_i_i_1 
       (.I0(\GEN_ASYNC_WRITE.bvalid_i_reg ),
        .I1(scndry_out),
        .I2(\GEN_ASYNC_WRITE.bvalid_i_reg_0 ),
        .I3(s_axi_lite_bvalid),
        .I4(s_axi_lite_bready),
        .O(\GEN_ASYNC_WRITE.rdy_to2_reg ));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT2 #(
    .INIT(4'h2)) 
    s_axi_lite_wready_INST_0
       (.I0(\GEN_ASYNC_WRITE.bvalid_i_reg ),
        .I1(scndry_out),
        .O(s_axi_lite_wready));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync_11
   (\GEN_ASYNC_WRITE.ip_addr_cap0 ,
    scndry_out,
    \GEN_ASYNC_WRITE.rdy_back ,
    \GEN_ASYNC_WRITE.rdy_cdc_from_reg ,
    prmry_in,
    m_axi_sg_aclk);
  output \GEN_ASYNC_WRITE.ip_addr_cap0 ;
  output scndry_out;
  input \GEN_ASYNC_WRITE.rdy_back ;
  input \GEN_ASYNC_WRITE.rdy_cdc_from_reg ;
  input prmry_in;
  input m_axi_sg_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire \GEN_ASYNC_WRITE.ip_addr_cap0 ;
  wire \GEN_ASYNC_WRITE.rdy_back ;
  wire \GEN_ASYNC_WRITE.rdy_cdc_from_reg ;
  wire Q;
  wire m_axi_sg_aclk;
  wire prmry_in;
  wire scndry_out;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(prmry_in),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(scndry_out),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h4F)) 
    \GEN_ASYNC_WRITE.ip_addr_cap_i_1 
       (.I0(\GEN_ASYNC_WRITE.rdy_back ),
        .I1(scndry_out),
        .I2(\GEN_ASYNC_WRITE.rdy_cdc_from_reg ),
        .O(\GEN_ASYNC_WRITE.ip_addr_cap0 ));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync_12
   (scndry_out,
    prmry_in,
    m_axi_sg_aclk);
  output scndry_out;
  input prmry_in;
  input m_axi_sg_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire Q;
  wire m_axi_sg_aclk;
  wire prmry_in;
  wire scndry_out;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(prmry_in),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(scndry_out),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync_2
   (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ,
    mm2s_all_idle,
    soft_reset,
    soft_reset_clr,
    s_soft_reset_i,
    prmry_in,
    m_axi_sg_aclk);
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
  input mm2s_all_idle;
  input soft_reset;
  input soft_reset_clr;
  input s_soft_reset_i;
  input prmry_in;
  input m_axi_sg_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire Q;
  wire m_axi_sg_aclk;
  wire mm2s_all_idle;
  wire prmry_in;
  wire s_halt_cmplt;
  wire s_soft_reset_i;
  wire soft_reset;
  wire soft_reset_clr;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(prmry_in),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(s_halt_cmplt),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80FF8080)) 
    \GEN_ASYNC_RESET.s_soft_reset_i_i_1 
       (.I0(mm2s_all_idle),
        .I1(s_halt_cmplt),
        .I2(soft_reset),
        .I3(soft_reset_clr),
        .I4(s_soft_reset_i),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync_3
   (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ,
    scndry_out,
    mm2s_halt,
    \GEN_ASYNC_RESET.halt_i_reg ,
    prmry_in,
    m_axi_mm2s_aclk);
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
  output scndry_out;
  input mm2s_halt;
  input \GEN_ASYNC_RESET.halt_i_reg ;
  input prmry_in;
  input m_axi_mm2s_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire \GEN_ASYNC_RESET.halt_i_reg ;
  wire Q;
  wire m_axi_mm2s_aclk;
  wire mm2s_halt;
  wire prmry_in;
  wire scndry_out;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(prmry_in),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(scndry_out),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hA8)) 
    \GEN_ASYNC_RESET.halt_i_i_1 
       (.I0(scndry_out),
        .I1(mm2s_halt),
        .I2(\GEN_ASYNC_RESET.halt_i_reg ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync_8
   (mm2s_introut,
    prmry_in,
    s_axi_lite_aclk);
  output mm2s_introut;
  input prmry_in;
  input s_axi_lite_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire Q;
  wire mm2s_introut;
  wire prmry_in;
  wire s_axi_lite_aclk;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_in),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(mm2s_introut),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync_9
   (scndry_out,
    prmry_in,
    m_axi_sg_aclk);
  output scndry_out;
  input prmry_in;
  input m_axi_sg_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire Q;
  wire m_axi_sg_aclk;
  wire prmry_in;
  wire scndry_out;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(prmry_in),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(scndry_out),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync__parameterized0
   (\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_0 ,
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_0 ,
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_1 ,
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_2 ,
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ,
    \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4] ,
    rdy,
    s_axi_lite_awaddr,
    m_axi_sg_aclk);
  output \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_0 ;
  output \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_0 ;
  output \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_1 ;
  output \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_2 ;
  output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
  input \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4] ;
  input rdy;
  input [4:0]s_axi_lite_awaddr;
  input m_axi_sg_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_1 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ;
  wire [6:2]\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig ;
  wire \GEN_ASYNC_WRITE.axi2ip_wrce_reg[4] ;
  wire m_axi_sg_aclk;
  wire rdy;
  wire [4:0]s_axi_lite_awaddr;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_awaddr[0]),
        .Q(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_awaddr[1]),
        .Q(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_awaddr[2]),
        .Q(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_awaddr[3]),
        .Q(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_awaddr[4]),
        .Q(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [6]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \GEN_ASYNC_WRITE.axi2ip_wrce[0]_i_1 
       (.I0(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [4]),
        .I1(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [3]),
        .I2(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [2]),
        .O(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_2 ));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT3 #(
    .INIT(8'h10)) 
    \GEN_ASYNC_WRITE.axi2ip_wrce[1]_i_1 
       (.I0(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [4]),
        .I1(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [3]),
        .I2(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [2]),
        .O(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_1 ));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \GEN_ASYNC_WRITE.axi2ip_wrce[2]_i_1 
       (.I0(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [4]),
        .I1(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [3]),
        .I2(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [2]),
        .O(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_0 ));
  LUT4 #(
    .INIT(16'hFFF7)) 
    \GEN_ASYNC_WRITE.axi2ip_wrce[4]_i_1 
       (.I0(\GEN_ASYNC_WRITE.axi2ip_wrce_reg[4] ),
        .I1(rdy),
        .I2(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [6]),
        .I3(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [5]),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \GEN_ASYNC_WRITE.axi2ip_wrce[4]_i_2 
       (.I0(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [3]),
        .I1(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [4]),
        .I2(\GEN_ASYNC_WRITE.awaddr_d1_cdc_tig [2]),
        .O(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_0 ));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync__parameterized1
   (irqthresh_wren0,
    scndry_vect_out,
    irqdelay_wren0,
    SS,
    \dmacr_i_reg[2] ,
    Q,
    \dmacr_i_reg[23] ,
    irqthresh_wren_reg,
    mm2s_dmacr,
    irqdelay_wren_reg,
    out,
    \dmacr_i_reg[2]_0 ,
    soft_reset_clr,
    s_axi_lite_wdata,
    m_axi_sg_aclk);
  output irqthresh_wren0;
  output [28:0]scndry_vect_out;
  output irqdelay_wren0;
  output [0:0]SS;
  output \dmacr_i_reg[2] ;
  input [1:0]Q;
  input \dmacr_i_reg[23] ;
  input irqthresh_wren_reg;
  input [1:0]mm2s_dmacr;
  input irqdelay_wren_reg;
  input out;
  input \dmacr_i_reg[2]_0 ;
  input soft_reset_clr;
  input [29:0]s_axi_lite_wdata;
  input m_axi_sg_aclk;

  wire [1:0]Q;
  wire [0:0]SS;
  wire [2:2]axi2ip_wrdata;
  wire \dmacr_i[23]_i_2_n_0 ;
  wire \dmacr_i_reg[23] ;
  wire \dmacr_i_reg[2] ;
  wire \dmacr_i_reg[2]_0 ;
  wire irqdelay_wren0;
  wire irqdelay_wren_reg;
  wire irqthresh_wren0;
  wire irqthresh_wren_reg;
  wire m_axi_sg_aclk;
  wire [1:0]mm2s_dmacr;
  wire out;
  wire [29:0]s_axi_lite_wdata;
  wire [28:0]scndry_vect_out;
  wire soft_reset_clr;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[0]),
        .Q(scndry_vect_out[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[8]),
        .Q(scndry_vect_out[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[9]),
        .Q(scndry_vect_out[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[10]),
        .Q(scndry_vect_out[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[11]),
        .Q(scndry_vect_out[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[12]),
        .Q(scndry_vect_out[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[13]),
        .Q(scndry_vect_out[12]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[14]),
        .Q(scndry_vect_out[13]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[15]),
        .Q(scndry_vect_out[14]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[16]),
        .Q(scndry_vect_out[15]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[17]),
        .Q(scndry_vect_out[16]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[18]),
        .Q(scndry_vect_out[17]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[19]),
        .Q(scndry_vect_out[18]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[20]),
        .Q(scndry_vect_out[19]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[21]),
        .Q(scndry_vect_out[20]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[22]),
        .Q(scndry_vect_out[21]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[23]),
        .Q(scndry_vect_out[22]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[24]),
        .Q(scndry_vect_out[23]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[25]),
        .Q(scndry_vect_out[24]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[26]),
        .Q(scndry_vect_out[25]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[27]),
        .Q(scndry_vect_out[26]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[1]),
        .Q(axi2ip_wrdata),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[28]),
        .Q(scndry_vect_out[27]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[29]),
        .Q(scndry_vect_out[28]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[2]),
        .Q(scndry_vect_out[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[3]),
        .Q(scndry_vect_out[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[4]),
        .Q(scndry_vect_out[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[5]),
        .Q(scndry_vect_out[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[6]),
        .Q(scndry_vect_out[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_wdata[7]),
        .Q(scndry_vect_out[6]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h1000FFFF)) 
    \dmacr_i[23]_i_1 
       (.I0(scndry_vect_out[14]),
        .I1(scndry_vect_out[13]),
        .I2(\dmacr_i_reg[23] ),
        .I3(\dmacr_i[23]_i_2_n_0 ),
        .I4(out),
        .O(SS));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \dmacr_i[23]_i_2 
       (.I0(scndry_vect_out[15]),
        .I1(scndry_vect_out[16]),
        .I2(scndry_vect_out[17]),
        .I3(scndry_vect_out[18]),
        .I4(scndry_vect_out[20]),
        .I5(scndry_vect_out[19]),
        .O(\dmacr_i[23]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h00EA)) 
    \dmacr_i[2]_i_1 
       (.I0(\dmacr_i_reg[2]_0 ),
        .I1(\dmacr_i_reg[23] ),
        .I2(axi2ip_wrdata),
        .I3(soft_reset_clr),
        .O(\dmacr_i_reg[2] ));
  LUT6 #(
    .INIT(64'hF060F0F0F0F0F060)) 
    irqdelay_wren_i_1
       (.I0(scndry_vect_out[28]),
        .I1(mm2s_dmacr[1]),
        .I2(\dmacr_i_reg[23] ),
        .I3(irqdelay_wren_reg),
        .I4(scndry_vect_out[27]),
        .I5(mm2s_dmacr[0]),
        .O(irqdelay_wren0));
  LUT6 #(
    .INIT(64'hF060F0F0F0F0F060)) 
    irqthresh_wren_i_1
       (.I0(scndry_vect_out[20]),
        .I1(Q[1]),
        .I2(\dmacr_i_reg[23] ),
        .I3(irqthresh_wren_reg),
        .I4(scndry_vect_out[19]),
        .I5(Q[0]),
        .O(irqthresh_wren0));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync__parameterized2
   (scndry_vect_out,
    s_axi_lite_araddr,
    m_axi_sg_aclk);
  output [9:0]scndry_vect_out;
  input [9:0]s_axi_lite_araddr;
  input m_axi_sg_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire [9:0]\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 ;
  wire [9:0]\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 ;
  wire Q;
  wire m_axi_sg_aclk;
  wire [9:0]s_axi_lite_araddr;
  wire [9:0]scndry_vect_out;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [0]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [1]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [2]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [3]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [4]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [5]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [6]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [7]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [8]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [9]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [0]),
        .Q(scndry_vect_out[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [1]),
        .Q(scndry_vect_out[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [2]),
        .Q(scndry_vect_out[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [3]),
        .Q(scndry_vect_out[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [4]),
        .Q(scndry_vect_out[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [5]),
        .Q(scndry_vect_out[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [6]),
        .Q(scndry_vect_out[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [7]),
        .Q(scndry_vect_out[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [8]),
        .Q(scndry_vect_out[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [9]),
        .Q(scndry_vect_out[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_araddr[0]),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_araddr[1]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_araddr[2]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_araddr[3]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_araddr[4]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_araddr[5]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_araddr[6]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_araddr[7]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_araddr[8]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_araddr[9]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync__parameterized3
   (E,
    scndry_out,
    \GEN_ASYNC_READ.ip_arvalid_d3 ,
    s_axi_lite_arready,
    m_axi_sg_aclk);
  output [0:0]E;
  output scndry_out;
  input \GEN_ASYNC_READ.ip_arvalid_d3 ;
  input s_axi_lite_arready;
  input m_axi_sg_aclk;

  wire [0:0]E;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire \GEN_ASYNC_READ.ip_arvalid_d3 ;
  wire Q;
  wire m_axi_sg_aclk;
  wire s_axi_lite_arready;
  wire scndry_out;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(s_axi_lite_arready),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(scndry_out),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    \GEN_ASYNC_READ.rvalid_i_1 
       (.I0(scndry_out),
        .I1(\GEN_ASYNC_READ.ip_arvalid_d3 ),
        .O(E));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module Loopback_axi_dma_1_0_cdc_sync__parameterized4
   (scndry_vect_out,
    prmry_vect_in,
    s_axi_lite_aclk);
  output [31:0]scndry_vect_out;
  input [31:0]prmry_vect_in;
  input s_axi_lite_aclk;

  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ;
  wire [31:0]\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 ;
  wire [31:0]\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 ;
  wire Q;
  wire [31:0]prmry_vect_in;
  wire s_axi_lite_aclk;
  wire [31:0]scndry_vect_out;

  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [12]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [13]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [14]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [15]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [16]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [17]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [18]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [19]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [20]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [21]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [22]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [23]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [24]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [25]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [26]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [27]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [28]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [29]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [30]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [31]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [0]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [10]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [11]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [12]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [12]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [13]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [13]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [14]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [14]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [15]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [15]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [16]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [16]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [17]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [17]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [18]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [18]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [19]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [19]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [1]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [20]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [20]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [21]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [21]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [22]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [22]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [23]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [23]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [24]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [24]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [25]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [25]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [26]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [26]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [27]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [27]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [28]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [28]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [29]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [29]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [2]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [30]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [30]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [31]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [31]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [3]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [4]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [5]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [6]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [7]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [8]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d2 [9]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [0]),
        .Q(scndry_vect_out[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [10]),
        .Q(scndry_vect_out[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [11]),
        .Q(scndry_vect_out[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [12]),
        .Q(scndry_vect_out[12]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [13]),
        .Q(scndry_vect_out[13]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [14]),
        .Q(scndry_vect_out[14]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [15]),
        .Q(scndry_vect_out[15]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [16]),
        .Q(scndry_vect_out[16]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [17]),
        .Q(scndry_vect_out[17]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [18]),
        .Q(scndry_vect_out[18]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [19]),
        .Q(scndry_vect_out[19]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [1]),
        .Q(scndry_vect_out[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [20]),
        .Q(scndry_vect_out[20]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [21]),
        .Q(scndry_vect_out[21]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [22]),
        .Q(scndry_vect_out[22]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [23]),
        .Q(scndry_vect_out[23]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [24]),
        .Q(scndry_vect_out[24]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [25]),
        .Q(scndry_vect_out[25]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [26]),
        .Q(scndry_vect_out[26]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [27]),
        .Q(scndry_vect_out[27]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [28]),
        .Q(scndry_vect_out[28]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [29]),
        .Q(scndry_vect_out[29]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [2]),
        .Q(scndry_vect_out[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [30]),
        .Q(scndry_vect_out[30]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [31]),
        .Q(scndry_vect_out[31]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [3]),
        .Q(scndry_vect_out[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [4]),
        .Q(scndry_vect_out[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [5]),
        .Q(scndry_vect_out[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [6]),
        .Q(scndry_vect_out[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [7]),
        .Q(scndry_vect_out[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [8]),
        .Q(scndry_vect_out[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.s_level_out_bus_d3 [9]),
        .Q(scndry_vect_out[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[0]),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[10]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[11]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[12]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[13]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[14]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[15]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[16]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[17]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[18]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[19]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[1]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[20]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[21]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[22]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[23]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[24]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[25]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[26]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[27]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[28]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[29]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[2]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[30]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[31]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[3]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[4]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[5]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[6]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[7]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[8]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(s_axi_lite_aclk),
        .CE(1'b1),
        .D(prmry_vect_in[9]),
        .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_n_0 ),
        .R(1'b0));
endmodule

module Loopback_axi_dma_1_0_cntr_incr_decr_addn_f
   (fifo_full_p1,
    sig_next_sequential_reg_reg,
    Q,
    E,
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ,
    SR,
    D,
    sig_mmap_rst_reg_n_reg,
    sig_next_calc_error_reg_reg,
    sig_mmap_rst_reg_n_reg_0,
    \USE_SRL_FIFO.sig_wr_fifo ,
    \INFERRED_GEN.cnt_i_reg[1]_0 ,
    \INFERRED_GEN.cnt_i_reg[1]_1 ,
    sig_mstr2data_cmd_valid,
    sig_dqual_reg_empty,
    sig_dqual_reg_empty_reg,
    sig_next_sequential_reg,
    \sig_dbeat_cntr_reg[0] ,
    m_axi_mm2s_rlast,
    sig_mmap_rst_reg_n,
    \sig_dbeat_cntr_reg[7] ,
    \sig_dbeat_cntr_reg[6] ,
    \sig_dbeat_cntr_reg[5] ,
    out,
    sig_ld_new_cmd_reg,
    sig_rsc2stat_status_valid,
    sig_stat2rsc_status_ready,
    sig_next_calc_error_reg,
    m_axi_mm2s_rready,
    full,
    sig_dqual_reg_empty_reg_0,
    m_axi_mm2s_rvalid,
    sig_dqual_reg_empty_reg_1,
    sig_dqual_reg_full,
    sig_last_dbeat_reg,
    sig_last_dbeat_reg_0,
    SS,
    m_axi_mm2s_aclk);
  output fifo_full_p1;
  output sig_next_sequential_reg_reg;
  output [1:0]Q;
  output [0:0]E;
  output \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  output [0:0]SR;
  output [6:0]D;
  output sig_mmap_rst_reg_n_reg;
  output sig_next_calc_error_reg_reg;
  output sig_mmap_rst_reg_n_reg_0;
  input \USE_SRL_FIFO.sig_wr_fifo ;
  input \INFERRED_GEN.cnt_i_reg[1]_0 ;
  input \INFERRED_GEN.cnt_i_reg[1]_1 ;
  input sig_mstr2data_cmd_valid;
  input sig_dqual_reg_empty;
  input sig_dqual_reg_empty_reg;
  input sig_next_sequential_reg;
  input \sig_dbeat_cntr_reg[0] ;
  input m_axi_mm2s_rlast;
  input sig_mmap_rst_reg_n;
  input [7:0]\sig_dbeat_cntr_reg[7] ;
  input \sig_dbeat_cntr_reg[6] ;
  input \sig_dbeat_cntr_reg[5] ;
  input [2:0]out;
  input sig_ld_new_cmd_reg;
  input sig_rsc2stat_status_valid;
  input sig_stat2rsc_status_ready;
  input sig_next_calc_error_reg;
  input [2:0]m_axi_mm2s_rready;
  input full;
  input sig_dqual_reg_empty_reg_0;
  input m_axi_mm2s_rvalid;
  input sig_dqual_reg_empty_reg_1;
  input sig_dqual_reg_full;
  input sig_last_dbeat_reg;
  input sig_last_dbeat_reg_0;
  input [0:0]SS;
  input m_axi_mm2s_aclk;

  wire [6:0]D;
  wire [0:0]E;
  wire \INFERRED_GEN.cnt_i_reg[1]_0 ;
  wire \INFERRED_GEN.cnt_i_reg[1]_1 ;
  wire [1:0]Q;
  wire [0:0]SR;
  wire [0:0]SS;
  wire \USE_SRL_FIFO.sig_rd_empty ;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire [2:0]addr_i_p1;
  wire fifo_full_p1;
  wire full;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  wire m_axi_mm2s_aclk;
  wire m_axi_mm2s_rlast;
  wire [2:0]m_axi_mm2s_rready;
  wire m_axi_mm2s_rvalid;
  wire [2:0]out;
  wire \sig_dbeat_cntr_reg[0] ;
  wire \sig_dbeat_cntr_reg[5] ;
  wire \sig_dbeat_cntr_reg[6] ;
  wire [7:0]\sig_dbeat_cntr_reg[7] ;
  wire sig_dqual_reg_empty;
  wire sig_dqual_reg_empty_reg;
  wire sig_dqual_reg_empty_reg_0;
  wire sig_dqual_reg_empty_reg_1;
  wire sig_dqual_reg_full;
  wire sig_last_dbeat_reg;
  wire sig_last_dbeat_reg_0;
  wire sig_ld_new_cmd_reg;
  wire sig_mmap_rst_reg_n;
  wire sig_mmap_rst_reg_n_reg;
  wire sig_mmap_rst_reg_n_reg_0;
  wire sig_mstr2data_cmd_valid;
  wire sig_next_calc_error_reg;
  wire sig_next_calc_error_reg_reg;
  wire sig_next_sequential_reg;
  wire sig_next_sequential_reg_reg;
  wire \sig_next_tag_reg[0]_i_4_n_0 ;
  wire \sig_next_tag_reg[0]_i_5_n_0 ;
  wire sig_rsc2stat_status_valid;
  wire sig_stat2rsc_status_ready;

  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT5 #(
    .INIT(32'h80009400)) 
    FIFO_Full_i_1__1
       (.I0(sig_next_sequential_reg_reg),
        .I1(\USE_SRL_FIFO.sig_wr_fifo ),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(\USE_SRL_FIFO.sig_rd_empty ),
        .O(fifo_full_p1));
  LUT5 #(
    .INIT(32'h5595AA6A)) 
    \INFERRED_GEN.cnt_i[0]_i_1__1 
       (.I0(sig_next_sequential_reg_reg),
        .I1(sig_mstr2data_cmd_valid),
        .I2(\INFERRED_GEN.cnt_i_reg[1]_1 ),
        .I3(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I4(Q[0]),
        .O(addr_i_p1[0]));
  LUT6 #(
    .INIT(64'hFF4000BFBFFF4000)) 
    \INFERRED_GEN.cnt_i[1]_i_1__1 
       (.I0(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I1(\INFERRED_GEN.cnt_i_reg[1]_1 ),
        .I2(sig_mstr2data_cmd_valid),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(sig_next_sequential_reg_reg),
        .O(addr_i_p1[1]));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT5 #(
    .INIT(32'h00036AAA)) 
    \INFERRED_GEN.cnt_i[2]_i_1__1 
       (.I0(\USE_SRL_FIFO.sig_rd_empty ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\USE_SRL_FIFO.sig_wr_fifo ),
        .I4(sig_next_sequential_reg_reg),
        .O(addr_i_p1[2]));
  FDSE \INFERRED_GEN.cnt_i_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(addr_i_p1[0]),
        .Q(Q[0]),
        .S(SS));
  FDSE \INFERRED_GEN.cnt_i_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(addr_i_p1[1]),
        .Q(Q[1]),
        .S(SS));
  FDSE \INFERRED_GEN.cnt_i_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(addr_i_p1[2]),
        .Q(\USE_SRL_FIFO.sig_rd_empty ),
        .S(SS));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT5 #(
    .INIT(32'hAAABFFFF)) 
    m_axi_mm2s_rready_INST_0_i_1
       (.I0(sig_next_calc_error_reg),
        .I1(m_axi_mm2s_rready[1]),
        .I2(m_axi_mm2s_rready[0]),
        .I3(m_axi_mm2s_rready[2]),
        .I4(sig_dqual_reg_full),
        .O(sig_next_calc_error_reg_reg));
  LUT4 #(
    .INIT(16'hF909)) 
    \sig_dbeat_cntr[1]_i_1__0 
       (.I0(\sig_dbeat_cntr_reg[7] [1]),
        .I1(\sig_dbeat_cntr_reg[7] [0]),
        .I2(sig_next_sequential_reg_reg),
        .I3(out[0]),
        .O(D[0]));
  LUT5 #(
    .INIT(32'hFFE100E1)) 
    \sig_dbeat_cntr[2]_i_1__0 
       (.I0(\sig_dbeat_cntr_reg[7] [0]),
        .I1(\sig_dbeat_cntr_reg[7] [1]),
        .I2(\sig_dbeat_cntr_reg[7] [2]),
        .I3(sig_next_sequential_reg_reg),
        .I4(out[1]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hFFFFFE010000FE01)) 
    \sig_dbeat_cntr[3]_i_1__0 
       (.I0(\sig_dbeat_cntr_reg[7] [1]),
        .I1(\sig_dbeat_cntr_reg[7] [0]),
        .I2(\sig_dbeat_cntr_reg[7] [2]),
        .I3(\sig_dbeat_cntr_reg[7] [3]),
        .I4(sig_next_sequential_reg_reg),
        .I5(out[2]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'h4444444444444441)) 
    \sig_dbeat_cntr[4]_i_1__0 
       (.I0(sig_next_sequential_reg_reg),
        .I1(\sig_dbeat_cntr_reg[7] [4]),
        .I2(\sig_dbeat_cntr_reg[7] [0]),
        .I3(\sig_dbeat_cntr_reg[7] [1]),
        .I4(\sig_dbeat_cntr_reg[7] [2]),
        .I5(\sig_dbeat_cntr_reg[7] [3]),
        .O(D[3]));
  LUT6 #(
    .INIT(64'h4444444144444444)) 
    \sig_dbeat_cntr[5]_i_1__0 
       (.I0(sig_next_sequential_reg_reg),
        .I1(\sig_dbeat_cntr_reg[7] [5]),
        .I2(\sig_dbeat_cntr_reg[7] [4]),
        .I3(\sig_dbeat_cntr_reg[7] [3]),
        .I4(\sig_dbeat_cntr_reg[7] [2]),
        .I5(\sig_dbeat_cntr_reg[5] ),
        .O(D[4]));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT3 #(
    .INIT(8'h14)) 
    \sig_dbeat_cntr[6]_i_1__0 
       (.I0(sig_next_sequential_reg_reg),
        .I1(\sig_dbeat_cntr_reg[7] [6]),
        .I2(\sig_dbeat_cntr_reg[6] ),
        .O(D[5]));
  LUT6 #(
    .INIT(64'hFFFFFFFF32222222)) 
    \sig_dbeat_cntr[7]_i_1__0 
       (.I0(sig_dqual_reg_empty),
        .I1(\sig_next_tag_reg[0]_i_4_n_0 ),
        .I2(sig_dqual_reg_empty_reg),
        .I3(sig_next_sequential_reg),
        .I4(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ),
        .I5(\sig_dbeat_cntr_reg[0] ),
        .O(E));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT4 #(
    .INIT(16'h4144)) 
    \sig_dbeat_cntr[7]_i_2__0 
       (.I0(sig_next_sequential_reg_reg),
        .I1(\sig_dbeat_cntr_reg[7] [7]),
        .I2(\sig_dbeat_cntr_reg[7] [6]),
        .I3(\sig_dbeat_cntr_reg[6] ),
        .O(D[6]));
  LUT6 #(
    .INIT(64'h74FF303074003030)) 
    sig_last_dbeat_i_1
       (.I0(sig_last_dbeat_reg),
        .I1(sig_next_sequential_reg_reg),
        .I2(sig_last_dbeat_reg_0),
        .I3(E),
        .I4(sig_mmap_rst_reg_n),
        .I5(sig_dqual_reg_empty_reg),
        .O(sig_mmap_rst_reg_n_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT3 #(
    .INIT(8'h20)) 
    sig_ld_new_cmd_reg_i_1__0
       (.I0(sig_mmap_rst_reg_n),
        .I1(sig_ld_new_cmd_reg),
        .I2(sig_next_sequential_reg_reg),
        .O(sig_mmap_rst_reg_n_reg));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT4 #(
    .INIT(16'h40FF)) 
    \sig_next_tag_reg[0]_i_1 
       (.I0(sig_next_sequential_reg_reg),
        .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ),
        .I2(m_axi_mm2s_rlast),
        .I3(sig_mmap_rst_reg_n),
        .O(SR));
  LUT5 #(
    .INIT(32'h00FF0080)) 
    \sig_next_tag_reg[0]_i_2 
       (.I0(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ),
        .I1(sig_next_sequential_reg),
        .I2(sig_dqual_reg_empty_reg),
        .I3(\sig_next_tag_reg[0]_i_4_n_0 ),
        .I4(sig_dqual_reg_empty),
        .O(sig_next_sequential_reg_reg));
  LUT5 #(
    .INIT(32'h000000D0)) 
    \sig_next_tag_reg[0]_i_3 
       (.I0(full),
        .I1(sig_dqual_reg_empty_reg_0),
        .I2(m_axi_mm2s_rvalid),
        .I3(sig_dqual_reg_empty_reg_1),
        .I4(sig_next_calc_error_reg_reg),
        .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ));
  LUT5 #(
    .INIT(32'hFFFFFFAE)) 
    \sig_next_tag_reg[0]_i_4 
       (.I0(\sig_next_tag_reg[0]_i_5_n_0 ),
        .I1(sig_rsc2stat_status_valid),
        .I2(sig_stat2rsc_status_ready),
        .I3(\USE_SRL_FIFO.sig_rd_empty ),
        .I4(sig_next_calc_error_reg),
        .O(\sig_next_tag_reg[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \sig_next_tag_reg[0]_i_5 
       (.I0(m_axi_mm2s_rready[2]),
        .I1(m_axi_mm2s_rready[1]),
        .I2(m_axi_mm2s_rready[0]),
        .O(\sig_next_tag_reg[0]_i_5_n_0 ));
endmodule

(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) 
module Loopback_axi_dma_1_0_cntr_incr_decr_addn_f_19
   (fifo_full_p1,
    Q,
    \USE_SRL_FIFO.sig_wr_fifo ,
    \INFERRED_GEN.cnt_i_reg[0]_0 ,
    m_axi_sg_bvalid,
    sig_inhibit_rdy_n,
    \INFERRED_GEN.cnt_i_reg[1]_0 ,
    \INFERRED_GEN.cnt_i_reg[1]_1 ,
    sig_stream_rst,
    m_axi_sg_aclk);
  output fifo_full_p1;
  output [2:0]Q;
  input \USE_SRL_FIFO.sig_wr_fifo ;
  input \INFERRED_GEN.cnt_i_reg[0]_0 ;
  input m_axi_sg_bvalid;
  input sig_inhibit_rdy_n;
  input \INFERRED_GEN.cnt_i_reg[1]_0 ;
  input \INFERRED_GEN.cnt_i_reg[1]_1 ;
  input sig_stream_rst;
  input m_axi_sg_aclk;

  wire \INFERRED_GEN.cnt_i_reg[0]_0 ;
  wire \INFERRED_GEN.cnt_i_reg[1]_0 ;
  wire \INFERRED_GEN.cnt_i_reg[1]_1 ;
  wire [2:0]Q;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire [2:0]addr_i_p1;
  wire fifo_full_p1;
  wire m_axi_sg_aclk;
  wire m_axi_sg_bvalid;
  wire sig_inhibit_rdy_n;
  wire sig_stream_rst;

  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT5 #(
    .INIT(32'h04020208)) 
    FIFO_Full_i_1
       (.I0(Q[1]),
        .I1(\USE_SRL_FIFO.sig_wr_fifo ),
        .I2(Q[2]),
        .I3(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .I4(Q[0]),
        .O(fifo_full_p1));
  LUT6 #(
    .INIT(64'hE1EEEEEE1E111111)) 
    \INFERRED_GEN.cnt_i[0]_i_1 
       (.I0(Q[2]),
        .I1(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .I2(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I3(sig_inhibit_rdy_n),
        .I4(m_axi_sg_bvalid),
        .I5(Q[0]),
        .O(addr_i_p1[0]));
  LUT6 #(
    .INIT(64'hFF0800F7F7FF0800)) 
    \INFERRED_GEN.cnt_i[1]_i_1 
       (.I0(m_axi_sg_bvalid),
        .I1(sig_inhibit_rdy_n),
        .I2(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\INFERRED_GEN.cnt_i_reg[1]_1 ),
        .O(addr_i_p1[1]));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT5 #(
    .INIT(32'h58F0F0F1)) 
    \INFERRED_GEN.cnt_i[2]_i_1 
       (.I0(Q[0]),
        .I1(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .I2(Q[2]),
        .I3(\USE_SRL_FIFO.sig_wr_fifo ),
        .I4(Q[1]),
        .O(addr_i_p1[2]));
  FDSE \INFERRED_GEN.cnt_i_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(addr_i_p1[0]),
        .Q(Q[0]),
        .S(sig_stream_rst));
  FDSE \INFERRED_GEN.cnt_i_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(addr_i_p1[1]),
        .Q(Q[1]),
        .S(sig_stream_rst));
  FDSE \INFERRED_GEN.cnt_i_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(addr_i_p1[2]),
        .Q(Q[2]),
        .S(sig_stream_rst));
endmodule

(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) 
module Loopback_axi_dma_1_0_cntr_incr_decr_addn_f_20
   (fifo_full_p1,
    Q,
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ,
    FIFO_Full_reg,
    \USE_SRL_FIFO.sig_wr_fifo ,
    D,
    \INFERRED_GEN.cnt_i_reg[1]_0 ,
    sig_coelsc_reg_empty,
    \INFERRED_GEN.cnt_i_reg[1]_1 ,
    sig_stream_rst,
    m_axi_sg_aclk);
  output fifo_full_p1;
  output [2:0]Q;
  output \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ;
  input FIFO_Full_reg;
  input \USE_SRL_FIFO.sig_wr_fifo ;
  input [0:0]D;
  input \INFERRED_GEN.cnt_i_reg[1]_0 ;
  input sig_coelsc_reg_empty;
  input [0:0]\INFERRED_GEN.cnt_i_reg[1]_1 ;
  input sig_stream_rst;
  input m_axi_sg_aclk;

  wire [0:0]D;
  wire FIFO_Full_reg;
  wire \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ;
  wire \INFERRED_GEN.cnt_i_reg[1]_0 ;
  wire [0:0]\INFERRED_GEN.cnt_i_reg[1]_1 ;
  wire [2:0]Q;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire [2:1]addr_i_p1;
  wire fifo_full_p1;
  wire m_axi_sg_aclk;
  wire sig_coelsc_reg_empty;
  wire sig_stream_rst;

  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT5 #(
    .INIT(32'h04101040)) 
    FIFO_Full_i_1__0
       (.I0(Q[2]),
        .I1(FIFO_Full_reg),
        .I2(Q[1]),
        .I3(\USE_SRL_FIFO.sig_wr_fifo ),
        .I4(Q[0]),
        .O(fifo_full_p1));
  LUT4 #(
    .INIT(16'h78E1)) 
    \INFERRED_GEN.cnt_i[1]_i_1__0 
       (.I0(\USE_SRL_FIFO.sig_wr_fifo ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .O(addr_i_p1[1]));
  LUT3 #(
    .INIT(8'h02)) 
    \INFERRED_GEN.cnt_i[1]_i_2__0 
       (.I0(sig_coelsc_reg_empty),
        .I1(Q[2]),
        .I2(\INFERRED_GEN.cnt_i_reg[1]_1 ),
        .O(\GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT5 #(
    .INIT(32'h7F7F8001)) 
    \INFERRED_GEN.cnt_i[2]_i_1__0 
       (.I0(Q[0]),
        .I1(\USE_SRL_FIFO.sig_wr_fifo ),
        .I2(Q[1]),
        .I3(FIFO_Full_reg),
        .I4(Q[2]),
        .O(addr_i_p1[2]));
  FDSE \INFERRED_GEN.cnt_i_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(D),
        .Q(Q[0]),
        .S(sig_stream_rst));
  FDSE \INFERRED_GEN.cnt_i_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(addr_i_p1[1]),
        .Q(Q[1]),
        .S(sig_stream_rst));
  FDSE \INFERRED_GEN.cnt_i_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(addr_i_p1[2]),
        .Q(Q[2]),
        .S(sig_stream_rst));
endmodule

(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) 
module Loopback_axi_dma_1_0_cntr_incr_decr_addn_f_4
   (fifo_full_p1,
    sig_halt_reg_reg,
    Q,
    sig_addr_reg_empty_reg,
    \USE_SRL_FIFO.sig_wr_fifo ,
    sig_mstr2addr_cmd_valid,
    \INFERRED_GEN.cnt_i_reg[1]_0 ,
    \INFERRED_GEN.cnt_i_reg[1]_1 ,
    sig_addr_reg_empty,
    sig_sf_allow_addr_req,
    sig_data2addr_stop_req,
    sig_mmap_rst_reg_n,
    SS,
    m_axi_mm2s_aclk);
  output fifo_full_p1;
  output sig_halt_reg_reg;
  output [1:0]Q;
  output sig_addr_reg_empty_reg;
  input \USE_SRL_FIFO.sig_wr_fifo ;
  input sig_mstr2addr_cmd_valid;
  input \INFERRED_GEN.cnt_i_reg[1]_0 ;
  input \INFERRED_GEN.cnt_i_reg[1]_1 ;
  input sig_addr_reg_empty;
  input sig_sf_allow_addr_req;
  input sig_data2addr_stop_req;
  input sig_mmap_rst_reg_n;
  input [0:0]SS;
  input m_axi_mm2s_aclk;

  wire \INFERRED_GEN.cnt_i_reg[1]_0 ;
  wire \INFERRED_GEN.cnt_i_reg[1]_1 ;
  wire [1:0]Q;
  wire [0:0]SS;
  wire \USE_SRL_FIFO.sig_rd_empty ;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire [2:0]addr_i_p1;
  wire fifo_full_p1;
  wire m_axi_mm2s_aclk;
  wire sig_addr_reg_empty;
  wire sig_addr_reg_empty_reg;
  wire sig_data2addr_stop_req;
  wire sig_halt_reg_reg;
  wire sig_mmap_rst_reg_n;
  wire sig_mstr2addr_cmd_valid;
  wire sig_sf_allow_addr_req;

  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT5 #(
    .INIT(32'h80008440)) 
    FIFO_Full_i_1__3
       (.I0(sig_halt_reg_reg),
        .I1(Q[1]),
        .I2(\USE_SRL_FIFO.sig_wr_fifo ),
        .I3(Q[0]),
        .I4(\USE_SRL_FIFO.sig_rd_empty ),
        .O(fifo_full_p1));
  LUT5 #(
    .INIT(32'h69666666)) 
    \INFERRED_GEN.cnt_i[0]_i_1__3 
       (.I0(sig_halt_reg_reg),
        .I1(Q[0]),
        .I2(\INFERRED_GEN.cnt_i_reg[1]_1 ),
        .I3(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I4(sig_mstr2addr_cmd_valid),
        .O(addr_i_p1[0]));
  LUT6 #(
    .INIT(64'hC6C6C6C69CC6C6C6)) 
    \INFERRED_GEN.cnt_i[1]_i_1__3 
       (.I0(sig_halt_reg_reg),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(sig_mstr2addr_cmd_valid),
        .I4(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I5(\INFERRED_GEN.cnt_i_reg[1]_1 ),
        .O(addr_i_p1[1]));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT5 #(
    .INIT(32'h00036AAA)) 
    \INFERRED_GEN.cnt_i[2]_i_1__3 
       (.I0(\USE_SRL_FIFO.sig_rd_empty ),
        .I1(Q[0]),
        .I2(\USE_SRL_FIFO.sig_wr_fifo ),
        .I3(Q[1]),
        .I4(sig_halt_reg_reg),
        .O(addr_i_p1[2]));
  FDSE \INFERRED_GEN.cnt_i_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(addr_i_p1[0]),
        .Q(Q[0]),
        .S(SS));
  FDSE \INFERRED_GEN.cnt_i_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(addr_i_p1[1]),
        .Q(Q[1]),
        .S(SS));
  FDSE \INFERRED_GEN.cnt_i_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(addr_i_p1[2]),
        .Q(\USE_SRL_FIFO.sig_rd_empty ),
        .S(SS));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    \sig_next_addr_reg[31]_i_2__1 
       (.I0(sig_data2addr_stop_req),
        .I1(sig_sf_allow_addr_req),
        .I2(\USE_SRL_FIFO.sig_rd_empty ),
        .I3(sig_addr_reg_empty),
        .O(sig_halt_reg_reg));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    sig_posted_to_axi_2_i_1__0
       (.I0(sig_addr_reg_empty),
        .I1(\USE_SRL_FIFO.sig_rd_empty ),
        .I2(sig_sf_allow_addr_req),
        .I3(sig_data2addr_stop_req),
        .I4(sig_mmap_rst_reg_n),
        .O(sig_addr_reg_empty_reg));
endmodule

(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) 
module Loopback_axi_dma_1_0_cntr_incr_decr_addn_f_5
   (fifo_full_p1,
    Q,
    sig_inhibit_rdy_n_reg,
    FIFO_Full_reg,
    \INFERRED_GEN.cnt_i_reg[2]_0 ,
    \INFERRED_GEN.cnt_i_reg[1]_0 ,
    \INFERRED_GEN.cnt_i_reg[0]_0 ,
    sig_mstr2sf_cmd_valid,
    \INFERRED_GEN.cnt_i_reg[0]_1 ,
    SS,
    m_axi_mm2s_aclk);
  output fifo_full_p1;
  output [0:0]Q;
  output sig_inhibit_rdy_n_reg;
  input FIFO_Full_reg;
  input \INFERRED_GEN.cnt_i_reg[2]_0 ;
  input \INFERRED_GEN.cnt_i_reg[1]_0 ;
  input \INFERRED_GEN.cnt_i_reg[0]_0 ;
  input sig_mstr2sf_cmd_valid;
  input \INFERRED_GEN.cnt_i_reg[0]_1 ;
  input [0:0]SS;
  input m_axi_mm2s_aclk;

  wire FIFO_Full_reg;
  wire \INFERRED_GEN.cnt_i_reg[0]_0 ;
  wire \INFERRED_GEN.cnt_i_reg[0]_1 ;
  wire \INFERRED_GEN.cnt_i_reg[1]_0 ;
  wire \INFERRED_GEN.cnt_i_reg[2]_0 ;
  wire \INFERRED_GEN.cnt_i_reg_n_0_[0] ;
  wire \INFERRED_GEN.cnt_i_reg_n_0_[1] ;
  wire [0:0]Q;
  wire [0:0]SS;
  wire [2:0]addr_i_p1;
  wire fifo_full_p1;
  wire m_axi_mm2s_aclk;
  wire sig_inhibit_rdy_n_reg;
  wire sig_mstr2sf_cmd_valid;

  LUT6 #(
    .INIT(64'h5104040000000000)) 
    FIFO_Full_i_1__2
       (.I0(Q),
        .I1(FIFO_Full_reg),
        .I2(\INFERRED_GEN.cnt_i_reg[2]_0 ),
        .I3(\INFERRED_GEN.cnt_i_reg_n_0_[0] ),
        .I4(sig_inhibit_rdy_n_reg),
        .I5(\INFERRED_GEN.cnt_i_reg_n_0_[1] ),
        .O(fifo_full_p1));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT5 #(
    .INIT(32'h9AAA6555)) 
    \INFERRED_GEN.cnt_i[0]_i_1__2 
       (.I0(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I1(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .I2(sig_mstr2sf_cmd_valid),
        .I3(\INFERRED_GEN.cnt_i_reg[0]_1 ),
        .I4(\INFERRED_GEN.cnt_i_reg_n_0_[0] ),
        .O(addr_i_p1[0]));
  LUT6 #(
    .INIT(64'hC9C9C9C96CC9C9C9)) 
    \INFERRED_GEN.cnt_i[1]_i_1__2 
       (.I0(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I1(\INFERRED_GEN.cnt_i_reg_n_0_[1] ),
        .I2(\INFERRED_GEN.cnt_i_reg_n_0_[0] ),
        .I3(\INFERRED_GEN.cnt_i_reg[0]_1 ),
        .I4(sig_mstr2sf_cmd_valid),
        .I5(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .O(addr_i_p1[1]));
  LUT6 #(
    .INIT(64'h04AAAAAAAAAAAAFB)) 
    \INFERRED_GEN.cnt_i[2]_i_1__2 
       (.I0(Q),
        .I1(FIFO_Full_reg),
        .I2(\INFERRED_GEN.cnt_i_reg[2]_0 ),
        .I3(\INFERRED_GEN.cnt_i_reg_n_0_[0] ),
        .I4(sig_inhibit_rdy_n_reg),
        .I5(\INFERRED_GEN.cnt_i_reg_n_0_[1] ),
        .O(addr_i_p1[2]));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \INFERRED_GEN.cnt_i[2]_i_3 
       (.I0(\INFERRED_GEN.cnt_i_reg[0]_1 ),
        .I1(sig_mstr2sf_cmd_valid),
        .I2(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .O(sig_inhibit_rdy_n_reg));
  FDSE \INFERRED_GEN.cnt_i_reg[0] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(addr_i_p1[0]),
        .Q(\INFERRED_GEN.cnt_i_reg_n_0_[0] ),
        .S(SS));
  FDSE \INFERRED_GEN.cnt_i_reg[1] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(addr_i_p1[1]),
        .Q(\INFERRED_GEN.cnt_i_reg_n_0_[1] ),
        .S(SS));
  FDSE \INFERRED_GEN.cnt_i_reg[2] 
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(addr_i_p1[2]),
        .Q(Q),
        .S(SS));
endmodule

(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) 
module Loopback_axi_dma_1_0_cntr_incr_decr_addn_f__parameterized0
   (fifo_full_p1,
    Q,
    \GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ,
    m_axis_mm2s_ftch_tvalid_new,
    mm2s_halt,
    \INFERRED_GEN.cnt_i_reg[1]_0 ,
    \INFERRED_GEN.cnt_i_reg[0]_0 ,
    sinit,
    m_axi_sg_aclk);
  output fifo_full_p1;
  output [3:0]Q;
  output \GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ;
  input m_axis_mm2s_ftch_tvalid_new;
  input mm2s_halt;
  input \INFERRED_GEN.cnt_i_reg[1]_0 ;
  input \INFERRED_GEN.cnt_i_reg[0]_0 ;
  input sinit;
  input m_axi_sg_aclk;

  wire FIFO_Full_i_2_n_0;
  wire \GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ;
  wire \INFERRED_GEN.cnt_i[4]_i_2_n_0 ;
  wire \INFERRED_GEN.cnt_i_reg[0]_0 ;
  wire \INFERRED_GEN.cnt_i_reg[1]_0 ;
  wire \INFERRED_GEN.cnt_i_reg_n_0_[4] ;
  wire [3:0]Q;
  wire [4:0]addr_i_p1;
  wire fifo_full_p1;
  wire m_axi_sg_aclk;
  wire m_axis_mm2s_ftch_tvalid_new;
  wire mm2s_halt;
  wire sinit;

  LUT5 #(
    .INIT(32'h0280A82A)) 
    FIFO_Full_i_1__4
       (.I0(FIFO_Full_i_2_n_0),
        .I1(\INFERRED_GEN.cnt_i[4]_i_2_n_0 ),
        .I2(Q[3]),
        .I3(\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ),
        .I4(\INFERRED_GEN.cnt_i_reg_n_0_[4] ),
        .O(fifo_full_p1));
  LUT6 #(
    .INIT(64'h8020200000000004)) 
    FIFO_Full_i_2
       (.I0(Q[3]),
        .I1(\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ),
        .I2(Q[1]),
        .I3(m_axis_mm2s_ftch_tvalid_new),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(FIFO_Full_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT5 #(
    .INIT(32'h04FBFB04)) 
    \INFERRED_GEN.cnt_i[0]_i_1__4 
       (.I0(mm2s_halt),
        .I1(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I2(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .I3(m_axis_mm2s_ftch_tvalid_new),
        .I4(Q[0]),
        .O(addr_i_p1[0]));
  LUT6 #(
    .INIT(64'h04FBFF00FF00FB04)) 
    \INFERRED_GEN.cnt_i[1]_i_1__4 
       (.I0(mm2s_halt),
        .I1(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I2(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .I3(Q[1]),
        .I4(m_axis_mm2s_ftch_tvalid_new),
        .I5(Q[0]),
        .O(addr_i_p1[1]));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT5 #(
    .INIT(32'hFE017F80)) 
    \INFERRED_GEN.cnt_i[2]_i_1__4 
       (.I0(m_axis_mm2s_ftch_tvalid_new),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ),
        .O(addr_i_p1[2]));
  LUT6 #(
    .INIT(64'h9AAAAAAAAAAAAAA6)) 
    \INFERRED_GEN.cnt_i[3]_i_1 
       (.I0(Q[3]),
        .I1(\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ),
        .I2(Q[1]),
        .I3(m_axis_mm2s_ftch_tvalid_new),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(addr_i_p1[3]));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \INFERRED_GEN.cnt_i[3]_i_2 
       (.I0(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .I1(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I2(mm2s_halt),
        .O(\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ));
  LUT6 #(
    .INIT(64'h5565AAAAAAAAAA9A)) 
    \INFERRED_GEN.cnt_i[4]_i_1 
       (.I0(\INFERRED_GEN.cnt_i_reg_n_0_[4] ),
        .I1(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .I2(\INFERRED_GEN.cnt_i_reg[1]_0 ),
        .I3(mm2s_halt),
        .I4(Q[3]),
        .I5(\INFERRED_GEN.cnt_i[4]_i_2_n_0 ),
        .O(addr_i_p1[4]));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT5 #(
    .INIT(32'hFF80FE00)) 
    \INFERRED_GEN.cnt_i[4]_i_2 
       (.I0(Q[1]),
        .I1(m_axis_mm2s_ftch_tvalid_new),
        .I2(Q[0]),
        .I3(\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ),
        .I4(Q[2]),
        .O(\INFERRED_GEN.cnt_i[4]_i_2_n_0 ));
  FDSE \INFERRED_GEN.cnt_i_reg[0] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(addr_i_p1[0]),
        .Q(Q[0]),
        .S(sinit));
  FDSE \INFERRED_GEN.cnt_i_reg[1] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(addr_i_p1[1]),
        .Q(Q[1]),
        .S(sinit));
  FDSE \INFERRED_GEN.cnt_i_reg[2] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(addr_i_p1[2]),
        .Q(Q[2]),
        .S(sinit));
  FDSE \INFERRED_GEN.cnt_i_reg[3] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(addr_i_p1[3]),
        .Q(Q[3]),
        .S(sinit));
  FDSE \INFERRED_GEN.cnt_i_reg[4] 
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(addr_i_p1[4]),
        .Q(\INFERRED_GEN.cnt_i_reg_n_0_[4] ),
        .S(sinit));
endmodule

module Loopback_axi_dma_1_0_dynshreg_f
   (sel,
    sig_coelsc_decerr_reg0,
    out,
    sig_coelsc_slverr_reg0,
    FIFO_Full_reg,
    sig_inhibit_rdy_n,
    m_axi_sg_bvalid,
    D,
    \GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ,
    m_axi_sg_bresp,
    addr,
    m_axi_sg_aclk);
  output sel;
  output sig_coelsc_decerr_reg0;
  output [0:0]out;
  output sig_coelsc_slverr_reg0;
  input FIFO_Full_reg;
  input sig_inhibit_rdy_n;
  input m_axi_sg_bvalid;
  input [1:0]D;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ;
  input [1:0]m_axi_sg_bresp;
  input [0:1]addr;
  input m_axi_sg_aclk;

  wire [1:0]D;
  wire FIFO_Full_reg;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ;
  wire [0:1]addr;
  wire m_axi_sg_aclk;
  wire [1:0]m_axi_sg_bresp;
  wire m_axi_sg_bvalid;
  wire [0:0]out;
  wire sel;
  wire sig_coelsc_decerr_reg0;
  wire sig_coelsc_slverr_reg0;
  wire sig_inhibit_rdy_n;
  wire [0:0]sig_wresp_sfifo_out;

  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'h00EA)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_decerr_reg_i_1 
       (.I0(D[0]),
        .I1(sig_wresp_sfifo_out),
        .I2(out),
        .I3(\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ),
        .O(sig_coelsc_decerr_reg0));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'h00DC)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_i_1 
       (.I0(sig_wresp_sfifo_out),
        .I1(D[1]),
        .I2(out),
        .I3(\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ),
        .O(sig_coelsc_slverr_reg0));
  (* srl_bus_name = "U0/\\GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[2] " *) 
  (* srl_name = "U0/\\GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[2][0]_srl3 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[2][0]_srl3 
       (.A0(addr[1]),
        .A1(addr[0]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(sel),
        .CLK(m_axi_sg_aclk),
        .D(m_axi_sg_bresp[1]),
        .Q(out));
  (* srl_bus_name = "U0/\\GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[2] " *) 
  (* srl_name = "U0/\\GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[2][1]_srl3 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[2][1]_srl3 
       (.A0(addr[1]),
        .A1(addr[0]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(sel),
        .CLK(m_axi_sg_aclk),
        .D(m_axi_sg_bresp[0]),
        .Q(sig_wresp_sfifo_out));
  LUT3 #(
    .INIT(8'h40)) 
    \INFERRED_GEN.data_reg[2][1]_srl3_i_1 
       (.I0(FIFO_Full_reg),
        .I1(sig_inhibit_rdy_n),
        .I2(m_axi_sg_bvalid),
        .O(sel));
endmodule

(* ORIG_REF_NAME = "dynshreg_f" *) 
module Loopback_axi_dma_1_0_dynshreg_f__parameterized0
   (sig_coelsc_interr_reg0,
    out,
    \INFERRED_GEN.cnt_i_reg[0] ,
    \INFERRED_GEN.cnt_i_reg[2] ,
    E,
    \sig_wdc_statcnt_reg[2] ,
    sig_push_coelsc_reg,
    \INFERRED_GEN.cnt_i_reg[2]_0 ,
    sig_data2wsc_cmd_cmplt_reg,
    \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ,
    D,
    Q,
    sig_push_to_wsc,
    \INFERRED_GEN.cnt_i_reg[0]_0 ,
    \INFERRED_GEN.cnt_i_reg[0]_1 ,
    sig_tlast_err_stop,
    \sig_wdc_statcnt_reg[1] ,
    \USE_SRL_FIFO.sig_wr_fifo ,
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ,
    sig_coelsc_reg_empty,
    \GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ,
    in,
    m_axi_sg_aclk);
  output sig_coelsc_interr_reg0;
  output [1:0]out;
  output [0:0]\INFERRED_GEN.cnt_i_reg[0] ;
  output \INFERRED_GEN.cnt_i_reg[2] ;
  output [0:0]E;
  output [1:0]\sig_wdc_statcnt_reg[2] ;
  output sig_push_coelsc_reg;
  output \INFERRED_GEN.cnt_i_reg[2]_0 ;
  output sig_data2wsc_cmd_cmplt_reg;
  output \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ;
  input [2:0]D;
  input [2:0]Q;
  input sig_push_to_wsc;
  input \INFERRED_GEN.cnt_i_reg[0]_0 ;
  input \INFERRED_GEN.cnt_i_reg[0]_1 ;
  input sig_tlast_err_stop;
  input [2:0]\sig_wdc_statcnt_reg[1] ;
  input \USE_SRL_FIFO.sig_wr_fifo ;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ;
  input sig_coelsc_reg_empty;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ;
  input [2:0]in;
  input m_axi_sg_aclk;

  wire [2:0]D;
  wire [0:0]E;
  wire \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ;
  wire [1:1]\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out ;
  wire [0:0]\INFERRED_GEN.cnt_i_reg[0] ;
  wire \INFERRED_GEN.cnt_i_reg[0]_0 ;
  wire \INFERRED_GEN.cnt_i_reg[0]_1 ;
  wire \INFERRED_GEN.cnt_i_reg[2] ;
  wire \INFERRED_GEN.cnt_i_reg[2]_0 ;
  wire [2:0]Q;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire [2:0]in;
  wire m_axi_sg_aclk;
  wire [1:0]out;
  wire sig_coelsc_interr_reg0;
  wire sig_coelsc_reg_empty;
  wire sig_data2wsc_cmd_cmplt_reg;
  wire sig_push_coelsc_reg;
  wire sig_push_to_wsc;
  wire sig_tlast_err_stop;
  wire \sig_wdc_statcnt[2]_i_3_n_0 ;
  wire [2:0]\sig_wdc_statcnt_reg[1] ;
  wire [1:0]\sig_wdc_statcnt_reg[2] ;

  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT5 #(
    .INIT(32'h0000FD00)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_i_2 
       (.I0(\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .I1(\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out ),
        .I2(out[1]),
        .I3(sig_coelsc_reg_empty),
        .I4(Q[2]),
        .O(sig_push_coelsc_reg));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_i_3 
       (.I0(D[0]),
        .I1(\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out ),
        .I2(out[1]),
        .O(sig_coelsc_interr_reg0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_i_1 
       (.I0(out[1]),
        .I1(\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out ),
        .I2(D[0]),
        .I3(\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ),
        .I4(D[1]),
        .I5(D[2]),
        .O(\GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ));
  LUT1 #(
    .INIT(2'h1)) 
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_i_1 
       (.I0(out[0]),
        .O(sig_data2wsc_cmd_cmplt_reg));
  LUT6 #(
    .INIT(64'h9999999999996999)) 
    \INFERRED_GEN.cnt_i[0]_i_1__0 
       (.I0(\INFERRED_GEN.cnt_i_reg[2] ),
        .I1(Q[0]),
        .I2(sig_push_to_wsc),
        .I3(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .I4(\INFERRED_GEN.cnt_i_reg[0]_1 ),
        .I5(sig_tlast_err_stop),
        .O(\INFERRED_GEN.cnt_i_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT5 #(
    .INIT(32'hBBBFBBBB)) 
    \INFERRED_GEN.cnt_i[2]_i_2 
       (.I0(Q[2]),
        .I1(sig_coelsc_reg_empty),
        .I2(out[1]),
        .I3(\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out ),
        .I4(\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .O(\INFERRED_GEN.cnt_i_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT4 #(
    .INIT(16'h02FF)) 
    \INFERRED_GEN.cnt_i[2]_i_2__0 
       (.I0(\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .I1(\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out ),
        .I2(out[1]),
        .I3(sig_coelsc_reg_empty),
        .O(\INFERRED_GEN.cnt_i_reg[2]_0 ));
  (* srl_bus_name = "U0/\\GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[2] " *) 
  (* srl_name = "U0/\\GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[2][4]_srl3 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[2][4]_srl3 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_sg_aclk),
        .D(in[2]),
        .Q(out[1]));
  (* srl_bus_name = "U0/\\GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[2] " *) 
  (* srl_name = "U0/\\GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[2][5]_srl3 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[2][5]_srl3 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_sg_aclk),
        .D(in[1]),
        .Q(\GEN_OMIT_INDET_BTT.sig_dcntl_sfifo_out ));
  (* srl_bus_name = "U0/\\GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[2] " *) 
  (* srl_name = "U0/\\GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[2][6]_srl3 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[2][6]_srl3 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_sg_aclk),
        .D(in[0]),
        .Q(out[0]));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'hD33C)) 
    \sig_wdc_statcnt[1]_i_1 
       (.I0(\sig_wdc_statcnt_reg[1] [2]),
        .I1(\sig_wdc_statcnt[2]_i_3_n_0 ),
        .I2(\sig_wdc_statcnt_reg[1] [0]),
        .I3(\sig_wdc_statcnt_reg[1] [1]),
        .O(\sig_wdc_statcnt_reg[2] [0]));
  LUT5 #(
    .INIT(32'h83C3C3C2)) 
    \sig_wdc_statcnt[2]_i_1 
       (.I0(\sig_wdc_statcnt_reg[1] [2]),
        .I1(\USE_SRL_FIFO.sig_wr_fifo ),
        .I2(\INFERRED_GEN.cnt_i_reg[2] ),
        .I3(\sig_wdc_statcnt_reg[1] [1]),
        .I4(\sig_wdc_statcnt_reg[1] [0]),
        .O(E));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'h8CC6)) 
    \sig_wdc_statcnt[2]_i_2 
       (.I0(\sig_wdc_statcnt[2]_i_3_n_0 ),
        .I1(\sig_wdc_statcnt_reg[1] [2]),
        .I2(\sig_wdc_statcnt_reg[1] [1]),
        .I3(\sig_wdc_statcnt_reg[1] [0]),
        .O(\sig_wdc_statcnt_reg[2] [1]));
  LUT5 #(
    .INIT(32'hFDFFFFFF)) 
    \sig_wdc_statcnt[2]_i_3 
       (.I0(\INFERRED_GEN.cnt_i_reg[2] ),
        .I1(sig_tlast_err_stop),
        .I2(\INFERRED_GEN.cnt_i_reg[0]_1 ),
        .I3(\INFERRED_GEN.cnt_i_reg[0]_0 ),
        .I4(sig_push_to_wsc),
        .O(\sig_wdc_statcnt[2]_i_3_n_0 ));
endmodule

(* ORIG_REF_NAME = "dynshreg_f" *) 
module Loopback_axi_dma_1_0_dynshreg_f__parameterized1
   (out,
    m_axis_mm2s_ftch_tvalid_new,
    \updt_desc_reg2_reg[25] ,
    Q,
    m_axi_sg_aclk);
  output [25:0]out;
  input m_axis_mm2s_ftch_tvalid_new;
  input [25:0]\updt_desc_reg2_reg[25] ;
  input [3:0]Q;
  input m_axi_sg_aclk;

  wire [3:0]Q;
  wire m_axi_sg_aclk;
  wire m_axis_mm2s_ftch_tvalid_new;
  wire [25:0]out;
  wire [25:0]\updt_desc_reg2_reg[25] ;

  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][0]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [25]),
        .Q(out[25]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][10]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][10]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [15]),
        .Q(out[15]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][11]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][11]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [14]),
        .Q(out[14]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][12]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][12]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [13]),
        .Q(out[13]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][13]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][13]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [12]),
        .Q(out[12]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][14]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][14]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [11]),
        .Q(out[11]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][15]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][15]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [10]),
        .Q(out[10]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][16]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][16]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [9]),
        .Q(out[9]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][17]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][17]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [8]),
        .Q(out[8]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][18]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][18]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [7]),
        .Q(out[7]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][19]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][19]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [6]),
        .Q(out[6]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][1]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [24]),
        .Q(out[24]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][20]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][20]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [5]),
        .Q(out[5]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][21]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][21]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [4]),
        .Q(out[4]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][22]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][22]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [3]),
        .Q(out[3]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][23]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][23]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [2]),
        .Q(out[2]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][24]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][24]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [1]),
        .Q(out[1]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][25]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][25]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [0]),
        .Q(out[0]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][2]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [23]),
        .Q(out[23]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][3]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [22]),
        .Q(out[22]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][4]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [21]),
        .Q(out[21]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][5]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [20]),
        .Q(out[20]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][6]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [19]),
        .Q(out[19]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][7]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [18]),
        .Q(out[18]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][8]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][8]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [17]),
        .Q(out[17]));
  (* srl_bus_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) 
  (* srl_name = "U0/\\INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][9]_srl16 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[15][9]_srl16 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(m_axis_mm2s_ftch_tvalid_new),
        .CLK(m_axi_sg_aclk),
        .D(\updt_desc_reg2_reg[25] [16]),
        .Q(out[16]));
endmodule

(* ORIG_REF_NAME = "dynshreg_f" *) 
module Loopback_axi_dma_1_0_dynshreg_f__parameterized2
   (\USE_SRL_FIFO.sig_wr_fifo ,
    sig_calc_error_reg_reg,
    out,
    sig_mstr2addr_cmd_valid,
    sig_calc_error_reg_reg_0,
    sig_calc_error_reg_reg_1,
    in,
    Q,
    m_axi_mm2s_aclk);
  output \USE_SRL_FIFO.sig_wr_fifo ;
  output sig_calc_error_reg_reg;
  output [38:0]out;
  input sig_mstr2addr_cmd_valid;
  input sig_calc_error_reg_reg_0;
  input sig_calc_error_reg_reg_1;
  input [37:0]in;
  input [1:0]Q;
  input m_axi_mm2s_aclk;

  wire [1:0]Q;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire [37:0]in;
  wire m_axi_mm2s_aclk;
  wire [38:0]out;
  wire sig_calc_error_reg_reg;
  wire sig_calc_error_reg_reg_0;
  wire sig_calc_error_reg_reg_1;
  wire sig_mstr2addr_cmd_valid;

  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][11]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[36]),
        .Q(out[37]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][13]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(1'b1),
        .Q(out[36]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][19]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[35]),
        .Q(out[35]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][20]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[34]),
        .Q(out[34]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][21]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[33]),
        .Q(out[33]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][22]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[32]),
        .Q(out[32]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][23]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[31]),
        .Q(out[31]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][24]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][24]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[30]),
        .Q(out[30]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][25]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[29]),
        .Q(out[29]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][26]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][26]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[28]),
        .Q(out[28]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][27]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[27]),
        .Q(out[27]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][28]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][28]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[26]),
        .Q(out[26]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][29]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][29]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[25]),
        .Q(out[25]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][30]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[24]),
        .Q(out[24]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][31]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][31]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[23]),
        .Q(out[23]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][32]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[22]),
        .Q(out[22]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][33]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[21]),
        .Q(out[21]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][34]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[20]),
        .Q(out[20]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][35]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[19]),
        .Q(out[19]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][36]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[18]),
        .Q(out[18]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][37]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[17]),
        .Q(out[17]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][38]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[16]),
        .Q(out[16]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][39]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[15]),
        .Q(out[15]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][40]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][40]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[14]),
        .Q(out[14]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][41]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][41]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[13]),
        .Q(out[13]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][42]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][42]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[12]),
        .Q(out[12]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][43]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][43]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[11]),
        .Q(out[11]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][44]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[10]),
        .Q(out[10]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][45]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[9]),
        .Q(out[9]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][46]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][46]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[8]),
        .Q(out[8]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][47]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[7]),
        .Q(out[7]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][48]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][48]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[6]),
        .Q(out[6]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][49]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][49]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[5]),
        .Q(out[5]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][50]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[4]),
        .Q(out[4]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][51]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][51]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[3]),
        .Q(out[3]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][52]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][52]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[2]),
        .Q(out[2]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][53]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][53]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[1]),
        .Q(out[1]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][54]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][54]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[0]),
        .Q(out[0]));
  LUT3 #(
    .INIT(8'h08)) 
    \INFERRED_GEN.data_reg[3][54]_srl4_i_1 
       (.I0(sig_mstr2addr_cmd_valid),
        .I1(sig_calc_error_reg_reg_0),
        .I2(sig_calc_error_reg_reg_1),
        .O(\USE_SRL_FIFO.sig_wr_fifo ));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][8]_srl4 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[37]),
        .Q(out[38]));
  LUT1 #(
    .INIT(2'h1)) 
    sig_addr_valid_reg_i_1__1
       (.I0(out[38]),
        .O(sig_calc_error_reg_reg));
endmodule

(* ORIG_REF_NAME = "dynshreg_f" *) 
module Loopback_axi_dma_1_0_dynshreg_f__parameterized3
   (sig_mmap_rst_reg_n_reg,
    \INFERRED_GEN.cnt_i_reg[0] ,
    \USE_SRL_FIFO.sig_wr_fifo ,
    D,
    out,
    sig_mmap_rst_reg_n,
    sig_first_dbeat_reg,
    sig_first_dbeat_reg_0,
    \sig_dbeat_cntr_reg[0] ,
    sig_mstr2data_cmd_valid,
    sig_next_calc_error_reg_reg,
    sig_next_calc_error_reg_reg_0,
    Q,
    in,
    sig_next_calc_error_reg_reg_1,
    m_axi_mm2s_aclk);
  output sig_mmap_rst_reg_n_reg;
  output \INFERRED_GEN.cnt_i_reg[0] ;
  output \USE_SRL_FIFO.sig_wr_fifo ;
  output [0:0]D;
  output [15:0]out;
  input sig_mmap_rst_reg_n;
  input sig_first_dbeat_reg;
  input sig_first_dbeat_reg_0;
  input \sig_dbeat_cntr_reg[0] ;
  input sig_mstr2data_cmd_valid;
  input sig_next_calc_error_reg_reg;
  input sig_next_calc_error_reg_reg_0;
  input [0:0]Q;
  input [16:0]in;
  input [1:0]sig_next_calc_error_reg_reg_1;
  input m_axi_mm2s_aclk;

  wire [0:0]D;
  wire \INFERRED_GEN.cnt_i_reg[0] ;
  wire [0:0]Q;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire [16:0]in;
  wire m_axi_mm2s_aclk;
  wire [15:0]out;
  wire [6:6]sig_cmd_fifo_data_out;
  wire \sig_dbeat_cntr_reg[0] ;
  wire sig_first_dbeat_reg;
  wire sig_first_dbeat_reg_0;
  wire sig_mmap_rst_reg_n;
  wire sig_mmap_rst_reg_n_reg;
  wire sig_mstr2data_cmd_valid;
  wire sig_next_calc_error_reg_reg;
  wire sig_next_calc_error_reg_reg_0;
  wire [1:0]sig_next_calc_error_reg_reg_1;

  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][10]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[9]),
        .Q(out[8]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][11]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[8]),
        .Q(out[7]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][12]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[7]),
        .Q(out[6]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][13]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[6]),
        .Q(out[5]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][14]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[5]),
        .Q(out[4]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][19]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[4]),
        .Q(out[3]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][20]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[3]),
        .Q(out[2]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][21]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[2]),
        .Q(out[1]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][22]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[1]),
        .Q(sig_cmd_fifo_data_out));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][28]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][28]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[0]),
        .Q(out[0]));
  LUT3 #(
    .INIT(8'h08)) 
    \INFERRED_GEN.data_reg[3][28]_srl4_i_1 
       (.I0(sig_mstr2data_cmd_valid),
        .I1(sig_next_calc_error_reg_reg),
        .I2(sig_next_calc_error_reg_reg_0),
        .O(\USE_SRL_FIFO.sig_wr_fifo ));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][2]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][2]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[16]),
        .Q(out[15]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][3]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][3]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[15]),
        .Q(out[14]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][4]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[14]),
        .Q(out[13]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][5]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[13]),
        .Q(out[12]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][7]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[12]),
        .Q(out[11]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][8]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[11]),
        .Q(out[10]));
  (* srl_bus_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) 
  (* srl_name = "U0/\\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \INFERRED_GEN.data_reg[3][9]_srl4 
       (.A0(sig_next_calc_error_reg_reg_1[0]),
        .A1(sig_next_calc_error_reg_reg_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\USE_SRL_FIFO.sig_wr_fifo ),
        .CLK(m_axi_mm2s_aclk),
        .D(in[10]),
        .Q(out[9]));
  LUT3 #(
    .INIT(8'h8B)) 
    \sig_dbeat_cntr[0]_i_1__0 
       (.I0(sig_cmd_fifo_data_out),
        .I1(\sig_dbeat_cntr_reg[0] ),
        .I2(Q),
        .O(D));
  LUT5 #(
    .INIT(32'h888800A0)) 
    sig_first_dbeat_i_1
       (.I0(sig_mmap_rst_reg_n),
        .I1(\INFERRED_GEN.cnt_i_reg[0] ),
        .I2(sig_first_dbeat_reg),
        .I3(sig_first_dbeat_reg_0),
        .I4(\sig_dbeat_cntr_reg[0] ),
        .O(sig_mmap_rst_reg_n_reg));
  LUT4 #(
    .INIT(16'hFFFE)) 
    sig_last_dbeat_i_2
       (.I0(out[2]),
        .I1(out[1]),
        .I2(out[3]),
        .I3(sig_cmd_fifo_data_out),
        .O(\INFERRED_GEN.cnt_i_reg[0] ));
endmodule

module Loopback_axi_dma_1_0_srl_fifo_f
   (Q,
    m_axi_sg_bready,
    sig_coelsc_decerr_reg0,
    out,
    sig_coelsc_slverr_reg0,
    sig_stream_rst,
    m_axi_sg_aclk,
    \INFERRED_GEN.cnt_i_reg[0] ,
    m_axi_sg_bvalid,
    sig_inhibit_rdy_n,
    \INFERRED_GEN.cnt_i_reg[1] ,
    D,
    \GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ,
    m_axi_sg_bresp);
  output [0:0]Q;
  output m_axi_sg_bready;
  output sig_coelsc_decerr_reg0;
  output [0:0]out;
  output sig_coelsc_slverr_reg0;
  input sig_stream_rst;
  input m_axi_sg_aclk;
  input \INFERRED_GEN.cnt_i_reg[0] ;
  input m_axi_sg_bvalid;
  input sig_inhibit_rdy_n;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input [1:0]D;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ;
  input [1:0]m_axi_sg_bresp;

  wire [1:0]D;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ;
  wire \INFERRED_GEN.cnt_i_reg[0] ;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire [0:0]Q;
  wire m_axi_sg_aclk;
  wire m_axi_sg_bready;
  wire [1:0]m_axi_sg_bresp;
  wire m_axi_sg_bvalid;
  wire [0:0]out;
  wire sig_coelsc_decerr_reg0;
  wire sig_coelsc_slverr_reg0;
  wire sig_inhibit_rdy_n;
  wire sig_stream_rst;

  Loopback_axi_dma_1_0_srl_fifo_rbu_f I_SRL_FIFO_RBU_F
       (.D(D),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ),
        .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ),
        .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ),
        .Q(Q),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_bready(m_axi_sg_bready),
        .m_axi_sg_bresp(m_axi_sg_bresp),
        .m_axi_sg_bvalid(m_axi_sg_bvalid),
        .out(out),
        .sig_coelsc_decerr_reg0(sig_coelsc_decerr_reg0),
        .sig_coelsc_slverr_reg0(sig_coelsc_slverr_reg0),
        .sig_inhibit_rdy_n(sig_inhibit_rdy_n),
        .sig_stream_rst(sig_stream_rst));
endmodule

(* ORIG_REF_NAME = "srl_fifo_f" *) 
module Loopback_axi_dma_1_0_srl_fifo_f__parameterized0
   (FIFO_Full_reg,
    sig_coelsc_interr_reg0,
    out,
    \INFERRED_GEN.cnt_i_reg[2] ,
    E,
    \sig_wdc_statcnt_reg[2] ,
    sig_push_coelsc_reg,
    FIFO_Full_reg_0,
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ,
    sig_data2wsc_cmd_cmplt_reg,
    \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ,
    sig_stream_rst,
    m_axi_sg_aclk,
    D,
    \USE_SRL_FIFO.sig_wr_fifo ,
    sig_push_to_wsc,
    \INFERRED_GEN.cnt_i_reg[0] ,
    sig_tlast_err_stop,
    Q,
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ,
    sig_coelsc_reg_empty,
    \GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ,
    in);
  output FIFO_Full_reg;
  output sig_coelsc_interr_reg0;
  output [1:0]out;
  output \INFERRED_GEN.cnt_i_reg[2] ;
  output [0:0]E;
  output [1:0]\sig_wdc_statcnt_reg[2] ;
  output sig_push_coelsc_reg;
  output FIFO_Full_reg_0;
  output \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ;
  output sig_data2wsc_cmd_cmplt_reg;
  output \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ;
  input sig_stream_rst;
  input m_axi_sg_aclk;
  input [2:0]D;
  input \USE_SRL_FIFO.sig_wr_fifo ;
  input sig_push_to_wsc;
  input \INFERRED_GEN.cnt_i_reg[0] ;
  input sig_tlast_err_stop;
  input [2:0]Q;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ;
  input sig_coelsc_reg_empty;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ;
  input [2:0]in;

  wire [2:0]D;
  wire [0:0]E;
  wire FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ;
  wire \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ;
  wire \INFERRED_GEN.cnt_i_reg[0] ;
  wire \INFERRED_GEN.cnt_i_reg[2] ;
  wire [2:0]Q;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire [2:0]in;
  wire m_axi_sg_aclk;
  wire [1:0]out;
  wire sig_coelsc_interr_reg0;
  wire sig_coelsc_reg_empty;
  wire sig_data2wsc_cmd_cmplt_reg;
  wire sig_push_coelsc_reg;
  wire sig_push_to_wsc;
  wire sig_stream_rst;
  wire sig_tlast_err_stop;
  wire [1:0]\sig_wdc_statcnt_reg[2] ;

  Loopback_axi_dma_1_0_srl_fifo_rbu_f__parameterized0 I_SRL_FIFO_RBU_F
       (.D(D),
        .E(E),
        .FIFO_Full_reg_0(FIFO_Full_reg),
        .FIFO_Full_reg_1(FIFO_Full_reg_0),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ),
        .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ),
        .Q(Q),
        .\USE_SRL_FIFO.sig_wr_fifo (\USE_SRL_FIFO.sig_wr_fifo ),
        .in(in),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .out(out),
        .sig_coelsc_interr_reg0(sig_coelsc_interr_reg0),
        .sig_coelsc_reg_empty(sig_coelsc_reg_empty),
        .sig_data2wsc_cmd_cmplt_reg(sig_data2wsc_cmd_cmplt_reg),
        .sig_push_coelsc_reg(sig_push_coelsc_reg),
        .sig_push_to_wsc(sig_push_to_wsc),
        .sig_stream_rst(sig_stream_rst),
        .sig_tlast_err_stop(sig_tlast_err_stop),
        .\sig_wdc_statcnt_reg[2] (\sig_wdc_statcnt_reg[2] ));
endmodule

(* ORIG_REF_NAME = "srl_fifo_f" *) 
module Loopback_axi_dma_1_0_srl_fifo_f__parameterized1
   (queue_empty_new0,
    FIFO_Full_reg,
    D,
    write_cmnd_cmb,
    FIFO_Full_reg_0,
    updt_data_reg,
    sts_received_re,
    out,
    sinit,
    m_axi_sg_aclk,
    \GEN_MM2S.queue_empty_new_reg ,
    \GEN_MM2S.queue_dout_new_reg[90] ,
    \GEN_MM2S.queue_dout_new_reg[90]_0 ,
    Q,
    \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ,
    ch1_ftch_queue_empty,
    m_axis_mm2s_ftch_tvalid_new,
    mm2s_halt,
    \INFERRED_GEN.cnt_i_reg[1] ,
    \INFERRED_GEN.cnt_i_reg[0] ,
    \updt_desc_reg2_reg[25] );
  output queue_empty_new0;
  output [0:0]FIFO_Full_reg;
  output [0:0]D;
  output write_cmnd_cmb;
  output FIFO_Full_reg_0;
  output updt_data_reg;
  output sts_received_re;
  output [25:0]out;
  input sinit;
  input m_axi_sg_aclk;
  input [0:0]\GEN_MM2S.queue_empty_new_reg ;
  input \GEN_MM2S.queue_dout_new_reg[90] ;
  input \GEN_MM2S.queue_dout_new_reg[90]_0 ;
  input [1:0]Q;
  input \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ;
  input ch1_ftch_queue_empty;
  input m_axis_mm2s_ftch_tvalid_new;
  input mm2s_halt;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input \INFERRED_GEN.cnt_i_reg[0] ;
  input [25:0]\updt_desc_reg2_reg[25] ;

  wire [0:0]D;
  wire [0:0]FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ;
  wire \GEN_MM2S.queue_dout_new_reg[90] ;
  wire \GEN_MM2S.queue_dout_new_reg[90]_0 ;
  wire [0:0]\GEN_MM2S.queue_empty_new_reg ;
  wire \INFERRED_GEN.cnt_i_reg[0] ;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire [1:0]Q;
  wire ch1_ftch_queue_empty;
  wire m_axi_sg_aclk;
  wire m_axis_mm2s_ftch_tvalid_new;
  wire mm2s_halt;
  wire [25:0]out;
  wire queue_empty_new0;
  wire sinit;
  wire sts_received_re;
  wire updt_data_reg;
  wire [25:0]\updt_desc_reg2_reg[25] ;
  wire write_cmnd_cmb;

  Loopback_axi_dma_1_0_srl_fifo_rbu_f__parameterized1 I_SRL_FIFO_RBU_F
       (.D(D),
        .FIFO_Full_reg_0(FIFO_Full_reg),
        .FIFO_Full_reg_1(FIFO_Full_reg_0),
        .\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg (\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ),
        .\GEN_MM2S.queue_dout_new_reg[90] (\GEN_MM2S.queue_dout_new_reg[90] ),
        .\GEN_MM2S.queue_dout_new_reg[90]_0 (\GEN_MM2S.queue_dout_new_reg[90]_0 ),
        .\GEN_MM2S.queue_empty_new_reg (\GEN_MM2S.queue_empty_new_reg ),
        .\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg (sts_received_re),
        .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ),
        .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ),
        .Q(Q),
        .ch1_ftch_queue_empty(ch1_ftch_queue_empty),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_mm2s_ftch_tvalid_new(m_axis_mm2s_ftch_tvalid_new),
        .mm2s_halt(mm2s_halt),
        .out(out),
        .queue_empty_new0(queue_empty_new0),
        .sinit(sinit),
        .updt_data_reg(updt_data_reg),
        .\updt_desc_reg2_reg[25] (\updt_desc_reg2_reg[25] ),
        .write_cmnd_cmb(write_cmnd_cmb));
endmodule

(* ORIG_REF_NAME = "srl_fifo_f" *) 
module Loopback_axi_dma_1_0_srl_fifo_f__parameterized2
   (FIFO_Full_reg,
    sig_halt_reg_reg,
    FIFO_Full_reg_0,
    sig_addr_reg_empty_reg,
    sig_calc_error_reg_reg,
    out,
    SS,
    m_axi_mm2s_aclk,
    sig_mstr2addr_cmd_valid,
    \INFERRED_GEN.cnt_i_reg[1] ,
    sig_addr_reg_empty,
    sig_sf_allow_addr_req,
    sig_data2addr_stop_req,
    sig_mmap_rst_reg_n,
    in);
  output FIFO_Full_reg;
  output sig_halt_reg_reg;
  output FIFO_Full_reg_0;
  output sig_addr_reg_empty_reg;
  output sig_calc_error_reg_reg;
  output [38:0]out;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input sig_mstr2addr_cmd_valid;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input sig_addr_reg_empty;
  input sig_sf_allow_addr_req;
  input sig_data2addr_stop_req;
  input sig_mmap_rst_reg_n;
  input [37:0]in;

  wire FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire [0:0]SS;
  wire [37:0]in;
  wire m_axi_mm2s_aclk;
  wire [38:0]out;
  wire sig_addr_reg_empty;
  wire sig_addr_reg_empty_reg;
  wire sig_calc_error_reg_reg;
  wire sig_data2addr_stop_req;
  wire sig_halt_reg_reg;
  wire sig_mmap_rst_reg_n;
  wire sig_mstr2addr_cmd_valid;
  wire sig_sf_allow_addr_req;

  Loopback_axi_dma_1_0_srl_fifo_rbu_f__parameterized2 I_SRL_FIFO_RBU_F
       (.FIFO_Full_reg_0(FIFO_Full_reg),
        .FIFO_Full_reg_1(FIFO_Full_reg_0),
        .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ),
        .SS(SS),
        .in(in),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .out(out),
        .sig_addr_reg_empty(sig_addr_reg_empty),
        .sig_addr_reg_empty_reg(sig_addr_reg_empty_reg),
        .sig_calc_error_reg_reg(sig_calc_error_reg_reg),
        .sig_data2addr_stop_req(sig_data2addr_stop_req),
        .sig_halt_reg_reg(sig_halt_reg_reg),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid),
        .sig_sf_allow_addr_req(sig_sf_allow_addr_req));
endmodule

(* ORIG_REF_NAME = "srl_fifo_f" *) 
module Loopback_axi_dma_1_0_srl_fifo_f__parameterized3
   (FIFO_Full_reg,
    sig_mmap_rst_reg_n_reg,
    sig_next_sequential_reg_reg,
    FIFO_Full_reg_0,
    E,
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ,
    SR,
    D,
    sig_mmap_rst_reg_n_reg_0,
    sig_next_calc_error_reg_reg,
    sig_mmap_rst_reg_n_reg_1,
    out,
    SS,
    m_axi_mm2s_aclk,
    sig_mmap_rst_reg_n,
    sig_first_dbeat_reg,
    sig_first_dbeat_reg_0,
    \INFERRED_GEN.cnt_i_reg[1] ,
    sig_mstr2data_cmd_valid,
    sig_dqual_reg_empty,
    sig_dqual_reg_empty_reg,
    sig_next_sequential_reg,
    m_axi_mm2s_rlast,
    Q,
    \sig_dbeat_cntr_reg[6] ,
    \sig_dbeat_cntr_reg[5] ,
    sig_ld_new_cmd_reg,
    sig_rsc2stat_status_valid,
    sig_stat2rsc_status_ready,
    sig_next_calc_error_reg,
    m_axi_mm2s_rready,
    full,
    sig_dqual_reg_empty_reg_0,
    m_axi_mm2s_rvalid,
    sig_dqual_reg_empty_reg_1,
    sig_dqual_reg_full,
    sig_last_dbeat_reg,
    in);
  output FIFO_Full_reg;
  output sig_mmap_rst_reg_n_reg;
  output sig_next_sequential_reg_reg;
  output FIFO_Full_reg_0;
  output [0:0]E;
  output \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  output [0:0]SR;
  output [7:0]D;
  output sig_mmap_rst_reg_n_reg_0;
  output sig_next_calc_error_reg_reg;
  output sig_mmap_rst_reg_n_reg_1;
  output [12:0]out;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input sig_mmap_rst_reg_n;
  input sig_first_dbeat_reg;
  input sig_first_dbeat_reg_0;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input sig_mstr2data_cmd_valid;
  input sig_dqual_reg_empty;
  input sig_dqual_reg_empty_reg;
  input sig_next_sequential_reg;
  input m_axi_mm2s_rlast;
  input [7:0]Q;
  input \sig_dbeat_cntr_reg[6] ;
  input \sig_dbeat_cntr_reg[5] ;
  input sig_ld_new_cmd_reg;
  input sig_rsc2stat_status_valid;
  input sig_stat2rsc_status_ready;
  input sig_next_calc_error_reg;
  input [2:0]m_axi_mm2s_rready;
  input full;
  input sig_dqual_reg_empty_reg_0;
  input m_axi_mm2s_rvalid;
  input sig_dqual_reg_empty_reg_1;
  input sig_dqual_reg_full;
  input sig_last_dbeat_reg;
  input [16:0]in;

  wire [7:0]D;
  wire [0:0]E;
  wire FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire [7:0]Q;
  wire [0:0]SR;
  wire [0:0]SS;
  wire full;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  wire [16:0]in;
  wire m_axi_mm2s_aclk;
  wire m_axi_mm2s_rlast;
  wire [2:0]m_axi_mm2s_rready;
  wire m_axi_mm2s_rvalid;
  wire [12:0]out;
  wire \sig_dbeat_cntr_reg[5] ;
  wire \sig_dbeat_cntr_reg[6] ;
  wire sig_dqual_reg_empty;
  wire sig_dqual_reg_empty_reg;
  wire sig_dqual_reg_empty_reg_0;
  wire sig_dqual_reg_empty_reg_1;
  wire sig_dqual_reg_full;
  wire sig_first_dbeat_reg;
  wire sig_first_dbeat_reg_0;
  wire sig_last_dbeat_reg;
  wire sig_ld_new_cmd_reg;
  wire sig_mmap_rst_reg_n;
  wire sig_mmap_rst_reg_n_reg;
  wire sig_mmap_rst_reg_n_reg_0;
  wire sig_mmap_rst_reg_n_reg_1;
  wire sig_mstr2data_cmd_valid;
  wire sig_next_calc_error_reg;
  wire sig_next_calc_error_reg_reg;
  wire sig_next_sequential_reg;
  wire sig_next_sequential_reg_reg;
  wire sig_rsc2stat_status_valid;
  wire sig_stat2rsc_status_ready;

  Loopback_axi_dma_1_0_srl_fifo_rbu_f__parameterized3 I_SRL_FIFO_RBU_F
       (.D(D),
        .E(E),
        .FIFO_Full_reg_0(FIFO_Full_reg),
        .FIFO_Full_reg_1(FIFO_Full_reg_0),
        .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ),
        .Q(Q),
        .SR(SR),
        .SS(SS),
        .full(full),
        .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg (\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ),
        .in(in),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axi_mm2s_rlast(m_axi_mm2s_rlast),
        .m_axi_mm2s_rready(m_axi_mm2s_rready),
        .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid),
        .out(out),
        .\sig_dbeat_cntr_reg[5] (\sig_dbeat_cntr_reg[5] ),
        .\sig_dbeat_cntr_reg[6] (\sig_dbeat_cntr_reg[6] ),
        .sig_dqual_reg_empty(sig_dqual_reg_empty),
        .sig_dqual_reg_empty_reg(sig_dqual_reg_empty_reg),
        .sig_dqual_reg_empty_reg_0(sig_dqual_reg_empty_reg_0),
        .sig_dqual_reg_empty_reg_1(sig_dqual_reg_empty_reg_1),
        .sig_dqual_reg_full(sig_dqual_reg_full),
        .sig_first_dbeat_reg(sig_first_dbeat_reg),
        .sig_first_dbeat_reg_0(sig_first_dbeat_reg_0),
        .sig_last_dbeat_reg(sig_last_dbeat_reg),
        .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mmap_rst_reg_n_reg(sig_mmap_rst_reg_n_reg),
        .sig_mmap_rst_reg_n_reg_0(sig_mmap_rst_reg_n_reg_0),
        .sig_mmap_rst_reg_n_reg_1(sig_mmap_rst_reg_n_reg_1),
        .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid),
        .sig_next_calc_error_reg(sig_next_calc_error_reg),
        .sig_next_calc_error_reg_reg(sig_next_calc_error_reg_reg),
        .sig_next_sequential_reg(sig_next_sequential_reg),
        .sig_next_sequential_reg_reg(sig_next_sequential_reg_reg),
        .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid),
        .sig_stat2rsc_status_ready(sig_stat2rsc_status_ready));
endmodule

(* ORIG_REF_NAME = "srl_fifo_f" *) 
module Loopback_axi_dma_1_0_srl_fifo_f__parameterized4
   (FIFO_Full_reg,
    Q,
    sig_inhibit_rdy_n_reg,
    SS,
    m_axi_mm2s_aclk,
    FIFO_Full_reg_0,
    \INFERRED_GEN.cnt_i_reg[2] ,
    \INFERRED_GEN.cnt_i_reg[1] ,
    sig_mstr2sf_cmd_valid,
    \INFERRED_GEN.cnt_i_reg[0] );
  output FIFO_Full_reg;
  output [0:0]Q;
  output sig_inhibit_rdy_n_reg;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input FIFO_Full_reg_0;
  input \INFERRED_GEN.cnt_i_reg[2] ;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input sig_mstr2sf_cmd_valid;
  input \INFERRED_GEN.cnt_i_reg[0] ;

  wire FIFO_Full_reg;
  wire FIFO_Full_reg_0;
  wire \INFERRED_GEN.cnt_i_reg[0] ;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire \INFERRED_GEN.cnt_i_reg[2] ;
  wire [0:0]Q;
  wire [0:0]SS;
  wire m_axi_mm2s_aclk;
  wire sig_inhibit_rdy_n_reg;
  wire sig_mstr2sf_cmd_valid;

  Loopback_axi_dma_1_0_srl_fifo_rbu_f__parameterized4 I_SRL_FIFO_RBU_F
       (.FIFO_Full_reg_0(FIFO_Full_reg),
        .FIFO_Full_reg_1(FIFO_Full_reg_0),
        .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ),
        .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ),
        .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ),
        .Q(Q),
        .SS(SS),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg),
        .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid));
endmodule

module Loopback_axi_dma_1_0_srl_fifo_rbu_f
   (Q,
    m_axi_sg_bready,
    sig_coelsc_decerr_reg0,
    out,
    sig_coelsc_slverr_reg0,
    sig_stream_rst,
    m_axi_sg_aclk,
    \INFERRED_GEN.cnt_i_reg[0] ,
    m_axi_sg_bvalid,
    sig_inhibit_rdy_n,
    \INFERRED_GEN.cnt_i_reg[1] ,
    D,
    \GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ,
    m_axi_sg_bresp);
  output [0:0]Q;
  output m_axi_sg_bready;
  output sig_coelsc_decerr_reg0;
  output [0:0]out;
  output sig_coelsc_slverr_reg0;
  input sig_stream_rst;
  input m_axi_sg_aclk;
  input \INFERRED_GEN.cnt_i_reg[0] ;
  input m_axi_sg_bvalid;
  input sig_inhibit_rdy_n;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input [1:0]D;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ;
  input [1:0]m_axi_sg_bresp;

  wire CNTR_INCR_DECR_ADDN_F_I_n_2;
  wire CNTR_INCR_DECR_ADDN_F_I_n_3;
  wire [1:0]D;
  wire FIFO_Full_reg_n_0;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ;
  wire \INFERRED_GEN.cnt_i_reg[0] ;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire [0:0]Q;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire fifo_full_p1;
  wire m_axi_sg_aclk;
  wire m_axi_sg_bready;
  wire [1:0]m_axi_sg_bresp;
  wire m_axi_sg_bvalid;
  wire [0:0]out;
  wire sig_coelsc_decerr_reg0;
  wire sig_coelsc_slverr_reg0;
  wire sig_inhibit_rdy_n;
  wire sig_stream_rst;

  Loopback_axi_dma_1_0_cntr_incr_decr_addn_f_19 CNTR_INCR_DECR_ADDN_F_I
       (.\INFERRED_GEN.cnt_i_reg[0]_0 (\INFERRED_GEN.cnt_i_reg[0] ),
        .\INFERRED_GEN.cnt_i_reg[1]_0 (FIFO_Full_reg_n_0),
        .\INFERRED_GEN.cnt_i_reg[1]_1 (\INFERRED_GEN.cnt_i_reg[1] ),
        .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}),
        .\USE_SRL_FIFO.sig_wr_fifo (\USE_SRL_FIFO.sig_wr_fifo ),
        .fifo_full_p1(fifo_full_p1),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_bvalid(m_axi_sg_bvalid),
        .sig_inhibit_rdy_n(sig_inhibit_rdy_n),
        .sig_stream_rst(sig_stream_rst));
  Loopback_axi_dma_1_0_dynshreg_f DYNSHREG_F_I
       (.D(D),
        .FIFO_Full_reg(FIFO_Full_reg_n_0),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_slverr_reg_reg ),
        .addr({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axi_sg_bresp(m_axi_sg_bresp),
        .m_axi_sg_bvalid(m_axi_sg_bvalid),
        .out(out),
        .sel(\USE_SRL_FIFO.sig_wr_fifo ),
        .sig_coelsc_decerr_reg0(sig_coelsc_decerr_reg0),
        .sig_coelsc_slverr_reg0(sig_coelsc_slverr_reg0),
        .sig_inhibit_rdy_n(sig_inhibit_rdy_n));
  FDRE FIFO_Full_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(fifo_full_p1),
        .Q(FIFO_Full_reg_n_0),
        .R(sig_stream_rst));
  LUT2 #(
    .INIT(4'h2)) 
    m_axi_sg_bready_INST_0
       (.I0(sig_inhibit_rdy_n),
        .I1(FIFO_Full_reg_n_0),
        .O(m_axi_sg_bready));
endmodule

(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) 
module Loopback_axi_dma_1_0_srl_fifo_rbu_f__parameterized0
   (FIFO_Full_reg_0,
    sig_coelsc_interr_reg0,
    out,
    \INFERRED_GEN.cnt_i_reg[2] ,
    E,
    \sig_wdc_statcnt_reg[2] ,
    sig_push_coelsc_reg,
    FIFO_Full_reg_1,
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ,
    sig_data2wsc_cmd_cmplt_reg,
    \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ,
    sig_stream_rst,
    m_axi_sg_aclk,
    D,
    \USE_SRL_FIFO.sig_wr_fifo ,
    sig_push_to_wsc,
    \INFERRED_GEN.cnt_i_reg[0] ,
    sig_tlast_err_stop,
    Q,
    \GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ,
    sig_coelsc_reg_empty,
    \GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ,
    in);
  output FIFO_Full_reg_0;
  output sig_coelsc_interr_reg0;
  output [1:0]out;
  output \INFERRED_GEN.cnt_i_reg[2] ;
  output [0:0]E;
  output [1:0]\sig_wdc_statcnt_reg[2] ;
  output sig_push_coelsc_reg;
  output FIFO_Full_reg_1;
  output \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ;
  output sig_data2wsc_cmd_cmplt_reg;
  output \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ;
  input sig_stream_rst;
  input m_axi_sg_aclk;
  input [2:0]D;
  input \USE_SRL_FIFO.sig_wr_fifo ;
  input sig_push_to_wsc;
  input \INFERRED_GEN.cnt_i_reg[0] ;
  input sig_tlast_err_stop;
  input [2:0]Q;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ;
  input sig_coelsc_reg_empty;
  input [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ;
  input [2:0]in;

  wire CNTR_INCR_DECR_ADDN_F_I_n_2;
  wire CNTR_INCR_DECR_ADDN_F_I_n_3;
  wire [2:0]D;
  wire DYNSHREG_F_I_n_9;
  wire [0:0]E;
  wire FIFO_Full_reg_0;
  wire FIFO_Full_reg_1;
  wire \GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ;
  wire \GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ;
  wire [0:0]\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ;
  wire \INFERRED_GEN.cnt_i_reg[0] ;
  wire \INFERRED_GEN.cnt_i_reg[2] ;
  wire [2:0]Q;
  wire \USE_SRL_FIFO.sig_rd_empty ;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire [0:0]addr_i_p1;
  wire fifo_full_p1;
  wire [2:0]in;
  wire m_axi_sg_aclk;
  wire [1:0]out;
  wire sig_coelsc_interr_reg0;
  wire sig_coelsc_reg_empty;
  wire sig_data2wsc_cmd_cmplt_reg;
  wire sig_push_coelsc_reg;
  wire sig_push_to_wsc;
  wire sig_stream_rst;
  wire sig_tlast_err_stop;
  wire [1:0]\sig_wdc_statcnt_reg[2] ;

  Loopback_axi_dma_1_0_cntr_incr_decr_addn_f_20 CNTR_INCR_DECR_ADDN_F_I
       (.D(addr_i_p1),
        .FIFO_Full_reg(DYNSHREG_F_I_n_9),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_reg_empty_reg ),
        .\INFERRED_GEN.cnt_i_reg[1]_0 (\INFERRED_GEN.cnt_i_reg[2] ),
        .\INFERRED_GEN.cnt_i_reg[1]_1 (\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .Q({\USE_SRL_FIFO.sig_rd_empty ,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}),
        .\USE_SRL_FIFO.sig_wr_fifo (\USE_SRL_FIFO.sig_wr_fifo ),
        .fifo_full_p1(fifo_full_p1),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .sig_coelsc_reg_empty(sig_coelsc_reg_empty),
        .sig_stream_rst(sig_stream_rst));
  Loopback_axi_dma_1_0_dynshreg_f__parameterized0 DYNSHREG_F_I
       (.D(D),
        .E(E),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_interr_reg_reg ),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_okay_reg_reg ),
        .\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg (\GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg ),
        .\INFERRED_GEN.cnt_i_reg[0] (addr_i_p1),
        .\INFERRED_GEN.cnt_i_reg[0]_0 (\INFERRED_GEN.cnt_i_reg[0] ),
        .\INFERRED_GEN.cnt_i_reg[0]_1 (FIFO_Full_reg_0),
        .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ),
        .\INFERRED_GEN.cnt_i_reg[2]_0 (DYNSHREG_F_I_n_9),
        .Q({\USE_SRL_FIFO.sig_rd_empty ,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}),
        .\USE_SRL_FIFO.sig_wr_fifo (\USE_SRL_FIFO.sig_wr_fifo ),
        .in(in),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .out(out),
        .sig_coelsc_interr_reg0(sig_coelsc_interr_reg0),
        .sig_coelsc_reg_empty(sig_coelsc_reg_empty),
        .sig_data2wsc_cmd_cmplt_reg(sig_data2wsc_cmd_cmplt_reg),
        .sig_push_coelsc_reg(sig_push_coelsc_reg),
        .sig_push_to_wsc(sig_push_to_wsc),
        .sig_tlast_err_stop(sig_tlast_err_stop),
        .\sig_wdc_statcnt_reg[1] (Q),
        .\sig_wdc_statcnt_reg[2] (\sig_wdc_statcnt_reg[2] ));
  FDRE FIFO_Full_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(fifo_full_p1),
        .Q(FIFO_Full_reg_0),
        .R(sig_stream_rst));
  LUT3 #(
    .INIT(8'h40)) 
    sig_push_to_wsc_i_3
       (.I0(FIFO_Full_reg_0),
        .I1(\INFERRED_GEN.cnt_i_reg[0] ),
        .I2(sig_push_to_wsc),
        .O(FIFO_Full_reg_1));
endmodule

(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) 
module Loopback_axi_dma_1_0_srl_fifo_rbu_f__parameterized1
   (queue_empty_new0,
    FIFO_Full_reg_0,
    D,
    write_cmnd_cmb,
    FIFO_Full_reg_1,
    updt_data_reg,
    \GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ,
    out,
    sinit,
    m_axi_sg_aclk,
    \GEN_MM2S.queue_empty_new_reg ,
    \GEN_MM2S.queue_dout_new_reg[90] ,
    \GEN_MM2S.queue_dout_new_reg[90]_0 ,
    Q,
    \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ,
    ch1_ftch_queue_empty,
    m_axis_mm2s_ftch_tvalid_new,
    mm2s_halt,
    \INFERRED_GEN.cnt_i_reg[1] ,
    \INFERRED_GEN.cnt_i_reg[0] ,
    \updt_desc_reg2_reg[25] );
  output queue_empty_new0;
  output [0:0]FIFO_Full_reg_0;
  output [0:0]D;
  output write_cmnd_cmb;
  output FIFO_Full_reg_1;
  output updt_data_reg;
  output \GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ;
  output [25:0]out;
  input sinit;
  input m_axi_sg_aclk;
  input [0:0]\GEN_MM2S.queue_empty_new_reg ;
  input \GEN_MM2S.queue_dout_new_reg[90] ;
  input \GEN_MM2S.queue_dout_new_reg[90]_0 ;
  input [1:0]Q;
  input \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ;
  input ch1_ftch_queue_empty;
  input m_axis_mm2s_ftch_tvalid_new;
  input mm2s_halt;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input \INFERRED_GEN.cnt_i_reg[0] ;
  input [25:0]\updt_desc_reg2_reg[25] ;

  wire CNTR_INCR_DECR_ADDN_F_I_n_1;
  wire CNTR_INCR_DECR_ADDN_F_I_n_2;
  wire CNTR_INCR_DECR_ADDN_F_I_n_3;
  wire CNTR_INCR_DECR_ADDN_F_I_n_4;
  wire [0:0]D;
  wire [0:0]FIFO_Full_reg_0;
  wire FIFO_Full_reg_1;
  wire \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ;
  wire \GEN_MM2S.queue_dout_new_reg[90] ;
  wire \GEN_MM2S.queue_dout_new_reg[90]_0 ;
  wire [0:0]\GEN_MM2S.queue_empty_new_reg ;
  wire \GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ;
  wire \GEN_UPDT_FOR_QUEUE.xb_fifo_full ;
  wire \INFERRED_GEN.cnt_i_reg[0] ;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire [1:0]Q;
  wire ch1_ftch_queue_empty;
  wire fifo_full_p1;
  wire m_axi_sg_aclk;
  wire m_axis_mm2s_ftch_tvalid_new;
  wire mm2s_halt;
  wire [25:0]out;
  wire queue_empty_new0;
  wire sinit;
  wire updt_data_reg;
  wire [25:0]\updt_desc_reg2_reg[25] ;
  wire write_cmnd_cmb;

  Loopback_axi_dma_1_0_cntr_incr_decr_addn_f__parameterized0 CNTR_INCR_DECR_ADDN_F_I
       (.\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg (\GEN_UPDT_FOR_QUEUE.sts_received_d1_reg ),
        .\INFERRED_GEN.cnt_i_reg[0]_0 (\INFERRED_GEN.cnt_i_reg[0] ),
        .\INFERRED_GEN.cnt_i_reg[1]_0 (\INFERRED_GEN.cnt_i_reg[1] ),
        .Q({CNTR_INCR_DECR_ADDN_F_I_n_1,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4}),
        .fifo_full_p1(fifo_full_p1),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_mm2s_ftch_tvalid_new(m_axis_mm2s_ftch_tvalid_new),
        .mm2s_halt(mm2s_halt),
        .sinit(sinit));
  Loopback_axi_dma_1_0_dynshreg_f__parameterized1 DYNSHREG_F_I
       (.Q({CNTR_INCR_DECR_ADDN_F_I_n_1,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4}),
        .m_axi_sg_aclk(m_axi_sg_aclk),
        .m_axis_mm2s_ftch_tvalid_new(m_axis_mm2s_ftch_tvalid_new),
        .out(out),
        .\updt_desc_reg2_reg[25] (\updt_desc_reg2_reg[25] ));
  FDRE FIFO_Full_reg
       (.C(m_axi_sg_aclk),
        .CE(1'b1),
        .D(fifo_full_p1),
        .Q(\GEN_UPDT_FOR_QUEUE.xb_fifo_full ),
        .R(sinit));
  LUT6 #(
    .INIT(64'h0000000E00000000)) 
    \FSM_sequential_mm2s_cs[1]_i_2 
       (.I0(\GEN_UPDT_FOR_QUEUE.xb_fifo_full ),
        .I1(\GEN_MM2S.queue_dout_new_reg[90] ),
        .I2(\GEN_MM2S.queue_dout_new_reg[90]_0 ),
        .I3(Q[1]),
        .I4(\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ),
        .I5(Q[0]),
        .O(D));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_sequential_mm2s_cs[1]_i_3 
       (.I0(\GEN_MM2S.queue_dout_new_reg[90] ),
        .I1(\GEN_UPDT_FOR_QUEUE.xb_fifo_full ),
        .O(updt_data_reg));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_i_1 
       (.I0(\GEN_UPDT_FOR_QUEUE.xb_fifo_full ),
        .I1(\GEN_MM2S.queue_dout_new_reg[90] ),
        .I2(\GEN_MM2S.queue_dout_new_reg[90]_0 ),
        .I3(Q[1]),
        .I4(\GEN_CMD_BTT_EQL_23.mm2s_cmnd_wr_i_reg ),
        .I5(Q[0]),
        .O(write_cmnd_cmb));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \GEN_MM2S.queue_dout_new[90]_i_1 
       (.I0(\GEN_MM2S.queue_dout_new_reg[90]_0 ),
        .I1(\GEN_UPDT_FOR_QUEUE.xb_fifo_full ),
        .I2(\GEN_MM2S.queue_dout_new_reg[90] ),
        .I3(ch1_ftch_queue_empty),
        .I4(Q[1]),
        .I5(Q[0]),
        .O(FIFO_Full_reg_0));
  LUT2 #(
    .INIT(4'hE)) 
    \GEN_MM2S.queue_empty_new_i_1 
       (.I0(FIFO_Full_reg_0),
        .I1(\GEN_MM2S.queue_empty_new_reg ),
        .O(queue_empty_new0));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT3 #(
    .INIT(8'h01)) 
    all_is_idle_d1_i_2
       (.I0(\GEN_UPDT_FOR_QUEUE.xb_fifo_full ),
        .I1(\GEN_MM2S.queue_dout_new_reg[90] ),
        .I2(ch1_ftch_queue_empty),
        .O(FIFO_Full_reg_1));
endmodule

(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) 
module Loopback_axi_dma_1_0_srl_fifo_rbu_f__parameterized2
   (FIFO_Full_reg_0,
    sig_halt_reg_reg,
    FIFO_Full_reg_1,
    sig_addr_reg_empty_reg,
    sig_calc_error_reg_reg,
    out,
    SS,
    m_axi_mm2s_aclk,
    sig_mstr2addr_cmd_valid,
    \INFERRED_GEN.cnt_i_reg[1] ,
    sig_addr_reg_empty,
    sig_sf_allow_addr_req,
    sig_data2addr_stop_req,
    sig_mmap_rst_reg_n,
    in);
  output FIFO_Full_reg_0;
  output sig_halt_reg_reg;
  output FIFO_Full_reg_1;
  output sig_addr_reg_empty_reg;
  output sig_calc_error_reg_reg;
  output [38:0]out;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input sig_mstr2addr_cmd_valid;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input sig_addr_reg_empty;
  input sig_sf_allow_addr_req;
  input sig_data2addr_stop_req;
  input sig_mmap_rst_reg_n;
  input [37:0]in;

  wire CNTR_INCR_DECR_ADDN_F_I_n_2;
  wire CNTR_INCR_DECR_ADDN_F_I_n_3;
  wire FIFO_Full_reg_0;
  wire FIFO_Full_reg_1;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire [0:0]SS;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire fifo_full_p1;
  wire [37:0]in;
  wire m_axi_mm2s_aclk;
  wire [38:0]out;
  wire sig_addr_reg_empty;
  wire sig_addr_reg_empty_reg;
  wire sig_calc_error_reg_reg;
  wire sig_data2addr_stop_req;
  wire sig_halt_reg_reg;
  wire sig_mmap_rst_reg_n;
  wire sig_mstr2addr_cmd_valid;
  wire sig_sf_allow_addr_req;

  Loopback_axi_dma_1_0_cntr_incr_decr_addn_f_4 CNTR_INCR_DECR_ADDN_F_I
       (.\INFERRED_GEN.cnt_i_reg[1]_0 (\INFERRED_GEN.cnt_i_reg[1] ),
        .\INFERRED_GEN.cnt_i_reg[1]_1 (FIFO_Full_reg_0),
        .Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}),
        .SS(SS),
        .\USE_SRL_FIFO.sig_wr_fifo (\USE_SRL_FIFO.sig_wr_fifo ),
        .fifo_full_p1(fifo_full_p1),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .sig_addr_reg_empty(sig_addr_reg_empty),
        .sig_addr_reg_empty_reg(sig_addr_reg_empty_reg),
        .sig_data2addr_stop_req(sig_data2addr_stop_req),
        .sig_halt_reg_reg(sig_halt_reg_reg),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid),
        .sig_sf_allow_addr_req(sig_sf_allow_addr_req));
  Loopback_axi_dma_1_0_dynshreg_f__parameterized2 DYNSHREG_F_I
       (.Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}),
        .\USE_SRL_FIFO.sig_wr_fifo (\USE_SRL_FIFO.sig_wr_fifo ),
        .in(in),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .out(out),
        .sig_calc_error_reg_reg(sig_calc_error_reg_reg),
        .sig_calc_error_reg_reg_0(\INFERRED_GEN.cnt_i_reg[1] ),
        .sig_calc_error_reg_reg_1(FIFO_Full_reg_0),
        .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid));
  FDRE FIFO_Full_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(fifo_full_p1),
        .Q(FIFO_Full_reg_0),
        .R(SS));
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_onehot_sig_pcc_sm_state[6]_i_3 
       (.I0(FIFO_Full_reg_0),
        .I1(\INFERRED_GEN.cnt_i_reg[1] ),
        .O(FIFO_Full_reg_1));
endmodule

(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) 
module Loopback_axi_dma_1_0_srl_fifo_rbu_f__parameterized3
   (FIFO_Full_reg_0,
    sig_mmap_rst_reg_n_reg,
    sig_next_sequential_reg_reg,
    FIFO_Full_reg_1,
    E,
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ,
    SR,
    D,
    sig_mmap_rst_reg_n_reg_0,
    sig_next_calc_error_reg_reg,
    sig_mmap_rst_reg_n_reg_1,
    out,
    SS,
    m_axi_mm2s_aclk,
    sig_mmap_rst_reg_n,
    sig_first_dbeat_reg,
    sig_first_dbeat_reg_0,
    \INFERRED_GEN.cnt_i_reg[1] ,
    sig_mstr2data_cmd_valid,
    sig_dqual_reg_empty,
    sig_dqual_reg_empty_reg,
    sig_next_sequential_reg,
    m_axi_mm2s_rlast,
    Q,
    \sig_dbeat_cntr_reg[6] ,
    \sig_dbeat_cntr_reg[5] ,
    sig_ld_new_cmd_reg,
    sig_rsc2stat_status_valid,
    sig_stat2rsc_status_ready,
    sig_next_calc_error_reg,
    m_axi_mm2s_rready,
    full,
    sig_dqual_reg_empty_reg_0,
    m_axi_mm2s_rvalid,
    sig_dqual_reg_empty_reg_1,
    sig_dqual_reg_full,
    sig_last_dbeat_reg,
    in);
  output FIFO_Full_reg_0;
  output sig_mmap_rst_reg_n_reg;
  output sig_next_sequential_reg_reg;
  output FIFO_Full_reg_1;
  output [0:0]E;
  output \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  output [0:0]SR;
  output [7:0]D;
  output sig_mmap_rst_reg_n_reg_0;
  output sig_next_calc_error_reg_reg;
  output sig_mmap_rst_reg_n_reg_1;
  output [12:0]out;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input sig_mmap_rst_reg_n;
  input sig_first_dbeat_reg;
  input sig_first_dbeat_reg_0;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input sig_mstr2data_cmd_valid;
  input sig_dqual_reg_empty;
  input sig_dqual_reg_empty_reg;
  input sig_next_sequential_reg;
  input m_axi_mm2s_rlast;
  input [7:0]Q;
  input \sig_dbeat_cntr_reg[6] ;
  input \sig_dbeat_cntr_reg[5] ;
  input sig_ld_new_cmd_reg;
  input sig_rsc2stat_status_valid;
  input sig_stat2rsc_status_ready;
  input sig_next_calc_error_reg;
  input [2:0]m_axi_mm2s_rready;
  input full;
  input sig_dqual_reg_empty_reg_0;
  input m_axi_mm2s_rvalid;
  input sig_dqual_reg_empty_reg_1;
  input sig_dqual_reg_full;
  input sig_last_dbeat_reg;
  input [16:0]in;

  wire CNTR_INCR_DECR_ADDN_F_I_n_2;
  wire CNTR_INCR_DECR_ADDN_F_I_n_3;
  wire [7:0]D;
  wire DYNSHREG_F_I_n_1;
  wire [0:0]E;
  wire FIFO_Full_reg_0;
  wire FIFO_Full_reg_1;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire [7:0]Q;
  wire [0:0]SR;
  wire [0:0]SS;
  wire \USE_SRL_FIFO.sig_wr_fifo ;
  wire fifo_full_p1;
  wire full;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  wire [16:0]in;
  wire m_axi_mm2s_aclk;
  wire m_axi_mm2s_rlast;
  wire [2:0]m_axi_mm2s_rready;
  wire m_axi_mm2s_rvalid;
  wire [12:0]out;
  wire [9:7]sig_cmd_fifo_data_out;
  wire \sig_dbeat_cntr_reg[5] ;
  wire \sig_dbeat_cntr_reg[6] ;
  wire sig_dqual_reg_empty;
  wire sig_dqual_reg_empty_reg;
  wire sig_dqual_reg_empty_reg_0;
  wire sig_dqual_reg_empty_reg_1;
  wire sig_dqual_reg_full;
  wire sig_first_dbeat_reg;
  wire sig_first_dbeat_reg_0;
  wire sig_last_dbeat_reg;
  wire sig_ld_new_cmd_reg;
  wire sig_mmap_rst_reg_n;
  wire sig_mmap_rst_reg_n_reg;
  wire sig_mmap_rst_reg_n_reg_0;
  wire sig_mmap_rst_reg_n_reg_1;
  wire sig_mstr2data_cmd_valid;
  wire sig_next_calc_error_reg;
  wire sig_next_calc_error_reg_reg;
  wire sig_next_sequential_reg;
  wire sig_next_sequential_reg_reg;
  wire sig_rsc2stat_status_valid;
  wire sig_stat2rsc_status_ready;

  Loopback_axi_dma_1_0_cntr_incr_decr_addn_f CNTR_INCR_DECR_ADDN_F_I
       (.D(D[7:1]),
        .E(E),
        .\INFERRED_GEN.cnt_i_reg[1]_0 (FIFO_Full_reg_0),
        .\INFERRED_GEN.cnt_i_reg[1]_1 (\INFERRED_GEN.cnt_i_reg[1] ),
        .Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}),
        .SR(SR),
        .SS(SS),
        .\USE_SRL_FIFO.sig_wr_fifo (\USE_SRL_FIFO.sig_wr_fifo ),
        .fifo_full_p1(fifo_full_p1),
        .full(full),
        .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg (\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .m_axi_mm2s_rlast(m_axi_mm2s_rlast),
        .m_axi_mm2s_rready(m_axi_mm2s_rready),
        .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid),
        .out(sig_cmd_fifo_data_out),
        .\sig_dbeat_cntr_reg[0] (sig_first_dbeat_reg_0),
        .\sig_dbeat_cntr_reg[5] (\sig_dbeat_cntr_reg[5] ),
        .\sig_dbeat_cntr_reg[6] (\sig_dbeat_cntr_reg[6] ),
        .\sig_dbeat_cntr_reg[7] (Q),
        .sig_dqual_reg_empty(sig_dqual_reg_empty),
        .sig_dqual_reg_empty_reg(sig_dqual_reg_empty_reg),
        .sig_dqual_reg_empty_reg_0(sig_dqual_reg_empty_reg_0),
        .sig_dqual_reg_empty_reg_1(sig_dqual_reg_empty_reg_1),
        .sig_dqual_reg_full(sig_dqual_reg_full),
        .sig_last_dbeat_reg(DYNSHREG_F_I_n_1),
        .sig_last_dbeat_reg_0(sig_last_dbeat_reg),
        .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mmap_rst_reg_n_reg(sig_mmap_rst_reg_n_reg_0),
        .sig_mmap_rst_reg_n_reg_0(sig_mmap_rst_reg_n_reg_1),
        .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid),
        .sig_next_calc_error_reg(sig_next_calc_error_reg),
        .sig_next_calc_error_reg_reg(sig_next_calc_error_reg_reg),
        .sig_next_sequential_reg(sig_next_sequential_reg),
        .sig_next_sequential_reg_reg(sig_next_sequential_reg_reg),
        .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid),
        .sig_stat2rsc_status_ready(sig_stat2rsc_status_ready));
  Loopback_axi_dma_1_0_dynshreg_f__parameterized3 DYNSHREG_F_I
       (.D(D[0]),
        .\INFERRED_GEN.cnt_i_reg[0] (DYNSHREG_F_I_n_1),
        .Q(Q[0]),
        .\USE_SRL_FIFO.sig_wr_fifo (\USE_SRL_FIFO.sig_wr_fifo ),
        .in(in),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .out({out[12:1],sig_cmd_fifo_data_out,out[0]}),
        .\sig_dbeat_cntr_reg[0] (sig_next_sequential_reg_reg),
        .sig_first_dbeat_reg(sig_first_dbeat_reg),
        .sig_first_dbeat_reg_0(sig_first_dbeat_reg_0),
        .sig_mmap_rst_reg_n(sig_mmap_rst_reg_n),
        .sig_mmap_rst_reg_n_reg(sig_mmap_rst_reg_n_reg),
        .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid),
        .sig_next_calc_error_reg_reg(\INFERRED_GEN.cnt_i_reg[1] ),
        .sig_next_calc_error_reg_reg_0(FIFO_Full_reg_0),
        .sig_next_calc_error_reg_reg_1({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}));
  FDRE FIFO_Full_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(fifo_full_p1),
        .Q(FIFO_Full_reg_0),
        .R(SS));
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_onehot_sig_pcc_sm_state[6]_i_4 
       (.I0(FIFO_Full_reg_0),
        .I1(\INFERRED_GEN.cnt_i_reg[1] ),
        .O(FIFO_Full_reg_1));
endmodule

(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) 
module Loopback_axi_dma_1_0_srl_fifo_rbu_f__parameterized4
   (FIFO_Full_reg_0,
    Q,
    sig_inhibit_rdy_n_reg,
    SS,
    m_axi_mm2s_aclk,
    FIFO_Full_reg_1,
    \INFERRED_GEN.cnt_i_reg[2] ,
    \INFERRED_GEN.cnt_i_reg[1] ,
    sig_mstr2sf_cmd_valid,
    \INFERRED_GEN.cnt_i_reg[0] );
  output FIFO_Full_reg_0;
  output [0:0]Q;
  output sig_inhibit_rdy_n_reg;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input FIFO_Full_reg_1;
  input \INFERRED_GEN.cnt_i_reg[2] ;
  input \INFERRED_GEN.cnt_i_reg[1] ;
  input sig_mstr2sf_cmd_valid;
  input \INFERRED_GEN.cnt_i_reg[0] ;

  wire FIFO_Full_reg_0;
  wire FIFO_Full_reg_1;
  wire \INFERRED_GEN.cnt_i_reg[0] ;
  wire \INFERRED_GEN.cnt_i_reg[1] ;
  wire \INFERRED_GEN.cnt_i_reg[2] ;
  wire [0:0]Q;
  wire [0:0]SS;
  wire fifo_full_p1;
  wire m_axi_mm2s_aclk;
  wire sig_inhibit_rdy_n_reg;
  wire sig_mstr2sf_cmd_valid;

  Loopback_axi_dma_1_0_cntr_incr_decr_addn_f_5 CNTR_INCR_DECR_ADDN_F_I
       (.FIFO_Full_reg(FIFO_Full_reg_1),
        .\INFERRED_GEN.cnt_i_reg[0]_0 (FIFO_Full_reg_0),
        .\INFERRED_GEN.cnt_i_reg[0]_1 (\INFERRED_GEN.cnt_i_reg[0] ),
        .\INFERRED_GEN.cnt_i_reg[1]_0 (\INFERRED_GEN.cnt_i_reg[1] ),
        .\INFERRED_GEN.cnt_i_reg[2]_0 (\INFERRED_GEN.cnt_i_reg[2] ),
        .Q(Q),
        .SS(SS),
        .fifo_full_p1(fifo_full_p1),
        .m_axi_mm2s_aclk(m_axi_mm2s_aclk),
        .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg),
        .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid));
  FDRE FIFO_Full_reg
       (.C(m_axi_mm2s_aclk),
        .CE(1'b1),
        .D(fifo_full_p1),
        .Q(FIFO_Full_reg_0),
        .R(SS));
endmodule

module Loopback_axi_dma_1_0_sync_fifo_fg
   (D,
    E,
    \GEN_ASYNC_RESET.scndry_resetn_reg ,
    \counter_reg[0] ,
    rst,
    m_axi_sg_aclk,
    m_axi_sg_rlast,
    \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ,
    out,
    m_axi_sg_rvalid,
    Q,
    \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ,
    \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ,
    ftch_cmnd_data,
    sof_ftch_desc,
    m_axi_sg_rdata,
    sof_ftch_desc_del1,
    follower_empty_mm2s);
  output [32:0]D;
  output [0:0]E;
  output \GEN_ASYNC_RESET.scndry_resetn_reg ;
  output \counter_reg[0] ;
  input rst;
  input m_axi_sg_aclk;
  input m_axi_sg_rlast;
  input \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  input out;
  input m_axi_sg_rvalid;
  input [2:0]Q;
  input \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ;
  input \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ;
  input [0:0]ftch_cmnd_data;
  input sof_ftch_desc;
  input [31:0]m_axi_sg_rdata;
  input sof_ftch_desc_del1;
  input follower_empty_mm2s;

  wire [32:0]D;
  wire [0:0]E;
  wire \FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ;
  wire \GEN_ASYNC_RESET.scndry_resetn_reg ;
  wire \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ;
  wire \GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ;
  wire [2:0]Q;
  wire cntrl_fifo_empty;
  wire \counter_reg[0] ;
  wire follower_empty_mm2s;
  wire [0:0]ftch_cmnd_data;
  wire m_axi_sg_aclk;
  wire [31:0]m_axi_sg_rdata;
  wire m_axi_sg_rlast;
  wire m_axi_sg_rvalid;
  wire out;
  wire [31:0]queue_din;
  wire queue_full;
  wire queue_wren;
  wire rst;
  wire sof_ftch_desc;
  wire sof_ftch_desc_del1;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_almost_empty_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_almost_full_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_data_valid_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_dbiterr_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_overflow_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_prog_empty_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_prog_full_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_rd_rst_busy_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_sbiterr_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_underflow_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_ack_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_rst_busy_UNCONNECTED ;
  wire [3:0]\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_rd_data_count_UNCONNECTED ;
  wire [7:0]\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_data_count_UNCONNECTED ;

  LUT5 #(
    .INIT(32'h80000000)) 
    \GEN_STALE_DESC_CHECK.ftch_stale_desc_i_1 
       (.I0(\FLOP_FOR_NOQUEUE.FETCH_Q.data_concat_reg0 ),
        .I1(out),
        .I2(m_axi_sg_rvalid),
        .I3(Q[2]),
        .I4(\counter_reg[0] ),
        .O(\GEN_ASYNC_RESET.scndry_resetn_reg ));
  LUT2 #(
    .INIT(4'h2)) 
    \GEN_SYNC_FIFO.follower_reg_mm2s[31]_i_2 
       (.I0(follower_empty_mm2s),
        .I1(cntrl_fifo_empty),
        .O(E));
  LUT6 #(
    .INIT(64'hF0FE00EEF0FF00EE)) 
    \TLAST_GEN.sof_ftch_desc_i_2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg ),
        .I3(\GEN_STALE_DESC_CHECK.ftch_stale_desc_reg_0 ),
        .I4(ftch_cmnd_data),
        .I5(queue_full),
        .O(\counter_reg[0] ));
  (* CASCADE_HEIGHT = "0" *) 
  (* DOUT_RESET_VALUE = "0" *) 
  (* ECC_MODE = "0" *) 
  (* EN_ADV_FEATURE_SYNC = "16'b0001111100011111" *) 
  (* EN_SIM_ASSERT_ERR = "warning" *) 
  (* FIFO_MEMORY_TYPE = "0" *) 
  (* FIFO_READ_LATENCY = "0" *) 
  (* FIFO_WRITE_DEPTH = "128" *) 
  (* FULL_RESET_VALUE = "1" *) 
  (* PROG_EMPTY_THRESH = "10" *) 
  (* PROG_FULL_THRESH = "10" *) 
  (* P_COMMON_CLOCK = "1" *) 
  (* P_ECC_MODE = "0" *) 
  (* P_FIFO_MEMORY_TYPE = "0" *) 
  (* P_READ_MODE = "1" *) 
  (* P_WAKEUP_TIME = "2" *) 
  (* RD_DATA_COUNT_WIDTH = "4" *) 
  (* READ_DATA_WIDTH = "33" *) 
  (* READ_MODE = "0" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_ADV_FEATURES = "1F1F" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WRITE_DATA_WIDTH = "33" *) 
  (* WR_DATA_COUNT_WIDTH = "8" *) 
  (* XPM_MODULE = "TRUE" *) 
  Loopback_axi_dma_1_0_xpm_fifo_sync \xpm_fifo_instance.xpm_fifo_sync_inst 
       (.almost_empty(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_almost_empty_UNCONNECTED ),
        .almost_full(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_almost_full_UNCONNECTED ),
        .data_valid(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_data_valid_UNCONNECTED ),
        .dbiterr(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_dbiterr_UNCONNECTED ),
        .din({m_axi_sg_rlast,queue_din}),
        .dout(D),
        .empty(cntrl_fifo_empty),
        .full(queue_full),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .overflow(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_overflow_UNCONNECTED ),
        .prog_empty(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_prog_empty_UNCONNECTED ),
        .prog_full(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_prog_full_UNCONNECTED ),
        .rd_data_count(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_rd_data_count_UNCONNECTED [3:0]),
        .rd_en(E),
        .rd_rst_busy(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_rd_rst_busy_UNCONNECTED ),
        .rst(rst),
        .sbiterr(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_sbiterr_UNCONNECTED ),
        .sleep(1'b0),
        .underflow(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_underflow_UNCONNECTED ),
        .wr_ack(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_ack_UNCONNECTED ),
        .wr_clk(m_axi_sg_aclk),
        .wr_data_count(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_data_count_UNCONNECTED [7:0]),
        .wr_en(queue_wren),
        .wr_rst_busy(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_rst_busy_UNCONNECTED ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_10__0 
       (.I0(m_axi_sg_rdata[24]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[24]));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_11 
       (.I0(m_axi_sg_rdata[23]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[23]));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_12 
       (.I0(m_axi_sg_rdata[22]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[22]));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_13 
       (.I0(m_axi_sg_rdata[21]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[21]));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_14 
       (.I0(m_axi_sg_rdata[20]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[20]));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_15 
       (.I0(m_axi_sg_rdata[19]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[19]));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_16 
       (.I0(m_axi_sg_rdata[18]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[18]));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_17 
       (.I0(m_axi_sg_rdata[17]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[17]));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_18 
       (.I0(m_axi_sg_rdata[16]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[16]));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_19 
       (.I0(m_axi_sg_rdata[15]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[15]));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_20 
       (.I0(m_axi_sg_rdata[14]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[14]));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_21 
       (.I0(m_axi_sg_rdata[13]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[13]));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_22 
       (.I0(m_axi_sg_rdata[12]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[12]));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_23 
       (.I0(m_axi_sg_rdata[11]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[11]));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_24 
       (.I0(m_axi_sg_rdata[10]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[10]));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_25 
       (.I0(m_axi_sg_rdata[9]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[9]));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_26 
       (.I0(m_axi_sg_rdata[8]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[8]));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_27 
       (.I0(m_axi_sg_rdata[7]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[7]));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_28 
       (.I0(m_axi_sg_rdata[6]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[6]));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_29 
       (.I0(m_axi_sg_rdata[5]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[5]));
  LUT4 #(
    .INIT(16'h4000)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_2__0 
       (.I0(queue_full),
        .I1(sof_ftch_desc),
        .I2(ftch_cmnd_data),
        .I3(m_axi_sg_rvalid),
        .O(queue_wren));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_30 
       (.I0(m_axi_sg_rdata[4]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[4]));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_31 
       (.I0(m_axi_sg_rdata[3]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[3]));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_32 
       (.I0(m_axi_sg_rdata[2]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[2]));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_33 
       (.I0(m_axi_sg_rdata[1]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[1]));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_34 
       (.I0(m_axi_sg_rdata[0]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[0]));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_3__0 
       (.I0(m_axi_sg_rdata[31]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[31]));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_4__0 
       (.I0(m_axi_sg_rdata[30]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[30]));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_5 
       (.I0(m_axi_sg_rdata[29]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[29]));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_6 
       (.I0(m_axi_sg_rdata[28]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[28]));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_7 
       (.I0(m_axi_sg_rdata[27]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[27]));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_8 
       (.I0(m_axi_sg_rdata[26]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[26]));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_9__0 
       (.I0(m_axi_sg_rdata[25]),
        .I1(sof_ftch_desc_del1),
        .I2(sof_ftch_desc),
        .O(queue_din[25]));
endmodule

(* ORIG_REF_NAME = "sync_fifo_fg" *) 
module Loopback_axi_dma_1_0_sync_fifo_fg__parameterized0
   (full,
    dout,
    empty,
    sig_last_skid_mux_out,
    sig_slast_with_stop,
    sig_s_ready_out_reg,
    sig_s_ready_out_reg_0,
    \gen_fwft.empty_fwft_i_reg ,
    sig_posted_to_axi_2_reg,
    \INFERRED_GEN.cnt_i_reg[2] ,
    SS,
    m_axi_mm2s_aclk,
    wr_en,
    din,
    \OMIT_UNPACKING.lsig_cmd_loaded_reg ,
    sig_sstrb_stop_mask,
    out,
    sig_last_skid_reg,
    \OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ,
    Q,
    sig_ok_to_post_rd_addr_reg,
    sig_ok_to_post_rd_addr_reg_0,
    sig_mmap_rst_reg_n,
    sig_ok_to_post_rd_addr_reg_1,
    sig_ok_to_post_rd_addr_reg_2);
  output full;
  output [35:0]dout;
  output empty;
  output sig_last_skid_mux_out;
  output sig_slast_with_stop;
  output sig_s_ready_out_reg;
  output sig_s_ready_out_reg_0;
  output \gen_fwft.empty_fwft_i_reg ;
  output sig_posted_to_axi_2_reg;
  output \INFERRED_GEN.cnt_i_reg[2] ;
  input [0:0]SS;
  input m_axi_mm2s_aclk;
  input wr_en;
  input [37:0]din;
  input \OMIT_UNPACKING.lsig_cmd_loaded_reg ;
  input [0:0]sig_sstrb_stop_mask;
  input out;
  input sig_last_skid_reg;
  input \OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ;
  input [0:0]Q;
  input sig_ok_to_post_rd_addr_reg;
  input sig_ok_to_post_rd_addr_reg_0;
  input sig_mmap_rst_reg_n;
  input [3:0]sig_ok_to_post_rd_addr_reg_1;
  input sig_ok_to_post_rd_addr_reg_2;

  wire \INFERRED_GEN.cnt_i_reg[2] ;
  wire \OMIT_UNPACKING.lsig_cmd_loaded_reg ;
  wire \OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ;
  wire [0:0]Q;
  wire [0:0]SS;
  wire [37:0]din;
  wire [35:0]dout;
  wire empty;
  wire full;
  wire \gen_fwft.empty_fwft_i_reg ;
  wire m_axi_mm2s_aclk;
  wire out;
  wire [37:36]sig_data_fifo_data_out;
  wire [7:4]sig_data_fifo_wr_cnt;
  wire sig_last_skid_mux_out;
  wire sig_last_skid_reg;
  wire sig_mmap_rst_reg_n;
  wire sig_ok_to_post_rd_addr_i_3_n_0;
  wire sig_ok_to_post_rd_addr_i_4_n_0;
  wire sig_ok_to_post_rd_addr_reg;
  wire sig_ok_to_post_rd_addr_reg_0;
  wire [3:0]sig_ok_to_post_rd_addr_reg_1;
  wire sig_ok_to_post_rd_addr_reg_2;
  wire sig_pop_data_fifo;
  wire sig_posted_to_axi_2_reg;
  wire sig_s_ready_out_reg;
  wire sig_s_ready_out_reg_0;
  wire sig_slast_with_stop;
  wire [0:0]sig_sstrb_stop_mask;
  wire wr_en;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_almost_empty_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_almost_full_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_data_valid_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_dbiterr_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_overflow_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_prog_empty_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_prog_full_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_rd_rst_busy_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_sbiterr_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_underflow_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_ack_UNCONNECTED ;
  wire \NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_rst_busy_UNCONNECTED ;
  wire [38:38]\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_dout_UNCONNECTED ;
  wire [3:0]\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_rd_data_count_UNCONNECTED ;
  wire [3:0]\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_data_count_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT5 #(
    .INIT(32'hFFFFF070)) 
    \INFERRED_GEN.cnt_i[1]_i_2 
       (.I0(\OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ),
        .I1(sig_data_fifo_data_out[37]),
        .I2(\OMIT_UNPACKING.lsig_cmd_loaded_reg ),
        .I3(empty),
        .I4(Q),
        .O(sig_s_ready_out_reg));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \INFERRED_GEN.cnt_i[2]_i_2__1 
       (.I0(\OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ),
        .I1(sig_data_fifo_data_out[37]),
        .I2(\OMIT_UNPACKING.lsig_cmd_loaded_reg ),
        .I3(empty),
        .O(sig_s_ready_out_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT5 #(
    .INIT(32'hD5F5F5F5)) 
    \OMIT_UNPACKING.lsig_cmd_loaded_i_1 
       (.I0(Q),
        .I1(empty),
        .I2(\OMIT_UNPACKING.lsig_cmd_loaded_reg ),
        .I3(sig_data_fifo_data_out[37]),
        .I4(\OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ),
        .O(\INFERRED_GEN.cnt_i_reg[2] ));
  LUT6 #(
    .INIT(64'hFF40FFFFFF400000)) 
    sig_last_reg_out_i_1
       (.I0(empty),
        .I1(\OMIT_UNPACKING.lsig_cmd_loaded_reg ),
        .I2(sig_data_fifo_data_out[36]),
        .I3(sig_sstrb_stop_mask),
        .I4(out),
        .I5(sig_last_skid_reg),
        .O(sig_last_skid_mux_out));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT4 #(
    .INIT(16'hFF40)) 
    sig_last_skid_reg_i_1
       (.I0(empty),
        .I1(\OMIT_UNPACKING.lsig_cmd_loaded_reg ),
        .I2(sig_data_fifo_data_out[36]),
        .I3(sig_sstrb_stop_mask),
        .O(sig_slast_with_stop));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT2 #(
    .INIT(4'hB)) 
    sig_m_valid_dup_i_3
       (.I0(empty),
        .I1(\OMIT_UNPACKING.lsig_cmd_loaded_reg ),
        .O(\gen_fwft.empty_fwft_i_reg ));
  LUT5 #(
    .INIT(32'h00100000)) 
    sig_ok_to_post_rd_addr_i_1
       (.I0(sig_ok_to_post_rd_addr_reg),
        .I1(sig_ok_to_post_rd_addr_reg_0),
        .I2(sig_mmap_rst_reg_n),
        .I3(sig_data_fifo_wr_cnt[7]),
        .I4(sig_ok_to_post_rd_addr_i_3_n_0),
        .O(sig_posted_to_axi_2_reg));
  LUT6 #(
    .INIT(64'h4FFFFFFF44444444)) 
    sig_ok_to_post_rd_addr_i_3
       (.I0(sig_ok_to_post_rd_addr_reg_1[3]),
        .I1(sig_ok_to_post_rd_addr_i_4_n_0),
        .I2(sig_data_fifo_wr_cnt[6]),
        .I3(sig_data_fifo_wr_cnt[5]),
        .I4(sig_data_fifo_wr_cnt[4]),
        .I5(sig_ok_to_post_rd_addr_reg_2),
        .O(sig_ok_to_post_rd_addr_i_3_n_0));
  LUT6 #(
    .INIT(64'h00D00000FDFF00D0)) 
    sig_ok_to_post_rd_addr_i_4
       (.I0(sig_data_fifo_wr_cnt[4]),
        .I1(sig_ok_to_post_rd_addr_reg_1[0]),
        .I2(sig_ok_to_post_rd_addr_reg_1[1]),
        .I3(sig_data_fifo_wr_cnt[5]),
        .I4(sig_ok_to_post_rd_addr_reg_1[2]),
        .I5(sig_data_fifo_wr_cnt[6]),
        .O(sig_ok_to_post_rd_addr_i_4_n_0));
  (* CASCADE_HEIGHT = "0" *) 
  (* DOUT_RESET_VALUE = "0" *) 
  (* ECC_MODE = "0" *) 
  (* EN_ADV_FEATURE_SYNC = "16'b0001111100011111" *) 
  (* EN_SIM_ASSERT_ERR = "warning" *) 
  (* FIFO_MEMORY_TYPE = "0" *) 
  (* FIFO_READ_LATENCY = "0" *) 
  (* FIFO_WRITE_DEPTH = "128" *) 
  (* FULL_RESET_VALUE = "1" *) 
  (* PROG_EMPTY_THRESH = "10" *) 
  (* PROG_FULL_THRESH = "10" *) 
  (* P_COMMON_CLOCK = "1" *) 
  (* P_ECC_MODE = "0" *) 
  (* P_FIFO_MEMORY_TYPE = "2" *) 
  (* P_READ_MODE = "1" *) 
  (* P_WAKEUP_TIME = "2" *) 
  (* RD_DATA_COUNT_WIDTH = "4" *) 
  (* READ_DATA_WIDTH = "39" *) 
  (* READ_MODE = "0" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_ADV_FEATURES = "1F1F" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WRITE_DATA_WIDTH = "39" *) 
  (* WR_DATA_COUNT_WIDTH = "8" *) 
  (* XPM_MODULE = "TRUE" *) 
  Loopback_axi_dma_1_0_xpm_fifo_sync__parameterized1 \xpm_fifo_instance.xpm_fifo_sync_inst 
       (.almost_empty(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_almost_empty_UNCONNECTED ),
        .almost_full(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_almost_full_UNCONNECTED ),
        .data_valid(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_data_valid_UNCONNECTED ),
        .dbiterr(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_dbiterr_UNCONNECTED ),
        .din({1'b0,din}),
        .dout({\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_dout_UNCONNECTED [38],sig_data_fifo_data_out,dout}),
        .empty(empty),
        .full(full),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .overflow(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_overflow_UNCONNECTED ),
        .prog_empty(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_prog_empty_UNCONNECTED ),
        .prog_full(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_prog_full_UNCONNECTED ),
        .rd_data_count(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_rd_data_count_UNCONNECTED [3:0]),
        .rd_en(sig_pop_data_fifo),
        .rd_rst_busy(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_rd_rst_busy_UNCONNECTED ),
        .rst(SS),
        .sbiterr(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_sbiterr_UNCONNECTED ),
        .sleep(1'b0),
        .underflow(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_underflow_UNCONNECTED ),
        .wr_ack(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_ack_UNCONNECTED ),
        .wr_clk(m_axi_mm2s_aclk),
        .wr_data_count({sig_data_fifo_wr_cnt,\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_data_count_UNCONNECTED [3:0]}),
        .wr_en(wr_en),
        .wr_rst_busy(\NLW_xpm_fifo_instance.xpm_fifo_sync_inst_wr_rst_busy_UNCONNECTED ));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \xpm_fifo_instance.xpm_fifo_sync_inst_i_9 
       (.I0(\OMIT_UNPACKING.lsig_cmd_loaded_reg_0 ),
        .I1(\OMIT_UNPACKING.lsig_cmd_loaded_reg ),
        .I2(empty),
        .O(sig_pop_data_fifo));
endmodule

(* ORIG_REF_NAME = "xpm_counter_updn" *) 
module Loopback_axi_dma_1_0_xpm_counter_updn__parameterized1
   (Q,
    S,
    DI,
    ram_empty_i,
    \count_value_i_reg[0]_0 ,
    rd_en,
    \gwdc.wr_data_count_i_reg[7] ,
    \gwdc.wr_data_count_i_reg[7]_0 ,
    SR,
    wr_clk);
  output [0:0]Q;
  output [1:0]S;
  output [0:0]DI;
  input ram_empty_i;
  input [1:0]\count_value_i_reg[0]_0 ;
  input rd_en;
  input [1:0]\gwdc.wr_data_count_i_reg[7] ;
  input [1:0]\gwdc.wr_data_count_i_reg[7]_0 ;
  input [0:0]SR;
  input wr_clk;

  wire [0:0]DI;
  wire [0:0]Q;
  wire [1:0]S;
  wire [0:0]SR;
  wire [0:0]count_value_i;
  wire \count_value_i[0]_i_1__3_n_0 ;
  wire \count_value_i[1]_i_3_n_0 ;
  wire [1:0]\count_value_i_reg[0]_0 ;
  wire \gen_fwft.count_en ;
  wire [1:0]\gwdc.wr_data_count_i_reg[7] ;
  wire [1:0]\gwdc.wr_data_count_i_reg[7]_0 ;
  wire ram_empty_i;
  wire rd_en;
  wire wr_clk;

  LUT5 #(
    .INIT(32'h5AAAA655)) 
    \count_value_i[0]_i_1__3 
       (.I0(count_value_i),
        .I1(\count_value_i_reg[0]_0 [0]),
        .I2(rd_en),
        .I3(\count_value_i_reg[0]_0 [1]),
        .I4(ram_empty_i),
        .O(\count_value_i[0]_i_1__3_n_0 ));
  LUT4 #(
    .INIT(16'hC02F)) 
    \count_value_i[1]_i_2 
       (.I0(\count_value_i_reg[0]_0 [0]),
        .I1(rd_en),
        .I2(\count_value_i_reg[0]_0 [1]),
        .I3(ram_empty_i),
        .O(\gen_fwft.count_en ));
  LUT6 #(
    .INIT(64'hA999A9A96AAA6AAA)) 
    \count_value_i[1]_i_3 
       (.I0(Q),
        .I1(ram_empty_i),
        .I2(\count_value_i_reg[0]_0 [1]),
        .I3(rd_en),
        .I4(\count_value_i_reg[0]_0 [0]),
        .I5(count_value_i),
        .O(\count_value_i[1]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[0] 
       (.C(wr_clk),
        .CE(\gen_fwft.count_en ),
        .D(\count_value_i[0]_i_1__3_n_0 ),
        .Q(count_value_i),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[1] 
       (.C(wr_clk),
        .CE(\gen_fwft.count_en ),
        .D(\count_value_i[1]_i_3_n_0 ),
        .Q(Q),
        .R(SR));
  LUT4 #(
    .INIT(16'h9669)) 
    \gwdc.wr_data_count_i[7]_i_14 
       (.I0(DI),
        .I1(\gwdc.wr_data_count_i_reg[7] [1]),
        .I2(Q),
        .I3(\gwdc.wr_data_count_i_reg[7]_0 [1]),
        .O(S[1]));
  (* HLUTNM = "lutpair0" *) 
  LUT3 #(
    .INIT(8'h96)) 
    \gwdc.wr_data_count_i[7]_i_15 
       (.I0(count_value_i),
        .I1(\gwdc.wr_data_count_i_reg[7] [0]),
        .I2(\gwdc.wr_data_count_i_reg[7]_0 [0]),
        .O(S[0]));
  (* HLUTNM = "lutpair0" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \gwdc.wr_data_count_i[7]_i_7 
       (.I0(count_value_i),
        .I1(\gwdc.wr_data_count_i_reg[7] [0]),
        .O(DI));
endmodule

(* ORIG_REF_NAME = "xpm_counter_updn" *) 
module Loopback_axi_dma_1_0_xpm_counter_updn__parameterized2
   (DI,
    Q,
    S,
    \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ,
    leaving_empty0,
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ,
    \gwdc.wr_data_count_i_reg[7] ,
    \gwdc.wr_data_count_i_reg[7]_0 ,
    \count_value_i_reg[0]_0 ,
    rd_en,
    ram_empty_i,
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 ,
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 ,
    ram_wr_en_pf,
    clr_full,
    \count_value_i_reg[0]_1 ,
    wr_clk);
  output [0:0]DI;
  output [6:0]Q;
  output [4:0]S;
  output \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ;
  output leaving_empty0;
  output \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  input [0:0]\gwdc.wr_data_count_i_reg[7] ;
  input [7:0]\gwdc.wr_data_count_i_reg[7]_0 ;
  input [1:0]\count_value_i_reg[0]_0 ;
  input rd_en;
  input ram_empty_i;
  input [6:0]\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 ;
  input \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 ;
  input ram_wr_en_pf;
  input clr_full;
  input [0:0]\count_value_i_reg[0]_1 ;
  input wr_clk;

  wire [0:0]DI;
  wire \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ;
  wire [6:0]Q;
  wire [4:0]S;
  wire clr_full;
  wire \count_value_i[0]_i_1__1_n_0 ;
  wire \count_value_i[1]_i_1__1_n_0 ;
  wire \count_value_i[2]_i_1__1_n_0 ;
  wire \count_value_i[3]_i_1__1_n_0 ;
  wire \count_value_i[4]_i_1__1_n_0 ;
  wire \count_value_i[5]_i_1__1_n_0 ;
  wire \count_value_i[6]_i_1__1_n_0 ;
  wire \count_value_i[6]_i_2__1_n_0 ;
  wire \count_value_i[7]_i_1__0_n_0 ;
  wire \count_value_i[7]_i_2__0_n_0 ;
  wire [1:0]\count_value_i_reg[0]_0 ;
  wire [0:0]\count_value_i_reg[0]_1 ;
  wire \count_value_i_reg_n_0_[7] ;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5_n_0 ;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6_n_0 ;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_7_n_0 ;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_8_n_0 ;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  wire [6:0]\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 ;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 ;
  wire going_full1;
  wire [0:0]\gwdc.wr_data_count_i_reg[7] ;
  wire [7:0]\gwdc.wr_data_count_i_reg[7]_0 ;
  wire leaving_empty0;
  wire ram_empty_i;
  wire ram_wr_en_pf;
  wire rd_en;
  wire wr_clk;

  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT4 #(
    .INIT(16'h10EF)) 
    \count_value_i[0]_i_1__1 
       (.I0(rd_en),
        .I1(\count_value_i_reg[0]_0 [0]),
        .I2(\count_value_i_reg[0]_0 [1]),
        .I3(Q[0]),
        .O(\count_value_i[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT5 #(
    .INIT(32'h02FFFD00)) 
    \count_value_i[1]_i_1__1 
       (.I0(\count_value_i_reg[0]_0 [1]),
        .I1(\count_value_i_reg[0]_0 [0]),
        .I2(rd_en),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\count_value_i[1]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \count_value_i[2]_i_1__1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(\count_value_i[2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \count_value_i[3]_i_1__1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(\count_value_i[3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[4]_i_1__1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\count_value_i[4]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[5]_i_1__1 
       (.I0(Q[3]),
        .I1(\count_value_i[6]_i_2__1_n_0 ),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[5]),
        .O(\count_value_i[5]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \count_value_i[6]_i_1__1 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(\count_value_i[6]_i_2__1_n_0 ),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(Q[6]),
        .O(\count_value_i[6]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000AAA200000000)) 
    \count_value_i[6]_i_2__1 
       (.I0(Q[1]),
        .I1(\count_value_i_reg[0]_0 [1]),
        .I2(\count_value_i_reg[0]_0 [0]),
        .I3(rd_en),
        .I4(ram_empty_i),
        .I5(Q[0]),
        .O(\count_value_i[6]_i_2__1_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \count_value_i[7]_i_1__0 
       (.I0(Q[5]),
        .I1(\count_value_i[7]_i_2__0_n_0 ),
        .I2(Q[6]),
        .I3(\count_value_i_reg_n_0_[7] ),
        .O(\count_value_i[7]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \count_value_i[7]_i_2__0 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ),
        .I4(Q[1]),
        .I5(Q[3]),
        .O(\count_value_i[7]_i_2__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[0] 
       (.C(wr_clk),
        .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ),
        .D(\count_value_i[0]_i_1__1_n_0 ),
        .Q(Q[0]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[1] 
       (.C(wr_clk),
        .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ),
        .D(\count_value_i[1]_i_1__1_n_0 ),
        .Q(Q[1]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[2] 
       (.C(wr_clk),
        .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ),
        .D(\count_value_i[2]_i_1__1_n_0 ),
        .Q(Q[2]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[3] 
       (.C(wr_clk),
        .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ),
        .D(\count_value_i[3]_i_1__1_n_0 ),
        .Q(Q[3]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[4] 
       (.C(wr_clk),
        .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ),
        .D(\count_value_i[4]_i_1__1_n_0 ),
        .Q(Q[4]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[5] 
       (.C(wr_clk),
        .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ),
        .D(\count_value_i[5]_i_1__1_n_0 ),
        .Q(Q[5]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[6] 
       (.C(wr_clk),
        .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ),
        .D(\count_value_i[6]_i_1__1_n_0 ),
        .Q(Q[6]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[7] 
       (.C(wr_clk),
        .CE(\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ),
        .D(\count_value_i[7]_i_1__0_n_0 ),
        .Q(\count_value_i_reg_n_0_[7] ),
        .R(\count_value_i_reg[0]_1 ));
  LUT6 #(
    .INIT(64'h000000003B2A2A2A)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_1 
       (.I0(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 ),
        .I1(\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ),
        .I2(leaving_empty0),
        .I3(going_full1),
        .I4(ram_wr_en_pf),
        .I5(clr_full),
        .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ));
  LUT4 #(
    .INIT(16'h9000)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_2 
       (.I0(Q[6]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [6]),
        .I2(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5_n_0 ),
        .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6_n_0 ),
        .O(leaving_empty0));
  LUT4 #(
    .INIT(16'h9000)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_3 
       (.I0(Q[6]),
        .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [6]),
        .I2(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_7_n_0 ),
        .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_8_n_0 ),
        .O(going_full1));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5 
       (.I0(Q[3]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [3]),
        .I2(\gwdc.wr_data_count_i_reg[7]_0 [5]),
        .I3(Q[5]),
        .I4(\gwdc.wr_data_count_i_reg[7]_0 [4]),
        .I5(Q[4]),
        .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6 
       (.I0(Q[0]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [0]),
        .I2(\gwdc.wr_data_count_i_reg[7]_0 [2]),
        .I3(Q[2]),
        .I4(\gwdc.wr_data_count_i_reg[7]_0 [1]),
        .I5(Q[1]),
        .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_7 
       (.I0(Q[3]),
        .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [3]),
        .I2(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [5]),
        .I3(Q[5]),
        .I4(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [4]),
        .I5(Q[4]),
        .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_8 
       (.I0(Q[0]),
        .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [0]),
        .I2(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [2]),
        .I3(Q[2]),
        .I4(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [1]),
        .I5(Q[1]),
        .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h00FD)) 
    \gen_sdpram.xpm_memory_base_inst_i_2 
       (.I0(\count_value_i_reg[0]_0 [1]),
        .I1(\count_value_i_reg[0]_0 [0]),
        .I2(rd_en),
        .I3(ram_empty_i),
        .O(\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] ));
  LUT4 #(
    .INIT(16'hB44B)) 
    \gwdc.wr_data_count_i[7]_i_10 
       (.I0(Q[4]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [4]),
        .I2(Q[5]),
        .I3(\gwdc.wr_data_count_i_reg[7]_0 [5]),
        .O(S[2]));
  LUT4 #(
    .INIT(16'hB44B)) 
    \gwdc.wr_data_count_i[7]_i_11 
       (.I0(Q[3]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [3]),
        .I2(Q[4]),
        .I3(\gwdc.wr_data_count_i_reg[7]_0 [4]),
        .O(S[1]));
  LUT4 #(
    .INIT(16'hB44B)) 
    \gwdc.wr_data_count_i[7]_i_12 
       (.I0(Q[2]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [2]),
        .I2(Q[3]),
        .I3(\gwdc.wr_data_count_i_reg[7]_0 [3]),
        .O(S[0]));
  LUT3 #(
    .INIT(8'hD4)) 
    \gwdc.wr_data_count_i[7]_i_6 
       (.I0(Q[1]),
        .I1(\gwdc.wr_data_count_i_reg[7] ),
        .I2(\gwdc.wr_data_count_i_reg[7]_0 [1]),
        .O(DI));
  LUT4 #(
    .INIT(16'hB44B)) 
    \gwdc.wr_data_count_i[7]_i_8 
       (.I0(Q[6]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [6]),
        .I2(\count_value_i_reg_n_0_[7] ),
        .I3(\gwdc.wr_data_count_i_reg[7]_0 [7]),
        .O(S[4]));
  LUT4 #(
    .INIT(16'hB44B)) 
    \gwdc.wr_data_count_i[7]_i_9 
       (.I0(Q[5]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [5]),
        .I2(Q[6]),
        .I3(\gwdc.wr_data_count_i_reg[7]_0 [6]),
        .O(S[3]));
endmodule

(* ORIG_REF_NAME = "xpm_counter_updn" *) 
module Loopback_axi_dma_1_0_xpm_counter_updn__parameterized2_13
   (Q,
    leaving_empty0,
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ,
    enb,
    \count_value_i_reg[0]_0 ,
    rd_en,
    ram_empty_i,
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 ,
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 ,
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_2 ,
    E,
    clr_full,
    \count_value_i_reg[0]_1 ,
    rd_clk);
  output [6:0]Q;
  output leaving_empty0;
  output \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  output enb;
  input [1:0]\count_value_i_reg[0]_0 ;
  input rd_en;
  input ram_empty_i;
  input [6:0]\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 ;
  input [6:0]\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 ;
  input \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_2 ;
  input [0:0]E;
  input clr_full;
  input [0:0]\count_value_i_reg[0]_1 ;
  input rd_clk;

  wire [0:0]E;
  wire [6:0]Q;
  wire clr_full;
  wire \count_value_i[0]_i_1__1_n_0 ;
  wire \count_value_i[1]_i_1__1_n_0 ;
  wire \count_value_i[2]_i_1__1_n_0 ;
  wire \count_value_i[3]_i_1__1_n_0 ;
  wire \count_value_i[4]_i_1__1_n_0 ;
  wire \count_value_i[5]_i_1__1_n_0 ;
  wire \count_value_i[6]_i_1__1_n_0 ;
  wire \count_value_i[6]_i_2__1_n_0 ;
  wire [1:0]\count_value_i_reg[0]_0 ;
  wire [0:0]\count_value_i_reg[0]_1 ;
  wire enb;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5_n_0 ;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6_n_0 ;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_7_n_0 ;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_8_n_0 ;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ;
  wire [6:0]\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 ;
  wire [6:0]\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 ;
  wire \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_2 ;
  wire going_full1;
  wire leaving_empty0;
  wire ram_empty_i;
  wire rd_clk;
  wire rd_en;

  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT4 #(
    .INIT(16'h10EF)) 
    \count_value_i[0]_i_1__1 
       (.I0(rd_en),
        .I1(\count_value_i_reg[0]_0 [0]),
        .I2(\count_value_i_reg[0]_0 [1]),
        .I3(Q[0]),
        .O(\count_value_i[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT5 #(
    .INIT(32'h02FFFD00)) 
    \count_value_i[1]_i_1__1 
       (.I0(\count_value_i_reg[0]_0 [1]),
        .I1(\count_value_i_reg[0]_0 [0]),
        .I2(rd_en),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\count_value_i[1]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \count_value_i[2]_i_1__1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(\count_value_i[2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \count_value_i[3]_i_1__1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(\count_value_i[3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[4]_i_1__1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\count_value_i[4]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[5]_i_1__1 
       (.I0(Q[3]),
        .I1(\count_value_i[6]_i_2__1_n_0 ),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[5]),
        .O(\count_value_i[5]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \count_value_i[6]_i_1__1 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(\count_value_i[6]_i_2__1_n_0 ),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(Q[6]),
        .O(\count_value_i[6]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000AAA200000000)) 
    \count_value_i[6]_i_2__1 
       (.I0(Q[1]),
        .I1(\count_value_i_reg[0]_0 [1]),
        .I2(\count_value_i_reg[0]_0 [0]),
        .I3(rd_en),
        .I4(ram_empty_i),
        .I5(Q[0]),
        .O(\count_value_i[6]_i_2__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[0] 
       (.C(rd_clk),
        .CE(enb),
        .D(\count_value_i[0]_i_1__1_n_0 ),
        .Q(Q[0]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[1] 
       (.C(rd_clk),
        .CE(enb),
        .D(\count_value_i[1]_i_1__1_n_0 ),
        .Q(Q[1]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[2] 
       (.C(rd_clk),
        .CE(enb),
        .D(\count_value_i[2]_i_1__1_n_0 ),
        .Q(Q[2]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[3] 
       (.C(rd_clk),
        .CE(enb),
        .D(\count_value_i[3]_i_1__1_n_0 ),
        .Q(Q[3]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[4] 
       (.C(rd_clk),
        .CE(enb),
        .D(\count_value_i[4]_i_1__1_n_0 ),
        .Q(Q[4]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[5] 
       (.C(rd_clk),
        .CE(enb),
        .D(\count_value_i[5]_i_1__1_n_0 ),
        .Q(Q[5]),
        .R(\count_value_i_reg[0]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[6] 
       (.C(rd_clk),
        .CE(enb),
        .D(\count_value_i[6]_i_1__1_n_0 ),
        .Q(Q[6]),
        .R(\count_value_i_reg[0]_1 ));
  LUT6 #(
    .INIT(64'h000000003B2A2A2A)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_1 
       (.I0(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_2 ),
        .I1(enb),
        .I2(leaving_empty0),
        .I3(going_full1),
        .I4(E),
        .I5(clr_full),
        .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg ));
  LUT4 #(
    .INIT(16'h9000)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_2 
       (.I0(Q[6]),
        .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [6]),
        .I2(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5_n_0 ),
        .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6_n_0 ),
        .O(leaving_empty0));
  LUT4 #(
    .INIT(16'h9000)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_3 
       (.I0(Q[6]),
        .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 [6]),
        .I2(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_7_n_0 ),
        .I3(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_8_n_0 ),
        .O(going_full1));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5 
       (.I0(Q[3]),
        .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [3]),
        .I2(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [5]),
        .I3(Q[5]),
        .I4(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [4]),
        .I5(Q[4]),
        .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6 
       (.I0(Q[0]),
        .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [0]),
        .I2(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [2]),
        .I3(Q[2]),
        .I4(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 [1]),
        .I5(Q[1]),
        .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_7 
       (.I0(Q[3]),
        .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 [3]),
        .I2(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 [5]),
        .I3(Q[5]),
        .I4(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 [4]),
        .I5(Q[4]),
        .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_8 
       (.I0(Q[0]),
        .I1(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 [0]),
        .I2(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 [2]),
        .I3(Q[2]),
        .I4(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 [1]),
        .I5(Q[1]),
        .O(\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h00FD)) 
    \gen_sdpram.xpm_memory_base_inst_i_2 
       (.I0(\count_value_i_reg[0]_0 [1]),
        .I1(\count_value_i_reg[0]_0 [0]),
        .I2(rd_en),
        .I3(ram_empty_i),
        .O(enb));
endmodule

(* ORIG_REF_NAME = "xpm_counter_updn" *) 
module Loopback_axi_dma_1_0_xpm_counter_updn__parameterized2_16
   (ram_empty_i0,
    Q,
    enb,
    leaving_empty0,
    E,
    ram_empty_i,
    wr_en,
    \count_value_i_reg[5]_0 ,
    \count_value_i_reg[6]_0 ,
    rst_d1,
    \gen_pntr_flags_cc.ram_empty_i_reg ,
    rd_clk);
  output ram_empty_i0;
  output [6:0]Q;
  input enb;
  input leaving_empty0;
  input [0:0]E;
  input ram_empty_i;
  input wr_en;
  input \count_value_i_reg[5]_0 ;
  input [0:0]\count_value_i_reg[6]_0 ;
  input rst_d1;
  input [6:0]\gen_pntr_flags_cc.ram_empty_i_reg ;
  input rd_clk;

  wire [0:0]E;
  wire [6:0]Q;
  wire \count_value_i[0]_i_1_n_0 ;
  wire \count_value_i[1]_i_1_n_0 ;
  wire \count_value_i[2]_i_1_n_0 ;
  wire \count_value_i[3]_i_1_n_0 ;
  wire \count_value_i[4]_i_1_n_0 ;
  wire \count_value_i[5]_i_1__0_n_0 ;
  wire \count_value_i[6]_i_1__0_n_0 ;
  wire \count_value_i[6]_i_2__0_n_0 ;
  wire \count_value_i_reg[5]_0 ;
  wire [0:0]\count_value_i_reg[6]_0 ;
  wire enb;
  wire \gen_pntr_flags_cc.ram_empty_i_i_3_n_0 ;
  wire \gen_pntr_flags_cc.ram_empty_i_i_4_n_0 ;
  wire [6:0]\gen_pntr_flags_cc.ram_empty_i_reg ;
  wire going_empty1;
  wire leaving_empty0;
  wire ram_empty_i;
  wire ram_empty_i0;
  wire rd_clk;
  wire rst_d1;
  wire wr_en;

  LUT1 #(
    .INIT(2'h1)) 
    \count_value_i[0]_i_1 
       (.I0(Q[0]),
        .O(\count_value_i[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \count_value_i[1]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\count_value_i[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \count_value_i[2]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(\count_value_i[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \count_value_i[3]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(\count_value_i[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[4]_i_1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\count_value_i[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[5]_i_1__0 
       (.I0(Q[3]),
        .I1(\count_value_i[6]_i_2__0_n_0 ),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[5]),
        .O(\count_value_i[5]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \count_value_i[6]_i_1__0 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(\count_value_i[6]_i_2__0_n_0 ),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(Q[6]),
        .O(\count_value_i[6]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800000000)) 
    \count_value_i[6]_i_2__0 
       (.I0(Q[1]),
        .I1(wr_en),
        .I2(\count_value_i_reg[5]_0 ),
        .I3(\count_value_i_reg[6]_0 ),
        .I4(rst_d1),
        .I5(Q[0]),
        .O(\count_value_i[6]_i_2__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[0] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[0]_i_1_n_0 ),
        .Q(Q[0]),
        .R(\count_value_i_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[1] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[1]_i_1_n_0 ),
        .Q(Q[1]),
        .R(\count_value_i_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[2] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[2]_i_1_n_0 ),
        .Q(Q[2]),
        .R(\count_value_i_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[3] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[3]_i_1_n_0 ),
        .Q(Q[3]),
        .R(\count_value_i_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[4] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[4]_i_1_n_0 ),
        .Q(Q[4]),
        .R(\count_value_i_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[5] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[5]_i_1__0_n_0 ),
        .Q(Q[5]),
        .R(\count_value_i_reg[6]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[6] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[6]_i_1__0_n_0 ),
        .Q(Q[6]),
        .R(\count_value_i_reg[6]_0 ));
  LUT5 #(
    .INIT(32'h0FFF0088)) 
    \gen_pntr_flags_cc.ram_empty_i_i_1 
       (.I0(enb),
        .I1(going_empty1),
        .I2(leaving_empty0),
        .I3(E),
        .I4(ram_empty_i),
        .O(ram_empty_i0));
  LUT4 #(
    .INIT(16'h9000)) 
    \gen_pntr_flags_cc.ram_empty_i_i_2 
       (.I0(Q[6]),
        .I1(\gen_pntr_flags_cc.ram_empty_i_reg [6]),
        .I2(\gen_pntr_flags_cc.ram_empty_i_i_3_n_0 ),
        .I3(\gen_pntr_flags_cc.ram_empty_i_i_4_n_0 ),
        .O(going_empty1));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.ram_empty_i_i_3 
       (.I0(Q[3]),
        .I1(\gen_pntr_flags_cc.ram_empty_i_reg [3]),
        .I2(\gen_pntr_flags_cc.ram_empty_i_reg [5]),
        .I3(Q[5]),
        .I4(\gen_pntr_flags_cc.ram_empty_i_reg [4]),
        .I5(Q[4]),
        .O(\gen_pntr_flags_cc.ram_empty_i_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.ram_empty_i_i_4 
       (.I0(Q[0]),
        .I1(\gen_pntr_flags_cc.ram_empty_i_reg [0]),
        .I2(\gen_pntr_flags_cc.ram_empty_i_reg [2]),
        .I3(Q[2]),
        .I4(\gen_pntr_flags_cc.ram_empty_i_reg [1]),
        .I5(Q[1]),
        .O(\gen_pntr_flags_cc.ram_empty_i_i_4_n_0 ));
endmodule

(* ORIG_REF_NAME = "xpm_counter_updn" *) 
module Loopback_axi_dma_1_0_xpm_counter_updn__parameterized2_6
   (ram_empty_i0,
    Q,
    D,
    \gen_pntr_flags_cc.ram_empty_i_reg ,
    leaving_empty0,
    ram_wr_en_pf,
    ram_empty_i,
    wr_en,
    \count_value_i_reg[5]_0 ,
    \count_value_i_reg[7]_0 ,
    rst_d1,
    \gen_pntr_flags_cc.ram_empty_i_reg_0 ,
    DI,
    S,
    \gwdc.wr_data_count_i_reg[7] ,
    \gwdc.wr_data_count_i_reg[7]_0 ,
    wr_clk);
  output ram_empty_i0;
  output [7:0]Q;
  output [3:0]D;
  input \gen_pntr_flags_cc.ram_empty_i_reg ;
  input leaving_empty0;
  input ram_wr_en_pf;
  input ram_empty_i;
  input wr_en;
  input \count_value_i_reg[5]_0 ;
  input [0:0]\count_value_i_reg[7]_0 ;
  input rst_d1;
  input [6:0]\gen_pntr_flags_cc.ram_empty_i_reg_0 ;
  input [1:0]DI;
  input [6:0]S;
  input [0:0]\gwdc.wr_data_count_i_reg[7] ;
  input [4:0]\gwdc.wr_data_count_i_reg[7]_0 ;
  input wr_clk;

  wire [3:0]D;
  wire [1:0]DI;
  wire [7:0]Q;
  wire [6:0]S;
  wire \count_value_i[0]_i_1_n_0 ;
  wire \count_value_i[1]_i_1_n_0 ;
  wire \count_value_i[2]_i_1_n_0 ;
  wire \count_value_i[3]_i_1_n_0 ;
  wire \count_value_i[4]_i_1_n_0 ;
  wire \count_value_i[5]_i_1__0_n_0 ;
  wire \count_value_i[6]_i_1__0_n_0 ;
  wire \count_value_i[6]_i_2__0_n_0 ;
  wire \count_value_i[7]_i_1_n_0 ;
  wire \count_value_i[7]_i_2_n_0 ;
  wire \count_value_i_reg[5]_0 ;
  wire [0:0]\count_value_i_reg[7]_0 ;
  wire \gen_pntr_flags_cc.ram_empty_i_i_3_n_0 ;
  wire \gen_pntr_flags_cc.ram_empty_i_i_4_n_0 ;
  wire \gen_pntr_flags_cc.ram_empty_i_reg ;
  wire [6:0]\gen_pntr_flags_cc.ram_empty_i_reg_0 ;
  wire going_empty1;
  wire \gwdc.wr_data_count_i[7]_i_13_n_0 ;
  wire \gwdc.wr_data_count_i[7]_i_2_n_0 ;
  wire \gwdc.wr_data_count_i[7]_i_3_n_0 ;
  wire \gwdc.wr_data_count_i[7]_i_4_n_0 ;
  wire \gwdc.wr_data_count_i[7]_i_5_n_0 ;
  wire [0:0]\gwdc.wr_data_count_i_reg[7] ;
  wire [4:0]\gwdc.wr_data_count_i_reg[7]_0 ;
  wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ;
  wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ;
  wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ;
  wire \gwdc.wr_data_count_i_reg[7]_i_1_n_4 ;
  wire \gwdc.wr_data_count_i_reg[7]_i_1_n_5 ;
  wire \gwdc.wr_data_count_i_reg[7]_i_1_n_6 ;
  wire \gwdc.wr_data_count_i_reg[7]_i_1_n_7 ;
  wire leaving_empty0;
  wire ram_empty_i;
  wire ram_empty_i0;
  wire ram_wr_en_pf;
  wire rst_d1;
  wire wr_clk;
  wire wr_en;
  wire [7:7]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_CO_UNCONNECTED ;
  wire [3:0]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED ;

  LUT1 #(
    .INIT(2'h1)) 
    \count_value_i[0]_i_1 
       (.I0(Q[0]),
        .O(\count_value_i[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \count_value_i[1]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\count_value_i[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \count_value_i[2]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(\count_value_i[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \count_value_i[3]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(\count_value_i[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[4]_i_1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\count_value_i[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[5]_i_1__0 
       (.I0(Q[3]),
        .I1(\count_value_i[6]_i_2__0_n_0 ),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[5]),
        .O(\count_value_i[5]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \count_value_i[6]_i_1__0 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(\count_value_i[6]_i_2__0_n_0 ),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(Q[6]),
        .O(\count_value_i[6]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800000000)) 
    \count_value_i[6]_i_2__0 
       (.I0(Q[1]),
        .I1(wr_en),
        .I2(\count_value_i_reg[5]_0 ),
        .I3(\count_value_i_reg[7]_0 ),
        .I4(rst_d1),
        .I5(Q[0]),
        .O(\count_value_i[6]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \count_value_i[7]_i_1 
       (.I0(Q[5]),
        .I1(\count_value_i[7]_i_2_n_0 ),
        .I2(Q[6]),
        .I3(Q[7]),
        .O(\count_value_i[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \count_value_i[7]_i_2 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(ram_wr_en_pf),
        .I4(Q[1]),
        .I5(Q[3]),
        .O(\count_value_i[7]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[0] 
       (.C(wr_clk),
        .CE(ram_wr_en_pf),
        .D(\count_value_i[0]_i_1_n_0 ),
        .Q(Q[0]),
        .R(\count_value_i_reg[7]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[1] 
       (.C(wr_clk),
        .CE(ram_wr_en_pf),
        .D(\count_value_i[1]_i_1_n_0 ),
        .Q(Q[1]),
        .R(\count_value_i_reg[7]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[2] 
       (.C(wr_clk),
        .CE(ram_wr_en_pf),
        .D(\count_value_i[2]_i_1_n_0 ),
        .Q(Q[2]),
        .R(\count_value_i_reg[7]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[3] 
       (.C(wr_clk),
        .CE(ram_wr_en_pf),
        .D(\count_value_i[3]_i_1_n_0 ),
        .Q(Q[3]),
        .R(\count_value_i_reg[7]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[4] 
       (.C(wr_clk),
        .CE(ram_wr_en_pf),
        .D(\count_value_i[4]_i_1_n_0 ),
        .Q(Q[4]),
        .R(\count_value_i_reg[7]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[5] 
       (.C(wr_clk),
        .CE(ram_wr_en_pf),
        .D(\count_value_i[5]_i_1__0_n_0 ),
        .Q(Q[5]),
        .R(\count_value_i_reg[7]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[6] 
       (.C(wr_clk),
        .CE(ram_wr_en_pf),
        .D(\count_value_i[6]_i_1__0_n_0 ),
        .Q(Q[6]),
        .R(\count_value_i_reg[7]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[7] 
       (.C(wr_clk),
        .CE(ram_wr_en_pf),
        .D(\count_value_i[7]_i_1_n_0 ),
        .Q(Q[7]),
        .R(\count_value_i_reg[7]_0 ));
  LUT5 #(
    .INIT(32'h0FFF0088)) 
    \gen_pntr_flags_cc.ram_empty_i_i_1 
       (.I0(\gen_pntr_flags_cc.ram_empty_i_reg ),
        .I1(going_empty1),
        .I2(leaving_empty0),
        .I3(ram_wr_en_pf),
        .I4(ram_empty_i),
        .O(ram_empty_i0));
  LUT4 #(
    .INIT(16'h9000)) 
    \gen_pntr_flags_cc.ram_empty_i_i_2 
       (.I0(Q[6]),
        .I1(\gen_pntr_flags_cc.ram_empty_i_reg_0 [6]),
        .I2(\gen_pntr_flags_cc.ram_empty_i_i_3_n_0 ),
        .I3(\gen_pntr_flags_cc.ram_empty_i_i_4_n_0 ),
        .O(going_empty1));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.ram_empty_i_i_3 
       (.I0(Q[3]),
        .I1(\gen_pntr_flags_cc.ram_empty_i_reg_0 [3]),
        .I2(\gen_pntr_flags_cc.ram_empty_i_reg_0 [5]),
        .I3(Q[5]),
        .I4(\gen_pntr_flags_cc.ram_empty_i_reg_0 [4]),
        .I5(Q[4]),
        .O(\gen_pntr_flags_cc.ram_empty_i_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \gen_pntr_flags_cc.ram_empty_i_i_4 
       (.I0(Q[0]),
        .I1(\gen_pntr_flags_cc.ram_empty_i_reg_0 [0]),
        .I2(\gen_pntr_flags_cc.ram_empty_i_reg_0 [2]),
        .I3(Q[2]),
        .I4(\gen_pntr_flags_cc.ram_empty_i_reg_0 [1]),
        .I5(Q[1]),
        .O(\gen_pntr_flags_cc.ram_empty_i_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h718E8E71)) 
    \gwdc.wr_data_count_i[7]_i_13 
       (.I0(Q[1]),
        .I1(\gwdc.wr_data_count_i_reg[7] ),
        .I2(\gwdc.wr_data_count_i_reg[7]_0 [0]),
        .I3(\gwdc.wr_data_count_i_reg[7]_0 [1]),
        .I4(Q[2]),
        .O(\gwdc.wr_data_count_i[7]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \gwdc.wr_data_count_i[7]_i_2 
       (.I0(Q[5]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [4]),
        .O(\gwdc.wr_data_count_i[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \gwdc.wr_data_count_i[7]_i_3 
       (.I0(Q[4]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [3]),
        .O(\gwdc.wr_data_count_i[7]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \gwdc.wr_data_count_i[7]_i_4 
       (.I0(Q[3]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [2]),
        .O(\gwdc.wr_data_count_i[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \gwdc.wr_data_count_i[7]_i_5 
       (.I0(Q[2]),
        .I1(\gwdc.wr_data_count_i_reg[7]_0 [1]),
        .O(\gwdc.wr_data_count_i[7]_i_5_n_0 ));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \gwdc.wr_data_count_i_reg[7]_i_1 
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({\NLW_gwdc.wr_data_count_i_reg[7]_i_1_CO_UNCONNECTED [7],\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_4 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_5 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_6 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_7 }),
        .DI({1'b0,\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 ,DI,Q[0]}),
        .O({D,\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED [3:0]}),
        .S({S[6:2],\gwdc.wr_data_count_i[7]_i_13_n_0 ,S[1:0]}));
endmodule

(* ORIG_REF_NAME = "xpm_counter_updn" *) 
module Loopback_axi_dma_1_0_xpm_counter_updn__parameterized3
   (Q,
    \count_value_i_reg[1]_0 ,
    rd_en,
    ram_empty_i,
    \count_value_i_reg[0]_0 ,
    E,
    wr_clk);
  output [6:0]Q;
  input [1:0]\count_value_i_reg[1]_0 ;
  input rd_en;
  input ram_empty_i;
  input [0:0]\count_value_i_reg[0]_0 ;
  input [0:0]E;
  input wr_clk;

  wire [0:0]E;
  wire [6:0]Q;
  wire \count_value_i[0]_i_1__2_n_0 ;
  wire \count_value_i[1]_i_1__2_n_0 ;
  wire \count_value_i[2]_i_1__2_n_0 ;
  wire \count_value_i[3]_i_1__2_n_0 ;
  wire \count_value_i[4]_i_1__2_n_0 ;
  wire \count_value_i[5]_i_1__2_n_0 ;
  wire \count_value_i[6]_i_1__2_n_0 ;
  wire \count_value_i[6]_i_2__2_n_0 ;
  wire [0:0]\count_value_i_reg[0]_0 ;
  wire [1:0]\count_value_i_reg[1]_0 ;
  wire ram_empty_i;
  wire rd_en;
  wire wr_clk;

  LUT4 #(
    .INIT(16'h10EF)) 
    \count_value_i[0]_i_1__2 
       (.I0(rd_en),
        .I1(\count_value_i_reg[1]_0 [0]),
        .I2(\count_value_i_reg[1]_0 [1]),
        .I3(Q[0]),
        .O(\count_value_i[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h02FFFD00)) 
    \count_value_i[1]_i_1__2 
       (.I0(\count_value_i_reg[1]_0 [1]),
        .I1(\count_value_i_reg[1]_0 [0]),
        .I2(rd_en),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\count_value_i[1]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \count_value_i[2]_i_1__2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(\count_value_i[2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \count_value_i[3]_i_1__2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(\count_value_i[3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[4]_i_1__2 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\count_value_i[4]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[5]_i_1__2 
       (.I0(Q[3]),
        .I1(\count_value_i[6]_i_2__2_n_0 ),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[5]),
        .O(\count_value_i[5]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \count_value_i[6]_i_1__2 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(\count_value_i[6]_i_2__2_n_0 ),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(Q[6]),
        .O(\count_value_i[6]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000AAA200000000)) 
    \count_value_i[6]_i_2__2 
       (.I0(Q[1]),
        .I1(\count_value_i_reg[1]_0 [1]),
        .I2(\count_value_i_reg[1]_0 [0]),
        .I3(rd_en),
        .I4(ram_empty_i),
        .I5(Q[0]),
        .O(\count_value_i[6]_i_2__2_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \count_value_i_reg[0] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[0]_i_1__2_n_0 ),
        .Q(Q[0]),
        .S(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[1] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[1]_i_1__2_n_0 ),
        .Q(Q[1]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[2] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[2]_i_1__2_n_0 ),
        .Q(Q[2]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[3] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[3]_i_1__2_n_0 ),
        .Q(Q[3]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[4] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[4]_i_1__2_n_0 ),
        .Q(Q[4]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[5] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[5]_i_1__2_n_0 ),
        .Q(Q[5]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[6] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[6]_i_1__2_n_0 ),
        .Q(Q[6]),
        .R(\count_value_i_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "xpm_counter_updn" *) 
module Loopback_axi_dma_1_0_xpm_counter_updn__parameterized3_14
   (Q,
    \count_value_i_reg[1]_0 ,
    rd_en,
    ram_empty_i,
    \count_value_i_reg[0]_0 ,
    E,
    rd_clk);
  output [6:0]Q;
  input [1:0]\count_value_i_reg[1]_0 ;
  input rd_en;
  input ram_empty_i;
  input [0:0]\count_value_i_reg[0]_0 ;
  input [0:0]E;
  input rd_clk;

  wire [0:0]E;
  wire [6:0]Q;
  wire \count_value_i[0]_i_1__2_n_0 ;
  wire \count_value_i[1]_i_1__2_n_0 ;
  wire \count_value_i[2]_i_1__2_n_0 ;
  wire \count_value_i[3]_i_1__2_n_0 ;
  wire \count_value_i[4]_i_1__2_n_0 ;
  wire \count_value_i[5]_i_1__2_n_0 ;
  wire \count_value_i[6]_i_1__2_n_0 ;
  wire \count_value_i[6]_i_2__2_n_0 ;
  wire [0:0]\count_value_i_reg[0]_0 ;
  wire [1:0]\count_value_i_reg[1]_0 ;
  wire ram_empty_i;
  wire rd_clk;
  wire rd_en;

  LUT4 #(
    .INIT(16'h10EF)) 
    \count_value_i[0]_i_1__2 
       (.I0(rd_en),
        .I1(\count_value_i_reg[1]_0 [0]),
        .I2(\count_value_i_reg[1]_0 [1]),
        .I3(Q[0]),
        .O(\count_value_i[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h02FFFD00)) 
    \count_value_i[1]_i_1__2 
       (.I0(\count_value_i_reg[1]_0 [1]),
        .I1(\count_value_i_reg[1]_0 [0]),
        .I2(rd_en),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\count_value_i[1]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \count_value_i[2]_i_1__2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(\count_value_i[2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \count_value_i[3]_i_1__2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(\count_value_i[3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[4]_i_1__2 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\count_value_i[4]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[5]_i_1__2 
       (.I0(Q[3]),
        .I1(\count_value_i[6]_i_2__2_n_0 ),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[5]),
        .O(\count_value_i[5]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \count_value_i[6]_i_1__2 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(\count_value_i[6]_i_2__2_n_0 ),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(Q[6]),
        .O(\count_value_i[6]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000AAA200000000)) 
    \count_value_i[6]_i_2__2 
       (.I0(Q[1]),
        .I1(\count_value_i_reg[1]_0 [1]),
        .I2(\count_value_i_reg[1]_0 [0]),
        .I3(rd_en),
        .I4(ram_empty_i),
        .I5(Q[0]),
        .O(\count_value_i[6]_i_2__2_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \count_value_i_reg[0] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[0]_i_1__2_n_0 ),
        .Q(Q[0]),
        .S(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[1] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[1]_i_1__2_n_0 ),
        .Q(Q[1]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[2] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[2]_i_1__2_n_0 ),
        .Q(Q[2]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[3] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[3]_i_1__2_n_0 ),
        .Q(Q[3]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[4] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[4]_i_1__2_n_0 ),
        .Q(Q[4]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[5] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[5]_i_1__2_n_0 ),
        .Q(Q[5]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[6] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[6]_i_1__2_n_0 ),
        .Q(Q[6]),
        .R(\count_value_i_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "xpm_counter_updn" *) 
module Loopback_axi_dma_1_0_xpm_counter_updn__parameterized3_17
   (Q,
    wr_en,
    \count_value_i_reg[5]_0 ,
    \count_value_i_reg[0]_0 ,
    rst_d1,
    E,
    rd_clk);
  output [6:0]Q;
  input wr_en;
  input \count_value_i_reg[5]_0 ;
  input [0:0]\count_value_i_reg[0]_0 ;
  input rst_d1;
  input [0:0]E;
  input rd_clk;

  wire [0:0]E;
  wire [6:0]Q;
  wire \count_value_i[0]_i_1__0_n_0 ;
  wire \count_value_i[1]_i_1__0_n_0 ;
  wire \count_value_i[2]_i_1__0_n_0 ;
  wire \count_value_i[3]_i_1__0_n_0 ;
  wire \count_value_i[4]_i_1__0_n_0 ;
  wire \count_value_i[5]_i_1_n_0 ;
  wire \count_value_i[6]_i_1_n_0 ;
  wire \count_value_i[6]_i_2_n_0 ;
  wire [0:0]\count_value_i_reg[0]_0 ;
  wire \count_value_i_reg[5]_0 ;
  wire rd_clk;
  wire rst_d1;
  wire wr_en;

  LUT1 #(
    .INIT(2'h1)) 
    \count_value_i[0]_i_1__0 
       (.I0(Q[0]),
        .O(\count_value_i[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \count_value_i[1]_i_1__0 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\count_value_i[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \count_value_i[2]_i_1__0 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(\count_value_i[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \count_value_i[3]_i_1__0 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(\count_value_i[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[4]_i_1__0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\count_value_i[4]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[5]_i_1 
       (.I0(Q[3]),
        .I1(\count_value_i[6]_i_2_n_0 ),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[5]),
        .O(\count_value_i[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \count_value_i[6]_i_1 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(\count_value_i[6]_i_2_n_0 ),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(Q[6]),
        .O(\count_value_i[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800000000)) 
    \count_value_i[6]_i_2 
       (.I0(Q[1]),
        .I1(wr_en),
        .I2(\count_value_i_reg[5]_0 ),
        .I3(\count_value_i_reg[0]_0 ),
        .I4(rst_d1),
        .I5(Q[0]),
        .O(\count_value_i[6]_i_2_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \count_value_i_reg[0] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[0]_i_1__0_n_0 ),
        .Q(Q[0]),
        .S(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[1] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[1]_i_1__0_n_0 ),
        .Q(Q[1]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[2] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[2]_i_1__0_n_0 ),
        .Q(Q[2]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[3] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[3]_i_1__0_n_0 ),
        .Q(Q[3]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[4] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[4]_i_1__0_n_0 ),
        .Q(Q[4]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[5] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[5]_i_1_n_0 ),
        .Q(Q[5]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[6] 
       (.C(rd_clk),
        .CE(E),
        .D(\count_value_i[6]_i_1_n_0 ),
        .Q(Q[6]),
        .R(\count_value_i_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "xpm_counter_updn" *) 
module Loopback_axi_dma_1_0_xpm_counter_updn__parameterized3_7
   (Q,
    wr_en,
    \count_value_i_reg[5]_0 ,
    \count_value_i_reg[0]_0 ,
    rst_d1,
    E,
    wr_clk);
  output [6:0]Q;
  input wr_en;
  input \count_value_i_reg[5]_0 ;
  input [0:0]\count_value_i_reg[0]_0 ;
  input rst_d1;
  input [0:0]E;
  input wr_clk;

  wire [0:0]E;
  wire [6:0]Q;
  wire \count_value_i[0]_i_1__0_n_0 ;
  wire \count_value_i[1]_i_1__0_n_0 ;
  wire \count_value_i[2]_i_1__0_n_0 ;
  wire \count_value_i[3]_i_1__0_n_0 ;
  wire \count_value_i[4]_i_1__0_n_0 ;
  wire \count_value_i[5]_i_1_n_0 ;
  wire \count_value_i[6]_i_1_n_0 ;
  wire \count_value_i[6]_i_2_n_0 ;
  wire [0:0]\count_value_i_reg[0]_0 ;
  wire \count_value_i_reg[5]_0 ;
  wire rst_d1;
  wire wr_clk;
  wire wr_en;

  LUT1 #(
    .INIT(2'h1)) 
    \count_value_i[0]_i_1__0 
       (.I0(Q[0]),
        .O(\count_value_i[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \count_value_i[1]_i_1__0 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\count_value_i[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \count_value_i[2]_i_1__0 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(\count_value_i[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \count_value_i[3]_i_1__0 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(\count_value_i[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[4]_i_1__0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\count_value_i[4]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \count_value_i[5]_i_1 
       (.I0(Q[3]),
        .I1(\count_value_i[6]_i_2_n_0 ),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[5]),
        .O(\count_value_i[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \count_value_i[6]_i_1 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(\count_value_i[6]_i_2_n_0 ),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(Q[6]),
        .O(\count_value_i[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800000000)) 
    \count_value_i[6]_i_2 
       (.I0(Q[1]),
        .I1(wr_en),
        .I2(\count_value_i_reg[5]_0 ),
        .I3(\count_value_i_reg[0]_0 ),
        .I4(rst_d1),
        .I5(Q[0]),
        .O(\count_value_i[6]_i_2_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \count_value_i_reg[0] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[0]_i_1__0_n_0 ),
        .Q(Q[0]),
        .S(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[1] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[1]_i_1__0_n_0 ),
        .Q(Q[1]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[2] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[2]_i_1__0_n_0 ),
        .Q(Q[2]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[3] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[3]_i_1__0_n_0 ),
        .Q(Q[3]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[4] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[4]_i_1__0_n_0 ),
        .Q(Q[4]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[5] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[5]_i_1_n_0 ),
        .Q(Q[5]),
        .R(\count_value_i_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \count_value_i_reg[6] 
       (.C(wr_clk),
        .CE(E),
        .D(\count_value_i[6]_i_1_n_0 ),
        .Q(Q[6]),
        .R(\count_value_i_reg[0]_0 ));
endmodule

(* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "2" *) (* COMMON_CLOCK = "1" *) 
(* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) 
(* EN_ADV_FEATURE = "16'b0001111100011111" *) (* EN_AE = "1'b1" *) (* EN_AF = "1'b1" *) 
(* EN_DVLD = "1'b1" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) 
(* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_SIM_ASSERT_ERR = "warning" *) 
(* EN_UF = "1'b1" *) (* EN_WACK = "1'b1" *) (* EN_WDC = "1'b1" *) 
(* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "0" *) (* FIFO_MEM_TYPE = "0" *) 
(* FIFO_READ_DEPTH = "128" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "4224" *) 
(* FIFO_WRITE_DEPTH = "128" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) 
(* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "123" *) (* PE_THRESH_MIN = "5" *) 
(* PF_THRESH_ADJ = "8" *) (* PF_THRESH_MAX = "123" *) (* PF_THRESH_MIN = "5" *) 
(* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "10" *) (* RD_DATA_COUNT_WIDTH = "4" *) 
(* RD_DC_WIDTH_EXT = "8" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) 
(* RD_PNTR_WIDTH = "7" *) (* READ_DATA_WIDTH = "33" *) (* READ_MODE = "1" *) 
(* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) 
(* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "1F1F" *) (* VERSION = "0" *) 
(* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "33" *) 
(* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "8" *) (* WR_DEPTH_LOG = "7" *) 
(* WR_PNTR_WIDTH = "7" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) 
(* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) 
(* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) 
module Loopback_axi_dma_1_0_xpm_fifo_base
   (sleep,
    rst,
    wr_clk,
    wr_en,
    din,
    full,
    full_n,
    prog_full,
    wr_data_count,
    overflow,
    wr_rst_busy,
    almost_full,
    wr_ack,
    rd_clk,
    rd_en,
    dout,
    empty,
    prog_empty,
    rd_data_count,
    underflow,
    rd_rst_busy,
    almost_empty,
    data_valid,
    injectsbiterr,
    injectdbiterr,
    sbiterr,
    dbiterr);
  input sleep;
  input rst;
  input wr_clk;
  input wr_en;
  input [32:0]din;
  output full;
  output full_n;
  output prog_full;
  output [7:0]wr_data_count;
  output overflow;
  output wr_rst_busy;
  output almost_full;
  output wr_ack;
  input rd_clk;
  input rd_en;
  output [32:0]dout;
  output empty;
  output prog_empty;
  output [3:0]rd_data_count;
  output underflow;
  output rd_rst_busy;
  output almost_empty;
  output data_valid;
  input injectsbiterr;
  input injectdbiterr;
  output sbiterr;
  output dbiterr;

  wire \<const0> ;
  wire clr_full;
  wire [1:0]curr_fwft_state;
  wire data_valid_fwft1;
  wire [32:0]din;
  wire [32:0]dout;
  wire empty;
  wire full;
  wire \gen_fwft.ram_regout_en ;
  wire leaving_empty0;
  wire [1:0]next_fwft_state__0;
  wire ram_empty_i;
  wire ram_empty_i0;
  wire ram_wr_en_pf;
  wire rd_clk;
  wire rd_en;
  wire [6:0]rd_pntr_ext;
  wire rdp_inst_n_8;
  wire rdp_inst_n_9;
  wire rdpp1_inst_n_0;
  wire rdpp1_inst_n_1;
  wire rdpp1_inst_n_2;
  wire rdpp1_inst_n_3;
  wire rdpp1_inst_n_4;
  wire rdpp1_inst_n_5;
  wire rdpp1_inst_n_6;
  wire rst;
  wire rst_d1;
  wire sleep;
  wire wr_en;
  wire [6:0]wr_pntr_ext;
  wire wrpp1_inst_n_0;
  wire wrpp1_inst_n_1;
  wire wrpp1_inst_n_2;
  wire wrpp1_inst_n_3;
  wire wrpp1_inst_n_4;
  wire wrpp1_inst_n_5;
  wire wrpp1_inst_n_6;
  wire xpm_fifo_rst_inst_n_1;
  wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ;
  wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ;
  wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ;
  wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ;
  wire [32:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ;

  assign almost_empty = \<const0> ;
  assign almost_full = \<const0> ;
  assign data_valid = \<const0> ;
  assign dbiterr = \<const0> ;
  assign full_n = \<const0> ;
  assign overflow = \<const0> ;
  assign prog_empty = \<const0> ;
  assign prog_full = \<const0> ;
  assign rd_data_count[3] = \<const0> ;
  assign rd_data_count[2] = \<const0> ;
  assign rd_data_count[1] = \<const0> ;
  assign rd_data_count[0] = \<const0> ;
  assign rd_rst_busy = \<const0> ;
  assign sbiterr = \<const0> ;
  assign underflow = \<const0> ;
  assign wr_ack = \<const0> ;
  assign wr_data_count[7] = \<const0> ;
  assign wr_data_count[6] = \<const0> ;
  assign wr_data_count[5] = \<const0> ;
  assign wr_data_count[4] = \<const0> ;
  assign wr_data_count[3] = \<const0> ;
  assign wr_data_count[2] = \<const0> ;
  assign wr_data_count[1] = \<const0> ;
  assign wr_data_count[0] = \<const0> ;
  assign wr_rst_busy = \<const0> ;
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT4 #(
    .INIT(16'h6A85)) 
    \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 
       (.I0(curr_fwft_state[0]),
        .I1(rd_en),
        .I2(curr_fwft_state[1]),
        .I3(ram_empty_i),
        .O(next_fwft_state__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT3 #(
    .INIT(8'h7C)) 
    \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 
       (.I0(rd_en),
        .I1(curr_fwft_state[1]),
        .I2(curr_fwft_state[0]),
        .O(next_fwft_state__0[1]));
  (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] 
       (.C(rd_clk),
        .CE(1'b1),
        .D(next_fwft_state__0[0]),
        .Q(curr_fwft_state[0]),
        .R(xpm_fifo_rst_inst_n_1));
  (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] 
       (.C(rd_clk),
        .CE(1'b1),
        .D(next_fwft_state__0[1]),
        .Q(curr_fwft_state[1]),
        .R(xpm_fifo_rst_inst_n_1));
  GND GND
       (.G(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT4 #(
    .INIT(16'hF380)) 
    \gen_fwft.empty_fwft_i_i_1 
       (.I0(rd_en),
        .I1(curr_fwft_state[0]),
        .I2(curr_fwft_state[1]),
        .I3(empty),
        .O(data_valid_fwft1));
  FDSE #(
    .INIT(1'b1)) 
    \gen_fwft.empty_fwft_i_reg 
       (.C(rd_clk),
        .CE(1'b1),
        .D(data_valid_fwft1),
        .Q(empty),
        .S(xpm_fifo_rst_inst_n_1));
  FDSE #(
    .INIT(1'b1)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg 
       (.C(rd_clk),
        .CE(1'b1),
        .D(rdp_inst_n_8),
        .Q(full),
        .S(xpm_fifo_rst_inst_n_1));
  FDSE #(
    .INIT(1'b1)) 
    \gen_pntr_flags_cc.ram_empty_i_reg 
       (.C(rd_clk),
        .CE(1'b1),
        .D(ram_empty_i0),
        .Q(ram_empty_i),
        .S(xpm_fifo_rst_inst_n_1));
  (* ADDR_WIDTH_A = "7" *) 
  (* ADDR_WIDTH_B = "7" *) 
  (* AUTO_SLEEP_TIME = "0" *) 
  (* BYTE_WRITE_WIDTH_A = "33" *) 
  (* BYTE_WRITE_WIDTH_B = "33" *) 
  (* CASCADE_HEIGHT = "0" *) 
  (* CLOCKING_MODE = "0" *) 
  (* ECC_BIT_RANGE = "[7:0]" *) 
  (* ECC_MODE = "0" *) 
  (* ECC_TYPE = "NONE" *) 
  (* IGNORE_INIT_SYNTH = "0" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* MAX_NUM_CHAR = "0" *) 
  (* MEMORY_INIT_FILE = "none" *) 
  (* MEMORY_INIT_PARAM = "" *) 
  (* MEMORY_OPTIMIZATION = "true" *) 
  (* MEMORY_PRIMITIVE = "0" *) 
  (* MEMORY_SIZE = "4224" *) 
  (* MEMORY_TYPE = "1" *) 
  (* MESSAGE_CONTROL = "0" *) 
  (* NUM_CHAR_LOC = "0" *) 
  (* P_ECC_MODE = "no_ecc" *) 
  (* P_ENABLE_BYTE_WRITE_A = "0" *) 
  (* P_ENABLE_BYTE_WRITE_B = "0" *) 
  (* P_MAX_DEPTH_DATA = "128" *) 
  (* P_MEMORY_OPT = "yes" *) 
  (* P_MEMORY_PRIMITIVE = "auto" *) 
  (* P_MIN_WIDTH_DATA = "33" *) 
  (* P_MIN_WIDTH_DATA_A = "33" *) 
  (* P_MIN_WIDTH_DATA_B = "33" *) 
  (* P_MIN_WIDTH_DATA_ECC = "33" *) 
  (* P_MIN_WIDTH_DATA_LDW = "4" *) 
  (* P_MIN_WIDTH_DATA_SHFT = "33" *) 
  (* P_NUM_COLS_WRITE_A = "1" *) 
  (* P_NUM_COLS_WRITE_B = "1" *) 
  (* P_NUM_ROWS_READ_A = "1" *) 
  (* P_NUM_ROWS_READ_B = "1" *) 
  (* P_NUM_ROWS_WRITE_A = "1" *) 
  (* P_NUM_ROWS_WRITE_B = "1" *) 
  (* P_SDP_WRITE_MODE = "yes" *) 
  (* P_WIDTH_ADDR_LSB_READ_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) 
  (* P_WIDTH_ADDR_READ_A = "7" *) 
  (* P_WIDTH_ADDR_READ_B = "7" *) 
  (* P_WIDTH_ADDR_WRITE_A = "7" *) 
  (* P_WIDTH_ADDR_WRITE_B = "7" *) 
  (* P_WIDTH_COL_WRITE_A = "33" *) 
  (* P_WIDTH_COL_WRITE_B = "33" *) 
  (* RAM_DECOMP = "auto" *) 
  (* READ_DATA_WIDTH_A = "33" *) 
  (* READ_DATA_WIDTH_B = "33" *) 
  (* READ_LATENCY_A = "2" *) 
  (* READ_LATENCY_B = "2" *) 
  (* READ_RESET_VALUE_A = "0" *) 
  (* READ_RESET_VALUE_B = "0" *) 
  (* RST_MODE_A = "SYNC" *) 
  (* RST_MODE_B = "SYNC" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_EMBEDDED_CONSTRAINT = "0" *) 
  (* USE_MEM_INIT = "0" *) 
  (* USE_MEM_INIT_MMI = "0" *) 
  (* VERSION = "0" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WRITE_DATA_WIDTH_A = "33" *) 
  (* WRITE_DATA_WIDTH_B = "33" *) 
  (* WRITE_MODE_A = "2" *) 
  (* WRITE_MODE_B = "2" *) 
  (* WRITE_PROTECT = "1" *) 
  (* XPM_MODULE = "TRUE" *) 
  (* rsta_loop_iter = "36" *) 
  (* rstb_loop_iter = "36" *) 
  Loopback_axi_dma_1_0_xpm_memory_base \gen_sdpram.xpm_memory_base_inst 
       (.addra(wr_pntr_ext),
        .addrb(rd_pntr_ext),
        .clka(rd_clk),
        .clkb(1'b0),
        .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ),
        .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ),
        .dina(din),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [32:0]),
        .doutb(dout),
        .ena(1'b0),
        .enb(rdp_inst_n_9),
        .injectdbiterra(1'b0),
        .injectdbiterrb(1'b0),
        .injectsbiterra(1'b0),
        .injectsbiterrb(1'b0),
        .regcea(1'b0),
        .regceb(\gen_fwft.ram_regout_en ),
        .rsta(1'b0),
        .rstb(xpm_fifo_rst_inst_n_1),
        .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ),
        .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ),
        .sleep(sleep),
        .wea(ram_wr_en_pf),
        .web(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT3 #(
    .INIT(8'h62)) 
    \gen_sdpram.xpm_memory_base_inst_i_3 
       (.I0(curr_fwft_state[0]),
        .I1(curr_fwft_state[1]),
        .I2(rd_en),
        .O(\gen_fwft.ram_regout_en ));
  Loopback_axi_dma_1_0_xpm_counter_updn__parameterized2_13 rdp_inst
       (.E(ram_wr_en_pf),
        .Q(rd_pntr_ext),
        .clr_full(clr_full),
        .\count_value_i_reg[0]_0 (curr_fwft_state),
        .\count_value_i_reg[0]_1 (xpm_fifo_rst_inst_n_1),
        .enb(rdp_inst_n_9),
        .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg (rdp_inst_n_8),
        .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 (wr_pntr_ext),
        .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 ({wrpp1_inst_n_0,wrpp1_inst_n_1,wrpp1_inst_n_2,wrpp1_inst_n_3,wrpp1_inst_n_4,wrpp1_inst_n_5,wrpp1_inst_n_6}),
        .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_2 (full),
        .leaving_empty0(leaving_empty0),
        .ram_empty_i(ram_empty_i),
        .rd_clk(rd_clk),
        .rd_en(rd_en));
  Loopback_axi_dma_1_0_xpm_counter_updn__parameterized3_14 rdpp1_inst
       (.E(rdp_inst_n_9),
        .Q({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6}),
        .\count_value_i_reg[0]_0 (xpm_fifo_rst_inst_n_1),
        .\count_value_i_reg[1]_0 (curr_fwft_state),
        .ram_empty_i(ram_empty_i),
        .rd_clk(rd_clk),
        .rd_en(rd_en));
  Loopback_axi_dma_1_0_xpm_fifo_reg_bit_15 rst_d1_inst
       (.Q(xpm_fifo_rst_inst_n_1),
        .clr_full(clr_full),
        .rd_clk(rd_clk),
        .rst(rst),
        .rst_d1(rst_d1));
  Loopback_axi_dma_1_0_xpm_counter_updn__parameterized2_16 wrp_inst
       (.E(ram_wr_en_pf),
        .Q(wr_pntr_ext),
        .\count_value_i_reg[5]_0 (full),
        .\count_value_i_reg[6]_0 (xpm_fifo_rst_inst_n_1),
        .enb(rdp_inst_n_9),
        .\gen_pntr_flags_cc.ram_empty_i_reg ({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6}),
        .leaving_empty0(leaving_empty0),
        .ram_empty_i(ram_empty_i),
        .ram_empty_i0(ram_empty_i0),
        .rd_clk(rd_clk),
        .rst_d1(rst_d1),
        .wr_en(wr_en));
  Loopback_axi_dma_1_0_xpm_counter_updn__parameterized3_17 wrpp1_inst
       (.E(ram_wr_en_pf),
        .Q({wrpp1_inst_n_0,wrpp1_inst_n_1,wrpp1_inst_n_2,wrpp1_inst_n_3,wrpp1_inst_n_4,wrpp1_inst_n_5,wrpp1_inst_n_6}),
        .\count_value_i_reg[0]_0 (xpm_fifo_rst_inst_n_1),
        .\count_value_i_reg[5]_0 (full),
        .rd_clk(rd_clk),
        .rst_d1(rst_d1),
        .wr_en(wr_en));
  Loopback_axi_dma_1_0_xpm_fifo_rst_18 xpm_fifo_rst_inst
       (.E(ram_wr_en_pf),
        .Q(xpm_fifo_rst_inst_n_1),
        .\count_value_i_reg[6] (full),
        .rd_clk(rd_clk),
        .rst(rst),
        .rst_d1(rst_d1),
        .wr_en(wr_en));
endmodule

(* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "2" *) (* COMMON_CLOCK = "1" *) 
(* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) 
(* EN_ADV_FEATURE = "16'b0001111100011111" *) (* EN_AE = "1'b1" *) (* EN_AF = "1'b1" *) 
(* EN_DVLD = "1'b1" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) 
(* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_SIM_ASSERT_ERR = "warning" *) 
(* EN_UF = "1'b1" *) (* EN_WACK = "1'b1" *) (* EN_WDC = "1'b1" *) 
(* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) 
(* FIFO_READ_DEPTH = "128" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "4992" *) 
(* FIFO_WRITE_DEPTH = "128" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) 
(* ORIG_REF_NAME = "xpm_fifo_base" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "123" *) 
(* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "8" *) (* PF_THRESH_MAX = "123" *) 
(* PF_THRESH_MIN = "5" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "10" *) 
(* RD_DATA_COUNT_WIDTH = "4" *) (* RD_DC_WIDTH_EXT = "8" *) (* RD_LATENCY = "2" *) 
(* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "7" *) (* READ_DATA_WIDTH = "39" *) 
(* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) 
(* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "1F1F" *) 
(* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) 
(* WRITE_DATA_WIDTH = "39" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "8" *) 
(* WR_DEPTH_LOG = "7" *) (* WR_PNTR_WIDTH = "7" *) (* WR_RD_RATIO = "0" *) 
(* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) 
(* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) 
(* stage2_valid = "1" *) 
module Loopback_axi_dma_1_0_xpm_fifo_base__parameterized0
   (sleep,
    rst,
    wr_clk,
    wr_en,
    din,
    full,
    full_n,
    prog_full,
    wr_data_count,
    overflow,
    wr_rst_busy,
    almost_full,
    wr_ack,
    rd_clk,
    rd_en,
    dout,
    empty,
    prog_empty,
    rd_data_count,
    underflow,
    rd_rst_busy,
    almost_empty,
    data_valid,
    injectsbiterr,
    injectdbiterr,
    sbiterr,
    dbiterr);
  input sleep;
  input rst;
  input wr_clk;
  input wr_en;
  input [38:0]din;
  output full;
  output full_n;
  output prog_full;
  output [7:0]wr_data_count;
  output overflow;
  output wr_rst_busy;
  output almost_full;
  output wr_ack;
  input rd_clk;
  input rd_en;
  output [38:0]dout;
  output empty;
  output prog_empty;
  output [3:0]rd_data_count;
  output underflow;
  output rd_rst_busy;
  output almost_empty;
  output data_valid;
  input injectsbiterr;
  input injectdbiterr;
  output sbiterr;
  output dbiterr;

  wire \<const0> ;
  wire clr_full;
  wire [1:1]count_value_i;
  wire [1:0]curr_fwft_state;
  wire data_valid_fwft1;
  wire [38:0]din;
  wire [37:0]\^dout ;
  wire empty;
  wire full;
  wire \gen_fwft.count_rst ;
  wire \gen_fwft.ram_regout_en ;
  wire \gen_fwft.rdpp1_inst_n_1 ;
  wire \gen_fwft.rdpp1_inst_n_2 ;
  wire \gen_fwft.rdpp1_inst_n_3 ;
  wire [7:4]\grdc.diff_wr_rd_pntr_rdc ;
  wire leaving_empty0;
  wire [1:0]next_fwft_state__0;
  wire ram_empty_i;
  wire ram_empty_i0;
  wire ram_wr_en_pf;
  wire rd_en;
  wire [6:0]rd_pntr_ext;
  wire rdp_inst_n_0;
  wire rdp_inst_n_10;
  wire rdp_inst_n_11;
  wire rdp_inst_n_12;
  wire rdp_inst_n_13;
  wire rdp_inst_n_15;
  wire rdp_inst_n_8;
  wire rdp_inst_n_9;
  wire rdpp1_inst_n_0;
  wire rdpp1_inst_n_1;
  wire rdpp1_inst_n_2;
  wire rdpp1_inst_n_3;
  wire rdpp1_inst_n_4;
  wire rdpp1_inst_n_5;
  wire rdpp1_inst_n_6;
  wire rst;
  wire rst_d1;
  wire sleep;
  wire wr_clk;
  wire [7:4]\^wr_data_count ;
  wire wr_en;
  wire [6:0]wr_pntr_ext;
  wire wrp_inst_n_1;
  wire wrpp1_inst_n_0;
  wire wrpp1_inst_n_1;
  wire wrpp1_inst_n_2;
  wire wrpp1_inst_n_3;
  wire wrpp1_inst_n_4;
  wire wrpp1_inst_n_5;
  wire wrpp1_inst_n_6;
  wire xpm_fifo_rst_inst_n_1;
  wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ;
  wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ;
  wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ;
  wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ;
  wire [38:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ;
  wire [38:38]\NLW_gen_sdpram.xpm_memory_base_inst_doutb_UNCONNECTED ;

  assign almost_empty = \<const0> ;
  assign almost_full = \<const0> ;
  assign data_valid = \<const0> ;
  assign dbiterr = \<const0> ;
  assign dout[38] = \<const0> ;
  assign dout[37:0] = \^dout [37:0];
  assign full_n = \<const0> ;
  assign overflow = \<const0> ;
  assign prog_empty = \<const0> ;
  assign prog_full = \<const0> ;
  assign rd_data_count[3] = \<const0> ;
  assign rd_data_count[2] = \<const0> ;
  assign rd_data_count[1] = \<const0> ;
  assign rd_data_count[0] = \<const0> ;
  assign rd_rst_busy = \<const0> ;
  assign sbiterr = \<const0> ;
  assign underflow = \<const0> ;
  assign wr_ack = \<const0> ;
  assign wr_data_count[7:4] = \^wr_data_count [7:4];
  assign wr_data_count[3] = \<const0> ;
  assign wr_data_count[2] = \<const0> ;
  assign wr_data_count[1] = \<const0> ;
  assign wr_data_count[0] = \<const0> ;
  assign wr_rst_busy = \<const0> ;
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT4 #(
    .INIT(16'h6A85)) 
    \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 
       (.I0(curr_fwft_state[0]),
        .I1(rd_en),
        .I2(curr_fwft_state[1]),
        .I3(ram_empty_i),
        .O(next_fwft_state__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT3 #(
    .INIT(8'h7C)) 
    \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 
       (.I0(rd_en),
        .I1(curr_fwft_state[1]),
        .I2(curr_fwft_state[0]),
        .O(next_fwft_state__0[1]));
  (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] 
       (.C(wr_clk),
        .CE(1'b1),
        .D(next_fwft_state__0[0]),
        .Q(curr_fwft_state[0]),
        .R(xpm_fifo_rst_inst_n_1));
  (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] 
       (.C(wr_clk),
        .CE(1'b1),
        .D(next_fwft_state__0[1]),
        .Q(curr_fwft_state[1]),
        .R(xpm_fifo_rst_inst_n_1));
  GND GND
       (.G(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT4 #(
    .INIT(16'hF380)) 
    \gen_fwft.empty_fwft_i_i_1 
       (.I0(rd_en),
        .I1(curr_fwft_state[0]),
        .I2(curr_fwft_state[1]),
        .I3(empty),
        .O(data_valid_fwft1));
  FDSE #(
    .INIT(1'b1)) 
    \gen_fwft.empty_fwft_i_reg 
       (.C(wr_clk),
        .CE(1'b1),
        .D(data_valid_fwft1),
        .Q(empty),
        .S(xpm_fifo_rst_inst_n_1));
  Loopback_axi_dma_1_0_xpm_counter_updn__parameterized1 \gen_fwft.rdpp1_inst 
       (.DI(\gen_fwft.rdpp1_inst_n_3 ),
        .Q(count_value_i),
        .S({\gen_fwft.rdpp1_inst_n_1 ,\gen_fwft.rdpp1_inst_n_2 }),
        .SR(\gen_fwft.count_rst ),
        .\count_value_i_reg[0]_0 (curr_fwft_state),
        .\gwdc.wr_data_count_i_reg[7] (rd_pntr_ext[1:0]),
        .\gwdc.wr_data_count_i_reg[7]_0 (wr_pntr_ext[1:0]),
        .ram_empty_i(ram_empty_i),
        .rd_en(rd_en),
        .wr_clk(wr_clk));
  FDSE #(
    .INIT(1'b1)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg 
       (.C(wr_clk),
        .CE(1'b1),
        .D(rdp_inst_n_15),
        .Q(full),
        .S(xpm_fifo_rst_inst_n_1));
  FDSE #(
    .INIT(1'b1)) 
    \gen_pntr_flags_cc.ram_empty_i_reg 
       (.C(wr_clk),
        .CE(1'b1),
        .D(ram_empty_i0),
        .Q(ram_empty_i),
        .S(xpm_fifo_rst_inst_n_1));
  (* ADDR_WIDTH_A = "7" *) 
  (* ADDR_WIDTH_B = "7" *) 
  (* AUTO_SLEEP_TIME = "0" *) 
  (* BYTE_WRITE_WIDTH_A = "39" *) 
  (* BYTE_WRITE_WIDTH_B = "39" *) 
  (* CASCADE_HEIGHT = "0" *) 
  (* CLOCKING_MODE = "0" *) 
  (* ECC_BIT_RANGE = "[7:0]" *) 
  (* ECC_MODE = "0" *) 
  (* ECC_TYPE = "NONE" *) 
  (* IGNORE_INIT_SYNTH = "0" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* MAX_NUM_CHAR = "0" *) 
  (* \MEM.ADDRESS_SPACE  *) 
  (* \MEM.ADDRESS_SPACE_BEGIN  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_LSB  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_MSB  = "37" *) 
  (* \MEM.ADDRESS_SPACE_END  = "511" *) 
  (* \MEM.CORE_MEMORY_WIDTH  = "38" *) 
  (* MEMORY_INIT_FILE = "none" *) 
  (* MEMORY_INIT_PARAM = "" *) 
  (* MEMORY_OPTIMIZATION = "true" *) 
  (* MEMORY_PRIMITIVE = "2" *) 
  (* MEMORY_SIZE = "4992" *) 
  (* MEMORY_TYPE = "1" *) 
  (* MESSAGE_CONTROL = "0" *) 
  (* NUM_CHAR_LOC = "0" *) 
  (* P_ECC_MODE = "no_ecc" *) 
  (* P_ENABLE_BYTE_WRITE_A = "0" *) 
  (* P_ENABLE_BYTE_WRITE_B = "0" *) 
  (* P_MAX_DEPTH_DATA = "128" *) 
  (* P_MEMORY_OPT = "yes" *) 
  (* P_MEMORY_PRIMITIVE = "block" *) 
  (* P_MIN_WIDTH_DATA = "39" *) 
  (* P_MIN_WIDTH_DATA_A = "39" *) 
  (* P_MIN_WIDTH_DATA_B = "39" *) 
  (* P_MIN_WIDTH_DATA_ECC = "39" *) 
  (* P_MIN_WIDTH_DATA_LDW = "4" *) 
  (* P_MIN_WIDTH_DATA_SHFT = "39" *) 
  (* P_NUM_COLS_WRITE_A = "1" *) 
  (* P_NUM_COLS_WRITE_B = "1" *) 
  (* P_NUM_ROWS_READ_A = "1" *) 
  (* P_NUM_ROWS_READ_B = "1" *) 
  (* P_NUM_ROWS_WRITE_A = "1" *) 
  (* P_NUM_ROWS_WRITE_B = "1" *) 
  (* P_SDP_WRITE_MODE = "no" *) 
  (* P_WIDTH_ADDR_LSB_READ_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) 
  (* P_WIDTH_ADDR_READ_A = "7" *) 
  (* P_WIDTH_ADDR_READ_B = "7" *) 
  (* P_WIDTH_ADDR_WRITE_A = "7" *) 
  (* P_WIDTH_ADDR_WRITE_B = "7" *) 
  (* P_WIDTH_COL_WRITE_A = "39" *) 
  (* P_WIDTH_COL_WRITE_B = "39" *) 
  (* RAM_DECOMP = "auto" *) 
  (* READ_DATA_WIDTH_A = "39" *) 
  (* READ_DATA_WIDTH_B = "39" *) 
  (* READ_LATENCY_A = "2" *) 
  (* READ_LATENCY_B = "2" *) 
  (* READ_RESET_VALUE_A = "0" *) 
  (* READ_RESET_VALUE_B = "0" *) 
  (* RST_MODE_A = "SYNC" *) 
  (* RST_MODE_B = "SYNC" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_EMBEDDED_CONSTRAINT = "0" *) 
  (* USE_MEM_INIT = "0" *) 
  (* USE_MEM_INIT_MMI = "0" *) 
  (* VERSION = "0" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WRITE_DATA_WIDTH_A = "39" *) 
  (* WRITE_DATA_WIDTH_B = "39" *) 
  (* WRITE_MODE_A = "2" *) 
  (* WRITE_MODE_B = "2" *) 
  (* WRITE_PROTECT = "1" *) 
  (* XPM_MODULE = "TRUE" *) 
  (* rsta_loop_iter = "40" *) 
  (* rstb_loop_iter = "40" *) 
  Loopback_axi_dma_1_0_xpm_memory_base__parameterized0 \gen_sdpram.xpm_memory_base_inst 
       (.addra(wr_pntr_ext),
        .addrb(rd_pntr_ext),
        .clka(wr_clk),
        .clkb(1'b0),
        .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ),
        .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ),
        .dina({1'b0,din[37:0]}),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [38:0]),
        .doutb({\NLW_gen_sdpram.xpm_memory_base_inst_doutb_UNCONNECTED [38],\^dout }),
        .ena(1'b0),
        .enb(rdp_inst_n_13),
        .injectdbiterra(1'b0),
        .injectdbiterrb(1'b0),
        .injectsbiterra(1'b0),
        .injectsbiterrb(1'b0),
        .regcea(1'b0),
        .regceb(\gen_fwft.ram_regout_en ),
        .rsta(1'b0),
        .rstb(xpm_fifo_rst_inst_n_1),
        .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ),
        .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ),
        .sleep(sleep),
        .wea(ram_wr_en_pf),
        .web(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT3 #(
    .INIT(8'h62)) 
    \gen_sdpram.xpm_memory_base_inst_i_3 
       (.I0(curr_fwft_state[0]),
        .I1(curr_fwft_state[1]),
        .I2(rd_en),
        .O(\gen_fwft.ram_regout_en ));
  FDRE \gwdc.wr_data_count_i_reg[4] 
       (.C(wr_clk),
        .CE(1'b1),
        .D(\grdc.diff_wr_rd_pntr_rdc [4]),
        .Q(\^wr_data_count [4]),
        .R(xpm_fifo_rst_inst_n_1));
  FDRE \gwdc.wr_data_count_i_reg[5] 
       (.C(wr_clk),
        .CE(1'b1),
        .D(\grdc.diff_wr_rd_pntr_rdc [5]),
        .Q(\^wr_data_count [5]),
        .R(xpm_fifo_rst_inst_n_1));
  FDRE \gwdc.wr_data_count_i_reg[6] 
       (.C(wr_clk),
        .CE(1'b1),
        .D(\grdc.diff_wr_rd_pntr_rdc [6]),
        .Q(\^wr_data_count [6]),
        .R(xpm_fifo_rst_inst_n_1));
  FDRE \gwdc.wr_data_count_i_reg[7] 
       (.C(wr_clk),
        .CE(1'b1),
        .D(\grdc.diff_wr_rd_pntr_rdc [7]),
        .Q(\^wr_data_count [7]),
        .R(xpm_fifo_rst_inst_n_1));
  Loopback_axi_dma_1_0_xpm_counter_updn__parameterized2 rdp_inst
       (.DI(rdp_inst_n_0),
        .\FSM_sequential_gen_fwft.curr_fwft_state_reg[1] (rdp_inst_n_13),
        .Q(rd_pntr_ext),
        .S({rdp_inst_n_8,rdp_inst_n_9,rdp_inst_n_10,rdp_inst_n_11,rdp_inst_n_12}),
        .clr_full(clr_full),
        .\count_value_i_reg[0]_0 (curr_fwft_state),
        .\count_value_i_reg[0]_1 (xpm_fifo_rst_inst_n_1),
        .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg (rdp_inst_n_15),
        .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0 ({wrpp1_inst_n_0,wrpp1_inst_n_1,wrpp1_inst_n_2,wrpp1_inst_n_3,wrpp1_inst_n_4,wrpp1_inst_n_5,wrpp1_inst_n_6}),
        .\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1 (full),
        .\gwdc.wr_data_count_i_reg[7] (count_value_i),
        .\gwdc.wr_data_count_i_reg[7]_0 ({wrp_inst_n_1,wr_pntr_ext}),
        .leaving_empty0(leaving_empty0),
        .ram_empty_i(ram_empty_i),
        .ram_wr_en_pf(ram_wr_en_pf),
        .rd_en(rd_en),
        .wr_clk(wr_clk));
  Loopback_axi_dma_1_0_xpm_counter_updn__parameterized3 rdpp1_inst
       (.E(rdp_inst_n_13),
        .Q({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6}),
        .\count_value_i_reg[0]_0 (xpm_fifo_rst_inst_n_1),
        .\count_value_i_reg[1]_0 (curr_fwft_state),
        .ram_empty_i(ram_empty_i),
        .rd_en(rd_en),
        .wr_clk(wr_clk));
  Loopback_axi_dma_1_0_xpm_fifo_reg_bit rst_d1_inst
       (.Q(xpm_fifo_rst_inst_n_1),
        .clr_full(clr_full),
        .rst(rst),
        .rst_d1(rst_d1),
        .wr_clk(wr_clk));
  Loopback_axi_dma_1_0_xpm_counter_updn__parameterized2_6 wrp_inst
       (.D(\grdc.diff_wr_rd_pntr_rdc ),
        .DI({rdp_inst_n_0,\gen_fwft.rdpp1_inst_n_3 }),
        .Q({wrp_inst_n_1,wr_pntr_ext}),
        .S({rdp_inst_n_8,rdp_inst_n_9,rdp_inst_n_10,rdp_inst_n_11,rdp_inst_n_12,\gen_fwft.rdpp1_inst_n_1 ,\gen_fwft.rdpp1_inst_n_2 }),
        .\count_value_i_reg[5]_0 (full),
        .\count_value_i_reg[7]_0 (xpm_fifo_rst_inst_n_1),
        .\gen_pntr_flags_cc.ram_empty_i_reg (rdp_inst_n_13),
        .\gen_pntr_flags_cc.ram_empty_i_reg_0 ({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6}),
        .\gwdc.wr_data_count_i_reg[7] (count_value_i),
        .\gwdc.wr_data_count_i_reg[7]_0 (rd_pntr_ext[5:1]),
        .leaving_empty0(leaving_empty0),
        .ram_empty_i(ram_empty_i),
        .ram_empty_i0(ram_empty_i0),
        .ram_wr_en_pf(ram_wr_en_pf),
        .rst_d1(rst_d1),
        .wr_clk(wr_clk),
        .wr_en(wr_en));
  Loopback_axi_dma_1_0_xpm_counter_updn__parameterized3_7 wrpp1_inst
       (.E(ram_wr_en_pf),
        .Q({wrpp1_inst_n_0,wrpp1_inst_n_1,wrpp1_inst_n_2,wrpp1_inst_n_3,wrpp1_inst_n_4,wrpp1_inst_n_5,wrpp1_inst_n_6}),
        .\count_value_i_reg[0]_0 (xpm_fifo_rst_inst_n_1),
        .\count_value_i_reg[5]_0 (full),
        .rst_d1(rst_d1),
        .wr_clk(wr_clk),
        .wr_en(wr_en));
  Loopback_axi_dma_1_0_xpm_fifo_rst xpm_fifo_rst_inst
       (.E(ram_wr_en_pf),
        .Q(xpm_fifo_rst_inst_n_1),
        .SR(\gen_fwft.count_rst ),
        .\count_value_i_reg[1] (curr_fwft_state),
        .\count_value_i_reg[6] (full),
        .ram_empty_i(ram_empty_i),
        .rst(rst),
        .rst_d1(rst_d1),
        .wr_clk(wr_clk),
        .wr_en(wr_en));
endmodule

module Loopback_axi_dma_1_0_xpm_fifo_reg_bit
   (rst_d1,
    clr_full,
    Q,
    wr_clk,
    rst);
  output rst_d1;
  output clr_full;
  input [0:0]Q;
  input wr_clk;
  input rst;

  wire [0:0]Q;
  wire clr_full;
  wire rst;
  wire rst_d1;
  wire wr_clk;

  FDRE #(
    .INIT(1'b0)) 
    d_out_int_reg
       (.C(wr_clk),
        .CE(1'b1),
        .D(Q),
        .Q(rst_d1),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h04)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_4 
       (.I0(rst),
        .I1(rst_d1),
        .I2(Q),
        .O(clr_full));
endmodule

(* ORIG_REF_NAME = "xpm_fifo_reg_bit" *) 
module Loopback_axi_dma_1_0_xpm_fifo_reg_bit_15
   (rst_d1,
    clr_full,
    Q,
    rd_clk,
    rst);
  output rst_d1;
  output clr_full;
  input [0:0]Q;
  input rd_clk;
  input rst;

  wire [0:0]Q;
  wire clr_full;
  wire rd_clk;
  wire rst;
  wire rst_d1;

  FDRE #(
    .INIT(1'b0)) 
    d_out_int_reg
       (.C(rd_clk),
        .CE(1'b1),
        .D(Q),
        .Q(rst_d1),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h04)) 
    \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_4 
       (.I0(rst),
        .I1(rst_d1),
        .I2(Q),
        .O(clr_full));
endmodule

module Loopback_axi_dma_1_0_xpm_fifo_rst
   (E,
    Q,
    SR,
    rst,
    wr_en,
    \count_value_i_reg[6] ,
    rst_d1,
    ram_empty_i,
    \count_value_i_reg[1] ,
    wr_clk);
  output [0:0]E;
  output [0:0]Q;
  output [0:0]SR;
  input rst;
  input wr_en;
  input \count_value_i_reg[6] ;
  input rst_d1;
  input ram_empty_i;
  input [1:0]\count_value_i_reg[1] ;
  input wr_clk;

  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [1:0]\count_value_i_reg[1] ;
  wire \count_value_i_reg[6] ;
  wire [1:0]\gen_rst_cc.fifo_wr_rst_cc ;
  wire p_0_in;
  wire \power_on_rst_reg_n_0_[0] ;
  wire ram_empty_i;
  wire rst;
  wire rst_d1;
  wire rst_i;
  wire wr_clk;
  wire wr_en;

  LUT4 #(
    .INIT(16'hAAAE)) 
    \count_value_i[1]_i_1__3 
       (.I0(Q),
        .I1(ram_empty_i),
        .I2(\count_value_i_reg[1] [1]),
        .I3(\count_value_i_reg[1] [0]),
        .O(SR));
  LUT2 #(
    .INIT(4'hE)) 
    \gen_rst_cc.fifo_wr_rst_cc[2]_i_1 
       (.I0(p_0_in),
        .I1(rst),
        .O(rst_i));
  FDSE #(
    .INIT(1'b0)) 
    \gen_rst_cc.fifo_wr_rst_cc_reg[0] 
       (.C(wr_clk),
        .CE(1'b1),
        .D(1'b0),
        .Q(\gen_rst_cc.fifo_wr_rst_cc [0]),
        .S(rst_i));
  FDSE #(
    .INIT(1'b0)) 
    \gen_rst_cc.fifo_wr_rst_cc_reg[1] 
       (.C(wr_clk),
        .CE(1'b1),
        .D(\gen_rst_cc.fifo_wr_rst_cc [0]),
        .Q(\gen_rst_cc.fifo_wr_rst_cc [1]),
        .S(rst_i));
  FDSE #(
    .INIT(1'b0)) 
    \gen_rst_cc.fifo_wr_rst_cc_reg[2] 
       (.C(wr_clk),
        .CE(1'b1),
        .D(\gen_rst_cc.fifo_wr_rst_cc [1]),
        .Q(Q),
        .S(rst_i));
  LUT4 #(
    .INIT(16'h0002)) 
    \gen_sdpram.xpm_memory_base_inst_i_1 
       (.I0(wr_en),
        .I1(\count_value_i_reg[6] ),
        .I2(Q),
        .I3(rst_d1),
        .O(E));
  FDRE #(
    .INIT(1'b1)) 
    \power_on_rst_reg[0] 
       (.C(wr_clk),
        .CE(1'b1),
        .D(1'b0),
        .Q(\power_on_rst_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \power_on_rst_reg[1] 
       (.C(wr_clk),
        .CE(1'b1),
        .D(\power_on_rst_reg_n_0_[0] ),
        .Q(p_0_in),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xpm_fifo_rst" *) 
module Loopback_axi_dma_1_0_xpm_fifo_rst_18
   (E,
    Q,
    rst,
    wr_en,
    \count_value_i_reg[6] ,
    rst_d1,
    rd_clk);
  output [0:0]E;
  output [0:0]Q;
  input rst;
  input wr_en;
  input \count_value_i_reg[6] ;
  input rst_d1;
  input rd_clk;

  wire [0:0]E;
  wire [0:0]Q;
  wire \count_value_i_reg[6] ;
  wire [1:0]\gen_rst_cc.fifo_wr_rst_cc ;
  wire p_0_in;
  wire \power_on_rst_reg_n_0_[0] ;
  wire rd_clk;
  wire rst;
  wire rst_d1;
  wire rst_i;
  wire wr_en;

  LUT2 #(
    .INIT(4'hE)) 
    \gen_rst_cc.fifo_wr_rst_cc[2]_i_1 
       (.I0(p_0_in),
        .I1(rst),
        .O(rst_i));
  FDSE #(
    .INIT(1'b0)) 
    \gen_rst_cc.fifo_wr_rst_cc_reg[0] 
       (.C(rd_clk),
        .CE(1'b1),
        .D(1'b0),
        .Q(\gen_rst_cc.fifo_wr_rst_cc [0]),
        .S(rst_i));
  FDSE #(
    .INIT(1'b0)) 
    \gen_rst_cc.fifo_wr_rst_cc_reg[1] 
       (.C(rd_clk),
        .CE(1'b1),
        .D(\gen_rst_cc.fifo_wr_rst_cc [0]),
        .Q(\gen_rst_cc.fifo_wr_rst_cc [1]),
        .S(rst_i));
  FDSE #(
    .INIT(1'b0)) 
    \gen_rst_cc.fifo_wr_rst_cc_reg[2] 
       (.C(rd_clk),
        .CE(1'b1),
        .D(\gen_rst_cc.fifo_wr_rst_cc [1]),
        .Q(Q),
        .S(rst_i));
  LUT4 #(
    .INIT(16'h0002)) 
    \gen_sdpram.xpm_memory_base_inst_i_1 
       (.I0(wr_en),
        .I1(\count_value_i_reg[6] ),
        .I2(Q),
        .I3(rst_d1),
        .O(E));
  FDRE #(
    .INIT(1'b1)) 
    \power_on_rst_reg[0] 
       (.C(rd_clk),
        .CE(1'b1),
        .D(1'b0),
        .Q(\power_on_rst_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \power_on_rst_reg[1] 
       (.C(rd_clk),
        .CE(1'b1),
        .D(\power_on_rst_reg_n_0_[0] ),
        .Q(p_0_in),
        .R(1'b0));
endmodule

(* CASCADE_HEIGHT = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) 
(* EN_ADV_FEATURE_SYNC = "16'b0001111100011111" *) (* EN_SIM_ASSERT_ERR = "warning" *) (* FIFO_MEMORY_TYPE = "auto" *) 
(* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "128" *) (* FULL_RESET_VALUE = "1" *) 
(* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "10" *) (* P_COMMON_CLOCK = "1" *) 
(* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "0" *) (* P_READ_MODE = "1" *) 
(* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "4" *) (* READ_DATA_WIDTH = "33" *) 
(* READ_MODE = "fwft" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "1F1F" *) 
(* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "33" *) (* WR_DATA_COUNT_WIDTH = "8" *) 
(* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) 
module Loopback_axi_dma_1_0_xpm_fifo_sync
   (sleep,
    rst,
    wr_clk,
    wr_en,
    din,
    full,
    prog_full,
    wr_data_count,
    overflow,
    wr_rst_busy,
    almost_full,
    wr_ack,
    rd_en,
    dout,
    empty,
    prog_empty,
    rd_data_count,
    underflow,
    rd_rst_busy,
    almost_empty,
    data_valid,
    injectsbiterr,
    injectdbiterr,
    sbiterr,
    dbiterr);
  input sleep;
  input rst;
  input wr_clk;
  input wr_en;
  input [32:0]din;
  output full;
  output prog_full;
  output [7:0]wr_data_count;
  output overflow;
  output wr_rst_busy;
  output almost_full;
  output wr_ack;
  input rd_en;
  output [32:0]dout;
  output empty;
  output prog_empty;
  output [3:0]rd_data_count;
  output underflow;
  output rd_rst_busy;
  output almost_empty;
  output data_valid;
  input injectsbiterr;
  input injectdbiterr;
  output sbiterr;
  output dbiterr;

  wire \<const0> ;
  wire [32:0]din;
  wire [32:0]dout;
  wire empty;
  wire full;
  wire rd_en;
  wire rst;
  wire sleep;
  wire wr_clk;
  wire wr_en;
  wire NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_full_n_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_overflow_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_underflow_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED;
  wire [3:0]NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED;
  wire [7:0]NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED;

  assign almost_empty = \<const0> ;
  assign almost_full = \<const0> ;
  assign data_valid = \<const0> ;
  assign dbiterr = \<const0> ;
  assign overflow = \<const0> ;
  assign prog_empty = \<const0> ;
  assign prog_full = \<const0> ;
  assign rd_data_count[3] = \<const0> ;
  assign rd_data_count[2] = \<const0> ;
  assign rd_data_count[1] = \<const0> ;
  assign rd_data_count[0] = \<const0> ;
  assign rd_rst_busy = \<const0> ;
  assign sbiterr = \<const0> ;
  assign underflow = \<const0> ;
  assign wr_ack = \<const0> ;
  assign wr_data_count[7] = \<const0> ;
  assign wr_data_count[6] = \<const0> ;
  assign wr_data_count[5] = \<const0> ;
  assign wr_data_count[4] = \<const0> ;
  assign wr_data_count[3] = \<const0> ;
  assign wr_data_count[2] = \<const0> ;
  assign wr_data_count[1] = \<const0> ;
  assign wr_data_count[0] = \<const0> ;
  assign wr_rst_busy = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* CASCADE_HEIGHT = "0" *) 
  (* CDC_DEST_SYNC_FF = "2" *) 
  (* COMMON_CLOCK = "1" *) 
  (* DOUT_RESET_VALUE = "0" *) 
  (* ECC_MODE = "0" *) 
  (* ENABLE_ECC = "0" *) 
  (* EN_ADV_FEATURE = "16'b0001111100011111" *) 
  (* EN_AE = "1'b1" *) 
  (* EN_AF = "1'b1" *) 
  (* EN_DVLD = "1'b1" *) 
  (* EN_OF = "1'b1" *) 
  (* EN_PE = "1'b1" *) 
  (* EN_PF = "1'b1" *) 
  (* EN_RDC = "1'b1" *) 
  (* EN_SIM_ASSERT_ERR = "warning" *) 
  (* EN_UF = "1'b1" *) 
  (* EN_WACK = "1'b1" *) 
  (* EN_WDC = "1'b1" *) 
  (* FG_EQ_ASYM_DOUT = "1'b0" *) 
  (* FIFO_MEMORY_TYPE = "0" *) 
  (* FIFO_MEM_TYPE = "0" *) 
  (* FIFO_READ_DEPTH = "128" *) 
  (* FIFO_READ_LATENCY = "0" *) 
  (* FIFO_SIZE = "4224" *) 
  (* FIFO_WRITE_DEPTH = "128" *) 
  (* FULL_RESET_VALUE = "1" *) 
  (* FULL_RST_VAL = "1'b1" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* PE_THRESH_ADJ = "8" *) 
  (* PE_THRESH_MAX = "123" *) 
  (* PE_THRESH_MIN = "5" *) 
  (* PF_THRESH_ADJ = "8" *) 
  (* PF_THRESH_MAX = "123" *) 
  (* PF_THRESH_MIN = "5" *) 
  (* PROG_EMPTY_THRESH = "10" *) 
  (* PROG_FULL_THRESH = "10" *) 
  (* RD_DATA_COUNT_WIDTH = "4" *) 
  (* RD_DC_WIDTH_EXT = "8" *) 
  (* RD_LATENCY = "2" *) 
  (* RD_MODE = "1" *) 
  (* RD_PNTR_WIDTH = "7" *) 
  (* READ_DATA_WIDTH = "33" *) 
  (* READ_MODE = "1" *) 
  (* READ_MODE_LL = "1" *) 
  (* RELATED_CLOCKS = "0" *) 
  (* REMOVE_WR_RD_PROT_LOGIC = "0" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_ADV_FEATURES = "1F1F" *) 
  (* VERSION = "0" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WIDTH_RATIO = "1" *) 
  (* WRITE_DATA_WIDTH = "33" *) 
  (* WR_DATA_COUNT_WIDTH = "8" *) 
  (* WR_DC_WIDTH_EXT = "8" *) 
  (* WR_DEPTH_LOG = "7" *) 
  (* WR_PNTR_WIDTH = "7" *) 
  (* WR_RD_RATIO = "0" *) 
  (* WR_WIDTH_LOG = "6" *) 
  (* XPM_MODULE = "TRUE" *) 
  (* both_stages_valid = "3" *) 
  (* invalid = "0" *) 
  (* stage1_valid = "2" *) 
  (* stage2_valid = "1" *) 
  Loopback_axi_dma_1_0_xpm_fifo_base xpm_fifo_base_inst
       (.almost_empty(NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED),
        .almost_full(NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED),
        .data_valid(NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED),
        .dbiterr(NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED),
        .din(din),
        .dout(dout),
        .empty(empty),
        .full(full),
        .full_n(NLW_xpm_fifo_base_inst_full_n_UNCONNECTED),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .overflow(NLW_xpm_fifo_base_inst_overflow_UNCONNECTED),
        .prog_empty(NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED),
        .prog_full(NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED),
        .rd_clk(wr_clk),
        .rd_data_count(NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED[3:0]),
        .rd_en(rd_en),
        .rd_rst_busy(NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED),
        .rst(rst),
        .sbiterr(NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED),
        .sleep(sleep),
        .underflow(NLW_xpm_fifo_base_inst_underflow_UNCONNECTED),
        .wr_ack(NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED),
        .wr_clk(1'b0),
        .wr_data_count(NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED[7:0]),
        .wr_en(wr_en),
        .wr_rst_busy(NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED));
endmodule

(* CASCADE_HEIGHT = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) 
(* EN_ADV_FEATURE_SYNC = "16'b0001111100011111" *) (* EN_SIM_ASSERT_ERR = "warning" *) (* FIFO_MEMORY_TYPE = "block" *) 
(* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "128" *) (* FULL_RESET_VALUE = "1" *) 
(* ORIG_REF_NAME = "xpm_fifo_sync" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "10" *) 
(* P_COMMON_CLOCK = "1" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "2" *) 
(* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "4" *) 
(* READ_DATA_WIDTH = "39" *) (* READ_MODE = "fwft" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_ADV_FEATURES = "1F1F" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "39" *) 
(* WR_DATA_COUNT_WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) 
module Loopback_axi_dma_1_0_xpm_fifo_sync__parameterized1
   (sleep,
    rst,
    wr_clk,
    wr_en,
    din,
    full,
    prog_full,
    wr_data_count,
    overflow,
    wr_rst_busy,
    almost_full,
    wr_ack,
    rd_en,
    dout,
    empty,
    prog_empty,
    rd_data_count,
    underflow,
    rd_rst_busy,
    almost_empty,
    data_valid,
    injectsbiterr,
    injectdbiterr,
    sbiterr,
    dbiterr);
  input sleep;
  input rst;
  input wr_clk;
  input wr_en;
  input [38:0]din;
  output full;
  output prog_full;
  output [7:0]wr_data_count;
  output overflow;
  output wr_rst_busy;
  output almost_full;
  output wr_ack;
  input rd_en;
  output [38:0]dout;
  output empty;
  output prog_empty;
  output [3:0]rd_data_count;
  output underflow;
  output rd_rst_busy;
  output almost_empty;
  output data_valid;
  input injectsbiterr;
  input injectdbiterr;
  output sbiterr;
  output dbiterr;

  wire \<const0> ;
  wire [38:0]din;
  wire [37:0]\^dout ;
  wire empty;
  wire full;
  wire rd_en;
  wire rst;
  wire sleep;
  wire wr_clk;
  wire [7:4]\^wr_data_count ;
  wire wr_en;
  wire NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_full_n_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_overflow_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_underflow_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED;
  wire NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED;
  wire [38:38]NLW_xpm_fifo_base_inst_dout_UNCONNECTED;
  wire [3:0]NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED;
  wire [3:0]NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED;

  assign almost_empty = \<const0> ;
  assign almost_full = \<const0> ;
  assign data_valid = \<const0> ;
  assign dbiterr = \<const0> ;
  assign dout[38] = \<const0> ;
  assign dout[37:0] = \^dout [37:0];
  assign overflow = \<const0> ;
  assign prog_empty = \<const0> ;
  assign prog_full = \<const0> ;
  assign rd_data_count[3] = \<const0> ;
  assign rd_data_count[2] = \<const0> ;
  assign rd_data_count[1] = \<const0> ;
  assign rd_data_count[0] = \<const0> ;
  assign rd_rst_busy = \<const0> ;
  assign sbiterr = \<const0> ;
  assign underflow = \<const0> ;
  assign wr_ack = \<const0> ;
  assign wr_data_count[7:4] = \^wr_data_count [7:4];
  assign wr_data_count[3] = \<const0> ;
  assign wr_data_count[2] = \<const0> ;
  assign wr_data_count[1] = \<const0> ;
  assign wr_data_count[0] = \<const0> ;
  assign wr_rst_busy = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* CASCADE_HEIGHT = "0" *) 
  (* CDC_DEST_SYNC_FF = "2" *) 
  (* COMMON_CLOCK = "1" *) 
  (* DOUT_RESET_VALUE = "0" *) 
  (* ECC_MODE = "0" *) 
  (* ENABLE_ECC = "0" *) 
  (* EN_ADV_FEATURE = "16'b0001111100011111" *) 
  (* EN_AE = "1'b1" *) 
  (* EN_AF = "1'b1" *) 
  (* EN_DVLD = "1'b1" *) 
  (* EN_OF = "1'b1" *) 
  (* EN_PE = "1'b1" *) 
  (* EN_PF = "1'b1" *) 
  (* EN_RDC = "1'b1" *) 
  (* EN_SIM_ASSERT_ERR = "warning" *) 
  (* EN_UF = "1'b1" *) 
  (* EN_WACK = "1'b1" *) 
  (* EN_WDC = "1'b1" *) 
  (* FG_EQ_ASYM_DOUT = "1'b0" *) 
  (* FIFO_MEMORY_TYPE = "2" *) 
  (* FIFO_MEM_TYPE = "2" *) 
  (* FIFO_READ_DEPTH = "128" *) 
  (* FIFO_READ_LATENCY = "0" *) 
  (* FIFO_SIZE = "4992" *) 
  (* FIFO_WRITE_DEPTH = "128" *) 
  (* FULL_RESET_VALUE = "1" *) 
  (* FULL_RST_VAL = "1'b1" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* PE_THRESH_ADJ = "8" *) 
  (* PE_THRESH_MAX = "123" *) 
  (* PE_THRESH_MIN = "5" *) 
  (* PF_THRESH_ADJ = "8" *) 
  (* PF_THRESH_MAX = "123" *) 
  (* PF_THRESH_MIN = "5" *) 
  (* PROG_EMPTY_THRESH = "10" *) 
  (* PROG_FULL_THRESH = "10" *) 
  (* RD_DATA_COUNT_WIDTH = "4" *) 
  (* RD_DC_WIDTH_EXT = "8" *) 
  (* RD_LATENCY = "2" *) 
  (* RD_MODE = "1" *) 
  (* RD_PNTR_WIDTH = "7" *) 
  (* READ_DATA_WIDTH = "39" *) 
  (* READ_MODE = "1" *) 
  (* READ_MODE_LL = "1" *) 
  (* RELATED_CLOCKS = "0" *) 
  (* REMOVE_WR_RD_PROT_LOGIC = "0" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_ADV_FEATURES = "1F1F" *) 
  (* VERSION = "0" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WIDTH_RATIO = "1" *) 
  (* WRITE_DATA_WIDTH = "39" *) 
  (* WR_DATA_COUNT_WIDTH = "8" *) 
  (* WR_DC_WIDTH_EXT = "8" *) 
  (* WR_DEPTH_LOG = "7" *) 
  (* WR_PNTR_WIDTH = "7" *) 
  (* WR_RD_RATIO = "0" *) 
  (* WR_WIDTH_LOG = "6" *) 
  (* XPM_MODULE = "TRUE" *) 
  (* both_stages_valid = "3" *) 
  (* invalid = "0" *) 
  (* stage1_valid = "2" *) 
  (* stage2_valid = "1" *) 
  Loopback_axi_dma_1_0_xpm_fifo_base__parameterized0 xpm_fifo_base_inst
       (.almost_empty(NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED),
        .almost_full(NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED),
        .data_valid(NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED),
        .dbiterr(NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED),
        .din({1'b0,din[37:0]}),
        .dout({NLW_xpm_fifo_base_inst_dout_UNCONNECTED[38],\^dout }),
        .empty(empty),
        .full(full),
        .full_n(NLW_xpm_fifo_base_inst_full_n_UNCONNECTED),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .overflow(NLW_xpm_fifo_base_inst_overflow_UNCONNECTED),
        .prog_empty(NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED),
        .prog_full(NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED),
        .rd_clk(1'b0),
        .rd_data_count(NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED[3:0]),
        .rd_en(rd_en),
        .rd_rst_busy(NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED),
        .rst(rst),
        .sbiterr(NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED),
        .sleep(sleep),
        .underflow(NLW_xpm_fifo_base_inst_underflow_UNCONNECTED),
        .wr_ack(NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED),
        .wr_clk(wr_clk),
        .wr_data_count({\^wr_data_count ,NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED[3:0]}),
        .wr_en(wr_en),
        .wr_rst_busy(NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED));
endmodule

(* ADDR_WIDTH_A = "7" *) (* ADDR_WIDTH_B = "7" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "33" *) (* BYTE_WRITE_WIDTH_B = "33" *) (* CASCADE_HEIGHT = "0" *) 
(* CLOCKING_MODE = "0" *) (* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "0" *) 
(* ECC_TYPE = "NONE" *) (* IGNORE_INIT_SYNTH = "0" *) (* MAX_NUM_CHAR = "0" *) 
(* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) 
(* MEMORY_PRIMITIVE = "0" *) (* MEMORY_SIZE = "4224" *) (* MEMORY_TYPE = "1" *) 
(* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "0" *) 
(* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "128" *) 
(* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "auto" *) (* P_MIN_WIDTH_DATA = "33" *) 
(* P_MIN_WIDTH_DATA_A = "33" *) (* P_MIN_WIDTH_DATA_B = "33" *) (* P_MIN_WIDTH_DATA_ECC = "33" *) 
(* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "33" *) (* P_NUM_COLS_WRITE_A = "1" *) 
(* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) 
(* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "yes" *) 
(* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) 
(* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "7" *) (* P_WIDTH_ADDR_READ_B = "7" *) 
(* P_WIDTH_ADDR_WRITE_A = "7" *) (* P_WIDTH_ADDR_WRITE_B = "7" *) (* P_WIDTH_COL_WRITE_A = "33" *) 
(* P_WIDTH_COL_WRITE_B = "33" *) (* RAM_DECOMP = "auto" *) (* READ_DATA_WIDTH_A = "33" *) 
(* READ_DATA_WIDTH_B = "33" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) 
(* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) 
(* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) 
(* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) 
(* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "33" *) (* WRITE_DATA_WIDTH_B = "33" *) 
(* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) 
(* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "36" *) 
(* rstb_loop_iter = "36" *) 
module Loopback_axi_dma_1_0_xpm_memory_base
   (sleep,
    clka,
    rsta,
    ena,
    regcea,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    douta,
    sbiterra,
    dbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    web,
    addrb,
    dinb,
    injectsbiterrb,
    injectdbiterrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input rsta;
  input ena;
  input regcea;
  input [0:0]wea;
  input [6:0]addra;
  input [32:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  output [32:0]douta;
  output sbiterra;
  output dbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [0:0]web;
  input [6:0]addrb;
  input [32:0]dinb;
  input injectsbiterrb;
  input injectdbiterrb;
  output [32:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [6:0]addra;
  wire [6:0]addrb;
  wire clka;
  wire [32:0]dina;
  wire [32:0]doutb;
  wire enb;
  wire [32:0]\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg ;
  wire [32:0]\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_1 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_2 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_3 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_4 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_5 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_6 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_1 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_2 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_3 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_4 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_5 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_6 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_1 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_2 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_3 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_4 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_1 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_2 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_3 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_4 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_5 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_6 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_1 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_2 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_3 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_4 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_5 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_6 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_1 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_2 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_3 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_4 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_5 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_6 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_1 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_2 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_3 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_4 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_0 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_1 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_2 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_3 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_4 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_5 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_6 ;
  wire regceb;
  wire rstb;
  wire sleep;
  wire [0:0]wea;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_DOH_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_DOH_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_DOH_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_DOF_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_DOG_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_DOH_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_DOH_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_DOH_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_DOH_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_DOH_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_DOF_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_DOG_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_DOH_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_DOH_UNCONNECTED ;

  assign dbiterra = \<const0> ;
  assign dbiterrb = \<const0> ;
  assign douta[32] = \<const0> ;
  assign douta[31] = \<const0> ;
  assign douta[30] = \<const0> ;
  assign douta[29] = \<const0> ;
  assign douta[28] = \<const0> ;
  assign douta[27] = \<const0> ;
  assign douta[26] = \<const0> ;
  assign douta[25] = \<const0> ;
  assign douta[24] = \<const0> ;
  assign douta[23] = \<const0> ;
  assign douta[22] = \<const0> ;
  assign douta[21] = \<const0> ;
  assign douta[20] = \<const0> ;
  assign douta[19] = \<const0> ;
  assign douta[18] = \<const0> ;
  assign douta[17] = \<const0> ;
  assign douta[16] = \<const0> ;
  assign douta[15] = \<const0> ;
  assign douta[14] = \<const0> ;
  assign douta[13] = \<const0> ;
  assign douta[12] = \<const0> ;
  assign douta[11] = \<const0> ;
  assign douta[10] = \<const0> ;
  assign douta[9] = \<const0> ;
  assign douta[8] = \<const0> ;
  assign douta[7] = \<const0> ;
  assign douta[6] = \<const0> ;
  assign douta[5] = \<const0> ;
  assign douta[4] = \<const0> ;
  assign douta[3] = \<const0> ;
  assign douta[2] = \<const0> ;
  assign douta[1] = \<const0> ;
  assign douta[0] = \<const0> ;
  assign sbiterra = \<const0> ;
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][0] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [0]),
        .Q(doutb[0]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][10] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [10]),
        .Q(doutb[10]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][11] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [11]),
        .Q(doutb[11]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][12] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [12]),
        .Q(doutb[12]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][13] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [13]),
        .Q(doutb[13]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][14] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [14]),
        .Q(doutb[14]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][15] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [15]),
        .Q(doutb[15]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][16] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [16]),
        .Q(doutb[16]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][17] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [17]),
        .Q(doutb[17]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][18] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [18]),
        .Q(doutb[18]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][19] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [19]),
        .Q(doutb[19]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][1] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [1]),
        .Q(doutb[1]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][20] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [20]),
        .Q(doutb[20]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][21] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [21]),
        .Q(doutb[21]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][22] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [22]),
        .Q(doutb[22]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][23] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [23]),
        .Q(doutb[23]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][24] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [24]),
        .Q(doutb[24]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][25] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [25]),
        .Q(doutb[25]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][26] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [26]),
        .Q(doutb[26]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][27] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [27]),
        .Q(doutb[27]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][28] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [28]),
        .Q(doutb[28]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][29] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [29]),
        .Q(doutb[29]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][2] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [2]),
        .Q(doutb[2]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][30] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [30]),
        .Q(doutb[30]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][31] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [31]),
        .Q(doutb[31]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][32] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [32]),
        .Q(doutb[32]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][3] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [3]),
        .Q(doutb[3]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][4] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [4]),
        .Q(doutb[4]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][5] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [5]),
        .Q(doutb[5]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][6] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [6]),
        .Q(doutb[6]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][7] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [7]),
        .Q(doutb[7]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][8] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [8]),
        .Q(doutb[8]),
        .R(rstb));
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][9] 
       (.C(clka),
        .CE(regceb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [9]),
        .Q(doutb[9]),
        .R(rstb));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[0]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[10]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_3 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_3 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [10]));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[11]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_4 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_4 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [11]));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[12]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_5 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_5 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [12]));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[13]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_6 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_6 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [13]));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[14]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_0 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_0 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [14]));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[15]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_1 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_1 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [15]));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[16]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_2 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_2 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [16]));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[17]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_3 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_3 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [17]));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[18]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_4 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_4 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [18]));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[19]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_5 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_5 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [19]));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[1]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[20]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_6 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_6 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [20]));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[21]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_0 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_0 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [21]));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[22]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_1 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_1 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [22]));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[23]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_2 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_2 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [23]));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[24]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_3 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_3 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [24]));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[25]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_4 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_4 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [25]));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[26]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_5 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_5 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [26]));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[27]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_6 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_6 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [27]));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[28]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_0 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_0 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [28]));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[29]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_1 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_1 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [29]));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[2]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[30]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_2 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_2 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [30]));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[31]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_3 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_3 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [31]));
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[32]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_4 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_4 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [32]));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[3]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[4]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[5]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[6]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[7]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_0 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_0 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[8]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_1 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_1 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg[9]_i_1 
       (.I0(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_2 ),
        .I1(addrb[6]),
        .I2(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_2 ),
        .O(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [9]));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[0] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [0]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [0]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[10] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [10]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [10]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[11] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [11]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [11]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[12] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [12]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [12]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[13] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [13]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [13]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[14] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [14]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [14]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[15] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [15]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [15]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[16] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [16]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [16]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[17] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [17]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [17]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[18] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [18]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [18]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[19] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [19]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [19]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[1] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [1]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [1]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[20] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [20]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [20]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[21] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [21]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [21]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[22] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [22]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [22]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[23] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [23]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [23]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[24] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [24]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [24]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[25] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [25]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [25]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[26] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [26]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [26]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[27] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [27]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [27]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[28] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [28]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [28]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[29] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [29]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [29]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[2] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [2]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [2]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[30] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [30]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [30]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[31] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [31]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [31]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[32] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [32]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [32]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[3] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [3]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [3]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[4] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [4]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [4]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[5] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [5]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [5]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[6] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [6]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [6]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[7] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [7]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [7]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[8] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [8]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [8]),
        .R(1'b0));
  (* dram_emb_xdc = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[9] 
       (.C(clka),
        .CE(enb),
        .D(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0 [9]),
        .Q(\gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg [9]),
        .R(1'b0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "4224" *) 
  (* RTL_RAM_NAME = "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_STYLE = "auto" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "6" *) 
  RAM64M8 #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .INIT_E(64'h0000000000000000),
    .INIT_F(64'h0000000000000000),
    .INIT_G(64'h0000000000000000),
    .INIT_H(64'h0000000000000000)) 
    \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6 
       (.ADDRA(addrb[5:0]),
        .ADDRB(addrb[5:0]),
        .ADDRC(addrb[5:0]),
        .ADDRD(addrb[5:0]),
        .ADDRE(addrb[5:0]),
        .ADDRF(addrb[5:0]),
        .ADDRG(addrb[5:0]),
        .ADDRH(addra[5:0]),
        .DIA(dina[0]),
        .DIB(dina[1]),
        .DIC(dina[2]),
        .DID(dina[3]),
        .DIE(dina[4]),
        .DIF(dina[5]),
        .DIG(dina[6]),
        .DIH(1'b0),
        .DOA(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0 ),
        .DOB(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1 ),
        .DOC(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2 ),
        .DOD(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3 ),
        .DOE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4 ),
        .DOF(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5 ),
        .DOG(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6 ),
        .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_DOH_UNCONNECTED ),
        .WCLK(clka),
        .WE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1 
       (.I0(wea),
        .I1(addra[6]),
        .O(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "4224" *) 
  (* RTL_RAM_NAME = "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_STYLE = "auto" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "14" *) 
  (* ram_slice_end = "20" *) 
  RAM64M8 #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .INIT_E(64'h0000000000000000),
    .INIT_F(64'h0000000000000000),
    .INIT_G(64'h0000000000000000),
    .INIT_H(64'h0000000000000000)) 
    \gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20 
       (.ADDRA(addrb[5:0]),
        .ADDRB(addrb[5:0]),
        .ADDRC(addrb[5:0]),
        .ADDRD(addrb[5:0]),
        .ADDRE(addrb[5:0]),
        .ADDRF(addrb[5:0]),
        .ADDRG(addrb[5:0]),
        .ADDRH(addra[5:0]),
        .DIA(dina[14]),
        .DIB(dina[15]),
        .DIC(dina[16]),
        .DID(dina[17]),
        .DIE(dina[18]),
        .DIF(dina[19]),
        .DIG(dina[20]),
        .DIH(1'b0),
        .DOA(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_0 ),
        .DOB(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_1 ),
        .DOC(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_2 ),
        .DOD(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_3 ),
        .DOE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_4 ),
        .DOF(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_5 ),
        .DOG(\gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_n_6 ),
        .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_14_20_DOH_UNCONNECTED ),
        .WCLK(clka),
        .WE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "4224" *) 
  (* RTL_RAM_NAME = "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_STYLE = "auto" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "21" *) 
  (* ram_slice_end = "27" *) 
  RAM64M8 #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .INIT_E(64'h0000000000000000),
    .INIT_F(64'h0000000000000000),
    .INIT_G(64'h0000000000000000),
    .INIT_H(64'h0000000000000000)) 
    \gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27 
       (.ADDRA(addrb[5:0]),
        .ADDRB(addrb[5:0]),
        .ADDRC(addrb[5:0]),
        .ADDRD(addrb[5:0]),
        .ADDRE(addrb[5:0]),
        .ADDRF(addrb[5:0]),
        .ADDRG(addrb[5:0]),
        .ADDRH(addra[5:0]),
        .DIA(dina[21]),
        .DIB(dina[22]),
        .DIC(dina[23]),
        .DID(dina[24]),
        .DIE(dina[25]),
        .DIF(dina[26]),
        .DIG(dina[27]),
        .DIH(1'b0),
        .DOA(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_0 ),
        .DOB(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_1 ),
        .DOC(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_2 ),
        .DOD(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_3 ),
        .DOE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_4 ),
        .DOF(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_5 ),
        .DOG(\gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_n_6 ),
        .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_21_27_DOH_UNCONNECTED ),
        .WCLK(clka),
        .WE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "4224" *) 
  (* RTL_RAM_NAME = "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_STYLE = "auto" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "28" *) 
  (* ram_slice_end = "32" *) 
  RAM64M8 #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .INIT_E(64'h0000000000000000),
    .INIT_F(64'h0000000000000000),
    .INIT_G(64'h0000000000000000),
    .INIT_H(64'h0000000000000000)) 
    \gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32 
       (.ADDRA(addrb[5:0]),
        .ADDRB(addrb[5:0]),
        .ADDRC(addrb[5:0]),
        .ADDRD(addrb[5:0]),
        .ADDRE(addrb[5:0]),
        .ADDRF(addrb[5:0]),
        .ADDRG(addrb[5:0]),
        .ADDRH(addra[5:0]),
        .DIA(dina[28]),
        .DIB(dina[29]),
        .DIC(dina[30]),
        .DID(dina[31]),
        .DIE(dina[32]),
        .DIF(1'b0),
        .DIG(1'b0),
        .DIH(1'b0),
        .DOA(\gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_0 ),
        .DOB(\gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_1 ),
        .DOC(\gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_2 ),
        .DOD(\gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_3 ),
        .DOE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_n_4 ),
        .DOF(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_DOF_UNCONNECTED ),
        .DOG(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_DOG_UNCONNECTED ),
        .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_28_32_DOH_UNCONNECTED ),
        .WCLK(clka),
        .WE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "4224" *) 
  (* RTL_RAM_NAME = "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_STYLE = "auto" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "7" *) 
  (* ram_slice_end = "13" *) 
  RAM64M8 #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .INIT_E(64'h0000000000000000),
    .INIT_F(64'h0000000000000000),
    .INIT_G(64'h0000000000000000),
    .INIT_H(64'h0000000000000000)) 
    \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13 
       (.ADDRA(addrb[5:0]),
        .ADDRB(addrb[5:0]),
        .ADDRC(addrb[5:0]),
        .ADDRD(addrb[5:0]),
        .ADDRE(addrb[5:0]),
        .ADDRF(addrb[5:0]),
        .ADDRG(addrb[5:0]),
        .ADDRH(addra[5:0]),
        .DIA(dina[7]),
        .DIB(dina[8]),
        .DIC(dina[9]),
        .DID(dina[10]),
        .DIE(dina[11]),
        .DIF(dina[12]),
        .DIG(dina[13]),
        .DIH(1'b0),
        .DOA(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_0 ),
        .DOB(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_1 ),
        .DOC(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_2 ),
        .DOD(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_3 ),
        .DOE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_4 ),
        .DOF(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_5 ),
        .DOG(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_n_6 ),
        .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_7_13_DOH_UNCONNECTED ),
        .WCLK(clka),
        .WE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "4224" *) 
  (* RTL_RAM_NAME = "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_STYLE = "auto" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "6" *) 
  RAM64M8 #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .INIT_E(64'h0000000000000000),
    .INIT_F(64'h0000000000000000),
    .INIT_G(64'h0000000000000000),
    .INIT_H(64'h0000000000000000)) 
    \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6 
       (.ADDRA(addrb[5:0]),
        .ADDRB(addrb[5:0]),
        .ADDRC(addrb[5:0]),
        .ADDRD(addrb[5:0]),
        .ADDRE(addrb[5:0]),
        .ADDRF(addrb[5:0]),
        .ADDRG(addrb[5:0]),
        .ADDRH(addra[5:0]),
        .DIA(dina[0]),
        .DIB(dina[1]),
        .DIC(dina[2]),
        .DID(dina[3]),
        .DIE(dina[4]),
        .DIF(dina[5]),
        .DIG(dina[6]),
        .DIH(1'b0),
        .DOA(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0 ),
        .DOB(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1 ),
        .DOC(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2 ),
        .DOD(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3 ),
        .DOE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4 ),
        .DOF(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5 ),
        .DOG(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6 ),
        .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_DOH_UNCONNECTED ),
        .WCLK(clka),
        .WE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1 
       (.I0(wea),
        .I1(addra[6]),
        .O(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "4224" *) 
  (* RTL_RAM_NAME = "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_STYLE = "auto" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "14" *) 
  (* ram_slice_end = "20" *) 
  RAM64M8 #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .INIT_E(64'h0000000000000000),
    .INIT_F(64'h0000000000000000),
    .INIT_G(64'h0000000000000000),
    .INIT_H(64'h0000000000000000)) 
    \gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20 
       (.ADDRA(addrb[5:0]),
        .ADDRB(addrb[5:0]),
        .ADDRC(addrb[5:0]),
        .ADDRD(addrb[5:0]),
        .ADDRE(addrb[5:0]),
        .ADDRF(addrb[5:0]),
        .ADDRG(addrb[5:0]),
        .ADDRH(addra[5:0]),
        .DIA(dina[14]),
        .DIB(dina[15]),
        .DIC(dina[16]),
        .DID(dina[17]),
        .DIE(dina[18]),
        .DIF(dina[19]),
        .DIG(dina[20]),
        .DIH(1'b0),
        .DOA(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_0 ),
        .DOB(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_1 ),
        .DOC(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_2 ),
        .DOD(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_3 ),
        .DOE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_4 ),
        .DOF(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_5 ),
        .DOG(\gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_n_6 ),
        .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_14_20_DOH_UNCONNECTED ),
        .WCLK(clka),
        .WE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "4224" *) 
  (* RTL_RAM_NAME = "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_STYLE = "auto" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "21" *) 
  (* ram_slice_end = "27" *) 
  RAM64M8 #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .INIT_E(64'h0000000000000000),
    .INIT_F(64'h0000000000000000),
    .INIT_G(64'h0000000000000000),
    .INIT_H(64'h0000000000000000)) 
    \gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27 
       (.ADDRA(addrb[5:0]),
        .ADDRB(addrb[5:0]),
        .ADDRC(addrb[5:0]),
        .ADDRD(addrb[5:0]),
        .ADDRE(addrb[5:0]),
        .ADDRF(addrb[5:0]),
        .ADDRG(addrb[5:0]),
        .ADDRH(addra[5:0]),
        .DIA(dina[21]),
        .DIB(dina[22]),
        .DIC(dina[23]),
        .DID(dina[24]),
        .DIE(dina[25]),
        .DIF(dina[26]),
        .DIG(dina[27]),
        .DIH(1'b0),
        .DOA(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_0 ),
        .DOB(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_1 ),
        .DOC(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_2 ),
        .DOD(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_3 ),
        .DOE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_4 ),
        .DOF(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_5 ),
        .DOG(\gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_n_6 ),
        .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_21_27_DOH_UNCONNECTED ),
        .WCLK(clka),
        .WE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "4224" *) 
  (* RTL_RAM_NAME = "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_STYLE = "auto" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "28" *) 
  (* ram_slice_end = "32" *) 
  RAM64M8 #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .INIT_E(64'h0000000000000000),
    .INIT_F(64'h0000000000000000),
    .INIT_G(64'h0000000000000000),
    .INIT_H(64'h0000000000000000)) 
    \gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32 
       (.ADDRA(addrb[5:0]),
        .ADDRB(addrb[5:0]),
        .ADDRC(addrb[5:0]),
        .ADDRD(addrb[5:0]),
        .ADDRE(addrb[5:0]),
        .ADDRF(addrb[5:0]),
        .ADDRG(addrb[5:0]),
        .ADDRH(addra[5:0]),
        .DIA(dina[28]),
        .DIB(dina[29]),
        .DIC(dina[30]),
        .DID(dina[31]),
        .DIE(dina[32]),
        .DIF(1'b0),
        .DIG(1'b0),
        .DIH(1'b0),
        .DOA(\gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_0 ),
        .DOB(\gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_1 ),
        .DOC(\gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_2 ),
        .DOD(\gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_3 ),
        .DOE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_n_4 ),
        .DOF(\NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_DOF_UNCONNECTED ),
        .DOG(\NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_DOG_UNCONNECTED ),
        .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_28_32_DOH_UNCONNECTED ),
        .WCLK(clka),
        .WE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "4224" *) 
  (* RTL_RAM_NAME = "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_STYLE = "auto" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "7" *) 
  (* ram_slice_end = "13" *) 
  RAM64M8 #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .INIT_E(64'h0000000000000000),
    .INIT_F(64'h0000000000000000),
    .INIT_G(64'h0000000000000000),
    .INIT_H(64'h0000000000000000)) 
    \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13 
       (.ADDRA(addrb[5:0]),
        .ADDRB(addrb[5:0]),
        .ADDRC(addrb[5:0]),
        .ADDRD(addrb[5:0]),
        .ADDRE(addrb[5:0]),
        .ADDRF(addrb[5:0]),
        .ADDRG(addrb[5:0]),
        .ADDRH(addra[5:0]),
        .DIA(dina[7]),
        .DIB(dina[8]),
        .DIC(dina[9]),
        .DID(dina[10]),
        .DIE(dina[11]),
        .DIF(dina[12]),
        .DIG(dina[13]),
        .DIH(1'b0),
        .DOA(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_0 ),
        .DOB(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_1 ),
        .DOC(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_2 ),
        .DOD(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_3 ),
        .DOE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_4 ),
        .DOF(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_5 ),
        .DOG(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_n_6 ),
        .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_7_13_DOH_UNCONNECTED ),
        .WCLK(clka),
        .WE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 ));
endmodule

(* ADDR_WIDTH_A = "7" *) (* ADDR_WIDTH_B = "7" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "39" *) (* BYTE_WRITE_WIDTH_B = "39" *) (* CASCADE_HEIGHT = "0" *) 
(* CLOCKING_MODE = "0" *) (* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "0" *) 
(* ECC_TYPE = "NONE" *) (* IGNORE_INIT_SYNTH = "0" *) (* MAX_NUM_CHAR = "0" *) 
(* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) 
(* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "4992" *) (* MEMORY_TYPE = "1" *) 
(* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) 
(* P_ECC_MODE = "0" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) 
(* P_MAX_DEPTH_DATA = "128" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) 
(* P_MIN_WIDTH_DATA = "39" *) (* P_MIN_WIDTH_DATA_A = "39" *) (* P_MIN_WIDTH_DATA_B = "39" *) 
(* P_MIN_WIDTH_DATA_ECC = "39" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "39" *) 
(* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) 
(* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) 
(* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "7" *) 
(* P_WIDTH_ADDR_READ_B = "7" *) (* P_WIDTH_ADDR_WRITE_A = "7" *) (* P_WIDTH_ADDR_WRITE_B = "7" *) 
(* P_WIDTH_COL_WRITE_A = "39" *) (* P_WIDTH_COL_WRITE_B = "39" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_A = "39" *) (* READ_DATA_WIDTH_B = "39" *) (* READ_LATENCY_A = "2" *) 
(* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) 
(* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "39" *) 
(* WRITE_DATA_WIDTH_B = "39" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) 
(* rsta_loop_iter = "40" *) (* rstb_loop_iter = "40" *) 
module Loopback_axi_dma_1_0_xpm_memory_base__parameterized0
   (sleep,
    clka,
    rsta,
    ena,
    regcea,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    douta,
    sbiterra,
    dbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    web,
    addrb,
    dinb,
    injectsbiterrb,
    injectdbiterrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input rsta;
  input ena;
  input regcea;
  input [0:0]wea;
  input [6:0]addra;
  input [38:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  output [38:0]douta;
  output sbiterra;
  output dbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [0:0]web;
  input [6:0]addrb;
  input [38:0]dinb;
  input injectsbiterrb;
  input injectdbiterrb;
  output [38:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [6:0]addra;
  wire [6:0]addrb;
  wire clka;
  wire [38:0]dina;
  wire [37:0]\^doutb ;
  wire enb;
  wire regceb;
  wire rstb;
  wire sleep;
  wire [0:0]wea;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ;
  wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED ;
  wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED ;
  wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED ;
  wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED ;
  wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED ;
  wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED ;
  wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED ;
  wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED ;
  wire [31:6]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED ;
  wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED ;
  wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED ;
  wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ;

  assign dbiterra = \<const0> ;
  assign dbiterrb = \<const0> ;
  assign douta[38] = \<const0> ;
  assign douta[37] = \<const0> ;
  assign douta[36] = \<const0> ;
  assign douta[35] = \<const0> ;
  assign douta[34] = \<const0> ;
  assign douta[33] = \<const0> ;
  assign douta[32] = \<const0> ;
  assign douta[31] = \<const0> ;
  assign douta[30] = \<const0> ;
  assign douta[29] = \<const0> ;
  assign douta[28] = \<const0> ;
  assign douta[27] = \<const0> ;
  assign douta[26] = \<const0> ;
  assign douta[25] = \<const0> ;
  assign douta[24] = \<const0> ;
  assign douta[23] = \<const0> ;
  assign douta[22] = \<const0> ;
  assign douta[21] = \<const0> ;
  assign douta[20] = \<const0> ;
  assign douta[19] = \<const0> ;
  assign douta[18] = \<const0> ;
  assign douta[17] = \<const0> ;
  assign douta[16] = \<const0> ;
  assign douta[15] = \<const0> ;
  assign douta[14] = \<const0> ;
  assign douta[13] = \<const0> ;
  assign douta[12] = \<const0> ;
  assign douta[11] = \<const0> ;
  assign douta[10] = \<const0> ;
  assign douta[9] = \<const0> ;
  assign douta[8] = \<const0> ;
  assign douta[7] = \<const0> ;
  assign douta[6] = \<const0> ;
  assign douta[5] = \<const0> ;
  assign douta[4] = \<const0> ;
  assign douta[3] = \<const0> ;
  assign douta[2] = \<const0> ;
  assign douta[1] = \<const0> ;
  assign douta[0] = \<const0> ;
  assign doutb[38] = \<const0> ;
  assign doutb[37:0] = \^doutb [37:0];
  assign sbiterra = \<const0> ;
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* \MEM.PORTA.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTA.ADDRESS_END  = "511" *) 
  (* \MEM.PORTA.DATA_BIT_LAYOUT  = "p0_d38" *) 
  (* \MEM.PORTA.DATA_LSB  = "0" *) 
  (* \MEM.PORTA.DATA_MSB  = "37" *) 
  (* \MEM.PORTB.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTB.ADDRESS_END  = "511" *) 
  (* \MEM.PORTB.DATA_BIT_LAYOUT  = "p0_d38" *) 
  (* \MEM.PORTB.DATA_LSB  = "0" *) 
  (* \MEM.PORTB.DATA_MSB  = "37" *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE" *) 
  (* RTL_RAM_BITS = "4992" *) 
  (* RTL_RAM_NAME = "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_STYLE = "block" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "511" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "37" *) 
  RAMB36E2 #(
    .CASCADE_ORDER_A("NONE"),
    .CASCADE_ORDER_B("NONE"),
    .CLOCK_DOMAINS("COMMON"),
    .DOA_REG(1),
    .DOB_REG(1),
    .ENADDRENA("FALSE"),
    .ENADDRENB("FALSE"),
    .EN_ECC_PIPE("FALSE"),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .RDADDRCHANGEA("FALSE"),
    .RDADDRCHANGEB("FALSE"),
    .READ_WIDTH_A(72),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SLEEP_ASYNC("FALSE"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("NO_CHANGE"),
    .WRITE_WIDTH_A(0),
    .WRITE_WIDTH_B(72)) 
    \gen_wr_a.gen_word_narrow.mem_reg 
       (.ADDRARDADDR({1'b0,1'b0,addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b0,1'b0,addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRENA(1'b1),
        .ADDRENB(1'b1),
        .CASDIMUXA(1'b0),
        .CASDIMUXB(1'b0),
        .CASDINA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED [31:0]),
        .CASDINB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED [31:0]),
        .CASDINPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED [3:0]),
        .CASDINPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED [3:0]),
        .CASDOMUXA(1'b0),
        .CASDOMUXB(1'b0),
        .CASDOMUXEN_A(1'b1),
        .CASDOMUXEN_B(1'b1),
        .CASDOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED [31:0]),
        .CASDOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED [31:0]),
        .CASDOUTPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED [3:0]),
        .CASDOUTPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED [3:0]),
        .CASINDBITERR(1'b0),
        .CASINSBITERR(1'b0),
        .CASOREGIMUXA(1'b0),
        .CASOREGIMUXB(1'b0),
        .CASOREGIMUXEN_A(1'b1),
        .CASOREGIMUXEN_B(1'b1),
        .CASOUTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ),
        .CASOUTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ),
        .CLKARDCLK(clka),
        .CLKBWRCLK(clka),
        .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ),
        .DINADIN(dina[31:0]),
        .DINBDIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,dina[37:32]}),
        .DINPADINP({1'b1,1'b1,1'b1,1'b1}),
        .DINPBDINP({1'b1,1'b1,1'b1,1'b1}),
        .DOUTADOUT(\^doutb [31:0]),
        .DOUTBDOUT({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED [31:6],\^doutb [37:32]}),
        .DOUTPADOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED [3:0]),
        .DOUTPBDOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED [3:0]),
        .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]),
        .ECCPIPECE(1'b1),
        .ENARDEN(enb),
        .ENBWREN(1'b1),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(regceb),
        .REGCEB(1'b0),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(rstb),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ),
        .SLEEP(1'b0),
        .WEA({1'b0,1'b0,1'b0,1'b0}),
        .WEBWE({wea,wea,wea,wea,wea,wea,wea,wea}));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
