-------------------------------------
| Tool Version : Vivado v.2024.2
| Date         : Wed Jun 10 12:10:02 2026
| Host         : DrewPC2025
| Design       : design_1
| Device       : xczu48dr-ffvg1517-2-E-
-------------------------------------

For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US

***********************
Running Pre-CRP Checker
***********************
Number of global clocks: 1
	Number of BUFGCE: 0
	Number of BUFGCE_HDIO: 0
	Number of BUFG_CTRL: 0
	Number of BUFGCE_DIV: 0
	Number of BUFG_GT: 0
	Number of BUFG_PS: 1
	Number of BUFG_FABRIC: 0
Pre-CRP Checker took 0 secs

********************************
Clock Net Route Info (CRP Input)
********************************
Clock 1: GPIO_i/ZYNQ/inst/pl_clk0
	Clock source type: BUFG_PS
	Clock source region: X1Y2
	Clock regions with locked loads: X1Y0 X1Y1 
	initial rect ((0, 0), (2, 3))



*****************
User Constraints:
*****************
No user constraints found


