{ "cells": [ { "cell_type": "code", "execution_count": 10, "id": "ac34a9c0-3148-4b5d-8e5b-e71e3d33e15c", "metadata": {}, "outputs": [], "source": [ "from pynq import Overlay, MMIO\n", "from pynq.lib import AxiGPIO" ] }, { "cell_type": "markdown", "id": "5fd76b25-21bc-4e15-bb0f-435abc4f2399", "metadata": {}, "source": [ "download the bit file to the FPGA" ] }, { "cell_type": "code", "execution_count": 11, "id": "a619f6ca-7fb3-482e-83b0-ecd5276b8ad1", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "overlay completed\n" ] } ], "source": [ "base = Overlay(\"GPIO.bit\")\n", "print(\"overlay completed\")" ] }, { "cell_type": "markdown", "id": "f2d2977d-67b4-4373-83c6-194972d90d97", "metadata": {}, "source": [ "look in the dictionary to see what's there" ] }, { "cell_type": "code", "execution_count": 12, "id": "7b0d3674-1223-46ee-8c78-ec7c2e93da2b", "metadata": {}, "outputs": [ { "data": { "application/json": { "BUTTONS": { "addr_range": 65536, "bdtype": null, "device": "", "driver": "", "fullpath": "BUTTONS", "gpio": {}, "interrupts": {}, "mem_id": "S_AXI", "memtype": "REGISTER", "parameters": { "ADDR_WIDTH": "9", "ARUSER_WIDTH": "0", "AWUSER_WIDTH": "0", "BUSER_WIDTH": "0", "CLK_DOMAIN": "GPIO_zynq_ultra_ps_e_0_0_pl_clk0", "C_ALL_INPUTS": "1", "C_ALL_INPUTS_2": "0", "C_ALL_OUTPUTS": "0", "C_ALL_OUTPUTS_2": "0", "C_BASEADDR": "0xA0000000", "C_DOUT_DEFAULT": "0x00000000", "C_DOUT_DEFAULT_2": "0x00000000", "C_FAMILY": "zynquplus", "C_GPIO2_WIDTH": "32", "C_GPIO_WIDTH": "5", "C_HIGHADDR": "0xA000FFFF", "C_INTERRUPT_PRESENT": "0", "C_IS_DUAL": "0", "C_S_AXI_ADDR_WIDTH": "9", "C_S_AXI_DATA_WIDTH": "32", "C_TRI_DEFAULT": "0xFFFFFFFF", "C_TRI_DEFAULT_2": "0xFFFFFFFF", "Component_Name": "GPIO_axi_gpio_0_0", "DATA_WIDTH": "32", "EDK_IPTYPE": "PERIPHERAL", "FREQ_HZ": "99999985", "GPIO2_BOARD_INTERFACE": "Custom", "GPIO_BOARD_INTERFACE": "push_buttons_5bits", "HAS_BRESP": "1", "HAS_BURST": "0", "HAS_CACHE": "0", "HAS_LOCK": "0", "HAS_PROT": "0", "HAS_QOS": "0", "HAS_REGION": "0", "HAS_RRESP": "1", "HAS_WSTRB": "1", "ID_WIDTH": "0", "INSERT_VIP": "0", "MAX_BURST_LENGTH": "1", "NUM_READ_OUTSTANDING": "8", "NUM_READ_THREADS": "1", "NUM_WRITE_OUTSTANDING": "8", "NUM_WRITE_THREADS": "1", "PHASE": "0.0", "PROTOCOL": "AXI4LITE", "READ_WRITE_MODE": "READ_WRITE", "RUSER_BITS_PER_BYTE": "0", "RUSER_WIDTH": "0", "SUPPORTS_NARROW_BURST": "0", "USE_BOARD_FLOW": "true", "WUSER_BITS_PER_BYTE": "0", "WUSER_WIDTH": "0" }, "phys_addr": 2684354560, "registers": { "GIER": { "access": "read-write", "address_offset": 284, "description": "Global_Interrupt_Enable register", "fields": { "INT_EN": { "access": "read-write", "bit_offset": 31, "bit_width": 1, "description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n" } }, "size": 32 }, "GPIO2_DATA": { "access": "read-write", "address_offset": 8, "description": "Channel-2 AXI GPIO Data register", "fields": { "CH2_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 32 }, "GPIO2_TRI": { "access": "read-write", "address_offset": 12, "description": "Channel-2 AXI GPIO 3-State Control register", "fields": { "CH2_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 32 }, "GPIO_DATA": { "access": "read-write", "address_offset": 0, "description": "Channel-1 AXI GPIO Data register", "fields": { "CH1_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 5, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 5 }, "GPIO_TRI": { "access": "read-write", "address_offset": 4, "description": "Channel-1 AXI GPIO 3-State Control register", "fields": { "CH1_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 5, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 5 }, "IP_IER": { "access": "read-write", "address_offset": 296, "description": "IP Interrupt Enable register", "fields": { "CH1_INT_EN": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" }, "CH2_INT_EN": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" } }, "size": 32 }, "IP_ISR": { "access": "read-write", "address_offset": 288, "description": "IP Interrupt Status register", "fields": { "CH1_INT_S": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n" }, "CH2_INT_S": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n" } }, "size": 32 } }, "state": null, "type": "xilinx.com:ip:axi_gpio:2.0" }, "LEDS": { "addr_range": 65536, "bdtype": null, "device": "", "driver": "", "fullpath": "LEDS", "gpio": {}, "interrupts": {}, "mem_id": "S_AXI", "memtype": "REGISTER", "parameters": { "ADDR_WIDTH": "9", "ARUSER_WIDTH": "0", "AWUSER_WIDTH": "0", "BUSER_WIDTH": "0", "CLK_DOMAIN": "GPIO_zynq_ultra_ps_e_0_0_pl_clk0", "C_ALL_INPUTS": "0", "C_ALL_INPUTS_2": "0", "C_ALL_OUTPUTS": "1", "C_ALL_OUTPUTS_2": "0", "C_BASEADDR": "0xA0010000", "C_DOUT_DEFAULT": "0x00000000", "C_DOUT_DEFAULT_2": "0x00000000", "C_FAMILY": "zynquplus", "C_GPIO2_WIDTH": "32", "C_GPIO_WIDTH": "4", "C_HIGHADDR": "0xA001FFFF", "C_INTERRUPT_PRESENT": "0", "C_IS_DUAL": "0", "C_S_AXI_ADDR_WIDTH": "9", "C_S_AXI_DATA_WIDTH": "32", "C_TRI_DEFAULT": "0xFFFFFFFF", "C_TRI_DEFAULT_2": "0xFFFFFFFF", "Component_Name": "GPIO_axi_gpio_0_2", "DATA_WIDTH": "32", "EDK_IPTYPE": "PERIPHERAL", "FREQ_HZ": "99999985", "GPIO2_BOARD_INTERFACE": "Custom", "GPIO_BOARD_INTERFACE": "led_4bits", "HAS_BRESP": "1", "HAS_BURST": "0", "HAS_CACHE": "0", "HAS_LOCK": "0", "HAS_PROT": "0", "HAS_QOS": "0", "HAS_REGION": "0", "HAS_RRESP": "1", "HAS_WSTRB": "1", "ID_WIDTH": "0", "INSERT_VIP": "0", "MAX_BURST_LENGTH": "1", "NUM_READ_OUTSTANDING": "8", "NUM_READ_THREADS": "1", "NUM_WRITE_OUTSTANDING": "8", "NUM_WRITE_THREADS": "1", "PHASE": "0.0", "PROTOCOL": "AXI4LITE", "READ_WRITE_MODE": "READ_WRITE", "RUSER_BITS_PER_BYTE": "0", "RUSER_WIDTH": "0", "SUPPORTS_NARROW_BURST": "0", "USE_BOARD_FLOW": "true", "WUSER_BITS_PER_BYTE": "0", "WUSER_WIDTH": "0" }, "phys_addr": 2684420096, "registers": { "GIER": { "access": "read-write", "address_offset": 284, "description": "Global_Interrupt_Enable register", "fields": { "INT_EN": { "access": "read-write", "bit_offset": 31, "bit_width": 1, "description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n" } }, "size": 32 }, "GPIO2_DATA": { "access": "read-write", "address_offset": 8, "description": "Channel-2 AXI GPIO Data register", "fields": { "CH2_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 32 }, "GPIO2_TRI": { "access": "read-write", "address_offset": 12, "description": "Channel-2 AXI GPIO 3-State Control register", "fields": { "CH2_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 32 }, "GPIO_DATA": { "access": "read-write", "address_offset": 0, "description": "Channel-1 AXI GPIO Data register", "fields": { "CH1_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 4, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 4 }, "GPIO_TRI": { "access": "read-write", "address_offset": 4, "description": "Channel-1 AXI GPIO 3-State Control register", "fields": { "CH1_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 4, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 4 }, "IP_IER": { "access": "read-write", "address_offset": 296, "description": "IP Interrupt Enable register", "fields": { "CH1_INT_EN": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" }, "CH2_INT_EN": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" } }, "size": 32 }, "IP_ISR": { "access": "read-write", "address_offset": 288, "description": "IP Interrupt Status register", "fields": { "CH1_INT_S": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n" }, "CH2_INT_S": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n" } }, "size": 32 } }, "state": null, "type": "xilinx.com:ip:axi_gpio:2.0" }, "RGB0": { "addr_range": 65536, "bdtype": null, "device": "", "driver": "", "fullpath": "RGB0", "gpio": {}, "interrupts": {}, "mem_id": "S_AXI", "memtype": "REGISTER", "parameters": { "ADDR_WIDTH": "9", "ARUSER_WIDTH": "0", "AWUSER_WIDTH": "0", "BUSER_WIDTH": "0", "CLK_DOMAIN": "GPIO_zynq_ultra_ps_e_0_0_pl_clk0", "C_ALL_INPUTS": "0", "C_ALL_INPUTS_2": "0", "C_ALL_OUTPUTS": "1", "C_ALL_OUTPUTS_2": "0", "C_BASEADDR": "0xA0020000", "C_DOUT_DEFAULT": "0x00000000", "C_DOUT_DEFAULT_2": "0x00000000", "C_FAMILY": "zynquplus", "C_GPIO2_WIDTH": "32", "C_GPIO_WIDTH": "3", "C_HIGHADDR": "0xA002FFFF", "C_INTERRUPT_PRESENT": "0", "C_IS_DUAL": "0", "C_S_AXI_ADDR_WIDTH": "9", "C_S_AXI_DATA_WIDTH": "32", "C_TRI_DEFAULT": "0xFFFFFFFF", "C_TRI_DEFAULT_2": "0xFFFFFFFF", "Component_Name": "GPIO_axi_gpio_0_3", "DATA_WIDTH": "32", "EDK_IPTYPE": "PERIPHERAL", "FREQ_HZ": "99999985", "GPIO2_BOARD_INTERFACE": "Custom", "GPIO_BOARD_INTERFACE": "rgbled0", "HAS_BRESP": "1", "HAS_BURST": "0", "HAS_CACHE": "0", "HAS_LOCK": "0", "HAS_PROT": "0", "HAS_QOS": "0", "HAS_REGION": "0", "HAS_RRESP": "1", "HAS_WSTRB": "1", "ID_WIDTH": "0", "INSERT_VIP": "0", "MAX_BURST_LENGTH": "1", "NUM_READ_OUTSTANDING": "8", "NUM_READ_THREADS": "1", "NUM_WRITE_OUTSTANDING": "8", "NUM_WRITE_THREADS": "1", "PHASE": "0.0", "PROTOCOL": "AXI4LITE", "READ_WRITE_MODE": "READ_WRITE", "RUSER_BITS_PER_BYTE": "0", "RUSER_WIDTH": "0", "SUPPORTS_NARROW_BURST": "0", "USE_BOARD_FLOW": "true", "WUSER_BITS_PER_BYTE": "0", "WUSER_WIDTH": "0" }, "phys_addr": 2684485632, "registers": { "GIER": { "access": "read-write", "address_offset": 284, "description": "Global_Interrupt_Enable register", "fields": { "INT_EN": { "access": "read-write", "bit_offset": 31, "bit_width": 1, "description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n" } }, "size": 32 }, "GPIO2_DATA": { "access": "read-write", "address_offset": 8, "description": "Channel-2 AXI GPIO Data register", "fields": { "CH2_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 32 }, "GPIO2_TRI": { "access": "read-write", "address_offset": 12, "description": "Channel-2 AXI GPIO 3-State Control register", "fields": { "CH2_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 32 }, "GPIO_DATA": { "access": "read-write", "address_offset": 0, "description": "Channel-1 AXI GPIO Data register", "fields": { "CH1_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 3, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 3 }, "GPIO_TRI": { "access": "read-write", "address_offset": 4, "description": "Channel-1 AXI GPIO 3-State Control register", "fields": { "CH1_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 3, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 3 }, "IP_IER": { "access": "read-write", "address_offset": 296, "description": "IP Interrupt Enable register", "fields": { "CH1_INT_EN": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" }, "CH2_INT_EN": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" } }, "size": 32 }, "IP_ISR": { "access": "read-write", "address_offset": 288, "description": "IP Interrupt Status register", "fields": { "CH1_INT_S": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n" }, "CH2_INT_S": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n" } }, "size": 32 } }, "state": null, "type": "xilinx.com:ip:axi_gpio:2.0" }, "RGB1": { "addr_range": 65536, "bdtype": null, "device": "", "driver": "", "fullpath": "RGB1", "gpio": {}, "interrupts": {}, "mem_id": "S_AXI", "memtype": "REGISTER", "parameters": { "ADDR_WIDTH": "9", "ARUSER_WIDTH": "0", "AWUSER_WIDTH": "0", "BUSER_WIDTH": "0", "CLK_DOMAIN": "GPIO_zynq_ultra_ps_e_0_0_pl_clk0", "C_ALL_INPUTS": "0", "C_ALL_INPUTS_2": "0", "C_ALL_OUTPUTS": "1", "C_ALL_OUTPUTS_2": "0", "C_BASEADDR": "0xA0030000", "C_DOUT_DEFAULT": "0x00000000", "C_DOUT_DEFAULT_2": "0x00000000", "C_FAMILY": "zynquplus", "C_GPIO2_WIDTH": "32", "C_GPIO_WIDTH": "3", "C_HIGHADDR": "0xA003FFFF", "C_INTERRUPT_PRESENT": "0", "C_IS_DUAL": "0", "C_S_AXI_ADDR_WIDTH": "9", "C_S_AXI_DATA_WIDTH": "32", "C_TRI_DEFAULT": "0xFFFFFFFF", "C_TRI_DEFAULT_2": "0xFFFFFFFF", "Component_Name": "GPIO_axi_gpio_0_4", "DATA_WIDTH": "32", "EDK_IPTYPE": "PERIPHERAL", "FREQ_HZ": "99999985", "GPIO2_BOARD_INTERFACE": "Custom", "GPIO_BOARD_INTERFACE": "rgbled1", "HAS_BRESP": "1", "HAS_BURST": "0", "HAS_CACHE": "0", "HAS_LOCK": "0", "HAS_PROT": "0", "HAS_QOS": "0", "HAS_REGION": "0", "HAS_RRESP": "1", "HAS_WSTRB": "1", "ID_WIDTH": "0", "INSERT_VIP": "0", "MAX_BURST_LENGTH": "1", "NUM_READ_OUTSTANDING": "8", "NUM_READ_THREADS": "1", "NUM_WRITE_OUTSTANDING": "8", "NUM_WRITE_THREADS": "1", "PHASE": "0.0", "PROTOCOL": "AXI4LITE", "READ_WRITE_MODE": "READ_WRITE", "RUSER_BITS_PER_BYTE": "0", "RUSER_WIDTH": "0", "SUPPORTS_NARROW_BURST": "0", "USE_BOARD_FLOW": "true", "WUSER_BITS_PER_BYTE": "0", "WUSER_WIDTH": "0" }, "phys_addr": 2684551168, "registers": { "GIER": { "access": "read-write", "address_offset": 284, "description": "Global_Interrupt_Enable register", "fields": { "INT_EN": { "access": "read-write", "bit_offset": 31, "bit_width": 1, "description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n" } }, "size": 32 }, "GPIO2_DATA": { "access": "read-write", "address_offset": 8, "description": "Channel-2 AXI GPIO Data register", "fields": { "CH2_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 32 }, "GPIO2_TRI": { "access": "read-write", "address_offset": 12, "description": "Channel-2 AXI GPIO 3-State Control register", "fields": { "CH2_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 32 }, "GPIO_DATA": { "access": "read-write", "address_offset": 0, "description": "Channel-1 AXI GPIO Data register", "fields": { "CH1_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 3, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 3 }, "GPIO_TRI": { "access": "read-write", "address_offset": 4, "description": "Channel-1 AXI GPIO 3-State Control register", "fields": { "CH1_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 3, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 3 }, "IP_IER": { "access": "read-write", "address_offset": 296, "description": "IP Interrupt Enable register", "fields": { "CH1_INT_EN": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" }, "CH2_INT_EN": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" } }, "size": 32 }, "IP_ISR": { "access": "read-write", "address_offset": 288, "description": "IP Interrupt Status register", "fields": { "CH1_INT_S": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n" }, "CH2_INT_S": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n" } }, "size": 32 } }, "state": null, "type": "xilinx.com:ip:axi_gpio:2.0" }, "SWITCHES": { "addr_range": 65536, "bdtype": null, "device": "", "driver": "", "fullpath": "SWITCHES", "gpio": {}, "interrupts": {}, "mem_id": "S_AXI", "memtype": "REGISTER", "parameters": { "ADDR_WIDTH": "9", "ARUSER_WIDTH": "0", "AWUSER_WIDTH": "0", "BUSER_WIDTH": "0", "CLK_DOMAIN": "GPIO_zynq_ultra_ps_e_0_0_pl_clk0", "C_ALL_INPUTS": "1", "C_ALL_INPUTS_2": "0", "C_ALL_OUTPUTS": "0", "C_ALL_OUTPUTS_2": "0", "C_BASEADDR": "0xA0040000", "C_DOUT_DEFAULT": "0x00000000", "C_DOUT_DEFAULT_2": "0x00000000", "C_FAMILY": "zynquplus", "C_GPIO2_WIDTH": "32", "C_GPIO_WIDTH": "4", "C_HIGHADDR": "0xA004FFFF", "C_INTERRUPT_PRESENT": "0", "C_IS_DUAL": "0", "C_S_AXI_ADDR_WIDTH": "9", "C_S_AXI_DATA_WIDTH": "32", "C_TRI_DEFAULT": "0xFFFFFFFF", "C_TRI_DEFAULT_2": "0xFFFFFFFF", "Component_Name": "GPIO_axi_gpio_0_1", "DATA_WIDTH": "32", "EDK_IPTYPE": "PERIPHERAL", "FREQ_HZ": "99999985", "GPIO2_BOARD_INTERFACE": "Custom", "GPIO_BOARD_INTERFACE": "dip_switches_4bits", "HAS_BRESP": "1", "HAS_BURST": "0", "HAS_CACHE": "0", "HAS_LOCK": "0", "HAS_PROT": "0", "HAS_QOS": "0", "HAS_REGION": "0", "HAS_RRESP": "1", "HAS_WSTRB": "1", "ID_WIDTH": "0", "INSERT_VIP": "0", "MAX_BURST_LENGTH": "1", "NUM_READ_OUTSTANDING": "8", "NUM_READ_THREADS": "1", "NUM_WRITE_OUTSTANDING": "8", "NUM_WRITE_THREADS": "1", "PHASE": "0.0", "PROTOCOL": "AXI4LITE", "READ_WRITE_MODE": "READ_WRITE", "RUSER_BITS_PER_BYTE": "0", "RUSER_WIDTH": "0", "SUPPORTS_NARROW_BURST": "0", "USE_BOARD_FLOW": "true", "WUSER_BITS_PER_BYTE": "0", "WUSER_WIDTH": "0" }, "phys_addr": 2684616704, "registers": { "GIER": { "access": "read-write", "address_offset": 284, "description": "Global_Interrupt_Enable register", "fields": { "INT_EN": { "access": "read-write", "bit_offset": 31, "bit_width": 1, "description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n" } }, "size": 32 }, "GPIO2_DATA": { "access": "read-write", "address_offset": 8, "description": "Channel-2 AXI GPIO Data register", "fields": { "CH2_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 32 }, "GPIO2_TRI": { "access": "read-write", "address_offset": 12, "description": "Channel-2 AXI GPIO 3-State Control register", "fields": { "CH2_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 32 }, "GPIO_DATA": { "access": "read-write", "address_offset": 0, "description": "Channel-1 AXI GPIO Data register", "fields": { "CH1_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 4, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 4 }, "GPIO_TRI": { "access": "read-write", "address_offset": 4, "description": "Channel-1 AXI GPIO 3-State Control register", "fields": { "CH1_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 4, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 4 }, "IP_IER": { "access": "read-write", "address_offset": 296, "description": "IP Interrupt Enable register", "fields": { "CH1_INT_EN": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" }, "CH2_INT_EN": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" } }, "size": 32 }, "IP_ISR": { "access": "read-write", "address_offset": 288, "description": "IP Interrupt Status register", "fields": { "CH1_INT_S": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n" }, "CH2_INT_S": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n" } }, "size": 32 } }, "state": null, "type": "xilinx.com:ip:axi_gpio:2.0" }, "ZYNQ": { "device": "", "driver": "", "gpio": {}, "interrupts": {}, "parameters": { "ADDR_WIDTH": "40", "ARUSER_WIDTH": "16", "AWUSER_WIDTH": "16", "BUSER_WIDTH": "0", "CAN0_BOARD_INTERFACE": "custom", "CAN1_BOARD_INTERFACE": "custom", "CLK_DOMAIN": "GPIO_zynq_ultra_ps_e_0_0_pl_clk0", "CSU_BOARD_INTERFACE": "custom", "C_DP_USE_AUDIO": "0", "C_DP_USE_VIDEO": "0", "C_EMIO_GPIO_WIDTH": "41", "C_EN_EMIO_TRACE": "0", "C_EN_FIFO_ENET0": "0", "C_EN_FIFO_ENET1": "0", "C_EN_FIFO_ENET2": "0", "C_EN_FIFO_ENET3": "0", "C_MAXIGP0_DATA_WIDTH": "128", "C_MAXIGP1_DATA_WIDTH": "128", "C_MAXIGP2_DATA_WIDTH": "32", "C_NUM_F2P_0_INTR_INPUTS": "1", "C_NUM_F2P_1_INTR_INPUTS": "1", "C_NUM_FABRIC_RESETS": "1", "C_PL_CLK0_BUF": "TRUE", "C_PL_CLK1_BUF": "FALSE", "C_PL_CLK2_BUF": "FALSE", "C_PL_CLK3_BUF": "FALSE", "C_SAXIGP0_DATA_WIDTH": "128", "C_SAXIGP1_DATA_WIDTH": "128", "C_SAXIGP2_DATA_WIDTH": "128", "C_SAXIGP3_DATA_WIDTH": "128", "C_SAXIGP4_DATA_WIDTH": "128", "C_SAXIGP5_DATA_WIDTH": "128", "C_SAXIGP6_DATA_WIDTH": "128", "C_SD0_INTERNAL_BUS_WIDTH": "4", "C_SD1_INTERNAL_BUS_WIDTH": "5", "C_TRACE_DATA_WIDTH": "32", "C_TRACE_PIPELINE_WIDTH": "8", "C_USE_DEBUG_TEST": "0", "C_USE_DIFF_RW_CLK_GP0": "0", "C_USE_DIFF_RW_CLK_GP1": "0", "C_USE_DIFF_RW_CLK_GP2": "0", "C_USE_DIFF_RW_CLK_GP3": "0", "C_USE_DIFF_RW_CLK_GP4": "0", "C_USE_DIFF_RW_CLK_GP5": "0", "C_USE_DIFF_RW_CLK_GP6": "0", "Component_Name": "GPIO_zynq_ultra_ps_e_0_0", "DATA_WIDTH": "128", "DP_BOARD_INTERFACE": "custom", "EDK_IPTYPE": "PERIPHERAL", "FREQ_HZ": "99999985", "GEM0_BOARD_INTERFACE": "custom", "GEM1_BOARD_INTERFACE": "custom", "GEM2_BOARD_INTERFACE": "custom", "GEM3_BOARD_INTERFACE": "custom", "GPIO_BOARD_INTERFACE": "custom", "HAS_BRESP": "1", "HAS_BURST": "1", "HAS_CACHE": "1", "HAS_LOCK": "1", "HAS_PROT": "1", "HAS_QOS": "1", "HAS_REGION": "0", "HAS_RRESP": "1", "HAS_WSTRB": "1", "ID_WIDTH": "16", "IIC0_BOARD_INTERFACE": "custom", "IIC1_BOARD_INTERFACE": "custom", "INSERT_VIP": "0", "MAX_BURST_LENGTH": "256", "NAND_BOARD_INTERFACE": "custom", "NUM_READ_OUTSTANDING": "8", "NUM_READ_THREADS": "4", "NUM_WRITE_OUTSTANDING": "8", "NUM_WRITE_THREADS": "4", "PCIE_BOARD_INTERFACE": "custom", "PHASE": "0.0", "PJTAG_BOARD_INTERFACE": "custom", "PMU_BOARD_INTERFACE": "custom", "PROTOCOL": "AXI4", "PSU_BANK_0_IO_STANDARD": "LVCMOS33", "PSU_BANK_1_IO_STANDARD": "LVCMOS18", "PSU_BANK_2_IO_STANDARD": "LVCMOS18", "PSU_BANK_3_IO_STANDARD": "LVCMOS18", "PSU_DDR_RAM_HIGHADDR": "0xFFFFFFFF", "PSU_DDR_RAM_HIGHADDR_OFFSET": "0x800000000", "PSU_DDR_RAM_LOWADDR_OFFSET": "0x80000000", "PSU_DYNAMIC_DDR_CONFIG_EN": "0", "PSU_IMPORT_BOARD_PRESET": null, "PSU_MIO_0_DIRECTION": "inout", "PSU_MIO_0_DRIVE_STRENGTH": "12", "PSU_MIO_0_INPUT_TYPE": "cmos", "PSU_MIO_0_POLARITY": "Default", "PSU_MIO_0_PULLUPDOWN": "pullup", "PSU_MIO_0_SLEW": "fast", "PSU_MIO_10_DIRECTION": "inout", "PSU_MIO_10_DRIVE_STRENGTH": "12", "PSU_MIO_10_INPUT_TYPE": "cmos", "PSU_MIO_10_POLARITY": "Default", "PSU_MIO_10_PULLUPDOWN": "pullup", "PSU_MIO_10_SLEW": "fast", "PSU_MIO_11_DIRECTION": "inout", "PSU_MIO_11_DRIVE_STRENGTH": "12", "PSU_MIO_11_INPUT_TYPE": "cmos", "PSU_MIO_11_POLARITY": "Default", "PSU_MIO_11_PULLUPDOWN": "pullup", "PSU_MIO_11_SLEW": "fast", "PSU_MIO_12_DIRECTION": "inout", "PSU_MIO_12_DRIVE_STRENGTH": "12", "PSU_MIO_12_INPUT_TYPE": "cmos", "PSU_MIO_12_POLARITY": "Default", "PSU_MIO_12_PULLUPDOWN": "pullup", "PSU_MIO_12_SLEW": "fast", "PSU_MIO_13_DIRECTION": "inout", "PSU_MIO_13_DRIVE_STRENGTH": "12", "PSU_MIO_13_INPUT_TYPE": "cmos", "PSU_MIO_13_POLARITY": "Default", "PSU_MIO_13_PULLUPDOWN": "pullup", "PSU_MIO_13_SLEW": "fast", "PSU_MIO_14_DIRECTION": "inout", "PSU_MIO_14_DRIVE_STRENGTH": "12", "PSU_MIO_14_INPUT_TYPE": "cmos", "PSU_MIO_14_POLARITY": "Default", "PSU_MIO_14_PULLUPDOWN": "pullup", "PSU_MIO_14_SLEW": "fast", "PSU_MIO_15_DIRECTION": "inout", "PSU_MIO_15_DRIVE_STRENGTH": "12", "PSU_MIO_15_INPUT_TYPE": "cmos", "PSU_MIO_15_POLARITY": "Default", "PSU_MIO_15_PULLUPDOWN": "pullup", "PSU_MIO_15_SLEW": "fast", "PSU_MIO_16_DIRECTION": "inout", "PSU_MIO_16_DRIVE_STRENGTH": "12", "PSU_MIO_16_INPUT_TYPE": "cmos", "PSU_MIO_16_POLARITY": "Default", "PSU_MIO_16_PULLUPDOWN": "pullup", "PSU_MIO_16_SLEW": "fast", "PSU_MIO_17_DIRECTION": "inout", "PSU_MIO_17_DRIVE_STRENGTH": "12", "PSU_MIO_17_INPUT_TYPE": "cmos", "PSU_MIO_17_POLARITY": "Default", "PSU_MIO_17_PULLUPDOWN": "pullup", "PSU_MIO_17_SLEW": "fast", "PSU_MIO_18_DIRECTION": "inout", "PSU_MIO_18_DRIVE_STRENGTH": "12", "PSU_MIO_18_INPUT_TYPE": "cmos", "PSU_MIO_18_POLARITY": "Default", "PSU_MIO_18_PULLUPDOWN": "pullup", "PSU_MIO_18_SLEW": "fast", "PSU_MIO_19_DIRECTION": "inout", "PSU_MIO_19_DRIVE_STRENGTH": "12", "PSU_MIO_19_INPUT_TYPE": "cmos", "PSU_MIO_19_POLARITY": "Default", "PSU_MIO_19_PULLUPDOWN": "pullup", "PSU_MIO_19_SLEW": "fast", "PSU_MIO_1_DIRECTION": "out", "PSU_MIO_1_DRIVE_STRENGTH": "12", "PSU_MIO_1_INPUT_TYPE": "cmos", "PSU_MIO_1_POLARITY": "Default", "PSU_MIO_1_PULLUPDOWN": "pullup", "PSU_MIO_1_SLEW": "fast", "PSU_MIO_20_DIRECTION": "inout", "PSU_MIO_20_DRIVE_STRENGTH": "12", "PSU_MIO_20_INPUT_TYPE": "cmos", "PSU_MIO_20_POLARITY": "Default", "PSU_MIO_20_PULLUPDOWN": "pullup", "PSU_MIO_20_SLEW": "fast", "PSU_MIO_21_DIRECTION": "inout", "PSU_MIO_21_DRIVE_STRENGTH": "12", "PSU_MIO_21_INPUT_TYPE": "cmos", "PSU_MIO_21_POLARITY": "Default", "PSU_MIO_21_PULLUPDOWN": "pullup", "PSU_MIO_21_SLEW": "fast", "PSU_MIO_22_DIRECTION": "out", "PSU_MIO_22_DRIVE_STRENGTH": "12", "PSU_MIO_22_INPUT_TYPE": "cmos", "PSU_MIO_22_POLARITY": "Default", "PSU_MIO_22_PULLUPDOWN": "pullup", "PSU_MIO_22_SLEW": "fast", "PSU_MIO_23_DIRECTION": "inout", "PSU_MIO_23_DRIVE_STRENGTH": "12", "PSU_MIO_23_INPUT_TYPE": "cmos", "PSU_MIO_23_POLARITY": "Default", "PSU_MIO_23_PULLUPDOWN": "pullup", "PSU_MIO_23_SLEW": "fast", "PSU_MIO_24_DIRECTION": "in", "PSU_MIO_24_DRIVE_STRENGTH": "12", "PSU_MIO_24_INPUT_TYPE": "cmos", "PSU_MIO_24_POLARITY": "Default", "PSU_MIO_24_PULLUPDOWN": "pullup", "PSU_MIO_24_SLEW": "fast", "PSU_MIO_25_DIRECTION": "in", "PSU_MIO_25_DRIVE_STRENGTH": "12", "PSU_MIO_25_INPUT_TYPE": "cmos", "PSU_MIO_25_POLARITY": "Default", "PSU_MIO_25_PULLUPDOWN": "pullup", "PSU_MIO_25_SLEW": "fast", "PSU_MIO_26_DIRECTION": "inout", "PSU_MIO_26_DRIVE_STRENGTH": "12", "PSU_MIO_26_INPUT_TYPE": "cmos", "PSU_MIO_26_POLARITY": "Default", "PSU_MIO_26_PULLUPDOWN": "pullup", "PSU_MIO_26_SLEW": "fast", "PSU_MIO_27_DIRECTION": "out", "PSU_MIO_27_DRIVE_STRENGTH": "12", "PSU_MIO_27_INPUT_TYPE": "cmos", "PSU_MIO_27_POLARITY": "Default", "PSU_MIO_27_PULLUPDOWN": "pullup", "PSU_MIO_27_SLEW": "fast", "PSU_MIO_28_DIRECTION": "in", "PSU_MIO_28_DRIVE_STRENGTH": "12", "PSU_MIO_28_INPUT_TYPE": "cmos", "PSU_MIO_28_POLARITY": "Default", "PSU_MIO_28_PULLUPDOWN": "pullup", "PSU_MIO_28_SLEW": "fast", "PSU_MIO_29_DIRECTION": "out", "PSU_MIO_29_DRIVE_STRENGTH": "12", "PSU_MIO_29_INPUT_TYPE": "cmos", "PSU_MIO_29_POLARITY": "Default", "PSU_MIO_29_PULLUPDOWN": "pullup", "PSU_MIO_29_SLEW": "fast", "PSU_MIO_2_DIRECTION": "out", "PSU_MIO_2_DRIVE_STRENGTH": "12", "PSU_MIO_2_INPUT_TYPE": "cmos", "PSU_MIO_2_POLARITY": "Default", "PSU_MIO_2_PULLUPDOWN": "pullup", "PSU_MIO_2_SLEW": "fast", "PSU_MIO_30_DIRECTION": "in", "PSU_MIO_30_DRIVE_STRENGTH": "12", "PSU_MIO_30_INPUT_TYPE": "cmos", "PSU_MIO_30_POLARITY": "Default", "PSU_MIO_30_PULLUPDOWN": "pullup", "PSU_MIO_30_SLEW": "fast", "PSU_MIO_31_DIRECTION": "inout", "PSU_MIO_31_DRIVE_STRENGTH": "12", "PSU_MIO_31_INPUT_TYPE": "cmos", "PSU_MIO_31_POLARITY": "Default", "PSU_MIO_31_PULLUPDOWN": "pullup", "PSU_MIO_31_SLEW": "fast", "PSU_MIO_32_DIRECTION": "out", "PSU_MIO_32_DRIVE_STRENGTH": "12", "PSU_MIO_32_INPUT_TYPE": "cmos", "PSU_MIO_32_POLARITY": "Default", "PSU_MIO_32_PULLUPDOWN": "pullup", "PSU_MIO_32_SLEW": "fast", "PSU_MIO_33_DIRECTION": "in", "PSU_MIO_33_DRIVE_STRENGTH": "12", "PSU_MIO_33_INPUT_TYPE": "cmos", "PSU_MIO_33_POLARITY": "Default", "PSU_MIO_33_PULLUPDOWN": "pullup", "PSU_MIO_33_SLEW": "fast", "PSU_MIO_34_DIRECTION": "inout", "PSU_MIO_34_DRIVE_STRENGTH": "12", "PSU_MIO_34_INPUT_TYPE": "cmos", "PSU_MIO_34_POLARITY": "Default", "PSU_MIO_34_PULLUPDOWN": "pullup", "PSU_MIO_34_SLEW": "fast", "PSU_MIO_35_DIRECTION": "inout", "PSU_MIO_35_DRIVE_STRENGTH": "12", "PSU_MIO_35_INPUT_TYPE": "cmos", "PSU_MIO_35_POLARITY": "Default", "PSU_MIO_35_PULLUPDOWN": "pullup", "PSU_MIO_35_SLEW": "fast", "PSU_MIO_36_DIRECTION": "inout", "PSU_MIO_36_DRIVE_STRENGTH": "12", "PSU_MIO_36_INPUT_TYPE": "cmos", "PSU_MIO_36_POLARITY": "Default", "PSU_MIO_36_PULLUPDOWN": "pullup", "PSU_MIO_36_SLEW": "fast", "PSU_MIO_37_DIRECTION": "inout", "PSU_MIO_37_DRIVE_STRENGTH": "12", "PSU_MIO_37_INPUT_TYPE": "cmos", "PSU_MIO_37_POLARITY": "Default", "PSU_MIO_37_PULLUPDOWN": "pullup", "PSU_MIO_37_SLEW": "fast", "PSU_MIO_38_DIRECTION": "out", "PSU_MIO_38_DRIVE_STRENGTH": "12", "PSU_MIO_38_INPUT_TYPE": "cmos", "PSU_MIO_38_POLARITY": "Default", "PSU_MIO_38_PULLUPDOWN": "pullup", "PSU_MIO_38_SLEW": "fast", "PSU_MIO_39_DIRECTION": "out", "PSU_MIO_39_DRIVE_STRENGTH": "12", "PSU_MIO_39_INPUT_TYPE": "cmos", "PSU_MIO_39_POLARITY": "Default", "PSU_MIO_39_PULLUPDOWN": "pullup", "PSU_MIO_39_SLEW": "fast", "PSU_MIO_3_DIRECTION": "inout", "PSU_MIO_3_DRIVE_STRENGTH": "12", "PSU_MIO_3_INPUT_TYPE": "cmos", "PSU_MIO_3_POLARITY": "Default", "PSU_MIO_3_PULLUPDOWN": "pullup", "PSU_MIO_3_SLEW": "fast", "PSU_MIO_40_DIRECTION": "out", "PSU_MIO_40_DRIVE_STRENGTH": "12", "PSU_MIO_40_INPUT_TYPE": "cmos", "PSU_MIO_40_POLARITY": "Default", "PSU_MIO_40_PULLUPDOWN": "pullup", "PSU_MIO_40_SLEW": "fast", "PSU_MIO_41_DIRECTION": "out", "PSU_MIO_41_DRIVE_STRENGTH": "12", "PSU_MIO_41_INPUT_TYPE": "cmos", "PSU_MIO_41_POLARITY": "Default", "PSU_MIO_41_PULLUPDOWN": "pullup", "PSU_MIO_41_SLEW": "fast", "PSU_MIO_42_DIRECTION": "out", "PSU_MIO_42_DRIVE_STRENGTH": "12", "PSU_MIO_42_INPUT_TYPE": "cmos", "PSU_MIO_42_POLARITY": "Default", "PSU_MIO_42_PULLUPDOWN": "pullup", "PSU_MIO_42_SLEW": "fast", "PSU_MIO_43_DIRECTION": "out", "PSU_MIO_43_DRIVE_STRENGTH": "12", "PSU_MIO_43_INPUT_TYPE": "cmos", "PSU_MIO_43_POLARITY": "Default", "PSU_MIO_43_PULLUPDOWN": "pullup", "PSU_MIO_43_SLEW": "fast", "PSU_MIO_44_DIRECTION": "in", "PSU_MIO_44_DRIVE_STRENGTH": "12", "PSU_MIO_44_INPUT_TYPE": "cmos", "PSU_MIO_44_POLARITY": "Default", "PSU_MIO_44_PULLUPDOWN": "pullup", "PSU_MIO_44_SLEW": "fast", "PSU_MIO_45_DIRECTION": "in", "PSU_MIO_45_DRIVE_STRENGTH": "12", "PSU_MIO_45_INPUT_TYPE": "cmos", "PSU_MIO_45_POLARITY": "Default", "PSU_MIO_45_PULLUPDOWN": "pullup", "PSU_MIO_45_SLEW": "fast", "PSU_MIO_46_DIRECTION": "in", "PSU_MIO_46_DRIVE_STRENGTH": "12", "PSU_MIO_46_INPUT_TYPE": "cmos", "PSU_MIO_46_POLARITY": "Default", "PSU_MIO_46_PULLUPDOWN": "pullup", "PSU_MIO_46_SLEW": "fast", "PSU_MIO_47_DIRECTION": "in", "PSU_MIO_47_DRIVE_STRENGTH": "12", "PSU_MIO_47_INPUT_TYPE": "cmos", "PSU_MIO_47_POLARITY": "Default", "PSU_MIO_47_PULLUPDOWN": "pullup", "PSU_MIO_47_SLEW": "fast", "PSU_MIO_48_DIRECTION": "in", "PSU_MIO_48_DRIVE_STRENGTH": "12", "PSU_MIO_48_INPUT_TYPE": "cmos", "PSU_MIO_48_POLARITY": "Default", "PSU_MIO_48_PULLUPDOWN": "pullup", "PSU_MIO_48_SLEW": "fast", "PSU_MIO_49_DIRECTION": "in", "PSU_MIO_49_DRIVE_STRENGTH": "12", "PSU_MIO_49_INPUT_TYPE": "cmos", "PSU_MIO_49_POLARITY": "Default", "PSU_MIO_49_PULLUPDOWN": "pullup", "PSU_MIO_49_SLEW": "fast", "PSU_MIO_4_DIRECTION": "inout", "PSU_MIO_4_DRIVE_STRENGTH": "12", "PSU_MIO_4_INPUT_TYPE": "cmos", "PSU_MIO_4_POLARITY": "Default", "PSU_MIO_4_PULLUPDOWN": "pullup", "PSU_MIO_4_SLEW": "fast", "PSU_MIO_50_DIRECTION": "out", "PSU_MIO_50_DRIVE_STRENGTH": "12", "PSU_MIO_50_INPUT_TYPE": "cmos", "PSU_MIO_50_POLARITY": "Default", "PSU_MIO_50_PULLUPDOWN": "pullup", "PSU_MIO_50_SLEW": "fast", "PSU_MIO_51_DIRECTION": "inout", "PSU_MIO_51_DRIVE_STRENGTH": "12", "PSU_MIO_51_INPUT_TYPE": "cmos", "PSU_MIO_51_POLARITY": "Default", "PSU_MIO_51_PULLUPDOWN": "pullup", "PSU_MIO_51_SLEW": "fast", "PSU_MIO_52_DIRECTION": "in", "PSU_MIO_52_DRIVE_STRENGTH": "12", "PSU_MIO_52_INPUT_TYPE": "cmos", "PSU_MIO_52_POLARITY": "Default", "PSU_MIO_52_PULLUPDOWN": "pullup", "PSU_MIO_52_SLEW": "fast", "PSU_MIO_53_DIRECTION": "in", "PSU_MIO_53_DRIVE_STRENGTH": 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"PSU_MIO_58_INPUT_TYPE": "cmos", "PSU_MIO_58_POLARITY": "Default", "PSU_MIO_58_PULLUPDOWN": "pullup", "PSU_MIO_58_SLEW": "fast", "PSU_MIO_59_DIRECTION": "inout", "PSU_MIO_59_DRIVE_STRENGTH": "12", "PSU_MIO_59_INPUT_TYPE": "cmos", "PSU_MIO_59_POLARITY": "Default", "PSU_MIO_59_PULLUPDOWN": "pullup", "PSU_MIO_59_SLEW": "fast", "PSU_MIO_5_DIRECTION": "inout", "PSU_MIO_5_DRIVE_STRENGTH": "12", "PSU_MIO_5_INPUT_TYPE": "cmos", "PSU_MIO_5_POLARITY": "Default", "PSU_MIO_5_PULLUPDOWN": "pullup", "PSU_MIO_5_SLEW": "fast", "PSU_MIO_60_DIRECTION": "inout", "PSU_MIO_60_DRIVE_STRENGTH": "12", "PSU_MIO_60_INPUT_TYPE": "cmos", "PSU_MIO_60_POLARITY": "Default", "PSU_MIO_60_PULLUPDOWN": "pullup", "PSU_MIO_60_SLEW": "fast", "PSU_MIO_61_DIRECTION": "inout", "PSU_MIO_61_DRIVE_STRENGTH": "12", "PSU_MIO_61_INPUT_TYPE": "cmos", "PSU_MIO_61_POLARITY": "Default", "PSU_MIO_61_PULLUPDOWN": "pullup", "PSU_MIO_61_SLEW": "fast", "PSU_MIO_62_DIRECTION": "inout", "PSU_MIO_62_DRIVE_STRENGTH": "12", "PSU_MIO_62_INPUT_TYPE": "cmos", "PSU_MIO_62_POLARITY": "Default", "PSU_MIO_62_PULLUPDOWN": "pullup", "PSU_MIO_62_SLEW": "fast", "PSU_MIO_63_DIRECTION": "inout", "PSU_MIO_63_DRIVE_STRENGTH": "12", "PSU_MIO_63_INPUT_TYPE": "cmos", "PSU_MIO_63_POLARITY": "Default", "PSU_MIO_63_PULLUPDOWN": "pullup", "PSU_MIO_63_SLEW": "fast", "PSU_MIO_64_DIRECTION": "in", "PSU_MIO_64_DRIVE_STRENGTH": "12", "PSU_MIO_64_INPUT_TYPE": "cmos", "PSU_MIO_64_POLARITY": "Default", "PSU_MIO_64_PULLUPDOWN": "pullup", "PSU_MIO_64_SLEW": "fast", "PSU_MIO_65_DIRECTION": "in", "PSU_MIO_65_DRIVE_STRENGTH": "12", "PSU_MIO_65_INPUT_TYPE": "cmos", "PSU_MIO_65_POLARITY": "Default", "PSU_MIO_65_PULLUPDOWN": "pullup", "PSU_MIO_65_SLEW": "fast", "PSU_MIO_66_DIRECTION": "inout", "PSU_MIO_66_DRIVE_STRENGTH": "12", "PSU_MIO_66_INPUT_TYPE": "cmos", "PSU_MIO_66_POLARITY": "Default", "PSU_MIO_66_PULLUPDOWN": "pullup", "PSU_MIO_66_SLEW": "fast", "PSU_MIO_67_DIRECTION": "in", "PSU_MIO_67_DRIVE_STRENGTH": "12", "PSU_MIO_67_INPUT_TYPE": "cmos", "PSU_MIO_67_POLARITY": "Default", "PSU_MIO_67_PULLUPDOWN": "pullup", "PSU_MIO_67_SLEW": "fast", "PSU_MIO_68_DIRECTION": "inout", "PSU_MIO_68_DRIVE_STRENGTH": "12", "PSU_MIO_68_INPUT_TYPE": "cmos", "PSU_MIO_68_POLARITY": "Default", "PSU_MIO_68_PULLUPDOWN": "pullup", "PSU_MIO_68_SLEW": "fast", "PSU_MIO_69_DIRECTION": "inout", "PSU_MIO_69_DRIVE_STRENGTH": "12", "PSU_MIO_69_INPUT_TYPE": "cmos", "PSU_MIO_69_POLARITY": "Default", "PSU_MIO_69_PULLUPDOWN": "pullup", "PSU_MIO_69_SLEW": "fast", "PSU_MIO_6_DIRECTION": "inout", "PSU_MIO_6_DRIVE_STRENGTH": "12", "PSU_MIO_6_INPUT_TYPE": "cmos", "PSU_MIO_6_POLARITY": "Default", "PSU_MIO_6_PULLUPDOWN": "pullup", "PSU_MIO_6_SLEW": "fast", "PSU_MIO_70_DIRECTION": "out", "PSU_MIO_70_DRIVE_STRENGTH": "12", "PSU_MIO_70_INPUT_TYPE": "cmos", "PSU_MIO_70_POLARITY": "Default", "PSU_MIO_70_PULLUPDOWN": "pullup", "PSU_MIO_70_SLEW": "fast", "PSU_MIO_71_DIRECTION": "inout", "PSU_MIO_71_DRIVE_STRENGTH": "12", "PSU_MIO_71_INPUT_TYPE": "cmos", "PSU_MIO_71_POLARITY": "Default", "PSU_MIO_71_PULLUPDOWN": "pullup", "PSU_MIO_71_SLEW": "fast", "PSU_MIO_72_DIRECTION": "inout", "PSU_MIO_72_DRIVE_STRENGTH": "12", "PSU_MIO_72_INPUT_TYPE": "cmos", "PSU_MIO_72_POLARITY": "Default", "PSU_MIO_72_PULLUPDOWN": "pullup", "PSU_MIO_72_SLEW": "fast", "PSU_MIO_73_DIRECTION": "inout", "PSU_MIO_73_DRIVE_STRENGTH": "12", "PSU_MIO_73_INPUT_TYPE": "cmos", "PSU_MIO_73_POLARITY": "Default", "PSU_MIO_73_PULLUPDOWN": "pullup", "PSU_MIO_73_SLEW": "fast", "PSU_MIO_74_DIRECTION": "inout", "PSU_MIO_74_DRIVE_STRENGTH": "12", "PSU_MIO_74_INPUT_TYPE": "cmos", "PSU_MIO_74_POLARITY": "Default", "PSU_MIO_74_PULLUPDOWN": "pullup", "PSU_MIO_74_SLEW": "fast", "PSU_MIO_75_DIRECTION": "inout", "PSU_MIO_75_DRIVE_STRENGTH": "12", "PSU_MIO_75_INPUT_TYPE": "cmos", "PSU_MIO_75_POLARITY": "Default", "PSU_MIO_75_PULLUPDOWN": "pullup", "PSU_MIO_75_SLEW": "fast", "PSU_MIO_76_DIRECTION": "inout", "PSU_MIO_76_DRIVE_STRENGTH": "12", "PSU_MIO_76_INPUT_TYPE": "cmos", "PSU_MIO_76_POLARITY": "Default", "PSU_MIO_76_PULLUPDOWN": "pullup", "PSU_MIO_76_SLEW": "fast", "PSU_MIO_77_DIRECTION": "inout", "PSU_MIO_77_DRIVE_STRENGTH": "12", "PSU_MIO_77_INPUT_TYPE": "cmos", "PSU_MIO_77_POLARITY": "Default", "PSU_MIO_77_PULLUPDOWN": "pullup", "PSU_MIO_77_SLEW": "fast", "PSU_MIO_7_DIRECTION": "inout", "PSU_MIO_7_DRIVE_STRENGTH": "12", "PSU_MIO_7_INPUT_TYPE": "cmos", "PSU_MIO_7_POLARITY": "Default", "PSU_MIO_7_PULLUPDOWN": "pullup", "PSU_MIO_7_SLEW": "fast", "PSU_MIO_8_DIRECTION": "inout", "PSU_MIO_8_DRIVE_STRENGTH": "12", "PSU_MIO_8_INPUT_TYPE": "cmos", "PSU_MIO_8_POLARITY": "Default", "PSU_MIO_8_PULLUPDOWN": "pullup", "PSU_MIO_8_SLEW": "fast", "PSU_MIO_9_DIRECTION": "inout", "PSU_MIO_9_DRIVE_STRENGTH": "12", "PSU_MIO_9_INPUT_TYPE": "cmos", "PSU_MIO_9_POLARITY": "Default", "PSU_MIO_9_PULLUPDOWN": "pullup", "PSU_MIO_9_SLEW": "fast", "PSU_MIO_TREE_PERIPHERALS": "SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#SD 0#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#UART 1#UART 1#GPIO1 MIO#GPIO1 MIO#I2C 1#I2C 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#MDIO 1#MDIO 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO", "PSU_MIO_TREE_SIGNALS": "sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#scl_out#sda_out#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#sdio0_wp#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#txd#rxd#gpio1[34]#gpio1[35]#scl_out#sda_out#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem1_mdc#gem1_mdio_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]", "PSU_PERIPHERAL_BOARD_PRESET": null, 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'PSU__DDRC__ENABLE_LP4_SLOWBOOT': '0',\n", " 'PSU__DDRC__EN_2ND_CLK': '0',\n", " 'PSU__DDRC__FGRM': '1X',\n", " 'PSU__DDRC__FREQ_MHZ': '1',\n", " 'PSU__DDRC__HIGH_TEMP': '',\n", " 'PSU__DDRC__PER_BANK_REFRESH': '0',\n", " 'PSU__DDRC__PHY_DBI_MODE': '0',\n", " 'PSU__DDRC__PLL_BYPASS': '0',\n", " 'PSU__DDRC__PWR_DOWN_EN': '0',\n", " 'PSU__DDRC__RANK_ADDR_COUNT': '0',\n", " 'PSU__DDRC__RD_DQS_CENTER': '0',\n", " 'PSU__DDRC__ROW_ADDR_COUNT': '16',\n", " 'PSU__DDRC__SB_TARGET': '16-16-16',\n", " 'PSU__DDRC__SELF_REF_ABORT': '0',\n", " 'PSU__DDRC__SPEED_BIN': 'DDR4_2400R',\n", " 'PSU__DDRC__STATIC_RD_MODE': '0',\n", " 'PSU__DDRC__TRAIN_DATA_EYE': '1',\n", " 'PSU__DDRC__TRAIN_READ_GATE': '1',\n", " 'PSU__DDRC__TRAIN_WRITE_LEVEL': '1',\n", " 'PSU__DDRC__T_FAW': '30.0',\n", " ...},\n", " 'driver': pynq.overlay.DefaultIP,\n", " 'device': }}" ] }, "execution_count": 12, "metadata": { "application/json": { "expanded": false, "root": "ip_dict" } }, "output_type": "execute_result" } ], "source": [ "base.ip_dict" ] }, { "cell_type": "markdown", "id": "452486d9-0f82-4a7d-858f-7c5005f375e8", "metadata": {}, "source": [ "set up the LEDs" ] }, { "cell_type": "code", "execution_count": 13, "id": "23c26361-585a-4e65-98da-f2b9b63c959f", "metadata": {}, "outputs": [], "source": [ "mask = 0xffffffff # needed to specify what bits to use (all of them here)\n", "led_ip = base.ip_dict[\"LEDS\"] # this setups up the pointer to the address in the dictionary\n", "leds = AxiGPIO(led_ip).channel1 # we are using channel 1 of the 2 channels" ] }, { "cell_type": "markdown", "id": "2bdbb489-a2c2-4fed-abab-7f868bc2d5d3", "metadata": {}, "source": [ "write to the LEDs. as a test turn on led 0 and 2" ] }, { "cell_type": "code", "execution_count": 14, "id": "f5ed0656-1f80-475f-865f-02b92549ab3e", "metadata": {}, "outputs": [], "source": [ "leds.write(5,mask)" ] }, { "cell_type": "markdown", "id": "f776e99c-89be-435e-ba77-eb58dcc9a67a", "metadata": {}, "source": [ "alternate way of executing GPIO using MMIO\n", "\n", "first set up pointers to the addresses in the dictionary" ] }, { "cell_type": "code", "execution_count": 16, "id": "e5676b07-3c08-4cda-beb2-959f6f45b2af", "metadata": {}, "outputs": [], "source": [ "led_addr = base.ip_dict[\"LEDS\"][\"phys_addr\"]\n", "led_range = base.ip_dict[\"LEDS\"][\"addr_range\"]" ] }, { "cell_type": "markdown", "id": "a1540a6b-b92e-4030-ae63-17d90c5c8eb7", "metadata": {}, "source": [ "get the pointer to the memory location mapped to the above address. then led_pointer[0] maps to the LEDs, as a 4-bit word, so all you have to do is set bits in this set any of the 4 LEDS. writing 0xa = 10 decimal turns on bits 1 and 3" ] }, { "cell_type": "code", "execution_count": 17, "id": "e6fc8eba-e1d5-402e-b433-c61992ca2fad", "metadata": {}, "outputs": [], "source": [ "led_pointer = MMIO(led_addr, led_range).array\n", "led_pointer[0] = 0xa" ] }, { "cell_type": "markdown", "id": "bf8d2fd4-a18e-42cb-a575-f10e92a18179", "metadata": {}, "source": [ "now setup to read the 4 slide switches" ] }, { "cell_type": "code", "execution_count": 18, "id": "2a3034b7-c2f8-447c-9747-53968fd1a1a4", "metadata": {}, "outputs": [], "source": [ "switches_ip = base.ip_dict[\"SWITCHES\"]\n", "switches = AxiGPIO(switches_ip).channel1" ] }, { "cell_type": "markdown", "id": "2fd509b3-d6d5-4752-a7c8-c2de6c105252", "metadata": {}, "source": [ "read the switches" ] }, { "cell_type": "code", "execution_count": 19, "id": "a05ae929-25ea-4787-94a8-01140f64b857", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "Switches make a hex word: 0x5\n" ] } ], "source": [ "i = switches.read()\n", "print(\"Switches make a hex word: \"+hex(i))" ] }, { "cell_type": "markdown", "id": "0fa502f6-6beb-4bea-9f49-9bf9a2f93498", "metadata": {}, "source": [ "setup to read the push buttons" ] }, { "cell_type": "code", "execution_count": 20, "id": "cca6c6d4-b5d8-4d8b-a123-7fb648d6b998", "metadata": {}, "outputs": [], "source": [ "buttons_ip = base.ip_dict[\"BUTTONS\"]\n", "buttons = AxiGPIO(buttons_ip).channel1" ] }, { "cell_type": "markdown", "id": "6da899f6-18f7-4a39-9406-3158db84f44e", "metadata": {}, "source": [ "read the buttons" ] }, { "cell_type": "code", "execution_count": 21, "id": "8ab2b621-bc8c-43c2-9b34-36c45ab65c71", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "Push buttons make a hex word: 0x10\n" ] } ], "source": [ "j = buttons.read()\n", "print(\"Push buttons make a hex word: \"+hex(j))" ] }, { "cell_type": "markdown", "id": "282f6975-7fdb-4faa-bd11-5551db302c7e", "metadata": {}, "source": [ "setup to set the 2 colored LEDs. each LED takes a 3 bit word where red is LSB, blue is MSB, and green in the middle" ] }, { "cell_type": "code", "execution_count": 22, "id": "c5a5a138-7c97-436e-bb86-6d1ac77b59b9", "metadata": {}, "outputs": [], "source": [ "rgb0_ip = base.ip_dict[\"RGB0\"]\n", "rgb0 = AxiGPIO(rgb0_ip).channel1\n", "rgb1_ip = base.ip_dict[\"RGB1\"]\n", "rgb1 = AxiGPIO(rgb1_ip).channel1\n", "red = 1\n", "green = 2\n", "blue = 4" ] }, { "cell_type": "markdown", "id": "cd1fcbcc-a3d2-465c-b9aa-05be4a6ecbfb", "metadata": {}, "source": [ "set the LEDs" ] }, { "cell_type": "code", "execution_count": 23, "id": "a01b816c-b3f1-4e4d-bb72-64ac6452dbeb", "metadata": {}, "outputs": [], "source": [ "rgb0.write(blue,mask)\n", "rgb1.write(green,mask)" ] }, { "cell_type": "markdown", "id": "4463a81e-51dd-4060-b477-ccff926b9f37", "metadata": {}, "source": [ "turn the LEDs off" ] }, { "cell_type": "code", "execution_count": 24, "id": "853c0a71-65de-4c28-9381-5195ee438377", "metadata": {}, "outputs": [], "source": [ "rgb0.write(0,mask)\n", "rgb1.write(0,mask)" ] }, { "cell_type": "code", "execution_count": null, "id": "cbd82d9b-6ecf-4576-a823-fe3051815a40", "metadata": {}, "outputs": [], "source": [] } ], "metadata": { "kernelspec": { "display_name": "Python 3 (ipykernel)", "language": "python", "name": "python3" }, "language_info": { "codemirror_mode": { "name": "ipython", "version": 3 }, "file_extension": ".py", "mimetype": "text/x-python", "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", "version": "3.10.4" } }, "nbformat": 4, "nbformat_minor": 5 }