{ "cells": [ { "cell_type": "markdown", "id": "ec13b98d-aeff-4171-99a1-7a281c7ebba6", "metadata": {}, "source": [ "initialize python libraries" ] }, { "cell_type": "code", "execution_count": 68, "id": "f65cbc74-4598-4c1d-9178-dd14e3887f4c", "metadata": {}, "outputs": [], "source": [ "from pynq import Overlay, allocate\n", "from rfsoc4x2 import oled\n", "from pynq.lib import AxiGPIO\n", "import numpy as np\n", "import time" ] }, { "cell_type": "markdown", "id": "3ba312d2-d01b-4bf3-a35a-3f5180d1aa53", "metadata": {}, "source": [ "load the FPGA" ] }, { "cell_type": "code", "execution_count": 53, "id": "e1b1e73b-434d-4117-bfc2-02e4e8b17c88", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "overlay completed\n" ] } ], "source": [ "base = Overlay(\"DMA.bit\")\n", "print(\"overlay completed\")" ] }, { "cell_type": "markdown", "id": "1a8dac25-c70d-48b4-bc45-822f422f66f5", "metadata": {}, "source": [ "look at the dictionary (and defined the mask needed to do the IO reads)" ] }, { "cell_type": "code", "execution_count": 54, "id": "44727bef-ac7b-4e3f-b088-b8ee3abf068b", "metadata": {}, "outputs": [ { "data": { "application/json": { "AXI_DMA": { "addr_range": 65536, "bdtype": null, "device": "", "driver": "", "fullpath": "AXI_DMA", "gpio": {}, "interrupts": {}, "mem_id": "S_AXI_LITE", "memtype": "REGISTER", "parameters": { "ADDR_WIDTH": "10", "ARUSER_WIDTH": "0", "AWUSER_WIDTH": "0", "BUSER_WIDTH": "0", "CLK_DOMAIN": "top_zynq_ultra_ps_e_0_0_pl_clk0", "C_BASEADDR": "0xA0000000", "C_DLYTMR_RESOLUTION": "125", "C_ENABLE_MULTI_CHANNEL": "0", "C_FAMILY": "zynquplus", "C_HIGHADDR": "0xA000FFFF", "C_INCLUDE_MM2S": "1", "C_INCLUDE_MM2S_DRE": "0", "C_INCLUDE_MM2S_SF": "1", "C_INCLUDE_S2MM": "1", "C_INCLUDE_S2MM_DRE": "0", "C_INCLUDE_S2MM_SF": "1", "C_INCLUDE_SG": "0", "C_INCREASE_THROUGHPUT": "0", "C_MICRO_DMA": "0", "C_MM2S_BURST_SIZE": "16", "C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH": "32", "C_M_AXIS_MM2S_TDATA_WIDTH": "32", "C_M_AXI_MM2S_ADDR_WIDTH": "32", "C_M_AXI_MM2S_DATA_WIDTH": "32", "C_M_AXI_S2MM_ADDR_WIDTH": "32", "C_M_AXI_S2MM_DATA_WIDTH": "32", "C_M_AXI_SG_ADDR_WIDTH": "32", "C_M_AXI_SG_DATA_WIDTH": "32", "C_NUM_MM2S_CHANNELS": "1", "C_NUM_S2MM_CHANNELS": "1", "C_PRMRY_IS_ACLK_ASYNC": "0", "C_S2MM_BURST_SIZE": "16", "C_SG_INCLUDE_STSCNTRL_STRM": "0", "C_SG_LENGTH_WIDTH": "26", "C_SG_USE_STSAPP_LENGTH": "0", "C_S_AXIS_S2MM_STS_TDATA_WIDTH": "32", "C_S_AXIS_S2MM_TDATA_WIDTH": "32", "C_S_AXI_LITE_ADDR_WIDTH": "10", "C_S_AXI_LITE_DATA_WIDTH": "32", "Component_Name": "top_axi_dma_0_0", "DATA_WIDTH": "32", "EDK_IPTYPE": "PERIPHERAL", "FREQ_HZ": "99999985", "HAS_BRESP": "1", "HAS_BURST": "0", "HAS_CACHE": "0", "HAS_LOCK": "0", "HAS_PROT": "0", "HAS_QOS": "0", "HAS_REGION": "0", "HAS_RRESP": "1", "HAS_TKEEP": "1", "HAS_TLAST": "1", "HAS_TREADY": "1", "HAS_TSTRB": "0", "HAS_WSTRB": "0", "ID_WIDTH": "0", "INSERT_VIP": "0", "LAYERED_METADATA": "undef", "MAX_BURST_LENGTH": "1", "NUM_READ_OUTSTANDING": "8", "NUM_READ_THREADS": "1", "NUM_WRITE_OUTSTANDING": "8", "NUM_WRITE_THREADS": "1", "PHASE": "0.0", "PROTOCOL": "AXI4LITE", "READ_WRITE_MODE": "READ_WRITE", "RUSER_BITS_PER_BYTE": "0", "RUSER_WIDTH": "0", "SUPPORTS_NARROW_BURST": "0", "TDATA_NUM_BYTES": "4", "TDEST_WIDTH": "0", "TID_WIDTH": "0", "TUSER_WIDTH": "0", "WUSER_BITS_PER_BYTE": "0", "WUSER_WIDTH": "0", "c_addr_width": "32", "c_dlytmr_resolution": "125", "c_enable_multi_channel": "0", "c_include_mm2s": "1", "c_include_mm2s_dre": "0", "c_include_mm2s_sf": "1", "c_include_s2mm": "1", "c_include_s2mm_dre": "0", "c_include_s2mm_sf": "1", "c_include_sg": "0", "c_increase_throughput": "0", "c_m_axi_mm2s_data_width": "32", "c_m_axi_s2mm_data_width": "32", "c_m_axis_mm2s_tdata_width": "32", "c_micro_dma": "0", "c_mm2s_burst_size": "16", "c_num_mm2s_channels": "1", "c_num_s2mm_channels": "1", "c_prmry_is_aclk_async": "0", "c_s2mm_burst_size": "16", "c_s_axis_s2mm_tdata_width": "32", "c_sg_include_stscntrl_strm": "0", "c_sg_length_width": "26", "c_sg_use_stsapp_length": "0", "c_single_interface": "0" }, "phys_addr": 2684354560, "registers": { "MM2S_CURDESC": { "access": "read-write", "address_offset": 8, "description": "MM2S DMA Current Descriptor Pointer Register", "fields": { "Current_Descriptor_Pointer": { "access": "read-write", "bit_offset": 6, "bit_width": 26, "description": "Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.\nWhen the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.\nOn error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.\nNote: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.\n" } }, "size": 32 }, "MM2S_CURDESC_MSB": { "access": "read-write", "address_offset": 12, "description": "MM2S DMA Current Descriptor Pointer Register", "fields": { "Current_Descriptor_Pointer": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.\nWhen the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.\nOn error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.\nNote: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.\n" } }, "size": 32 }, "MM2S_DMACR": { "access": "read-write", "address_offset": 0, "description": "MM2S DMA Control Register", "fields": { "Cyclic_BD_Enable": { "access": "read-write", "bit_offset": 4, "bit_width": 1, "description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.\nThis bit is non functional when DMA operates in multichannel mode.\n" }, "Dly_IrqEn": { "access": "read-write", "bit_offset": 13, "bit_width": 1, "description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n" }, "Err_IrqEn": { "access": "read-write", "bit_offset": 14, "bit_width": 1, "description": "Interrupt on Error Interrupt Enable.\n 0 - Error Interrupt disabled\n 1 - Error Interrupt enabled\n" }, "IOC_IrqEn": { "access": "read-write", "bit_offset": 12, "bit_width": 1, "description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n" }, "IRQDelay": { "access": "read-write", "bit_offset": 24, "bit_width": 8, "description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: This field is ignored when AXI DMA is configured for Direct Register Mode.\n" }, "IRQThreshold": { "access": "read-write", "bit_offset": 16, "bit_width": 8, "description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.\n" }, "Keyhole": { "access": "read-write", "bit_offset": 3, "bit_width": 1, "description": "Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when the multichannel feature is enabled or in Direct Register mode.\n" }, "RS": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n" }, "Reset": { "access": "read-write", "bit_offset": 2, "bit_width": 1, "description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.\n" } }, "size": 32 }, "MM2S_DMASR": { "access": "read-write", "address_offset": 4, "description": "MM2S DMA Status Register", "fields": { "DMADecErr": { "access": "read-only", "bit_offset": 6, "bit_width": 1, "description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.\n" }, "DMAIntErr": { "access": "read-only", "bit_offset": 4, "bit_width": 1, "description": "DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts\n" }, "DMASlvErr": { "access": "read-only", "bit_offset": 5, "bit_width": 1, "description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts\n" }, "Dly_Irq": { "access": "read-write", "bit_offset": 13, "bit_width": 1, "description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n" }, "Err_Irq": { "access": "read-write", "bit_offset": 14, "bit_width": 1, "description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. \n0 - No error Interrupt. \n1 - Error interrupt detected.\n" }, "Halted": { "access": "read-only", "bit_offset": 0, "bit_width": 1, "description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n" }, "IOC_Irq": { "access": "read-write", "bit_offset": 12, "bit_width": 1, "description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n" }, "IRQDelaySts": { "access": "read-only", "bit_offset": 24, "bit_width": 8, "description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n" }, "IRQThresholdSts": { "access": "read-only", "bit_offset": 16, "bit_width": 8, "description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n" }, "Idle": { "access": "read-only", "bit_offset": 1, "bit_width": 1, "description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n" }, "SGDecErr": { "access": "read-only", "bit_offset": 10, "bit_width": 1, "description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n" }, "SGIncld": { "access": "read-only", "bit_offset": 3, "bit_width": 1, "description": "1 - Scatter Gather Enabled\n0 - Scatter Gather not enabled\n" }, "SGIntErr": { "access": "read-only", "bit_offset": 8, "bit_width": 1, "description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.\n" }, "SGSlvErr": { "access": "read-only", "bit_offset": 9, "bit_width": 1, "description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. \n" } }, "size": 32 }, "MM2S_LENGTH": { "access": "read-write", "address_offset": 40, "description": "MM2S DMA Transfer Length Register", "fields": { "Length": { "access": "read-write", "bit_offset": 0, "bit_width": 26, "description": "Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.\n" } }, "size": 32 }, "MM2S_SA": { "access": "read-write", "address_offset": 24, "description": "MM2S Source Address Register", "fields": { "Source_Address": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n" } }, "size": 32 }, "MM2S_SA_MSB": { "access": "read-write", "address_offset": 28, "description": "MM2S Source Address Register", "fields": { "Source_Address": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.\nNote: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.\n" } }, "size": 32 }, "MM2S_TAILDESC": { "access": "read-write", "address_offset": 16, "description": "MM2S DMA Tail Descriptor Pointer Register", "fields": { "Tail_Descriptor_Pointer": { "access": "read-write", "bit_offset": 6, "bit_width": 26, "description": "Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.\nWhen AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.\nIf the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.\nNote: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. \n" } }, "size": 32 }, "MM2S_TAILDESC_MSB": { "access": "read-write", "address_offset": 20, "description": "MM2S DMA Tail Descriptor Pointer Register", "fields": { "Tail_Descriptor_Pointer": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.\nWhen AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.\nIf the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.\nNote: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. \n" } }, "size": 32 }, "S2MM_CURDESC": { "access": "read-write", "address_offset": 56, "description": "S2MM DMA Current Descriptor Pointer Register", "fields": { "Current_Descriptor_Pointer": { "access": "read-write", "bit_offset": 6, "bit_width": 26, "description": "Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.\nWhen the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.\nOn error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.\nNote: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). \nBuffer Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and so forth. Any other alignment has undefined results.\n" } }, "size": 32 }, "S2MM_CURDESC_MSB": { "access": "read-write", "address_offset": 60, "description": "S2MM DMA Current Descriptor Pointer Register", "fields": { "Current_Descriptor_Pointer": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.\nWhen the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.\nOn error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.\nNote: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.\n" } }, "size": 32 }, "S2MM_DA": { "access": "read-write", "address_offset": 72, "description": "S2MM DMA Destination Address Register", "fields": { "Destination_Address": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.\n" } }, "size": 32 }, "S2MM_DA_MSB": { "access": "read-write", "address_offset": 76, "description": "S2MM Destination Address Register", "fields": { "Destination_Address": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.\nNote: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.\n" } }, "size": 32 }, "S2MM_DMACR": { "access": "read-write", "address_offset": 48, "description": "S2MM DMA Control Register", "fields": { "Cyclic_BD_Enable": { "access": "read-write", "bit_offset": 4, "bit_width": 1, "description": "When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.\nThis bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode\n" }, "Dly_IrqEn": { "access": "read-write", "bit_offset": 13, "bit_width": 1, "description": "Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.\n" }, "Err_IrqEn": { "access": "read-write", "bit_offset": 14, "bit_width": 1, "description": "Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled\n" }, "IOC_IrqEn": { "access": "read-write", "bit_offset": 12, "bit_width": 1, "description": "Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled\n" }, "IRQDelay": { "access": "read-write", "bit_offset": 24, "bit_width": 8, "description": "Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.\nNote: Setting this value to zero disables the delay timer interrupt.\nNote: Applicable only when Scatter Gather is enabled.\n" }, "IRQThreshold": { "access": "read-write", "bit_offset": 16, "bit_width": 8, "description": "Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.\nNote: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.\nNote: Applicable only when Scatter Gather is enabled.\n" }, "Keyhole": { "access": "read-write", "bit_offset": 3, "bit_width": 1, "description": "Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.\nThis bit is non functional when DMA is used in multichannel mode.\n" }, "RS": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Run / Stop control for controlling running and stopping of the DMA channel.\n 0 - Stop, DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. \n AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.\n For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.\n The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.\n 1 - Run, Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.\n" }, "Reset": { "access": "read-write", "bit_offset": 2, "bit_width": 1, "description": "Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.\nAXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress\n" } }, "size": 32 }, "S2MM_DMASR": { "access": "read-write", "address_offset": 52, "description": "S2MM DMA Status Register", "fields": { "DMADecErr": { "access": "read-only", "bit_offset": 6, "bit_width": 1, "description": "DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.\n" }, "DMAIntErr": { "access": "read-only", "bit_offset": 4, "bit_width": 1, "description": "DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.\nThis error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.\n" }, "DMASlvErr": { "access": "read-only", "bit_offset": 5, "bit_width": 1, "description": "DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.\n" }, "Dly_Irq": { "access": "read-write", "bit_offset": 13, "bit_width": 1, "description": "Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. \n" }, "Err_Irq": { "access": "read-write", "bit_offset": 14, "bit_width": 1, "description": "Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.\nWriting a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.\n" }, "Halted": { "access": "read-only", "bit_offset": 0, "bit_width": 1, "description": "DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 \nNote: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.\n" }, "IOC_Irq": { "access": "read-write", "bit_offset": 12, "bit_width": 1, "description": "Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.\n" }, "IRQDelaySts": { "access": "read-only", "bit_offset": 24, "bit_width": 8, "description": "Interrupt Delay Time Status. Indicates current interrupt delay time value.\nNote: Applicable only when Scatter Gather is enabled.\n" }, "IRQThresholdSts": { "access": "read-only", "bit_offset": 16, "bit_width": 8, "description": "Interrupt Threshold Status. Indicates current interrupt threshold value.\nNote: Applicable only when Scatter Gather is enabled.\n" }, "Idle": { "access": "read-only", "bit_offset": 1, "bit_width": 1, "description": "DMA Channel Idle. Indicates the state of AXI DMA operations.\nFor Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.\nFor Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.\n" }, "SGDecErr": { "access": "read-only", "bit_offset": 10, "bit_width": 1, "description": "Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n" }, "SGIncld": { "access": "read-only", "bit_offset": 3, "bit_width": 1, "description": "Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.\n" }, "SGIntErr": { "access": "read-only", "bit_offset": 8, "bit_width": 1, "description": "Scatter Gather Internal Error. This error occurs if a descriptor with the \"Complete bit\" already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled. \n" }, "SGSlvErr": { "access": "read-only", "bit_offset": 9, "bit_width": 1, "description": "Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. \n" } }, "size": 32 }, "S2MM_LENGTH": { "access": "read-write", "address_offset": 88, "description": "S2MM DMA Transfer Length Register", "fields": { "Length": { "access": "read-write", "bit_offset": 0, "bit_width": 26, "description": "Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.\nAt the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.\nNote: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. \n" } }, "size": 32 }, "S2MM_TAILDESC": { "access": "read-write", "address_offset": 64, "description": "S2MM DMA Tail Descriptor Pointer Register", "fields": { "Tail_Descriptor_Pointer": { "access": "read-write", "bit_offset": 6, "bit_width": 26, "description": "Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.\nWhen AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.\nIf the AXI DMA Channel DMACR.RS bit is set to 0 (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.\nNote: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. \nDescriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. \n" } }, "size": 32 }, "S2MM_TAILDESC_MSB": { "access": "read-write", "address_offset": 68, "description": "S2MM DMA Tail Descriptor Pointer Register", "fields": { "Tail_Descriptor_Pointer": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.\nWhen AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.\nIf the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.\nNote: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. \n" } }, "size": 32 }, "SG_CTL": { "access": "read-write", "address_offset": 44, "description": "Scatter/Gather User and Cache Control Register", "fields": { "SG_CACHE": { "access": "read-write", "bit_offset": 0, "bit_width": 4, "description": "Scatter/Gather Cache Control. Values written in this register reflect on the m_axi_sg_arcache and m_axi_sg_awcache signals of the M_AXI_SG interface.\n" }, "SG_USER": { "access": "read-write", "bit_offset": 8, "bit_width": 4, "description": "Scatter/Gather User Control. Values written in this register reflect on the m_axi_sg_aruser and m_axi_sg_awuser signals of the M_AXI_SG interface.\n" } }, "size": 32 } }, "state": null, "type": "xilinx.com:ip:axi_dma:7.1" }, "FIFO_RD": { "addr_range": 65536, "bdtype": null, "device": "", "driver": "", "fullpath": "FIFO_RD", "gpio": {}, "interrupts": {}, "mem_id": "S_AXI", "memtype": "REGISTER", "parameters": { "ADDR_WIDTH": "9", "ARUSER_WIDTH": "0", "AWUSER_WIDTH": "0", "BUSER_WIDTH": "0", "CLK_DOMAIN": "top_zynq_ultra_ps_e_0_0_pl_clk0", "C_ALL_INPUTS": "0", "C_ALL_INPUTS_2": "0", "C_ALL_OUTPUTS": "0", "C_ALL_OUTPUTS_2": "0", "C_BASEADDR": "0xA0010000", "C_DOUT_DEFAULT": "0x00000000", "C_DOUT_DEFAULT_2": "0x00000000", "C_FAMILY": "zynquplus", "C_GPIO2_WIDTH": "32", "C_GPIO_WIDTH": "32", "C_HIGHADDR": "0xA001FFFF", "C_INTERRUPT_PRESENT": "0", "C_IS_DUAL": "0", "C_S_AXI_ADDR_WIDTH": "9", "C_S_AXI_DATA_WIDTH": "32", "C_TRI_DEFAULT": "0xFFFFFFFF", "C_TRI_DEFAULT_2": "0xFFFFFFFF", "Component_Name": "top_axi_gpio_0_1", "DATA_WIDTH": "32", "EDK_IPTYPE": "PERIPHERAL", "FREQ_HZ": "99999985", "GPIO2_BOARD_INTERFACE": "Custom", "GPIO_BOARD_INTERFACE": "Custom", "HAS_BRESP": "1", "HAS_BURST": "0", "HAS_CACHE": "0", "HAS_LOCK": "0", "HAS_PROT": "0", "HAS_QOS": "0", "HAS_REGION": "0", "HAS_RRESP": "1", "HAS_WSTRB": "1", "ID_WIDTH": "0", "INSERT_VIP": "0", "MAX_BURST_LENGTH": "1", "NUM_READ_OUTSTANDING": "8", "NUM_READ_THREADS": "1", "NUM_WRITE_OUTSTANDING": "8", "NUM_WRITE_THREADS": "1", "PHASE": "0.0", "PROTOCOL": "AXI4LITE", "READ_WRITE_MODE": "READ_WRITE", "RUSER_BITS_PER_BYTE": "0", "RUSER_WIDTH": "0", "SUPPORTS_NARROW_BURST": "0", "USE_BOARD_FLOW": "false", "WUSER_BITS_PER_BYTE": "0", "WUSER_WIDTH": "0" }, "phys_addr": 2684420096, "registers": { "GIER": { "access": "read-write", "address_offset": 284, "description": "Global_Interrupt_Enable register", "fields": { "INT_EN": { "access": "read-write", "bit_offset": 31, "bit_width": 1, "description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n" } }, "size": 32 }, "GPIO2_DATA": { "access": "read-write", "address_offset": 8, "description": "Channel-2 AXI GPIO Data register", "fields": { "CH2_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 32 }, "GPIO2_TRI": { "access": "read-write", "address_offset": 12, "description": "Channel-2 AXI GPIO 3-State Control register", "fields": { "CH2_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 32 }, "GPIO_DATA": { "access": "read-write", "address_offset": 0, "description": "Channel-1 AXI GPIO Data register", "fields": { "CH1_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 32 }, "GPIO_TRI": { "access": "read-write", "address_offset": 4, "description": "Channel-1 AXI GPIO 3-State Control register", "fields": { "CH1_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 32 }, "IP_IER": { "access": "read-write", "address_offset": 296, "description": "IP Interrupt Enable register", "fields": { "CH1_INT_EN": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" }, "CH2_INT_EN": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" } }, "size": 32 }, "IP_ISR": { "access": "read-write", "address_offset": 288, "description": "IP Interrupt Status register", "fields": { "CH1_INT_S": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n" }, "CH2_INT_S": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n" } }, "size": 32 } }, "state": null, "type": "xilinx.com:ip:axi_gpio:2.0" }, "FIFO_WR": { "addr_range": 65536, "bdtype": null, "device": "", "driver": "", "fullpath": "FIFO_WR", "gpio": {}, "interrupts": {}, "mem_id": "S_AXI", "memtype": "REGISTER", "parameters": { "ADDR_WIDTH": "9", "ARUSER_WIDTH": "0", "AWUSER_WIDTH": "0", "BUSER_WIDTH": "0", "CLK_DOMAIN": "top_zynq_ultra_ps_e_0_0_pl_clk0", "C_ALL_INPUTS": "0", "C_ALL_INPUTS_2": "0", "C_ALL_OUTPUTS": "0", "C_ALL_OUTPUTS_2": "0", "C_BASEADDR": "0xA0020000", "C_DOUT_DEFAULT": "0x00000000", "C_DOUT_DEFAULT_2": "0x00000000", "C_FAMILY": "zynquplus", "C_GPIO2_WIDTH": "32", "C_GPIO_WIDTH": "32", "C_HIGHADDR": "0xA002FFFF", "C_INTERRUPT_PRESENT": "0", "C_IS_DUAL": "0", "C_S_AXI_ADDR_WIDTH": "9", "C_S_AXI_DATA_WIDTH": "32", "C_TRI_DEFAULT": "0xFFFFFFFF", "C_TRI_DEFAULT_2": "0xFFFFFFFF", "Component_Name": "top_axi_gpio_0_0", "DATA_WIDTH": "32", "EDK_IPTYPE": "PERIPHERAL", "FREQ_HZ": "99999985", "GPIO2_BOARD_INTERFACE": "Custom", "GPIO_BOARD_INTERFACE": "Custom", "HAS_BRESP": "1", "HAS_BURST": "0", "HAS_CACHE": "0", "HAS_LOCK": "0", "HAS_PROT": "0", "HAS_QOS": "0", "HAS_REGION": "0", "HAS_RRESP": "1", "HAS_WSTRB": "1", "ID_WIDTH": "0", "INSERT_VIP": "0", "MAX_BURST_LENGTH": "1", "NUM_READ_OUTSTANDING": "8", "NUM_READ_THREADS": "1", "NUM_WRITE_OUTSTANDING": "8", "NUM_WRITE_THREADS": "1", "PHASE": "0.0", "PROTOCOL": "AXI4LITE", "READ_WRITE_MODE": "READ_WRITE", "RUSER_BITS_PER_BYTE": "0", "RUSER_WIDTH": "0", "SUPPORTS_NARROW_BURST": "0", "USE_BOARD_FLOW": "false", "WUSER_BITS_PER_BYTE": "0", "WUSER_WIDTH": "0" }, "phys_addr": 2684485632, "registers": { "GIER": { "access": "read-write", "address_offset": 284, "description": "Global_Interrupt_Enable register", "fields": { "INT_EN": { "access": "read-write", "bit_offset": 31, "bit_width": 1, "description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n" } }, "size": 32 }, "GPIO2_DATA": { "access": "read-write", "address_offset": 8, "description": "Channel-2 AXI GPIO Data register", "fields": { "CH2_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 32 }, "GPIO2_TRI": { "access": "read-write", "address_offset": 12, "description": "Channel-2 AXI GPIO 3-State Control register", "fields": { "CH2_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 32 }, "GPIO_DATA": { "access": "read-write", "address_offset": 0, "description": "Channel-1 AXI GPIO Data register", "fields": { "CH1_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 32 }, "GPIO_TRI": { "access": "read-write", "address_offset": 4, "description": "Channel-1 AXI GPIO 3-State Control register", "fields": { "CH1_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 32 }, "IP_IER": { "access": "read-write", "address_offset": 296, "description": "IP Interrupt Enable register", "fields": { "CH1_INT_EN": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" }, "CH2_INT_EN": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" } }, "size": 32 }, "IP_ISR": { "access": "read-write", "address_offset": 288, "description": "IP Interrupt Status register", "fields": { "CH1_INT_S": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n" }, "CH2_INT_S": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n" } }, "size": 32 } }, "state": null, "type": "xilinx.com:ip:axi_gpio:2.0" }, "VERSION": { "addr_range": 65536, "bdtype": null, "device": "", "driver": "", "fullpath": "VERSION", "gpio": {}, "interrupts": {}, "mem_id": "S_AXI", "memtype": "REGISTER", "parameters": { "ADDR_WIDTH": "9", "ARUSER_WIDTH": "0", "AWUSER_WIDTH": "0", "BUSER_WIDTH": "0", "CLK_DOMAIN": "top_zynq_ultra_ps_e_0_0_pl_clk0", "C_ALL_INPUTS": "0", "C_ALL_INPUTS_2": "0", "C_ALL_OUTPUTS": "0", "C_ALL_OUTPUTS_2": "0", "C_BASEADDR": "0xA0030000", "C_DOUT_DEFAULT": "0x00000000", "C_DOUT_DEFAULT_2": "0x00000000", "C_FAMILY": "zynquplus", "C_GPIO2_WIDTH": "32", "C_GPIO_WIDTH": "32", "C_HIGHADDR": "0xA003FFFF", "C_INTERRUPT_PRESENT": "0", "C_IS_DUAL": "0", "C_S_AXI_ADDR_WIDTH": "9", "C_S_AXI_DATA_WIDTH": "32", "C_TRI_DEFAULT": "0xFFFFFFFF", "C_TRI_DEFAULT_2": "0xFFFFFFFF", "Component_Name": "top_axi_gpio_0_2", "DATA_WIDTH": "32", "EDK_IPTYPE": "PERIPHERAL", "FREQ_HZ": "99999985", "GPIO2_BOARD_INTERFACE": "Custom", "GPIO_BOARD_INTERFACE": "Custom", "HAS_BRESP": "1", "HAS_BURST": "0", "HAS_CACHE": "0", "HAS_LOCK": "0", "HAS_PROT": "0", "HAS_QOS": "0", "HAS_REGION": "0", "HAS_RRESP": "1", "HAS_WSTRB": "1", "ID_WIDTH": "0", "INSERT_VIP": "0", "MAX_BURST_LENGTH": "1", "NUM_READ_OUTSTANDING": "8", "NUM_READ_THREADS": "1", "NUM_WRITE_OUTSTANDING": "8", "NUM_WRITE_THREADS": "1", "PHASE": "0.0", "PROTOCOL": "AXI4LITE", "READ_WRITE_MODE": "READ_WRITE", "RUSER_BITS_PER_BYTE": "0", "RUSER_WIDTH": "0", "SUPPORTS_NARROW_BURST": "0", "USE_BOARD_FLOW": "false", "WUSER_BITS_PER_BYTE": "0", "WUSER_WIDTH": "0" }, "phys_addr": 2684551168, "registers": { "GIER": { "access": "read-write", "address_offset": 284, "description": "Global_Interrupt_Enable register", "fields": { "INT_EN": { "access": "read-write", "bit_offset": 31, "bit_width": 1, "description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n" } }, "size": 32 }, "GPIO2_DATA": { "access": "read-write", "address_offset": 8, "description": "Channel-2 AXI GPIO Data register", "fields": { "CH2_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 32 }, "GPIO2_TRI": { "access": "read-write", "address_offset": 12, "description": "Channel-2 AXI GPIO 3-State Control register", "fields": { "CH2_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 32 }, "GPIO_DATA": { "access": "read-write", "address_offset": 0, "description": "Channel-1 AXI GPIO Data register", "fields": { "CH1_DATA": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n" } }, "size": 32 }, "GPIO_TRI": { "access": "read-write", "address_offset": 4, "description": "Channel-1 AXI GPIO 3-State Control register", "fields": { "CH1_TRI": { "access": "read-write", "bit_offset": 0, "bit_width": 32, "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n" } }, "size": 32 }, "IP_IER": { "access": "read-write", "address_offset": 296, "description": "IP Interrupt Enable register", "fields": { "CH1_INT_EN": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" }, "CH2_INT_EN": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n" } }, "size": 32 }, "IP_ISR": { "access": "read-write", "address_offset": 288, "description": "IP Interrupt Status register", "fields": { "CH1_INT_S": { "access": "read-write", "bit_offset": 0, "bit_width": 1, "description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n" }, "CH2_INT_S": { "access": "read-write", "bit_offset": 1, "bit_width": 1, "description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n" } }, "size": 32 } }, "state": null, "type": "xilinx.com:ip:axi_gpio:2.0" }, "ZYNQ": { "device": "", "driver": "", "gpio": {}, "interrupts": {}, "parameters": { "ADDR_WIDTH": "40", "ARUSER_WIDTH": "16", "AWUSER_WIDTH": "16", "BUSER_WIDTH": "0", "CAN0_BOARD_INTERFACE": "custom", "CAN1_BOARD_INTERFACE": "custom", "CLK_DOMAIN": "top_zynq_ultra_ps_e_0_0_pl_clk0", "CSU_BOARD_INTERFACE": "custom", "C_BASEADDR": "0x00000000", "C_DP_USE_AUDIO": "0", "C_DP_USE_VIDEO": "0", "C_EMIO_GPIO_WIDTH": "41", "C_EN_EMIO_TRACE": "0", "C_EN_FIFO_ENET0": "0", "C_EN_FIFO_ENET1": "0", "C_EN_FIFO_ENET2": "0", "C_EN_FIFO_ENET3": "0", "C_HIGHADDR": "0x7FFFFFFF", "C_MAXIGP0_DATA_WIDTH": "128", "C_MAXIGP1_DATA_WIDTH": "128", "C_MAXIGP2_DATA_WIDTH": "32", "C_NUM_F2P_0_INTR_INPUTS": "1", "C_NUM_F2P_1_INTR_INPUTS": "1", "C_NUM_FABRIC_RESETS": "1", "C_PL_CLK0_BUF": "TRUE", "C_PL_CLK1_BUF": "FALSE", "C_PL_CLK2_BUF": "FALSE", "C_PL_CLK3_BUF": "FALSE", "C_SAXIGP0_DATA_WIDTH": "128", "C_SAXIGP1_DATA_WIDTH": "128", "C_SAXIGP2_DATA_WIDTH": "128", "C_SAXIGP3_DATA_WIDTH": "128", "C_SAXIGP4_DATA_WIDTH": "128", "C_SAXIGP5_DATA_WIDTH": "128", "C_SAXIGP6_DATA_WIDTH": "128", "C_SD0_INTERNAL_BUS_WIDTH": "4", "C_SD1_INTERNAL_BUS_WIDTH": "5", "C_TRACE_DATA_WIDTH": "32", "C_TRACE_PIPELINE_WIDTH": "8", "C_USE_DEBUG_TEST": "0", "C_USE_DIFF_RW_CLK_GP0": "0", "C_USE_DIFF_RW_CLK_GP1": "0", "C_USE_DIFF_RW_CLK_GP2": "0", "C_USE_DIFF_RW_CLK_GP3": "0", "C_USE_DIFF_RW_CLK_GP4": "0", "C_USE_DIFF_RW_CLK_GP5": "0", "C_USE_DIFF_RW_CLK_GP6": "0", "Component_Name": "top_zynq_ultra_ps_e_0_0", "DATA_WIDTH": "128", "DP_BOARD_INTERFACE": "custom", "EDK_IPTYPE": "PERIPHERAL", "FREQ_HZ": "99999985", "GEM0_BOARD_INTERFACE": "custom", "GEM1_BOARD_INTERFACE": "custom", "GEM2_BOARD_INTERFACE": "custom", "GEM3_BOARD_INTERFACE": "custom", "GPIO_BOARD_INTERFACE": "custom", "HAS_BRESP": "1", "HAS_BURST": "1", "HAS_CACHE": "1", "HAS_LOCK": "1", "HAS_PROT": "1", "HAS_QOS": "1", "HAS_REGION": "0", "HAS_RRESP": "1", "HAS_WSTRB": "1", "ID_WIDTH": "16", "IIC0_BOARD_INTERFACE": "custom", "IIC1_BOARD_INTERFACE": "custom", "INSERT_VIP": "0", "MAX_BURST_LENGTH": "256", "NAND_BOARD_INTERFACE": "custom", "NUM_READ_OUTSTANDING": "8", "NUM_READ_THREADS": "4", "NUM_WRITE_OUTSTANDING": "8", "NUM_WRITE_THREADS": "4", "PCIE_BOARD_INTERFACE": "custom", "PHASE": "0.0", "PJTAG_BOARD_INTERFACE": "custom", "PMU_BOARD_INTERFACE": "custom", "PROTOCOL": "AXI4", "PSU_BANK_0_IO_STANDARD": "LVCMOS33", "PSU_BANK_1_IO_STANDARD": "LVCMOS18", "PSU_BANK_2_IO_STANDARD": "LVCMOS18", "PSU_BANK_3_IO_STANDARD": "LVCMOS18", "PSU_DDR_RAM_HIGHADDR": "0xFFFFFFFF", "PSU_DDR_RAM_HIGHADDR_OFFSET": "0x800000000", "PSU_DDR_RAM_LOWADDR_OFFSET": "0x80000000", "PSU_DYNAMIC_DDR_CONFIG_EN": "0", "PSU_IMPORT_BOARD_PRESET": null, "PSU_MIO_0_DIRECTION": "inout", "PSU_MIO_0_DRIVE_STRENGTH": "12", "PSU_MIO_0_INPUT_TYPE": "cmos", "PSU_MIO_0_POLARITY": "Default", "PSU_MIO_0_PULLUPDOWN": "pullup", "PSU_MIO_0_SLEW": "fast", "PSU_MIO_10_DIRECTION": "inout", "PSU_MIO_10_DRIVE_STRENGTH": "12", "PSU_MIO_10_INPUT_TYPE": "cmos", "PSU_MIO_10_POLARITY": "Default", "PSU_MIO_10_PULLUPDOWN": "pullup", "PSU_MIO_10_SLEW": "fast", "PSU_MIO_11_DIRECTION": "inout", "PSU_MIO_11_DRIVE_STRENGTH": "12", "PSU_MIO_11_INPUT_TYPE": "cmos", "PSU_MIO_11_POLARITY": "Default", "PSU_MIO_11_PULLUPDOWN": "pullup", "PSU_MIO_11_SLEW": "fast", "PSU_MIO_12_DIRECTION": "inout", "PSU_MIO_12_DRIVE_STRENGTH": "12", "PSU_MIO_12_INPUT_TYPE": "cmos", "PSU_MIO_12_POLARITY": "Default", "PSU_MIO_12_PULLUPDOWN": "pullup", "PSU_MIO_12_SLEW": "fast", "PSU_MIO_13_DIRECTION": "inout", "PSU_MIO_13_DRIVE_STRENGTH": "12", "PSU_MIO_13_INPUT_TYPE": "cmos", "PSU_MIO_13_POLARITY": "Default", "PSU_MIO_13_PULLUPDOWN": "pullup", "PSU_MIO_13_SLEW": "fast", "PSU_MIO_14_DIRECTION": "inout", "PSU_MIO_14_DRIVE_STRENGTH": "12", "PSU_MIO_14_INPUT_TYPE": "cmos", "PSU_MIO_14_POLARITY": "Default", "PSU_MIO_14_PULLUPDOWN": "pullup", "PSU_MIO_14_SLEW": "fast", "PSU_MIO_15_DIRECTION": "inout", "PSU_MIO_15_DRIVE_STRENGTH": "12", "PSU_MIO_15_INPUT_TYPE": "cmos", "PSU_MIO_15_POLARITY": "Default", "PSU_MIO_15_PULLUPDOWN": "pullup", "PSU_MIO_15_SLEW": "fast", "PSU_MIO_16_DIRECTION": "inout", "PSU_MIO_16_DRIVE_STRENGTH": "12", "PSU_MIO_16_INPUT_TYPE": "cmos", "PSU_MIO_16_POLARITY": "Default", "PSU_MIO_16_PULLUPDOWN": "pullup", "PSU_MIO_16_SLEW": "fast", "PSU_MIO_17_DIRECTION": "inout", "PSU_MIO_17_DRIVE_STRENGTH": "12", "PSU_MIO_17_INPUT_TYPE": "cmos", "PSU_MIO_17_POLARITY": "Default", "PSU_MIO_17_PULLUPDOWN": "pullup", "PSU_MIO_17_SLEW": "fast", "PSU_MIO_18_DIRECTION": "inout", "PSU_MIO_18_DRIVE_STRENGTH": "12", "PSU_MIO_18_INPUT_TYPE": "cmos", "PSU_MIO_18_POLARITY": "Default", "PSU_MIO_18_PULLUPDOWN": "pullup", "PSU_MIO_18_SLEW": "fast", "PSU_MIO_19_DIRECTION": "inout", "PSU_MIO_19_DRIVE_STRENGTH": "12", "PSU_MIO_19_INPUT_TYPE": "cmos", "PSU_MIO_19_POLARITY": "Default", "PSU_MIO_19_PULLUPDOWN": "pullup", "PSU_MIO_19_SLEW": "fast", "PSU_MIO_1_DIRECTION": "out", "PSU_MIO_1_DRIVE_STRENGTH": "12", "PSU_MIO_1_INPUT_TYPE": "cmos", "PSU_MIO_1_POLARITY": "Default", "PSU_MIO_1_PULLUPDOWN": "pullup", "PSU_MIO_1_SLEW": "fast", "PSU_MIO_20_DIRECTION": "inout", "PSU_MIO_20_DRIVE_STRENGTH": "12", "PSU_MIO_20_INPUT_TYPE": "cmos", "PSU_MIO_20_POLARITY": "Default", "PSU_MIO_20_PULLUPDOWN": "pullup", "PSU_MIO_20_SLEW": "fast", "PSU_MIO_21_DIRECTION": "inout", "PSU_MIO_21_DRIVE_STRENGTH": "12", "PSU_MIO_21_INPUT_TYPE": "cmos", "PSU_MIO_21_POLARITY": "Default", "PSU_MIO_21_PULLUPDOWN": "pullup", "PSU_MIO_21_SLEW": "fast", "PSU_MIO_22_DIRECTION": "out", "PSU_MIO_22_DRIVE_STRENGTH": "12", "PSU_MIO_22_INPUT_TYPE": "cmos", "PSU_MIO_22_POLARITY": "Default", "PSU_MIO_22_PULLUPDOWN": "pullup", "PSU_MIO_22_SLEW": "fast", "PSU_MIO_23_DIRECTION": "inout", "PSU_MIO_23_DRIVE_STRENGTH": "12", "PSU_MIO_23_INPUT_TYPE": "cmos", "PSU_MIO_23_POLARITY": "Default", "PSU_MIO_23_PULLUPDOWN": "pullup", "PSU_MIO_23_SLEW": "fast", "PSU_MIO_24_DIRECTION": "in", "PSU_MIO_24_DRIVE_STRENGTH": "12", "PSU_MIO_24_INPUT_TYPE": "cmos", "PSU_MIO_24_POLARITY": "Default", "PSU_MIO_24_PULLUPDOWN": "pullup", "PSU_MIO_24_SLEW": "fast", "PSU_MIO_25_DIRECTION": "in", "PSU_MIO_25_DRIVE_STRENGTH": "12", "PSU_MIO_25_INPUT_TYPE": "cmos", "PSU_MIO_25_POLARITY": "Default", "PSU_MIO_25_PULLUPDOWN": "pullup", "PSU_MIO_25_SLEW": "fast", "PSU_MIO_26_DIRECTION": "inout", "PSU_MIO_26_DRIVE_STRENGTH": "12", "PSU_MIO_26_INPUT_TYPE": "cmos", "PSU_MIO_26_POLARITY": "Default", "PSU_MIO_26_PULLUPDOWN": "pullup", "PSU_MIO_26_SLEW": "fast", "PSU_MIO_27_DIRECTION": "out", "PSU_MIO_27_DRIVE_STRENGTH": "12", "PSU_MIO_27_INPUT_TYPE": "cmos", "PSU_MIO_27_POLARITY": "Default", "PSU_MIO_27_PULLUPDOWN": "pullup", "PSU_MIO_27_SLEW": "fast", "PSU_MIO_28_DIRECTION": "in", "PSU_MIO_28_DRIVE_STRENGTH": "12", "PSU_MIO_28_INPUT_TYPE": "cmos", "PSU_MIO_28_POLARITY": "Default", "PSU_MIO_28_PULLUPDOWN": "pullup", "PSU_MIO_28_SLEW": "fast", "PSU_MIO_29_DIRECTION": "out", "PSU_MIO_29_DRIVE_STRENGTH": "12", "PSU_MIO_29_INPUT_TYPE": "cmos", "PSU_MIO_29_POLARITY": "Default", "PSU_MIO_29_PULLUPDOWN": "pullup", "PSU_MIO_29_SLEW": "fast", "PSU_MIO_2_DIRECTION": "out", "PSU_MIO_2_DRIVE_STRENGTH": "12", "PSU_MIO_2_INPUT_TYPE": "cmos", "PSU_MIO_2_POLARITY": "Default", "PSU_MIO_2_PULLUPDOWN": "pullup", "PSU_MIO_2_SLEW": "fast", "PSU_MIO_30_DIRECTION": "in", "PSU_MIO_30_DRIVE_STRENGTH": "12", "PSU_MIO_30_INPUT_TYPE": "cmos", "PSU_MIO_30_POLARITY": "Default", "PSU_MIO_30_PULLUPDOWN": "pullup", "PSU_MIO_30_SLEW": "fast", "PSU_MIO_31_DIRECTION": "inout", "PSU_MIO_31_DRIVE_STRENGTH": "12", "PSU_MIO_31_INPUT_TYPE": "cmos", "PSU_MIO_31_POLARITY": "Default", "PSU_MIO_31_PULLUPDOWN": "pullup", "PSU_MIO_31_SLEW": "fast", "PSU_MIO_32_DIRECTION": "out", "PSU_MIO_32_DRIVE_STRENGTH": "12", "PSU_MIO_32_INPUT_TYPE": "cmos", "PSU_MIO_32_POLARITY": "Default", "PSU_MIO_32_PULLUPDOWN": "pullup", "PSU_MIO_32_SLEW": "fast", "PSU_MIO_33_DIRECTION": "in", "PSU_MIO_33_DRIVE_STRENGTH": "12", "PSU_MIO_33_INPUT_TYPE": "cmos", "PSU_MIO_33_POLARITY": "Default", "PSU_MIO_33_PULLUPDOWN": "pullup", "PSU_MIO_33_SLEW": "fast", "PSU_MIO_34_DIRECTION": "inout", "PSU_MIO_34_DRIVE_STRENGTH": "12", "PSU_MIO_34_INPUT_TYPE": "cmos", "PSU_MIO_34_POLARITY": "Default", "PSU_MIO_34_PULLUPDOWN": "pullup", "PSU_MIO_34_SLEW": "fast", "PSU_MIO_35_DIRECTION": "inout", "PSU_MIO_35_DRIVE_STRENGTH": "12", "PSU_MIO_35_INPUT_TYPE": "cmos", "PSU_MIO_35_POLARITY": "Default", "PSU_MIO_35_PULLUPDOWN": "pullup", "PSU_MIO_35_SLEW": "fast", "PSU_MIO_36_DIRECTION": "inout", "PSU_MIO_36_DRIVE_STRENGTH": "12", "PSU_MIO_36_INPUT_TYPE": "cmos", "PSU_MIO_36_POLARITY": "Default", "PSU_MIO_36_PULLUPDOWN": "pullup", "PSU_MIO_36_SLEW": "fast", "PSU_MIO_37_DIRECTION": "inout", "PSU_MIO_37_DRIVE_STRENGTH": "12", "PSU_MIO_37_INPUT_TYPE": "cmos", "PSU_MIO_37_POLARITY": "Default", "PSU_MIO_37_PULLUPDOWN": "pullup", "PSU_MIO_37_SLEW": "fast", "PSU_MIO_38_DIRECTION": "out", "PSU_MIO_38_DRIVE_STRENGTH": "12", "PSU_MIO_38_INPUT_TYPE": "cmos", "PSU_MIO_38_POLARITY": "Default", "PSU_MIO_38_PULLUPDOWN": "pullup", "PSU_MIO_38_SLEW": "fast", "PSU_MIO_39_DIRECTION": "out", "PSU_MIO_39_DRIVE_STRENGTH": "12", "PSU_MIO_39_INPUT_TYPE": "cmos", "PSU_MIO_39_POLARITY": "Default", "PSU_MIO_39_PULLUPDOWN": "pullup", "PSU_MIO_39_SLEW": "fast", "PSU_MIO_3_DIRECTION": "inout", "PSU_MIO_3_DRIVE_STRENGTH": "12", "PSU_MIO_3_INPUT_TYPE": "cmos", "PSU_MIO_3_POLARITY": "Default", "PSU_MIO_3_PULLUPDOWN": "pullup", "PSU_MIO_3_SLEW": "fast", "PSU_MIO_40_DIRECTION": "out", "PSU_MIO_40_DRIVE_STRENGTH": "12", "PSU_MIO_40_INPUT_TYPE": "cmos", "PSU_MIO_40_POLARITY": "Default", "PSU_MIO_40_PULLUPDOWN": "pullup", "PSU_MIO_40_SLEW": "fast", "PSU_MIO_41_DIRECTION": "out", "PSU_MIO_41_DRIVE_STRENGTH": "12", "PSU_MIO_41_INPUT_TYPE": "cmos", "PSU_MIO_41_POLARITY": "Default", "PSU_MIO_41_PULLUPDOWN": "pullup", "PSU_MIO_41_SLEW": "fast", "PSU_MIO_42_DIRECTION": "out", "PSU_MIO_42_DRIVE_STRENGTH": "12", "PSU_MIO_42_INPUT_TYPE": "cmos", "PSU_MIO_42_POLARITY": "Default", "PSU_MIO_42_PULLUPDOWN": "pullup", "PSU_MIO_42_SLEW": "fast", "PSU_MIO_43_DIRECTION": "out", "PSU_MIO_43_DRIVE_STRENGTH": "12", "PSU_MIO_43_INPUT_TYPE": "cmos", "PSU_MIO_43_POLARITY": "Default", "PSU_MIO_43_PULLUPDOWN": "pullup", "PSU_MIO_43_SLEW": "fast", "PSU_MIO_44_DIRECTION": "in", "PSU_MIO_44_DRIVE_STRENGTH": "12", "PSU_MIO_44_INPUT_TYPE": "cmos", "PSU_MIO_44_POLARITY": "Default", "PSU_MIO_44_PULLUPDOWN": "pullup", "PSU_MIO_44_SLEW": "fast", "PSU_MIO_45_DIRECTION": "in", "PSU_MIO_45_DRIVE_STRENGTH": "12", "PSU_MIO_45_INPUT_TYPE": "cmos", "PSU_MIO_45_POLARITY": "Default", "PSU_MIO_45_PULLUPDOWN": "pullup", "PSU_MIO_45_SLEW": "fast", "PSU_MIO_46_DIRECTION": "in", "PSU_MIO_46_DRIVE_STRENGTH": "12", "PSU_MIO_46_INPUT_TYPE": "cmos", "PSU_MIO_46_POLARITY": "Default", "PSU_MIO_46_PULLUPDOWN": "pullup", "PSU_MIO_46_SLEW": "fast", "PSU_MIO_47_DIRECTION": "in", "PSU_MIO_47_DRIVE_STRENGTH": "12", "PSU_MIO_47_INPUT_TYPE": "cmos", "PSU_MIO_47_POLARITY": "Default", "PSU_MIO_47_PULLUPDOWN": "pullup", "PSU_MIO_47_SLEW": "fast", "PSU_MIO_48_DIRECTION": "in", "PSU_MIO_48_DRIVE_STRENGTH": "12", "PSU_MIO_48_INPUT_TYPE": "cmos", "PSU_MIO_48_POLARITY": "Default", "PSU_MIO_48_PULLUPDOWN": "pullup", "PSU_MIO_48_SLEW": "fast", "PSU_MIO_49_DIRECTION": "in", "PSU_MIO_49_DRIVE_STRENGTH": "12", "PSU_MIO_49_INPUT_TYPE": "cmos", "PSU_MIO_49_POLARITY": "Default", "PSU_MIO_49_PULLUPDOWN": "pullup", "PSU_MIO_49_SLEW": "fast", "PSU_MIO_4_DIRECTION": "inout", "PSU_MIO_4_DRIVE_STRENGTH": "12", "PSU_MIO_4_INPUT_TYPE": "cmos", "PSU_MIO_4_POLARITY": "Default", "PSU_MIO_4_PULLUPDOWN": "pullup", "PSU_MIO_4_SLEW": "fast", "PSU_MIO_50_DIRECTION": "out", "PSU_MIO_50_DRIVE_STRENGTH": "12", "PSU_MIO_50_INPUT_TYPE": "cmos", "PSU_MIO_50_POLARITY": "Default", "PSU_MIO_50_PULLUPDOWN": "pullup", "PSU_MIO_50_SLEW": "fast", "PSU_MIO_51_DIRECTION": "inout", "PSU_MIO_51_DRIVE_STRENGTH": "12", "PSU_MIO_51_INPUT_TYPE": "cmos", "PSU_MIO_51_POLARITY": "Default", "PSU_MIO_51_PULLUPDOWN": "pullup", "PSU_MIO_51_SLEW": "fast", "PSU_MIO_52_DIRECTION": "in", "PSU_MIO_52_DRIVE_STRENGTH": "12", "PSU_MIO_52_INPUT_TYPE": "cmos", "PSU_MIO_52_POLARITY": "Default", "PSU_MIO_52_PULLUPDOWN": "pullup", "PSU_MIO_52_SLEW": "fast", "PSU_MIO_53_DIRECTION": "in", "PSU_MIO_53_DRIVE_STRENGTH": "12", "PSU_MIO_53_INPUT_TYPE": "cmos", "PSU_MIO_53_POLARITY": "Default", "PSU_MIO_53_PULLUPDOWN": "pullup", "PSU_MIO_53_SLEW": "fast", "PSU_MIO_54_DIRECTION": "inout", "PSU_MIO_54_DRIVE_STRENGTH": "12", "PSU_MIO_54_INPUT_TYPE": "cmos", "PSU_MIO_54_POLARITY": "Default", "PSU_MIO_54_PULLUPDOWN": "pullup", "PSU_MIO_54_SLEW": "fast", "PSU_MIO_55_DIRECTION": "in", "PSU_MIO_55_DRIVE_STRENGTH": "12", "PSU_MIO_55_INPUT_TYPE": "cmos", "PSU_MIO_55_POLARITY": "Default", "PSU_MIO_55_PULLUPDOWN": "pullup", "PSU_MIO_55_SLEW": "fast", "PSU_MIO_56_DIRECTION": "inout", "PSU_MIO_56_DRIVE_STRENGTH": "12", "PSU_MIO_56_INPUT_TYPE": "cmos", "PSU_MIO_56_POLARITY": "Default", "PSU_MIO_56_PULLUPDOWN": "pullup", "PSU_MIO_56_SLEW": "fast", "PSU_MIO_57_DIRECTION": "inout", "PSU_MIO_57_DRIVE_STRENGTH": "12", "PSU_MIO_57_INPUT_TYPE": "cmos", "PSU_MIO_57_POLARITY": "Default", "PSU_MIO_57_PULLUPDOWN": "pullup", "PSU_MIO_57_SLEW": "fast", "PSU_MIO_58_DIRECTION": "out", "PSU_MIO_58_DRIVE_STRENGTH": "12", "PSU_MIO_58_INPUT_TYPE": "cmos", "PSU_MIO_58_POLARITY": "Default", "PSU_MIO_58_PULLUPDOWN": "pullup", "PSU_MIO_58_SLEW": "fast", "PSU_MIO_59_DIRECTION": "inout", "PSU_MIO_59_DRIVE_STRENGTH": "12", "PSU_MIO_59_INPUT_TYPE": "cmos", "PSU_MIO_59_POLARITY": "Default", "PSU_MIO_59_PULLUPDOWN": "pullup", "PSU_MIO_59_SLEW": "fast", "PSU_MIO_5_DIRECTION": "inout", "PSU_MIO_5_DRIVE_STRENGTH": "12", "PSU_MIO_5_INPUT_TYPE": "cmos", "PSU_MIO_5_POLARITY": "Default", "PSU_MIO_5_PULLUPDOWN": "pullup", "PSU_MIO_5_SLEW": "fast", "PSU_MIO_60_DIRECTION": "inout", "PSU_MIO_60_DRIVE_STRENGTH": "12", "PSU_MIO_60_INPUT_TYPE": "cmos", "PSU_MIO_60_POLARITY": "Default", "PSU_MIO_60_PULLUPDOWN": "pullup", "PSU_MIO_60_SLEW": "fast", "PSU_MIO_61_DIRECTION": "inout", "PSU_MIO_61_DRIVE_STRENGTH": "12", "PSU_MIO_61_INPUT_TYPE": "cmos", "PSU_MIO_61_POLARITY": "Default", "PSU_MIO_61_PULLUPDOWN": "pullup", "PSU_MIO_61_SLEW": "fast", "PSU_MIO_62_DIRECTION": "inout", "PSU_MIO_62_DRIVE_STRENGTH": "12", "PSU_MIO_62_INPUT_TYPE": "cmos", "PSU_MIO_62_POLARITY": "Default", "PSU_MIO_62_PULLUPDOWN": "pullup", "PSU_MIO_62_SLEW": "fast", "PSU_MIO_63_DIRECTION": "inout", "PSU_MIO_63_DRIVE_STRENGTH": "12", "PSU_MIO_63_INPUT_TYPE": "cmos", "PSU_MIO_63_POLARITY": "Default", "PSU_MIO_63_PULLUPDOWN": "pullup", "PSU_MIO_63_SLEW": "fast", "PSU_MIO_64_DIRECTION": "in", "PSU_MIO_64_DRIVE_STRENGTH": "12", "PSU_MIO_64_INPUT_TYPE": "cmos", "PSU_MIO_64_POLARITY": "Default", "PSU_MIO_64_PULLUPDOWN": "pullup", "PSU_MIO_64_SLEW": "fast", "PSU_MIO_65_DIRECTION": "in", "PSU_MIO_65_DRIVE_STRENGTH": "12", "PSU_MIO_65_INPUT_TYPE": "cmos", "PSU_MIO_65_POLARITY": "Default", "PSU_MIO_65_PULLUPDOWN": "pullup", "PSU_MIO_65_SLEW": "fast", "PSU_MIO_66_DIRECTION": "inout", "PSU_MIO_66_DRIVE_STRENGTH": "12", "PSU_MIO_66_INPUT_TYPE": "cmos", "PSU_MIO_66_POLARITY": "Default", "PSU_MIO_66_PULLUPDOWN": "pullup", "PSU_MIO_66_SLEW": "fast", "PSU_MIO_67_DIRECTION": "in", "PSU_MIO_67_DRIVE_STRENGTH": "12", "PSU_MIO_67_INPUT_TYPE": "cmos", "PSU_MIO_67_POLARITY": "Default", "PSU_MIO_67_PULLUPDOWN": "pullup", "PSU_MIO_67_SLEW": "fast", "PSU_MIO_68_DIRECTION": "inout", "PSU_MIO_68_DRIVE_STRENGTH": "12", "PSU_MIO_68_INPUT_TYPE": "cmos", "PSU_MIO_68_POLARITY": "Default", "PSU_MIO_68_PULLUPDOWN": "pullup", "PSU_MIO_68_SLEW": "fast", "PSU_MIO_69_DIRECTION": "inout", "PSU_MIO_69_DRIVE_STRENGTH": "12", "PSU_MIO_69_INPUT_TYPE": "cmos", "PSU_MIO_69_POLARITY": "Default", "PSU_MIO_69_PULLUPDOWN": "pullup", "PSU_MIO_69_SLEW": "fast", "PSU_MIO_6_DIRECTION": "inout", "PSU_MIO_6_DRIVE_STRENGTH": "12", "PSU_MIO_6_INPUT_TYPE": "cmos", "PSU_MIO_6_POLARITY": "Default", "PSU_MIO_6_PULLUPDOWN": "pullup", "PSU_MIO_6_SLEW": "fast", "PSU_MIO_70_DIRECTION": "out", "PSU_MIO_70_DRIVE_STRENGTH": "12", "PSU_MIO_70_INPUT_TYPE": "cmos", "PSU_MIO_70_POLARITY": "Default", "PSU_MIO_70_PULLUPDOWN": "pullup", "PSU_MIO_70_SLEW": "fast", "PSU_MIO_71_DIRECTION": "inout", "PSU_MIO_71_DRIVE_STRENGTH": "12", "PSU_MIO_71_INPUT_TYPE": "cmos", "PSU_MIO_71_POLARITY": "Default", "PSU_MIO_71_PULLUPDOWN": "pullup", "PSU_MIO_71_SLEW": "fast", "PSU_MIO_72_DIRECTION": "inout", "PSU_MIO_72_DRIVE_STRENGTH": "12", "PSU_MIO_72_INPUT_TYPE": "cmos", "PSU_MIO_72_POLARITY": "Default", "PSU_MIO_72_PULLUPDOWN": "pullup", "PSU_MIO_72_SLEW": "fast", "PSU_MIO_73_DIRECTION": "inout", "PSU_MIO_73_DRIVE_STRENGTH": "12", "PSU_MIO_73_INPUT_TYPE": "cmos", "PSU_MIO_73_POLARITY": "Default", "PSU_MIO_73_PULLUPDOWN": "pullup", "PSU_MIO_73_SLEW": "fast", "PSU_MIO_74_DIRECTION": "inout", "PSU_MIO_74_DRIVE_STRENGTH": "12", "PSU_MIO_74_INPUT_TYPE": "cmos", "PSU_MIO_74_POLARITY": "Default", "PSU_MIO_74_PULLUPDOWN": "pullup", "PSU_MIO_74_SLEW": "fast", "PSU_MIO_75_DIRECTION": "inout", "PSU_MIO_75_DRIVE_STRENGTH": "12", "PSU_MIO_75_INPUT_TYPE": "cmos", "PSU_MIO_75_POLARITY": "Default", "PSU_MIO_75_PULLUPDOWN": "pullup", "PSU_MIO_75_SLEW": "fast", "PSU_MIO_76_DIRECTION": "inout", "PSU_MIO_76_DRIVE_STRENGTH": "12", "PSU_MIO_76_INPUT_TYPE": "cmos", "PSU_MIO_76_POLARITY": "Default", "PSU_MIO_76_PULLUPDOWN": "pullup", "PSU_MIO_76_SLEW": "fast", "PSU_MIO_77_DIRECTION": "inout", "PSU_MIO_77_DRIVE_STRENGTH": "12", "PSU_MIO_77_INPUT_TYPE": "cmos", "PSU_MIO_77_POLARITY": "Default", "PSU_MIO_77_PULLUPDOWN": "pullup", "PSU_MIO_77_SLEW": "fast", "PSU_MIO_7_DIRECTION": "inout", "PSU_MIO_7_DRIVE_STRENGTH": "12", "PSU_MIO_7_INPUT_TYPE": "cmos", "PSU_MIO_7_POLARITY": "Default", "PSU_MIO_7_PULLUPDOWN": "pullup", "PSU_MIO_7_SLEW": "fast", "PSU_MIO_8_DIRECTION": "inout", "PSU_MIO_8_DRIVE_STRENGTH": "12", "PSU_MIO_8_INPUT_TYPE": "cmos", "PSU_MIO_8_POLARITY": "Default", "PSU_MIO_8_PULLUPDOWN": "pullup", "PSU_MIO_8_SLEW": "fast", "PSU_MIO_9_DIRECTION": "inout", "PSU_MIO_9_DRIVE_STRENGTH": "12", "PSU_MIO_9_INPUT_TYPE": "cmos", "PSU_MIO_9_POLARITY": "Default", "PSU_MIO_9_PULLUPDOWN": "pullup", "PSU_MIO_9_SLEW": "fast", "PSU_MIO_TREE_PERIPHERALS": "SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#SD 0#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#UART 1#UART 1#GPIO1 MIO#GPIO1 MIO#I2C 1#I2C 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#MDIO 1#MDIO 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO", "PSU_MIO_TREE_SIGNALS": "sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#scl_out#sda_out#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#sdio0_wp#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#txd#rxd#gpio1[34]#gpio1[35]#scl_out#sda_out#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem1_mdc#gem1_mdio_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]", "PSU_PERIPHERAL_BOARD_PRESET": null, "PSU_SD0_INTERNAL_BUS_WIDTH": "4", "PSU_SD1_INTERNAL_BUS_WIDTH": "8", "PSU_SMC_CYCLE_T0": "NA", "PSU_SMC_CYCLE_T1": "NA", "PSU_SMC_CYCLE_T2": "NA", "PSU_SMC_CYCLE_T3": "NA", "PSU_SMC_CYCLE_T4": "NA", "PSU_SMC_CYCLE_T5": "NA", "PSU_SMC_CYCLE_T6": "NA", "PSU_UIPARAM_GENERATE_SUMMARY": "", "PSU__CAN0__PERIPHERAL__ENABLE": "0", "PSU__CAN0__PERIPHERAL__IO": "", "PSU__CAN1__PERIPHERAL__ENABLE": "0", "PSU__CAN1__PERIPHERAL__IO": "", "PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ": "249.999954", "PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0": "2", "PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ": "250", "PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL": "IOPLL", "PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ": "250", "PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0": "5", "PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ": "250", "PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL": "IOPLL", "PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ": "249.999954", "PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0": "2", "PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ": "250", "PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL": "IOPLL", "PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ": "599.999878", "PSU__CRF_APB__DDR_CTRL__DIVISOR0": "2", "PSU__CRF_APB__DDR_CTRL__FREQMHZ": "1200", "PSU__CRF_APB__DDR_CTRL__SRCSEL": "DPLL", "PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ": "599.999878", "PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0": "2", "PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ": "600", "PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL": "DPLL", "PSU__CRF_APB__DPLL_CTRL__DIV2": "1", "PSU__CRF_APB__DPLL_CTRL__FBDIV": "72", "PSU__CRF_APB__DPLL_CTRL__FRACDATA": "0.000000", "PSU__CRF_APB__DPLL_CTRL__FRACFREQ": "27.138", "PSU__CRF_APB__DPLL_CTRL__SRCSEL": "PSS_REF_CLK", "PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED": "0", "PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0": "3", "PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ": "24.999996", "PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0": "21", "PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1": "1", "PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ": "25", "PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL": "RPLL", "PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED": "0", "PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ": "26.249996", "PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0": "20", "PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1": "1", "PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ": "27", "PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL": "RPLL", "PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ": "299.999939", "PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0": "4", "PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1": "1", "PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ": "300", "PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL": "DPLL", "PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED": "0", "PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ": "599.999878", "PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0": "2", "PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ": "600", "PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL": "DPLL", "PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ": "0", "PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0": "3", "PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ": "600", "PSU__CRF_APB__GPU_REF_CTRL__SRCSEL": "DPLL", "PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ": "-1", "PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0": "-1", "PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ": "-1", "PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL": "NA", "PSU__CRF_APB__GTGREF0__ENABLE": "NA", "PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ": "250", "PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0": "6", "PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ": "250", "PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ": "250", "PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0": "5", "PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ": "250", "PSU__CRF_APB__SATA_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ": "99.999985", "PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0": "5", "PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ": "100", "PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL": "IOPLL", "PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ": "399.999908", "PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0": "3", "PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ": "533.33", "PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL": "DPLL", "PSU__CRF_APB__VPLL_CTRL__DIV2": "1", "PSU__CRF_APB__VPLL_CTRL__FBDIV": "90", "PSU__CRF_APB__VPLL_CTRL__FRACDATA": "0.000000", "PSU__CRF_APB__VPLL_CTRL__FRACFREQ": "27.138", "PSU__CRF_APB__VPLL_CTRL__SRCSEL": "PSS_REF_CLK", "PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED": "0", "PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0": "4", "PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ": "524.999939", "PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0": "2", "PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ": "533.333", "PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL": "RPLL", "PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ": "500", "PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0": "3", "PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ": "500", "PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__AFI6__ENABLE": "0", "PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ": "49.999992", "PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0": "30", "PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ": "50", "PSU__CRL_APB__AMS_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ": "100", "PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0": "15", "PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ": "100", "PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0": "15", "PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ": "499.999908", "PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0": "3", "PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ": "500", "PSU__CRL_APB__CPU_R5_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ": "180", "PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0": "3", "PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ": "180", "PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL": "SysOsc", "PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ": "249.999954", "PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0": "6", "PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ": "250", "PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ": "1000", "PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0": "6", "PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ": "1000", "PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL": "RPLL", "PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ": "1499.999756", "PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ": "1500", "PSU__CRL_APB__DLL_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ": "125", "PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0": "12", "PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ": "125", "PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ": "124.999977", "PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0": "12", "PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ": "125", "PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ": "125", "PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0": "12", "PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ": "125", "PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ": "125", "PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0": "12", "PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ": "125", "PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ": "249.999954", "PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0": "6", "PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ": "250", "PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ": "99.999985", "PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0": "15", "PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ": "99.999985", "PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0": "15", "PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__IOPLL_CTRL__DIV2": "1", "PSU__CRL_APB__IOPLL_CTRL__FBDIV": "90", "PSU__CRL_APB__IOPLL_CTRL__FRACDATA": "0.000000", "PSU__CRL_APB__IOPLL_CTRL__FRACFREQ": "27.138", "PSU__CRL_APB__IOPLL_CTRL__SRCSEL": "PSS_REF_CLK", "PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED": "0", "PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0": "3", "PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ": "262.499969", "PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0": "4", "PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ": "267", "PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL": "RPLL", "PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ": "99.999985", "PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0": "15", "PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ": "100", "PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ": "524.999939", "PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0": "2", "PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ": "533.333", "PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL": "RPLL", "PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ": "100", "PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0": "15", "PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__NAND_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ": "500", "PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0": "3", "PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ": "500", "PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ": "187.499969", "PSU__CRL_APB__PCAP_CTRL__DIVISOR0": "8", "PSU__CRL_APB__PCAP_CTRL__FREQMHZ": "200", "PSU__CRL_APB__PCAP_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ": "99.999985", "PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0": "15", "PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__PL0_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ": "100", "PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0": "4", "PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__PL1_REF_CTRL__SRCSEL": "RPLL", "PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ": "100", "PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0": "4", "PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__PL2_REF_CTRL__SRCSEL": "RPLL", "PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ": "100", "PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0": "4", "PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__PL3_REF_CTRL__SRCSEL": "RPLL", "PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ": "300", "PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0": "5", "PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ": "125", "PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__RPLL_CTRL__DIV2": "1", "PSU__CRL_APB__RPLL_CTRL__FBDIV": "63", "PSU__CRL_APB__RPLL_CTRL__FRACDATA": "0.000000", "PSU__CRL_APB__RPLL_CTRL__FRACFREQ": "27.138", "PSU__CRL_APB__RPLL_CTRL__SRCSEL": "PSS_REF_CLK", "PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED": "0", "PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0": "2", "PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ": "187.499969", "PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0": "8", "PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ": "200", "PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ": "200", "PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0": "7", "PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ": "200", "PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ": "187.499969", "PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0": "8", "PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ": "200", "PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ": "187.499969", "PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0": "8", "PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ": "200", "PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ": "33.333328", "PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0": "1", "PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL": "PSS_REF_CLK", "PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ": "100", "PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0": "15", "PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__UART0_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ": "99.999985", "PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0": "15", "PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ": "100", "PSU__CRL_APB__UART1_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ": "249.999954", "PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0": "6", "PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ": "250", "PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ": "249.999954", "PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0": "6", "PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1": "1", "PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ": "250", "PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ": "19.999996", "PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0": "25", "PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1": "3", "PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ": "20", "PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL": "IOPLL", "PSU__CRL_APB__USB3__ENABLE": "1", "PSU__CSUPMU__PERIPHERAL__VALID": "0", "PSU__CSU_COHERENCY": "0", "PSU__CSU__CSU_TAMPER_0__ENABLE": "0", "PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM": "0", "PSU__CSU__CSU_TAMPER_0__RESPONSE": "", "PSU__CSU__CSU_TAMPER_11__ENABLE": "0", "PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM": "0", "PSU__CSU__CSU_TAMPER_11__RESPONSE": "", "PSU__CSU__CSU_TAMPER_1__ENABLE": "0", "PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM": "0", "PSU__CSU__CSU_TAMPER_1__RESPONSE": "", "PSU__CSU__CSU_TAMPER_3__ENABLE": "0", "PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM": "0", "PSU__CSU__CSU_TAMPER_3__RESPONSE": "", "PSU__CSU__CSU_TAMPER_5__ENABLE": "0", "PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM": "0", "PSU__CSU__CSU_TAMPER_5__RESPONSE": "", "PSU__CSU__CSU_TAMPER_7__ENABLE": "0", "PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM": "0", "PSU__CSU__CSU_TAMPER_7__RESPONSE": "", "PSU__CSU__CSU_TAMPER_9__ENABLE": "0", "PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM": "0", "PSU__CSU__CSU_TAMPER_9__RESPONSE": "", "PSU__DDRC__ADDR_MIRROR": "0", "PSU__DDRC__AL": "0", "PSU__DDRC__BANK_ADDR_COUNT": "2", "PSU__DDRC__BG_ADDR_COUNT": "1", "PSU__DDRC__BRC_MAPPING": "ROW_BANK_COL", "PSU__DDRC__BUS_WIDTH": "64 Bit", "PSU__DDRC__CL": "16", "PSU__DDRC__CLOCK_STOP_EN": "0", "PSU__DDRC__COL_ADDR_COUNT": "10", "PSU__DDRC__COMPONENTS": "Components", "PSU__DDRC__CWL": "12", "PSU__DDRC__DDR3L_T_REF_RANGE": "NA", "PSU__DDRC__DDR3_T_REF_RANGE": "NA", "PSU__DDRC__DDR4_ADDR_MAPPING": "1", "PSU__DDRC__DDR4_CAL_MODE_ENABLE": "0", "PSU__DDRC__DDR4_CRC_CONTROL": "0", "PSU__DDRC__DDR4_MAXPWR_SAVING_EN": "0", "PSU__DDRC__DDR4_T_REF_MODE": "0", "PSU__DDRC__DDR4_T_REF_RANGE": "Normal (0-85)", "PSU__DDRC__DEEP_PWR_DOWN_EN": "0", "PSU__DDRC__DERATE_INT_D": "", "PSU__DDRC__LPDDR3_DUALRANK_SDP": "0", "PSU__DDRC__LPDDR3_T_REF_RANGE": "NA", "PSU__DDRC__LPDDR4_T_REF_RANGE": "NA", "PSU__DDRC__LP_ASR": "manual normal", "PSU__DDRC__MEMORY_TYPE": "DDR 4", "PSU__DDRC__PARITY_ENABLE": "0", "PSU__DDRC__PARTNO": "", "PSU__DDR_QOS_PORT1_VN1_TYPE": "", "PSU__DDR_QOS_PORT2_VN1_TYPE": "", "PSU__DDR_QOS_PORT3_TYPE": "", "PSU__DDR_QOS_PORT5_TYPE": "", "PSU__ENET0__PERIPHERAL__ENABLE": "0", "PSU__ENET0__PERIPHERAL__IO": "", "PSU__ENET2__PERIPHERAL__ENABLE": "0", "PSU__ENET2__PERIPHERAL__IO": "", "PSU__ENET3__PERIPHERAL__ENABLE": "0", "PSU__ENET3__PERIPHERAL__IO": "", "PSU__GEM0__REF_CLK_SEL": "", "PSU__GEM1__REF_CLK_SEL": "", "PSU__GEM2__REF_CLK_SEL": "", "PSU__GEM3__REF_CLK_SEL": "", "PSU__GEN_IPI_0__MASTER": "APU", "PSU__GEN_IPI_10__MASTER": "NONE", "PSU__GEN_IPI_1__MASTER": "RPU0", "PSU__GEN_IPI_2__MASTER": "RPU1", "PSU__GEN_IPI_3__MASTER": "PMU", "PSU__GEN_IPI_4__MASTER": "PMU", "PSU__GEN_IPI_5__MASTER": "PMU", "PSU__GEN_IPI_6__MASTER": "PMU", "PSU__GEN_IPI_7__MASTER": "NONE", "PSU__GEN_IPI_8__MASTER": "NONE", "PSU__GEN_IPI_9__MASTER": "NONE", "PSU__GEN_IPI__TRUSTZONE": "", "PSU__I2C0__PERIPHERAL__ENABLE": "1", "PSU__I2C0__PERIPHERAL__IO": "MIO 18 .. 19", "PSU__I2C1__GRP_INT__ENABLE": "0", "PSU__I2C1__GRP_INT__IO": "", "PSU__NAND__DATA_STROBE__ENABLE": "0", "PSU__NAND__DATA_STROBE__IO": "", "PSU__NAND__READY0_BUSY__ENABLE": "0", "PSU__NAND__READY0_BUSY__IO": "", "PSU__NAND__READY_BUSY__ENABLE": "0", "PSU__NAND__READY_BUSY__IO": "", "PSU__PCIE__BAR0_SIZE": "", "PSU__PCIE__BAR0_VAL": null, "PSU__PCIE__BAR1_64BIT": "0", "PSU__PCIE__BAR1_ENABLE": "0", "PSU__PCIE__BAR1_PREFETCHABLE": "0", "PSU__PCIE__BAR1_SCALE": "", "PSU__PCIE__BAR1_TYPE": "", "PSU__PCIE__BAR2_SIZE": "", "PSU__PCIE__BAR2_VAL": null, "PSU__PCIE__BAR3_64BIT": "0", "PSU__PCIE__BAR3_ENABLE": "0", "PSU__PCIE__BAR3_PREFETCHABLE": "0", "PSU__PCIE__BAR3_SCALE": "", "PSU__PCIE__BAR3_TYPE": "", "PSU__PCIE__BAR4_SIZE": "", "PSU__PCIE__BAR4_VAL": null, "PSU__PCIE__BAR5_64BIT": "0", "PSU__PCIE__BAR5_ENABLE": "0", "PSU__PCIE__BAR5_PREFETCHABLE": "0", "PSU__PCIE__BAR5_SCALE": "", "PSU__PCIE__BAR5_TYPE": "", "PSU__PCIE__BRIDGE_BAR_INDICATOR": "", "PSU__PCIE__CLASS_CODE_BASE": null, "PSU__PCIE__CLASS_CODE_INTERFACE": null, "PSU__PCIE__CLASS_CODE_SUB": null, "PSU__PCIE__CLASS_CODE_VALUE": null, "PSU__PCIE__COMPLETER_ABORT": "0", "PSU__PCIE__COMPLTION_TIMEOUT": "0", "PSU__PCIE__CORRECTABLE_INT_ERR": "0", "PSU__PCIE__CRS_SW_VISIBILITY": "0", "PSU__PCIE__DEVICE_ID": null, "PSU__PCIE__DEVICE_PORT_TYPE": "", "PSU__PCIE__EROM_SIZE": "", "PSU__PCIE__INTX_GENERATION": "0", "PSU__PCIE__INTX_PIN": "", "PSU__PCIE__LANE1__ENABLE": "0", "PSU__PCIE__LANE1__IO": "", "PSU__PCIE__LANE3__ENABLE": "0", "PSU__PCIE__LANE3__IO": "", "PSU__PCIE__LINK_SPEED": "", "PSU__PCIE__MAX_PAYLOAD_SIZE": "", "PSU__PCIE__MULTIHEADER": "0", "PSU__PCIE__PERIPHERAL__ENABLE": "0", "PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE": "1", "PSU__PCIE__PERIPHERAL__ENDPOINT_IO": "", "PSU__PCIE__PERM_ROOT_ERR_UPDATE": "0", "PSU__PCIE__RECEIVER_ERR": "0", "PSU__PCIE__RECEIVER_OVERFLOW": "0", "PSU__PCIE__REF_CLK_FREQ": "", "PSU__PCIE__RESET__POLARITY": "Active Low", "PSU__PCIE__REVISION_ID": null, "PSU__PCIE__SUBSYSTEM_ID": null, "PSU__PCIE__SUBSYSTEM_VENDOR_ID": null, "PSU__PCIE__SUB_CLASS_INTERFACE_MENU": "", "PSU__PCIE__VENDOR_ID": null, "PSU__PJTAG__PERIPHERAL__ENABLE": "0", "PSU__PJTAG__PERIPHERAL__IO": "", "PSU__PMU__GPI1__ENABLE": "0", "PSU__PMU__GPI1__IO": "", "PSU__PMU__GPI3__ENABLE": "0", "PSU__PMU__GPI3__IO": "", "PSU__PMU__GPI5__ENABLE": "0", "PSU__PMU__GPI5__IO": "", "PSU__PMU__GPO1__ENABLE": "0", "PSU__PMU__GPO1__IO": "", "PSU__PMU__GPO2__POLARITY": "", "PSU__PMU__GPO3__POLARITY": "", "PSU__PMU__GPO4__POLARITY": "", "PSU__PMU__GPO5__POLARITY": "", "PSU__PMU__PLERROR__ENABLE": "0", "PSU__PRESET_APPLIED": "1", "PSU__PROTECTION__DDR_SEGMENTS": "NONE", "PSU__PROTECTION__DEBUG": "0", "PSU__PROTECTION__ENABLE": "0", "PSU__PROTECTION__FPD_SEGMENTS": "SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem", "PSU__PROTECTION__LOCK_UNUSED_SEGMENTS": "0", "PSU__PROTECTION__LPD_SEGMENTS": "SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem", "PSU__PROTECTION__MASTERS": "USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;0|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;1|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1", "PSU__PROTECTION__MASTERS_TZ": "GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure", "PSU__PROTECTION__OCM_SEGMENTS": "NONE", "PSU__PROTECTION__PRESUBSYSTEMS": "NONE", "PSU__PROTECTION__SLAVES": "LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;0|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;0|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;1|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1", "PSU__PROTECTION__SUBSYSTEMS": "PMU Firmware:PMU|Secure Subsystem:", "PSU__PSS_ALT_REF_CLK__ENABLE": "0", "PSU__PSS_ALT_REF_CLK__FREQMHZ": "33.333", "PSU__PSS_ALT_REF_CLK__IO": "", "PSU__QSPI__PERIPHERAL__DATA_MODE": "", "PSU__QSPI__PERIPHERAL__MODE": "", "PSU__SATA__LANE1__ENABLE": "0", "PSU__SATA__LANE1__IO": "", "PSU__SATA__REF_CLK_SEL": "", "PSU__SD0__GRP_WP__ENABLE": "1", "PSU__SD0__GRP_WP__IO": "MIO 25", "PSU__SD0__PERIPHERAL__ENABLE": "1", "PSU__SD0__PERIPHERAL__IO": "MIO 13 .. 16 21 22", "PSU__SD0__RESET__ENABLE": "0", "PSU__SD0__SLOT_TYPE": "SD 2.0", "PSU__SD1_COHERENCY": "0", "PSU__SD1_ROUTE_THROUGH_FPD": "0", "PSU__SD1__CLK_100_SDR_OTAP_DLY": "0x00", "PSU__SD1__CLK_200_SDR_OTAP_DLY": "0x00", "PSU__SD1__CLK_50_DDR_ITAP_DLY": "0x00", "PSU__SD1__CLK_50_DDR_OTAP_DLY": "0x00", "PSU__SD1__CLK_50_SDR_ITAP_DLY": "0x00", "PSU__SD1__CLK_50_SDR_OTAP_DLY": "0x00", "PSU__SD1__DATA_TRANSFER_MODE": "", "PSU__SD1__GRP_POW__ENABLE": "0", "PSU__SD1__GRP_POW__IO": "", "PSU__SD1__PERIPHERAL__ENABLE": "0", "PSU__SD1__PERIPHERAL__IO": "", "PSU__SPI0_LOOP_SPI1__ENABLE": "0", "PSU__SPI0__GRP_SS0__ENABLE": "1", "PSU__SPI0__GRP_SS0__IO": "MIO 3", "PSU__SPI0__GRP_SS1__ENABLE": "1", "PSU__SPI0__GRP_SS1__IO": "MIO 2", "PSU__SPI0__GRP_SS2__ENABLE": "1", "PSU__SPI0__GRP_SS2__IO": "MIO 1", "PSU__SPI0__PERIPHERAL__ENABLE": "1", "PSU__SPI0__PERIPHERAL__IO": "MIO 0 .. 5", "PSU__SPI1__GRP_SS0__ENABLE": "1", "PSU__SPI1__GRP_SS0__IO": "MIO 9", "PSU__SPI1__GRP_SS1__ENABLE": "0", "PSU__SPI1__GRP_SS1__IO": "", "PSU__SPI1__PERIPHERAL__ENABLE": "1", "PSU__SPI1__PERIPHERAL__IO": "MIO 6 .. 11", "PSU__SWDT0__CLOCK__ENABLE": "0", "PSU__SWDT0__CLOCK__IO": "", "PSU__SWDT1__CLOCK__ENABLE": "0", "PSU__SWDT1__CLOCK__IO": "", "PSU__S_AXI_GP0__FREQMHZ": "10", "PSU__S_AXI_GP1__FREQMHZ": "10", "PSU__S_AXI_GP2__FREQMHZ": "99.999985", "PSU__S_AXI_GP3__FREQMHZ": "10", "PSU__S_AXI_GP4__FREQMHZ": "10", "PSU__S_AXI_GP5__FREQMHZ": "10", "PSU__S_AXI_GP6__FREQMHZ": "10", "PSU__TCM0A__POWER__ON": "1", "PSU__TCM0B__POWER__ON": "1", "PSU__TCM1A__POWER__ON": "1", "PSU__TCM1B__POWER__ON": "1", "PSU__TESTSCAN__PERIPHERAL__ENABLE": "0", "PSU__TRACE_PIPELINE_WIDTH": "8", "PSU__TRACE__INTERNAL_WIDTH": "32", "PSU__TRACE__PERIPHERAL__ENABLE": "0", "PSU__TRACE__PERIPHERAL__IO": "", "PSU__TRISTATE__INVERTED": "1", "PSU__TSU__BUFG_PORT_LOOPBACK": "0", "PSU__TSU__BUFG_PORT_PAIR": "0", "PSU__TTC0__CLOCK__ENABLE": "0", "PSU__TTC0__CLOCK__IO": "", "PSU__TTC1__CLOCK__ENABLE": "0", "PSU__TTC1__CLOCK__IO": "", "PSU__TTC2__CLOCK__ENABLE": "0", "PSU__TTC2__CLOCK__IO": "", "PSU__TTC3__CLOCK__ENABLE": "0", "PSU__TTC3__CLOCK__IO": "", "PSU__UART0_LOOP_UART1__ENABLE": "0", "PSU__UART0__BAUD_RATE": "", "PSU__UART1__BAUD_RATE": "115200", "PSU__UART1__MODEM__ENABLE": "0", "PSU__UART1__PERIPHERAL__ENABLE": "1", "PSU__UART1__PERIPHERAL__IO": "MIO 32 .. 33", "PSU__USB0_COHERENCY": "0", "PSU__USB0__PERIPHERAL__ENABLE": "1", "PSU__USB0__PERIPHERAL__IO": "MIO 52 .. 63", "PSU__USB0__REF_CLK_FREQ": "100", "PSU__USB0__REF_CLK_SEL": "Ref Clk1", "PSU__USB0__RESET__ENABLE": "0", "PSU__USB0__RESET__IO": "", "PSU__USB2_0__EMIO__ENABLE": "0", "PSU__USB2_1__EMIO__ENABLE": "0", "PSU__USB3_0__EMIO__ENABLE": "0", "PSU__USB3_0__PERIPHERAL__ENABLE": "1", "PSU__USB3_0__PERIPHERAL__IO": "GT Lane2", "PSU__USB3_1__EMIO__ENABLE": "0", "PSU__USB3_1__PERIPHERAL__ENABLE": "1", "PSU__USB3_1__PERIPHERAL__IO": "GT Lane3", "PSU__USB__RESET__MODE": "Boot Pin", "PSU__USB__RESET__POLARITY": "Active Low", "PSU__USE_DIFF_RW_CLK_GP0": "0", "PSU__USE_DIFF_RW_CLK_GP1": "0", "PSU__USE_DIFF_RW_CLK_GP2": "0", "PSU__USE_DIFF_RW_CLK_GP3": "0", "PSU__USE_DIFF_RW_CLK_GP4": "0", "PSU__USE_DIFF_RW_CLK_GP5": "0", "PSU__USE_DIFF_RW_CLK_GP6": "0", "PSU__USE__ADMA": "0", "PSU__USE__APU_LEGACY_INTERRUPT": "0", "PSU__USE__AUDIO": "0", "PSU__USE__CLK": "0", "PSU__USE__CLK0": "0", "PSU__USE__CLK1": "0", "PSU__USE__CLK2": "0", "PSU__USE__CLK3": "0", "PSU__USE__CROSS_TRIGGER": "0", "PSU__USE__DDR_INTF_REQUESTED": "0", "PSU__USE__DEBUG__TEST": "0", "PSU__USE__EVENT_RPU": "0", "PSU__USE__FABRIC__RST": "1", "PSU__USE__FTM": "0", "PSU__USE__GDMA": "0", "PSU__USE__IRQ": "0", "PSU__USE__IRQ0": "1", "PSU__USE__IRQ1": "1", "PSU__USE__M_AXI_GP0": "1", "PSU__USE__M_AXI_GP1": "1", "PSU__USE__M_AXI_GP2": "0", "PSU__USE__PROC_EVENT_BUS": "0", "PSU__USE__RPU_LEGACY_INTERRUPT": "0", "PSU__USE__RST0": "0", "PSU__USE__RST1": "0", "PSU__USE__RST2": "0", "PSU__USE__RST3": "0", "PSU__USE__RTC": "0", "PSU__USE__STM": "0", "PSU__USE__S_AXI_ACE": "0", "PSU__USE__S_AXI_ACP": "0", "PSU__USE__S_AXI_GP0": "0", "PSU__USE__S_AXI_GP1": "0", "PSU__USE__S_AXI_GP2": "1", "PSU__USE__S_AXI_GP3": "0", "PSU__USE__S_AXI_GP4": "0", "PSU__USE__S_AXI_GP5": "0", "PSU__USE__S_AXI_GP6": "0", "PSU__USE__USB3_0_HUB": "0", "PSU__USE__USB3_1_HUB": "0", "PSU__USE__VIDEO": "0", "PSU__VIDEO_REF_CLK__ENABLE": "0", "PSU__VIDEO_REF_CLK__FREQMHZ": "33.333", "PSU__VIDEO_REF_CLK__IO": "',\n", " 'PSU_USB3__DUAL_CLOCK_ENABLE': '1',\n", " 'PSU_VALUE_SILVERSION': '3',\n", " 'PSU__ACPU0__POWER__ON': '1',\n", " 'PSU__ACPU1__POWER__ON': '1',\n", " 'PSU__ACPU2__POWER__ON': '1',\n", " 'PSU__ACPU3__POWER__ON': '1',\n", " 'PSU__ACTUAL__IP': '1',\n", " 'PSU__ACT_DDR_FREQ_MHZ': '1199.999756',\n", " 'PSU__AFI0_COHERENCY': '0',\n", " 'PSU__AFI1_COHERENCY': '0',\n", " 'PSU__AUX_REF_CLK__FREQMHZ': '33.333',\n", " 'PSU__CAN0_LOOP_CAN1__ENABLE': '0',\n", " 'PSU__CAN0__GRP_CLK__ENABLE': '0',\n", " 'PSU__CAN0__GRP_CLK__IO': '',\n", " 'PSU__CAN1__GRP_CLK__ENABLE': '0',\n", " 'PSU__CAN1__GRP_CLK__IO': '',\n", " 'PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ': '1199.999756',\n", " 'PSU__CRF_APB__ACPU_CTRL__DIVISOR0': '1',\n", " 'PSU__CRF_APB__ACPU_CTRL__FREQMHZ': '1200',\n", " 'PSU__CRF_APB__ACPU_CTRL__SRCSEL': 'APLL',\n", " 'PSU__CRF_APB__ACPU__FRAC_ENABLED': '0',\n", " 'PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0': '2',\n", " 'PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__AFI0_REF__ENABLE': '0',\n", " 'PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0': '2',\n", " 'PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__AFI1_REF__ENABLE': '0',\n", " 'PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0': '2',\n", " 'PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__AFI2_REF__ENABLE': '0',\n", " 'PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0': '2',\n", " 'PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__AFI3_REF__ENABLE': '0',\n", " 'PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0': '2',\n", " 'PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__AFI4_REF__ENABLE': '0',\n", " 'PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0': '2',\n", " 'PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ': '667',\n", " 'PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__AFI5_REF__ENABLE': '0',\n", " 'PSU__CRF_APB__APLL_CTRL__DIV2': '1',\n", " 'PSU__CRF_APB__APLL_CTRL__FBDIV': '72',\n", " 'PSU__CRF_APB__APLL_CTRL__FRACDATA': '0.000000',\n", " 'PSU__CRF_APB__APLL_CTRL__FRACFREQ': '27.138',\n", " 'PSU__CRF_APB__APLL_CTRL__SRCSEL': 'PSS_REF_CLK',\n", " 'PSU__CRF_APB__APLL_FRAC_CFG__ENABLED': '0',\n", " 'PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0': '3',\n", " 'PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ': '1',\n", " 'PSU__CRF_APB__APM_CTRL__DIVISOR0': '1',\n", " 'PSU__CRF_APB__APM_CTRL__FREQMHZ': '1',\n", " 'PSU__CRF_APB__APM_CTRL__SRCSEL': '',\n", " 'PSU__CSU__CSU_TAMPER_10__ENABLE': '0',\n", " 'PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM': '0',\n", " 'PSU__CSU__CSU_TAMPER_10__RESPONSE': '',\n", " 'PSU__CSU__CSU_TAMPER_12__ENABLE': '0',\n", " 'PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM': '0',\n", " 'PSU__CSU__CSU_TAMPER_12__RESPONSE': '',\n", " 'PSU__CSU__CSU_TAMPER_2__ENABLE': '0',\n", " 'PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM': '0',\n", " 'PSU__CSU__CSU_TAMPER_2__RESPONSE': '',\n", " 'PSU__CSU__CSU_TAMPER_4__ENABLE': '0',\n", " 'PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM': '0',\n", " 'PSU__CSU__CSU_TAMPER_4__RESPONSE': '',\n", " 'PSU__CSU__CSU_TAMPER_6__ENABLE': '0',\n", " 'PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM': '0',\n", " 'PSU__CSU__CSU_TAMPER_6__RESPONSE': '',\n", " 'PSU__CSU__CSU_TAMPER_8__ENABLE': '0',\n", " 'PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM': '0',\n", " 'PSU__CSU__CSU_TAMPER_8__RESPONSE': '',\n", " 'PSU__CSU__PERIPHERAL__ENABLE': '0',\n", " 'PSU__CSU__PERIPHERAL__IO': '',\n", " 'PSU__DDRC__DEVICE_CAPACITY': '8192 MBits',\n", " 'PSU__DDRC__DIMM_ADDR_MIRROR': '0',\n", " 'PSU__DDRC__DM_DBI': 'DM_NO_DBI',\n", " 'PSU__DDRC__DQMAP_0_3': '0',\n", " 'PSU__DDRC__DQMAP_12_15': '0',\n", " 'PSU__DDRC__DQMAP_16_19': '0',\n", " 'PSU__DDRC__DQMAP_20_23': '0',\n", " 'PSU__DDRC__DQMAP_24_27': '0',\n", " 'PSU__DDRC__DQMAP_28_31': '0',\n", " 'PSU__DDRC__DQMAP_32_35': '0',\n", " 'PSU__DDRC__DQMAP_36_39': '0',\n", " 'PSU__DDRC__DQMAP_40_43': '0',\n", " 'PSU__DDRC__DQMAP_44_47': '0',\n", " 'PSU__DDRC__DQMAP_48_51': '0',\n", " 'PSU__DDRC__DQMAP_4_7': '0',\n", " 'PSU__DDRC__DQMAP_52_55': '0',\n", " 'PSU__DDRC__DQMAP_56_59': '0',\n", " 'PSU__DDRC__DQMAP_60_63': '0',\n", " 'PSU__DDRC__DQMAP_64_67': '0',\n", " 'PSU__DDRC__DQMAP_68_71': '0',\n", " 'PSU__DDRC__DQMAP_8_11': '0',\n", " 'PSU__DDRC__DRAM_WIDTH': '16 Bits',\n", " 'PSU__DDRC__ECC': 'Disabled',\n", " 'PSU__DDRC__ECC_SCRUB': '0',\n", " 'PSU__DDRC__ENABLE': '1',\n", " 'PSU__DDRC__ENABLE_2T_TIMING': '0',\n", " 'PSU__DDRC__ENABLE_DP_SWITCH': '0',\n", " 'PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP': '0',\n", " 'PSU__DDRC__ENABLE_LP4_SLOWBOOT': '0',\n", " 'PSU__DDRC__EN_2ND_CLK': '0',\n", " 'PSU__DDRC__FGRM': '1X',\n", " 'PSU__DDRC__FREQ_MHZ': '1',\n", " 'PSU__DDRC__HIGH_TEMP': '',\n", " 'PSU__DDRC__PER_BANK_REFRESH': '0',\n", " 'PSU__DDRC__PHY_DBI_MODE': '0',\n", " 'PSU__DDRC__PLL_BYPASS': '0',\n", " 'PSU__DDRC__PWR_DOWN_EN': '0',\n", " 'PSU__DDRC__RANK_ADDR_COUNT': '0',\n", " 'PSU__DDRC__RD_DQS_CENTER': '0',\n", " 'PSU__DDRC__ROW_ADDR_COUNT': '16',\n", " 'PSU__DDRC__SB_TARGET': '16-16-16',\n", " 'PSU__DDRC__SELF_REF_ABORT': '0',\n", " 'PSU__DDRC__SPEED_BIN': 'DDR4_2400R',\n", " 'PSU__DDRC__STATIC_RD_MODE': '0',\n", " 'PSU__DDRC__TRAIN_DATA_EYE': '1',\n", " 'PSU__DDRC__TRAIN_READ_GATE': '1',\n", " 'PSU__DDRC__TRAIN_WRITE_LEVEL': '1',\n", " 'PSU__DDRC__T_FAW': '30.0',\n", " ...},\n", " 'driver': pynq.overlay.DefaultIP,\n", " 'device': }}" ] }, "execution_count": 54, "metadata": { "application/json": { "expanded": false, "root": "ip_dict" } }, "output_type": "execute_result" } ], "source": [ "base.ip_dict" ] }, { "cell_type": "markdown", "id": "661fbbdc-2c17-4f2c-8ed8-ccb096bfab9d", "metadata": {}, "source": [ "define the mask needed to do the IO reads)" ] }, { "cell_type": "code", "execution_count": 55, "id": "0b9a1f3a-2b85-45b9-a7f3-75c7baca580b", "metadata": {}, "outputs": [], "source": [ "mask = 0xFFFFFFFF" ] }, { "cell_type": "markdown", "id": "c0341d76-a157-4b4d-b1f5-5f4562c63562", "metadata": {}, "source": [ "get the version number, print it here, and display it on the oled display" ] }, { "cell_type": "code", "execution_count": 56, "id": "8cc82bea-ea6f-49c9-8ead-bd608a8e6e3c", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "Version 0xa5000001\n" ] } ], "source": [ "version_ip = base.ip_dict[\"VERSION\"]\n", "version_ptr = AxiGPIO(version_ip).channel1\n", "version = version_ptr.read()\n", "print(\"Version \"+hex(version))\n", "oled_display = oled.oled_display()\n", "oled_display.write(hex(version)+\"\\n Loaded!!!\")" ] }, { "cell_type": "markdown", "id": "0909c8a9-46d1-47a1-8afc-02151731e51b", "metadata": {}, "source": [ "look at how memory is allocated on the ARM chip" ] }, { "cell_type": "code", "execution_count": 57, "id": "669753ad-491f-42b8-8de0-ade290a5a41b", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "MemTotal: 4023308 kB\n", "MemFree: 2999692 kB\n", "Cached: 399232 kB\n", "SwapCached: 0 kB\n", "Active: 230160 kB\n", "Inactive: 676984 kB\n", "Active(anon): 1708 kB\n", "Inactive(anon): 457772 kB\n", "Active(file): 228452 kB\n", "Inactive(file): 219212 kB\n", "CmaTotal: 131072 kB\n", "CmaFree: 119104 kB\n" ] } ], "source": [ " !cat /proc/meminfo | grep -E \"MemTotal|MemFree|Cached|Active|Inactive|Cma\"" ] }, { "cell_type": "markdown", "id": "881de663-883a-4da5-a7fa-628cf2d0769a", "metadata": {}, "source": [ "set up the class that allows you to do DMA and printout out the register map (or comment it out)" ] }, { "cell_type": "code", "execution_count": 61, "id": "c77ad49e-f8fa-410a-b2b8-d672f0b3ff19", "metadata": {}, "outputs": [], "source": [ "dma = base.AXI_DMA\n", "#dma.register_map" ] }, { "cell_type": "markdown", "id": "38359ad5-7916-4ade-a022-01f51c73a4e2", "metadata": {}, "source": [ "allocate buffers in the external DDR for input and output" ] }, { "cell_type": "code", "execution_count": 76, "id": "44ae144a-8819-4b1c-ac2a-0a5b1ab038e5", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "Into fifo values:\n", "0xcafe0000 0xcafe0001 0xcafe0002 0xcafe0003 0xcafe0004 0xcafe0005 0xcafe0006 0xcafe0007 0xcafe0008 0xcafe0009 0xcafe000a 0xcafe000b 0xcafe000c 0xcafe000d 0xcafe000e 0xcafe000f 0xcafe0010 0xcafe0011 0xcafe0012 0xcafe0013 0xcafe0014 0xcafe0015 0xcafe0016 0xcafe0017 0xcafe0018 0xcafe0019 0xcafe001a 0xcafe001b 0xcafe001c 0xcafe001d 0xcafe001e 0xcafe001f 0xcafe0020 0xcafe0021 0xcafe0022 0xcafe0023 0xcafe0024 0xcafe0025 0xcafe0026 0xcafe0027 0xcafe0028 0xcafe0029 0xcafe002a 0xcafe002b 0xcafe002c 0xcafe002d 0xcafe002e 0xcafe002f 0xcafe0030 0xcafe0031 0xcafe0032 0xcafe0033 0xcafe0034 0xcafe0035 0xcafe0036 0xcafe0037 0xcafe0038 0xcafe0039 0xcafe003a 0xcafe003b 0xcafe003c 0xcafe003d 0xcafe003e 0xcafe003f 0xcafe0040 0xcafe0041 0xcafe0042 0xcafe0043 0xcafe0044 0xcafe0045 0xcafe0046 0xcafe0047 0xcafe0048 0xcafe0049 0xcafe004a 0xcafe004b 0xcafe004c 0xcafe004d 0xcafe004e 0xcafe004f 0xcafe0050 0xcafe0051 0xcafe0052 0xcafe0053 0xcafe0054 0xcafe0055 0xcafe0056 0xcafe0057 0xcafe0058 0xcafe0059 0xcafe005a 0xcafe005b 0xcafe005c 0xcafe005d 0xcafe005e 0xcafe005f 0xcafe0060 0xcafe0061 0xcafe0062 0xcafe0063 \n", "From fifo values: (should be all 0)\n", "0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 " ] } ], "source": [ "into_size = 100\n", "into_buffer = allocate(shape=(into_size,), dtype=np.uint32)\n", "print(\"Into fifo values:\")\n", "for i in range(into_size):\n", " into_buffer[i] = 0xcafe0000 + i\n", " print(hex(into_buffer[i]), end=\" \")\n", "from_size = 100\n", "from_buffer = allocate(shape=(from_size,), dtype=np.uint32) \n", "print(\"\\nFrom fifo values: (should be all 0)\")\n", "for i in range(into_size):\n", " print(hex(from_buffer[i]), end=\" \")\n" ] }, { "cell_type": "markdown", "id": "a159040c-0336-4bbe-8539-74b4abe2f163", "metadata": {}, "source": [ "set up to read fifo read and write counts" ] }, { "cell_type": "code", "execution_count": 77, "id": "b8626f60-9aa8-4676-8b36-607210613941", "metadata": {}, "outputs": [], "source": [ "fifo_rd_ip = base.ip_dict[\"FIFO_RD\"]\n", "fifo_rd_ptr = AxiGPIO(fifo_rd_ip).channel1\n", "fifo_wr_ip = base.ip_dict[\"FIFO_WR\"]\n", "fifo_wr_ptr = AxiGPIO(fifo_wr_ip).channel1\n" ] }, { "cell_type": "markdown", "id": "f1795b96-e1a5-445a-bced-f1f9bdf2932c", "metadata": {}, "source": [ "set up objects to the dma channels for both sending and receiving" ] }, { "cell_type": "code", "execution_count": 78, "id": "e55b7476-8a13-4a39-a91d-7fe2b457fe2c", "metadata": {}, "outputs": [], "source": [ "dma_send = dma.sendchannel\n", "dma_recv = dma.recvchannel" ] }, { "cell_type": "markdown", "id": "1e894c7c-fe98-4589-8477-ec15e07a65de", "metadata": {}, "source": [ "initiate the DMA transfer. note that it's always best to first initiate the receive, and then the send. if you do it this way, the receive will wait until there's data in the FIFO. if you do send first and then receive you could overflow the FIFO etc. In this case we have a FIFO that is 512 words deep so we don't have to worry about it, but best to be safe! from the \"into_fifo\" by using the transfer method to the dma class.\n", "\n", "however, in this tutorial, the fifo size is greater than the buffer size, so we will do the transfer first, then read out the fifo write count, then do the receive, and read out the fifo read words.\n", "\n", "the .wait method is blocking, and it's good to use them so that the code doesn't get ahead of the hardware. but transfering 100 32 bit words at 100MHz clock means it only takes 1 microsecond (100/100MHz) so we don't really need them, but will add them just to be consistent in case we copy and past from this in the future.\n", "\n", "one more thing: the fifo has a \"primitive latency\" from the way Xilinx builds FIFOs. They use block ram (BRAM), and due to technicalities of BRAM, the first\n", "and last few words of a transaction are not reflected in the count immediately. That count is updated by the FIFO write clock, but the BRAM latency and\n", "the way the write pointer is updated and propagated to the logic can result in 4 words missing. So the count you will see for 100 words sent will be 96. \n", "\n", "Also, the read words is the number of words available to read, so it will be 96 before the read transaction, and 0 after.\n" ] }, { "cell_type": "code", "execution_count": 79, "id": "4c4edd19-e5f6-4c20-83a6-2f6b7a205326", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "Fifo words in the fifo: 96\n", "Fifo words available to read: 96\n", "Fifo words available after transfer: 0\n", "\n", "From fifo values: (should be same as Into values)\n", "0xcafe0000 0xcafe0001 0xcafe0002 0xcafe0003 0xcafe0004 0xcafe0005 0xcafe0006 0xcafe0007 0xcafe0008 0xcafe0009 0xcafe000a 0xcafe000b 0xcafe000c 0xcafe000d 0xcafe000e 0xcafe000f 0xcafe0010 0xcafe0011 0xcafe0012 0xcafe0013 0xcafe0014 0xcafe0015 0xcafe0016 0xcafe0017 0xcafe0018 0xcafe0019 0xcafe001a 0xcafe001b 0xcafe001c 0xcafe001d 0xcafe001e 0xcafe001f 0xcafe0020 0xcafe0021 0xcafe0022 0xcafe0023 0xcafe0024 0xcafe0025 0xcafe0026 0xcafe0027 0xcafe0028 0xcafe0029 0xcafe002a 0xcafe002b 0xcafe002c 0xcafe002d 0xcafe002e 0xcafe002f 0xcafe0030 0xcafe0031 0xcafe0032 0xcafe0033 0xcafe0034 0xcafe0035 0xcafe0036 0xcafe0037 0xcafe0038 0xcafe0039 0xcafe003a 0xcafe003b 0xcafe003c 0xcafe003d 0xcafe003e 0xcafe003f 0xcafe0040 0xcafe0041 0xcafe0042 0xcafe0043 0xcafe0044 0xcafe0045 0xcafe0046 0xcafe0047 0xcafe0048 0xcafe0049 0xcafe004a 0xcafe004b 0xcafe004c 0xcafe004d 0xcafe004e 0xcafe004f 0xcafe0050 0xcafe0051 0xcafe0052 0xcafe0053 0xcafe0054 0xcafe0055 0xcafe0056 0xcafe0057 0xcafe0058 0xcafe0059 0xcafe005a 0xcafe005b 0xcafe005c 0xcafe005d 0xcafe005e 0xcafe005f 0xcafe0060 0xcafe0061 0xcafe0062 0xcafe0063 " ] } ], "source": [ "dma_send.transfer(into_buffer)\n", "dma_send.wait()\n", "fifo_wr_data = fifo_wr_ptr.read()\n", "print(\"Fifo words in the fifo: \"+str(fifo_wr_data))\n", "fifo_rd_data = fifo_rd_ptr.read()\n", "print(\"Fifo words available to read: \"+str(fifo_rd_data))\n", "dma_recv.transfer(from_buffer)\n", "dma_recv.wait()\n", "fifo_rd_data = fifo_rd_ptr.read()\n", "print(\"Fifo words available after transfer: \"+str(fifo_rd_data))\n", "print(\"\\nFrom fifo values: (should be same as Into values)\")\n", "for i in range(into_size):\n", " print(hex(from_buffer[i]), end=\" \")\n" ] }, { "cell_type": "code", "execution_count": null, "id": "bdc5fe10-6aa1-4d49-b1c1-9fce7be4130d", "metadata": {}, "outputs": [], "source": [] } ], "metadata": { "kernelspec": { "display_name": "Python 3 (ipykernel)", "language": "python", "name": "python3" }, "language_info": { "codemirror_mode": { "name": "ipython", "version": 3 }, "file_extension": ".py", "mimetype": "text/x-python", "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", "version": "3.10.4" } }, "nbformat": 4, "nbformat_minor": 5 }