`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// takes 10ns input clk, produces 327us clock_slow and 20ns clk20 all on clock buffers
//
module ClkSynth(
    input clock_in,
    output clock_slow,
    output clk20
    );
    //
    // slow down the 100MHz system clock.   this thing does not need to
    // run that fast!    
    // clock_count[9] = 10us
    // count[14] = 327us (3.052kHz)
    // clock_count[19] = 10ms
    //
    reg [14:0] clock_count = 0;
    always @ (posedge clock_in) clock_count <= clock_count + 1;
    assign clock_slow = clock_count[14];
    //
    // make a 20ns clock.  we will use this to latch the extended 1-shots
    //
    reg clk2 = 0;
    always @ (posedge clock_in) clk2 <= ~clk2;
    assign clk20 = clk2;
    
endmodule