This board allows various tests including: HTR/SLB site
connectivity; 100Base-Ethernet for Luminosity project; HCAL self-triggering
for Slice test 2005; E/HCAL trigger link.
The mezzanine board can be mounted on the
HTR motherboard,
on one of the SLB-posts.
It allows to plug on top of it the
Vitesse Receiver Mezzanine from the Wisconsin RCT group.
This card is used for many projects...see below
FIRMWARE
| V2P Project | FPGAversionN (decimal, on reg 3) |
Notes |
| Sandwich2_v1.zip | 0001 |
Spying HTR TP data at 80MHz. Monitor clocks, BC0's, BCN. |
| Sandwich2_v3.zip | 0003 | Spying HTR TP data at 80MHz, spying vitesse (how) via the Local Bus (NB: Xilinx on the HTR motherboard is not required). Monitor clocks, BC0's, BCN. LVDS out (pulse or level), breathing LED. BUG: Vitesse RefClk is 160MHz instead of 120MHz. Fixed in Bat904 only. |
| Sandwich2_v7.zip | 0007 | Version for HTR production test bench. |
This stuff is for the "self triggering" project, to use these "sandwich" boards to make a trigger using HCAL. The intent is to use this in P5 during the Magnet/Cosmic tests in late 2005/early 2006.
FIRMWARE
| Self-Triggering Project | File to load | FPGAversionN |
Notes |
| s1.zip | s1.bit | 0x70001 |
"Sandwich" board for self-triggring, to be used with HTR version 0x70025. This is a test version of the firmware. |
| s2.zip | 0x70002 | This is the version that should work (same as above with some debugging removed) | |
| s4.zip | s4.mcs | 0x70004 | Send L1A out the other LVDS spigot instead of the TTC test signal |
REGISTERS
| Address | Bits | Name | R/W | Comments |
| 0x0 | 16 | CntrReg | RW | Control register, bits are:
|
| 0x1 | 16 | Test | R | Should be 'hFFFFF |
| 0x2 | 16 | Test | R | Should be 'h0 |
| 0x3 | 16 | Firmware Version | R | Should be 0x7nnn where nnn is the revision number (7 means "test") |
| 0x10 | 16 | Status Reg | R | Status register, bits are:
|
| 0x18 | 8 | LastTTCcommand | R | The last TTC command seen |
| 0x20-2F | 16 | TTC test | R | Counts how many times we have seen TTC command 0-F |
| 0x35 | 10 | SpyFIFO 1 | R | Read data from TPG set 1 (1st on TOP) {empty,TPG[9:0]} |
| 0x36 | 10 | SpyFIFO 2 | R | Read data from TPG set 2(2nd on TOP) {empty,TPG[9:0]} |
| 0x37 | 10 | SpyFIFO 3 | R | Read data from TPG set 3 (3rd on TOP) {empty,TPG[9:0]} |
| 0x38 | 10 | SpyFIFO 4 | R | Read data from TPG set 4 (4th on TOP) {empty,TPG[9:0]} |
| 0x39 | 10 | SpyFIFO 5 | R | Read data from TPG set 5 (1st on BOTTOM) {empty,TPG[9:0]} |
| 0x3A | 10 | SpyFIFO 6 | R | Read data from TPG set 6 (2nd on BOTTOM) {empty,TPG[9:0]} |
| 0x3B | 10 | SpyFIFO 7 | R | Read data from TPG set 7 (3rd on BOTTOM) {empty,TPG[9:0]} |
| 0x3C | 10 | SpyFIFO 8 | R | Read data from TPG set 8 (4th on BOTTOM) {empty,TPG[9:0]} |
| 0x3D | 16 | TTC cnt | R | Counts TTC clocks since last soft reset if run status is START |
| 0x3E | 16 | RXClk cnt | R | Counts clocks from RX_CLK since last soft reset if run status is START |
| 0x40 | 16 | RXBC0 cnt | R | Counts number of RX_BC0 seen |
| 0x61 | 16 | WriteOnlyCntrReg | W | Write only control register, bits are:
|
| 0x71 | 16 | TPSpyFifo Status | R | {TPSpyFifoFull[8:1],TPSpyFifoEmpty[8:1]} |
