Hcal Trigger Test mezzanine board (a.k.a. "sandwich board")


The purpose of this board is to allow various tests of the HCAL trigger generation and link.
The mezzanine board can be mounted on the HTR motherboard, on one of the SLB-posts. It allows to plug on top of it the Vitesse Receiver Mezzanine from the Wisconsin RCT group. It is also a first prototype for the HF Luminosity monitor and for the HF Trigger project.


Initial specifications.
Schematics.
Board design files from UMd shop (see: SLB Sandwich Adapter).

FIRMWARE
V2P Project FPGAversionN
(decimal)		 Notes
SLBS_t1.zip 1
LocalBus, TTCdecoder, clock scheme with 3x and ClkMux, input data from motherboard (PMC connectors).
SLBS_v5.zip 5 VitesseSpyFifos (depth = 2047 words); 8 spy fifos (clocked by TTC_Clk) for TP inputs from HTR
SLBS_v6.zip 6 Optional feature for the VitesseSpyFifos to start spying on a IDLE-to-DATA transition).
SLBS_v8.zip 7 Spying HTR TP data at 80MHz. This works only for some PMC positions (the other need an inverted clock). Plus, spying the two clocks and the two BC0s

VITESSE RECEIVER STATUS SIGNALS
ERRn KCHn IDLEn Priority Link Status
0007Valid Data
1102Loss of Sync
1112RESYNC (includes IDLE)


STATUS
 - Oct 04: received 5 boards assembled by Compunetix  (+5 non populated). Fixed the JTAG (pull-up on TDO), able to program the FPGA with cable only (EPROM is wrong size).
- Nov 04: HTR Data inputs, TTC interface and LocalBus ok.
- Dec 04: trigger link from old SLB to sandwich board established.
- 20 Jan 04: trigger link with production SLB.
- Feb 04: tested transmission at 80 Mb/s from HTR to sandwich board, multiplying by 2 the local TTC clock. Certain SLB locations need to invert the phase of the 80 MHz clock. Achieved 30-second error-free (BER < 10^11), with counter and shift-reg patterns.

Tullio Grassi - Feb 2005
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