Subject: Re: Re: CASE 35127199 {ID:1589464} Date: Wed, 11 Jul 2001 10:07:39 -0500 From: support@ti.com To: Tullio Grassi Tullio, from our product support: Best Regards, Jack Bourke - Why the trace of GTX_CLK is routed with a serpentine pattern ? Two reasons 1) To not cross over the parallel data lines which are on the bottom layer. 2) To match the length of the parallel data lines from the probe point into the chip. - There are no transmission line Charateristics for GTX_CLK, can you provide them similarly to Table 3-1? The formulas are from App. C in Howard Johnson & Martin Graham, "High-Speeed Digital Design: A Handbook of Black Magic." The book is highly recommended if you're going to do any quantity of high speed PCB design. 8-GTX_CLK Capacitance 5.24pF Inductance 13.7 nH Impedance 51.2 W Line Delay 268. pS - About the external RREF resistor: on the IC data sheet, page 19, you reccomend 200 Ohm, but on the EVM kit you use 100 Ohm. Why ? It appears that there's a mistake on the schematic. If you check the bill of materials, R41 is listed as 200W. - On page 13 of the IC data sheet : " The TLK2501 is optimized for ... 2.5 Gbps" We will work at 1.603 Gbps. Would you reccomend the TLK1501 ? No. You MUST work within the absolute range of the part. The PLL is optimized for the higher speed, but all of the spec's will be met throughout the range. The transmitter/receiver characteristics are actually better than what is listed, but at 2.5Gbps they would have even more margin. - About the PowerPAD soldered to a thermal land, on page 22 of the device Data Sheet: "... this thermal land should be grounded to the low inpedence groun plane...". Is it possible to connect the PowerPAD and the thermal land to 2.5 V ? Have you tested this solution ? This would optimize my PCB layer stack. NO! Do not connect the thermal ground to 2.5V. These also serve as electrical grounds. We will put 8 (or 12) TLK2501 per board, only as receivers. Do you have experience/reccomandation about coupling and noise between the chips ? You can use the TLK2501 to receive only, although typical applications use a TLK2501 to talk to another TLK2501 which is transmitting. Be sure to take care of the initialization/synchronization state machine. It is probably a good idea to take the transmit eye data and verify that it has the characteristics that you (and the TLK2501) expect. Also, you should terminate the transmit lines, even if you're not using them. The question about coupling and noise is very broad. Make sure that you follow high speed board layout practices, such as those noted in the book above. At that speed, don't closely couple lines from/for different chips. Beyond that, instead of summarizing board layout practices, the attached document provides several good recommendations on general high speed board layout. - What is the length from the silicon pad to the pin package of: DINRXP, DINRXN, DOUTTXP, DOUTTXN. What is the impedence of these lines in the package ? You can come up with an estimate of length by assuming that the die is 3mmx3mm, centered. The spice files provide the best estimate of impedance. It cannot be accurately estimated through a lumped element model at these high speeds. - Why the differential lines (DINRXP/N ; DOUTTXP/N ) are routed as single-ended on the EVM board ? Is it really the best approach or is to demonstrate something ? What if I route them as differential lines (close toghter, constant distance, matching the differential Z) ? We believe that it is the best approach. However, there's not a real consensus through the board design community about the optimal approach. Different places use different methods. Either practice can work. Close-together lines have a lower impedance, so traces may need to be narrowed. This raises skin effect losses. They also allow pairs to be routed more closely together.