HF Jet project

Sept 2005

Overview

The goal of the project is to move the so-called Trigger Primitive (TP) data from two groups of 9 HTR boards into a single board.
Data rate is: 9 (HTRs) x 48 (TP/HTR) x 8 (bits/TP) x 40 MHz = 9 (HTRs) x 15.36 Gb/s.
Baseline plan is to use 12x parallel optics at 1.6 Gb/s or higher.
Backup plan is 10GBASE on copper.

This data rate can be accomodate in several ways:
1) one 1.6 Gb/s 12-way parallel optic transmitter per HTR board, where all of the 12 optical links are used in 8b/10b mode. In this case the payload is identical to the channel capacity, with no room for frame bit and BC0 marker. If running with the TTC_clkx2 the framing should be locked to the IDLE-DATA transition. The BC0 marker could also be locked to the IDLE-DATA transition or associated with the reserved data word "FF". Energy levels should be remapped to the range [00; FE].
If running with a free-oscillating cristal we can run at a little higer frequency and insert an extra word as a BC0 marker. The receiver would use this word to set the BCN for that chennel and remove the word from the data stream.
2) one 1.6 Gb/s 12-way parallel optic transmitter per HTR board, where all of the 12 optical links are used in 64b/66b mode.
3) one 2.7 Gb/s 12-way parallel optic transmitter per HTR board, where 6 of the 12 optical links are used in 64b/66b mode.
The project requires one type of mezzanine board (called HFT) to be plugged on the HTR PMC connectors (on 4 SLB sites) and one VME board (called HFJ) to receive data from 9 mezzanines.
The VME board should receive the 9 parallel optic ribbon cables, likely with 9 Xilinx Virtex2Pro FPGAs, sharing data with LVDS connections (~100 pairs per FPGA). Data is than transmitted and concentrated on a single FPGA and the same board.
FPGA candidates as of July 22nd:

Device-package        UserI/O (RocketIO)     Lead Time              $                Note

XC2VP40-FF1152        692 (12)                                                                        70% more RAM than the main Xilinx on HTR.
XC2VP70-FF1517        964 (16)        4wk (memec, Avnet)        2.5k
XC2VP70-FF1704         996 (20)        4wk (memec, Avnet)         2.6k
XC2VP100-FF1704     1040 (20)        4wk (memec, Avnet)        6.2k

XC4VFX100-FF1152    576 (20)        call(memec)
XC4VFX140-FF1517    768 (24)        call(memec)

All FF packages (Flip-chip, ok for max RocketIO speed) have 1 mm pitch.
Use 24/12 via (.024 pad/.012 drill)

PROBLEMS:

1mm pitch BGAs on 9U board (reccomended to use the same company for fab and assembly)

Proposal (with physics studies)

HFJ Demo board.